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Generate the Verilog code corresponding to this FIRRTL code module MacUnit_226 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_226( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_50 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_50
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_128
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_50( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_50 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_128 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IDPool_1 :
input clock : Clock
input reset : Reset
output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}}
regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff)
regreset select : UInt<3>, clock, reset, UInt<3>(0h0)
regreset valid : UInt<1>, clock, reset, UInt<1>(0h1)
connect io.alloc.valid, valid
connect io.alloc.bits, select
node taken_shiftAmount = bits(io.alloc.bits, 2, 0)
node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount)
node _taken_T_1 = bits(_taken_T, 7, 0)
node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0))
node allocated_shiftAmount = bits(io.free.bits, 2, 0)
node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount)
node _allocated_T_1 = bits(_allocated_T, 7, 0)
node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0))
node _bitmap1_T = not(taken)
node _bitmap1_T_1 = and(bitmap, _bitmap1_T)
node bitmap1 = or(_bitmap1_T_1, allocated)
node _select1_T = bits(bitmap1, 0, 0)
node _select1_T_1 = bits(bitmap1, 1, 1)
node _select1_T_2 = bits(bitmap1, 2, 2)
node _select1_T_3 = bits(bitmap1, 3, 3)
node _select1_T_4 = bits(bitmap1, 4, 4)
node _select1_T_5 = bits(bitmap1, 5, 5)
node _select1_T_6 = bits(bitmap1, 6, 6)
node _select1_T_7 = bits(bitmap1, 7, 7)
node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7))
node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8)
node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9)
node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10)
node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11)
node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12)
node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13)
node _valid1_T = orr(bitmap)
node _valid1_T_1 = bits(bitmap, 0, 0)
node _valid1_T_2 = bits(bitmap, 1, 1)
node _valid1_T_3 = bits(bitmap, 2, 2)
node _valid1_T_4 = bits(bitmap, 3, 3)
node _valid1_T_5 = bits(bitmap, 4, 4)
node _valid1_T_6 = bits(bitmap, 5, 5)
node _valid1_T_7 = bits(bitmap, 6, 6)
node _valid1_T_8 = bits(bitmap, 7, 7)
node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2)
node _valid1_T_10 = bits(_valid1_T_9, 1, 0)
node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4)
node _valid1_T_12 = bits(_valid1_T_11, 1, 0)
node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12)
node _valid1_T_14 = bits(_valid1_T_13, 2, 0)
node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6)
node _valid1_T_16 = bits(_valid1_T_15, 1, 0)
node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8)
node _valid1_T_18 = bits(_valid1_T_17, 1, 0)
node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18)
node _valid1_T_20 = bits(_valid1_T_19, 2, 0)
node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20)
node _valid1_T_22 = bits(_valid1_T_21, 3, 0)
node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1))
node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready)
node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0))
node _valid1_T_26 = and(_valid1_T, _valid1_T_25)
node valid1 = or(_valid1_T_26, io.free.valid)
node _T = or(io.alloc.ready, io.free.valid)
when _T :
connect bitmap, bitmap1
connect valid, valid1
node _T_1 = eq(io.alloc.valid, UInt<1>(0h0))
node _T_2 = and(_T_1, io.free.valid)
node _T_3 = or(io.alloc.ready, _T_2)
when _T_3 :
connect select, select1
node _T_4 = eq(io.free.valid, UInt<1>(0h0))
node _T_5 = not(taken)
node _T_6 = and(bitmap, _T_5)
node _T_7 = dshr(_T_6, io.free.bits)
node _T_8 = bits(_T_7, 0, 0)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = or(_T_4, _T_9)
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))\n") : printf
assert(clock, _T_10, UInt<1>(0h1), "") : assert
node _T_14 = orr(bitmap)
node _T_15 = eq(valid, _T_14)
node _T_16 = asUInt(reset)
node _T_17 = eq(_T_16, UInt<1>(0h0))
when _T_17 :
node _T_18 = eq(_T_15, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1
assert(clock, _T_15, UInt<1>(0h1), "") : assert_1
node _T_19 = eq(io.alloc.valid, UInt<1>(0h0))
node _T_20 = and(_T_19, io.free.valid)
node _T_21 = or(io.alloc.ready, _T_20)
reg REG : UInt<1>, clock
connect REG, _T_21
node _T_22 = and(io.alloc.valid, REG)
when _T_22 :
node _T_23 = bits(bitmap, 0, 0)
node _T_24 = bits(bitmap, 1, 1)
node _T_25 = bits(bitmap, 2, 2)
node _T_26 = bits(bitmap, 3, 3)
node _T_27 = bits(bitmap, 4, 4)
node _T_28 = bits(bitmap, 5, 5)
node _T_29 = bits(bitmap, 6, 6)
node _T_30 = bits(bitmap, 7, 7)
node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7))
node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31)
node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32)
node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33)
node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34)
node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35)
node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36)
node _T_38 = eq(select, _T_37)
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
node _T_41 = eq(_T_38, UInt<1>(0h0))
when _T_41 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2
assert(clock, _T_38, UInt<1>(0h1), "") : assert_2 | module IDPool_1( // @[IDPool.scala:8:7]
input clock, // @[IDPool.scala:8:7]
input reset, // @[IDPool.scala:8:7]
input io_free_valid, // @[IDPool.scala:12:14]
input [2:0] io_free_bits, // @[IDPool.scala:12:14]
input io_alloc_ready, // @[IDPool.scala:12:14]
output io_alloc_valid, // @[IDPool.scala:12:14]
output [2:0] io_alloc_bits // @[IDPool.scala:12:14]
);
wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7]
wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7]
wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7]
wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7]
wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49]
wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49]
wire io_alloc_valid_0; // @[IDPool.scala:8:7]
reg [7:0] bitmap; // @[IDPool.scala:18:23]
reg [2:0] select; // @[IDPool.scala:19:23]
assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23]
reg valid; // @[IDPool.scala:20:23]
assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23]
wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}]
wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27]
wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}]
wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27]
wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27]
wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}]
wire [7:0] bitmap1 = _bitmap1_T_1 | allocated; // @[IDPool.scala:26:22, :27:{25,35}]
wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45]
wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45]
wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45]
wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45]
wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45]
wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45]
wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45]
wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45]
wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45]
wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45]
wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45]
wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45]
wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45]
wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45]
wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45]
wire _valid1_T = |bitmap; // @[IDPool.scala:18:23, :29:28]
wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46]
wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46]
wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46]
wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46]
wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46]
wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46]
wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46]
wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46]
wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46]
wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46]
wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46]
wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46]
wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46]
wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46]
wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46]
wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46]
wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46]
wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46]
wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46]
wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46]
wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46]
wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46]
wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}]
wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}]
wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}]
wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}]
wire valid1 = _valid1_T_26 | io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17]
reg REG; // @[IDPool.scala:51:36] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = and(_T_11, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_20, UInt<1>(0h1), "") : assert_1
node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_24 :
node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_30 = or(_T_28, _T_29)
node _T_31 = and(_T_27, _T_30)
node _T_32 = or(UInt<1>(0h0), _T_31)
node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_35 = cvt(_T_34)
node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000)))
node _T_37 = asSInt(_T_36)
node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0)))
node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_40 = cvt(_T_39)
node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000)))
node _T_42 = asSInt(_T_41)
node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0)))
node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_45 = cvt(_T_44)
node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000)))
node _T_47 = asSInt(_T_46)
node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0)))
node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_50 = cvt(_T_49)
node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000)))
node _T_52 = asSInt(_T_51)
node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0)))
node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<27>(0h4000000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = or(_T_38, _T_43)
node _T_75 = or(_T_74, _T_48)
node _T_76 = or(_T_75, _T_53)
node _T_77 = or(_T_76, _T_58)
node _T_78 = or(_T_77, _T_63)
node _T_79 = or(_T_78, _T_68)
node _T_80 = or(_T_79, _T_73)
node _T_81 = and(_T_33, _T_80)
node _T_82 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_83 = or(UInt<1>(0h0), _T_82)
node _T_84 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<17>(0h10000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<29>(0h10000000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = or(_T_88, _T_93)
node _T_95 = and(_T_83, _T_94)
node _T_96 = or(UInt<1>(0h0), _T_81)
node _T_97 = or(_T_96, _T_95)
node _T_98 = and(_T_32, _T_97)
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_98, UInt<1>(0h1), "") : assert_2
node _T_102 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_103 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE : UInt<1>[2]
connect _WIRE[0], _T_102
connect _WIRE[1], _T_103
node _T_104 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_105 = mux(_WIRE[0], _T_104, UInt<1>(0h0))
node _T_106 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = or(_T_105, _T_106)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_107
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = or(UInt<1>(0h0), _T_110)
node _T_112 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<14>(0h2000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<17>(0h10000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<27>(0h4000000)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_153 = cvt(_T_152)
node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000)))
node _T_155 = asSInt(_T_154)
node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_158 = cvt(_T_157)
node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000)))
node _T_160 = asSInt(_T_159)
node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0)))
node _T_162 = or(_T_116, _T_121)
node _T_163 = or(_T_162, _T_126)
node _T_164 = or(_T_163, _T_131)
node _T_165 = or(_T_164, _T_136)
node _T_166 = or(_T_165, _T_141)
node _T_167 = or(_T_166, _T_146)
node _T_168 = or(_T_167, _T_151)
node _T_169 = or(_T_168, _T_156)
node _T_170 = or(_T_169, _T_161)
node _T_171 = and(_T_111, _T_170)
node _T_172 = or(UInt<1>(0h0), _T_171)
node _T_173 = and(_WIRE_1, _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_173, UInt<1>(0h1), "") : assert_3
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(source_ok, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_180 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_180, UInt<1>(0h1), "") : assert_5
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(is_aligned, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_187 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_187, UInt<1>(0h1), "") : assert_7
node _T_191 = not(io.in.a.bits.mask)
node _T_192 = eq(_T_191, UInt<1>(0h0))
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(_T_192, UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_192, UInt<1>(0h1), "") : assert_8
node _T_196 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_197 = asUInt(reset)
node _T_198 = eq(_T_197, UInt<1>(0h0))
when _T_198 :
node _T_199 = eq(_T_196, UInt<1>(0h0))
when _T_199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_196, UInt<1>(0h1), "") : assert_9
node _T_200 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_200 :
node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_205 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_206 = or(_T_204, _T_205)
node _T_207 = and(_T_203, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<14>(0h2000)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_221 = cvt(_T_220)
node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000)))
node _T_223 = asSInt(_T_222)
node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0)))
node _T_225 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_226 = cvt(_T_225)
node _T_227 = and(_T_226, asSInt(UInt<18>(0h2f000)))
node _T_228 = asSInt(_T_227)
node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_231 = cvt(_T_230)
node _T_232 = and(_T_231, asSInt(UInt<17>(0h10000)))
node _T_233 = asSInt(_T_232)
node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0)))
node _T_235 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_236 = cvt(_T_235)
node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000)))
node _T_238 = asSInt(_T_237)
node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0)))
node _T_240 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_241 = cvt(_T_240)
node _T_242 = and(_T_241, asSInt(UInt<27>(0h4000000)))
node _T_243 = asSInt(_T_242)
node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_246 = cvt(_T_245)
node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000)))
node _T_248 = asSInt(_T_247)
node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0)))
node _T_250 = or(_T_214, _T_219)
node _T_251 = or(_T_250, _T_224)
node _T_252 = or(_T_251, _T_229)
node _T_253 = or(_T_252, _T_234)
node _T_254 = or(_T_253, _T_239)
node _T_255 = or(_T_254, _T_244)
node _T_256 = or(_T_255, _T_249)
node _T_257 = and(_T_209, _T_256)
node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_259 = or(UInt<1>(0h0), _T_258)
node _T_260 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_261 = cvt(_T_260)
node _T_262 = and(_T_261, asSInt(UInt<17>(0h10000)))
node _T_263 = asSInt(_T_262)
node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0)))
node _T_265 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_266 = cvt(_T_265)
node _T_267 = and(_T_266, asSInt(UInt<29>(0h10000000)))
node _T_268 = asSInt(_T_267)
node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0)))
node _T_270 = or(_T_264, _T_269)
node _T_271 = and(_T_259, _T_270)
node _T_272 = or(UInt<1>(0h0), _T_257)
node _T_273 = or(_T_272, _T_271)
node _T_274 = and(_T_208, _T_273)
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_274, UInt<1>(0h1), "") : assert_10
node _T_278 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE_2 : UInt<1>[2]
connect _WIRE_2[0], _T_278
connect _WIRE_2[1], _T_279
node _T_280 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_281 = mux(_WIRE_2[0], _T_280, UInt<1>(0h0))
node _T_282 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = or(_T_281, _T_282)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_283
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<14>(0h2000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<18>(0h2f000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<13>(0h1000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<27>(0h4000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<29>(0h10000000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = or(_T_292, _T_297)
node _T_339 = or(_T_338, _T_302)
node _T_340 = or(_T_339, _T_307)
node _T_341 = or(_T_340, _T_312)
node _T_342 = or(_T_341, _T_317)
node _T_343 = or(_T_342, _T_322)
node _T_344 = or(_T_343, _T_327)
node _T_345 = or(_T_344, _T_332)
node _T_346 = or(_T_345, _T_337)
node _T_347 = and(_T_287, _T_346)
node _T_348 = or(UInt<1>(0h0), _T_347)
node _T_349 = and(_WIRE_3, _T_348)
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(_T_349, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_349, UInt<1>(0h1), "") : assert_11
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(source_ok, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_356, UInt<1>(0h1), "") : assert_13
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(is_aligned, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_363, UInt<1>(0h1), "") : assert_15
node _T_367 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_367, UInt<1>(0h1), "") : assert_16
node _T_371 = not(io.in.a.bits.mask)
node _T_372 = eq(_T_371, UInt<1>(0h0))
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_T_372, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_372, UInt<1>(0h1), "") : assert_17
node _T_376 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_376, UInt<1>(0h1), "") : assert_18
node _T_380 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_380 :
node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_383 = and(_T_381, _T_382)
node _T_384 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_385 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_386 = or(_T_384, _T_385)
node _T_387 = and(_T_383, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(_T_388, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_388, UInt<1>(0h1), "") : assert_19
node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_394 = and(_T_392, _T_393)
node _T_395 = or(UInt<1>(0h0), _T_394)
node _T_396 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_397 = cvt(_T_396)
node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000)))
node _T_399 = asSInt(_T_398)
node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0)))
node _T_401 = and(_T_395, _T_400)
node _T_402 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_403 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_404 = and(_T_402, _T_403)
node _T_405 = or(UInt<1>(0h0), _T_404)
node _T_406 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_407 = cvt(_T_406)
node _T_408 = and(_T_407, asSInt(UInt<14>(0h2000)))
node _T_409 = asSInt(_T_408)
node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0)))
node _T_411 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_412 = cvt(_T_411)
node _T_413 = and(_T_412, asSInt(UInt<17>(0h10000)))
node _T_414 = asSInt(_T_413)
node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0)))
node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_417 = cvt(_T_416)
node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000)))
node _T_419 = asSInt(_T_418)
node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0)))
node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_422 = cvt(_T_421)
node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000)))
node _T_424 = asSInt(_T_423)
node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0)))
node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_437 = cvt(_T_436)
node _T_438 = and(_T_437, asSInt(UInt<27>(0h4000000)))
node _T_439 = asSInt(_T_438)
node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0)))
node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_447 = cvt(_T_446)
node _T_448 = and(_T_447, asSInt(UInt<29>(0h10000000)))
node _T_449 = asSInt(_T_448)
node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0)))
node _T_451 = or(_T_410, _T_415)
node _T_452 = or(_T_451, _T_420)
node _T_453 = or(_T_452, _T_425)
node _T_454 = or(_T_453, _T_430)
node _T_455 = or(_T_454, _T_435)
node _T_456 = or(_T_455, _T_440)
node _T_457 = or(_T_456, _T_445)
node _T_458 = or(_T_457, _T_450)
node _T_459 = and(_T_405, _T_458)
node _T_460 = or(UInt<1>(0h0), _T_401)
node _T_461 = or(_T_460, _T_459)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_461, UInt<1>(0h1), "") : assert_20
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(source_ok, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(is_aligned, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_471 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_471, UInt<1>(0h1), "") : assert_23
node _T_475 = eq(io.in.a.bits.mask, mask)
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_475, UInt<1>(0h1), "") : assert_24
node _T_479 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_479, UInt<1>(0h1), "") : assert_25
node _T_483 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_483 :
node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_486 = and(_T_484, _T_485)
node _T_487 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_488 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_489 = or(_T_487, _T_488)
node _T_490 = and(_T_486, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_494 = and(_T_492, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_497 = cvt(_T_496)
node _T_498 = and(_T_497, asSInt(UInt<13>(0h1000)))
node _T_499 = asSInt(_T_498)
node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0)))
node _T_501 = and(_T_495, _T_500)
node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_504 = and(_T_502, _T_503)
node _T_505 = or(UInt<1>(0h0), _T_504)
node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_507 = cvt(_T_506)
node _T_508 = and(_T_507, asSInt(UInt<14>(0h2000)))
node _T_509 = asSInt(_T_508)
node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0)))
node _T_511 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<18>(0h2f000)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<27>(0h4000000)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<13>(0h1000)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_542 = cvt(_T_541)
node _T_543 = and(_T_542, asSInt(UInt<29>(0h10000000)))
node _T_544 = asSInt(_T_543)
node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0)))
node _T_546 = or(_T_510, _T_515)
node _T_547 = or(_T_546, _T_520)
node _T_548 = or(_T_547, _T_525)
node _T_549 = or(_T_548, _T_530)
node _T_550 = or(_T_549, _T_535)
node _T_551 = or(_T_550, _T_540)
node _T_552 = or(_T_551, _T_545)
node _T_553 = and(_T_505, _T_552)
node _T_554 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_555 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_556 = cvt(_T_555)
node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000)))
node _T_558 = asSInt(_T_557)
node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0)))
node _T_560 = and(_T_554, _T_559)
node _T_561 = or(UInt<1>(0h0), _T_501)
node _T_562 = or(_T_561, _T_553)
node _T_563 = or(_T_562, _T_560)
node _T_564 = and(_T_491, _T_563)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_564, UInt<1>(0h1), "") : assert_26
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(source_ok, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(is_aligned, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_574 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_574, UInt<1>(0h1), "") : assert_29
node _T_578 = eq(io.in.a.bits.mask, mask)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_578, UInt<1>(0h1), "") : assert_30
node _T_582 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_582 :
node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_584 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_585 = and(_T_583, _T_584)
node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_587 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(_T_585, _T_588)
node _T_590 = or(UInt<1>(0h0), _T_589)
node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_593 = and(_T_591, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_596 = cvt(_T_595)
node _T_597 = and(_T_596, asSInt(UInt<13>(0h1000)))
node _T_598 = asSInt(_T_597)
node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0)))
node _T_600 = and(_T_594, _T_599)
node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_602 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_603 = and(_T_601, _T_602)
node _T_604 = or(UInt<1>(0h0), _T_603)
node _T_605 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_606 = cvt(_T_605)
node _T_607 = and(_T_606, asSInt(UInt<14>(0h2000)))
node _T_608 = asSInt(_T_607)
node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0)))
node _T_610 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_611 = cvt(_T_610)
node _T_612 = and(_T_611, asSInt(UInt<18>(0h2f000)))
node _T_613 = asSInt(_T_612)
node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0)))
node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<17>(0h10000)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_626 = cvt(_T_625)
node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000)))
node _T_628 = asSInt(_T_627)
node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0)))
node _T_630 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<27>(0h4000000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<29>(0h10000000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = or(_T_609, _T_614)
node _T_646 = or(_T_645, _T_619)
node _T_647 = or(_T_646, _T_624)
node _T_648 = or(_T_647, _T_629)
node _T_649 = or(_T_648, _T_634)
node _T_650 = or(_T_649, _T_639)
node _T_651 = or(_T_650, _T_644)
node _T_652 = and(_T_604, _T_651)
node _T_653 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_655 = cvt(_T_654)
node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000)))
node _T_657 = asSInt(_T_656)
node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0)))
node _T_659 = and(_T_653, _T_658)
node _T_660 = or(UInt<1>(0h0), _T_600)
node _T_661 = or(_T_660, _T_652)
node _T_662 = or(_T_661, _T_659)
node _T_663 = and(_T_590, _T_662)
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(_T_663, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_663, UInt<1>(0h1), "") : assert_31
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(source_ok, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(is_aligned, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_673, UInt<1>(0h1), "") : assert_34
node _T_677 = not(mask)
node _T_678 = and(io.in.a.bits.mask, _T_677)
node _T_679 = eq(_T_678, UInt<1>(0h0))
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(_T_679, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_679, UInt<1>(0h1), "") : assert_35
node _T_683 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_683 :
node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_685 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_686 = and(_T_684, _T_685)
node _T_687 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_688 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_689 = or(_T_687, _T_688)
node _T_690 = and(_T_686, _T_689)
node _T_691 = or(UInt<1>(0h0), _T_690)
node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_693 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _T_695 = or(UInt<1>(0h0), _T_694)
node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_697 = cvt(_T_696)
node _T_698 = and(_T_697, asSInt(UInt<14>(0h2000)))
node _T_699 = asSInt(_T_698)
node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0)))
node _T_701 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_702 = cvt(_T_701)
node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000)))
node _T_704 = asSInt(_T_703)
node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0)))
node _T_706 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<18>(0h2f000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<17>(0h10000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<17>(0h10000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<27>(0h4000000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<29>(0h10000000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = or(_T_700, _T_705)
node _T_742 = or(_T_741, _T_710)
node _T_743 = or(_T_742, _T_715)
node _T_744 = or(_T_743, _T_720)
node _T_745 = or(_T_744, _T_725)
node _T_746 = or(_T_745, _T_730)
node _T_747 = or(_T_746, _T_735)
node _T_748 = or(_T_747, _T_740)
node _T_749 = and(_T_695, _T_748)
node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = and(_T_750, _T_755)
node _T_757 = or(UInt<1>(0h0), _T_749)
node _T_758 = or(_T_757, _T_756)
node _T_759 = and(_T_691, _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_759, UInt<1>(0h1), "") : assert_36
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(source_ok, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(is_aligned, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_770 = asUInt(reset)
node _T_771 = eq(_T_770, UInt<1>(0h0))
when _T_771 :
node _T_772 = eq(_T_769, UInt<1>(0h0))
when _T_772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_769, UInt<1>(0h1), "") : assert_39
node _T_773 = eq(io.in.a.bits.mask, mask)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_773, UInt<1>(0h1), "") : assert_40
node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_777 :
node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_780 = and(_T_778, _T_779)
node _T_781 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_782 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_783 = or(_T_781, _T_782)
node _T_784 = and(_T_780, _T_783)
node _T_785 = or(UInt<1>(0h0), _T_784)
node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_787 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<14>(0h2000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<13>(0h1000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<18>(0h2f000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<17>(0h10000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<27>(0h4000000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<29>(0h10000000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = or(_T_794, _T_799)
node _T_836 = or(_T_835, _T_804)
node _T_837 = or(_T_836, _T_809)
node _T_838 = or(_T_837, _T_814)
node _T_839 = or(_T_838, _T_819)
node _T_840 = or(_T_839, _T_824)
node _T_841 = or(_T_840, _T_829)
node _T_842 = or(_T_841, _T_834)
node _T_843 = and(_T_789, _T_842)
node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_845 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_846 = cvt(_T_845)
node _T_847 = and(_T_846, asSInt(UInt<17>(0h10000)))
node _T_848 = asSInt(_T_847)
node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0)))
node _T_850 = and(_T_844, _T_849)
node _T_851 = or(UInt<1>(0h0), _T_843)
node _T_852 = or(_T_851, _T_850)
node _T_853 = and(_T_785, _T_852)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_853, UInt<1>(0h1), "") : assert_41
node _T_857 = asUInt(reset)
node _T_858 = eq(_T_857, UInt<1>(0h0))
when _T_858 :
node _T_859 = eq(source_ok, UInt<1>(0h0))
when _T_859 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(is_aligned, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_863 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_863, UInt<1>(0h1), "") : assert_44
node _T_867 = eq(io.in.a.bits.mask, mask)
node _T_868 = asUInt(reset)
node _T_869 = eq(_T_868, UInt<1>(0h0))
when _T_869 :
node _T_870 = eq(_T_867, UInt<1>(0h0))
when _T_870 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_867, UInt<1>(0h1), "") : assert_45
node _T_871 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_871 :
node _T_872 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_873 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_876 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_877 = or(_T_875, _T_876)
node _T_878 = and(_T_874, _T_877)
node _T_879 = or(UInt<1>(0h0), _T_878)
node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_882 = and(_T_880, _T_881)
node _T_883 = or(UInt<1>(0h0), _T_882)
node _T_884 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = and(_T_883, _T_888)
node _T_890 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_891 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<14>(0h2000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<18>(0h2f000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_912 = cvt(_T_911)
node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000)))
node _T_914 = asSInt(_T_913)
node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_917 = cvt(_T_916)
node _T_918 = and(_T_917, asSInt(UInt<27>(0h4000000)))
node _T_919 = asSInt(_T_918)
node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0)))
node _T_921 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<13>(0h1000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = or(_T_895, _T_900)
node _T_927 = or(_T_926, _T_905)
node _T_928 = or(_T_927, _T_910)
node _T_929 = or(_T_928, _T_915)
node _T_930 = or(_T_929, _T_920)
node _T_931 = or(_T_930, _T_925)
node _T_932 = and(_T_890, _T_931)
node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_934 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_935 = and(_T_933, _T_934)
node _T_936 = or(UInt<1>(0h0), _T_935)
node _T_937 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<29>(0h10000000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = or(_T_941, _T_946)
node _T_948 = and(_T_936, _T_947)
node _T_949 = or(UInt<1>(0h0), _T_889)
node _T_950 = or(_T_949, _T_932)
node _T_951 = or(_T_950, _T_948)
node _T_952 = and(_T_879, _T_951)
node _T_953 = asUInt(reset)
node _T_954 = eq(_T_953, UInt<1>(0h0))
when _T_954 :
node _T_955 = eq(_T_952, UInt<1>(0h0))
when _T_955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_952, UInt<1>(0h1), "") : assert_46
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(source_ok, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(is_aligned, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_962 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(_T_962, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_962, UInt<1>(0h1), "") : assert_49
node _T_966 = eq(io.in.a.bits.mask, mask)
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_966, UInt<1>(0h1), "") : assert_50
node _T_970 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_970, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_974 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_974, UInt<1>(0h1), "") : assert_52
node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_2
connect _source_ok_WIRE_1[1], _source_ok_T_3
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_978 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_978 :
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(source_ok_1, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_982 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_982, UInt<1>(0h1), "") : assert_54
node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_986, UInt<1>(0h1), "") : assert_55
node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_990, UInt<1>(0h1), "") : assert_56
node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_994, UInt<1>(0h1), "") : assert_57
node _T_998 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_998 :
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(source_ok_1, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(sink_ok, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_60
node _T_1009 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_61
node _T_1013 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_62
node _T_1017 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_63
node _T_1021 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1022 = or(UInt<1>(0h1), _T_1021)
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_64
node _T_1026 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1026 :
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(source_ok_1, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(sink_ok, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1033 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_67
node _T_1037 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_68
node _T_1041 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_69
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(_T_1045, io.in.d.bits.corrupt)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_70
node _T_1050 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1051 = or(UInt<1>(0h1), _T_1050)
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_71
node _T_1055 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(source_ok_1, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1059 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_73
node _T_1063 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_74
node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1068 = or(UInt<1>(0h1), _T_1067)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_75
node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1072 :
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(source_ok_1, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_77
node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1081 = or(_T_1080, io.in.d.bits.corrupt)
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_T_1081, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1081, UInt<1>(0h1), "") : assert_78
node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1086 = or(UInt<1>(0h1), _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_79
node _T_1090 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1090 :
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(source_ok_1, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_81
node _T_1098 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_82
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(UInt<1>(0h1), _T_1102)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1107 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_84
node _T_1111 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
node _T_1113 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1114 = cvt(_T_1113)
node _T_1115 = and(_T_1114, asSInt(UInt<1>(0h0)))
node _T_1116 = asSInt(_T_1115)
node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0)))
node _T_1118 = or(_T_1112, _T_1117)
node _T_1119 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
node _T_1121 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1122 = cvt(_T_1121)
node _T_1123 = and(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = asSInt(_T_1123)
node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0)))
node _T_1126 = or(_T_1120, _T_1125)
node _T_1127 = and(_T_1118, _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _legal_source_WIRE : UInt<1>[2]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3)
wire _legal_source_WIRE_1 : UInt<1>
connect _legal_source_WIRE_1, _legal_source_T_4
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1131 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1131 :
node _T_1132 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1133 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _WIRE_4 : UInt<1>[2]
connect _WIRE_4[0], _T_1132
connect _WIRE_4[1], _T_1133
node _T_1134 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1135 = mux(_WIRE_4[0], _T_1134, UInt<1>(0h0))
node _T_1136 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1137 = or(_T_1135, _T_1136)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1137
node _T_1138 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1139 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1140 = and(_T_1138, _T_1139)
node _T_1141 = or(UInt<1>(0h0), _T_1140)
node _T_1142 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1143 = cvt(_T_1142)
node _T_1144 = and(_T_1143, asSInt(UInt<14>(0h2000)))
node _T_1145 = asSInt(_T_1144)
node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1148 = cvt(_T_1147)
node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000)))
node _T_1150 = asSInt(_T_1149)
node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0)))
node _T_1152 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<17>(0h10000)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1158 = cvt(_T_1157)
node _T_1159 = and(_T_1158, asSInt(UInt<18>(0h2f000)))
node _T_1160 = asSInt(_T_1159)
node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0)))
node _T_1162 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1163 = cvt(_T_1162)
node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000)))
node _T_1165 = asSInt(_T_1164)
node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0)))
node _T_1167 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1168 = cvt(_T_1167)
node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000)))
node _T_1170 = asSInt(_T_1169)
node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0)))
node _T_1172 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1173 = cvt(_T_1172)
node _T_1174 = and(_T_1173, asSInt(UInt<17>(0h10000)))
node _T_1175 = asSInt(_T_1174)
node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0)))
node _T_1177 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1178 = cvt(_T_1177)
node _T_1179 = and(_T_1178, asSInt(UInt<27>(0h4000000)))
node _T_1180 = asSInt(_T_1179)
node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0)))
node _T_1182 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1183 = cvt(_T_1182)
node _T_1184 = and(_T_1183, asSInt(UInt<13>(0h1000)))
node _T_1185 = asSInt(_T_1184)
node _T_1186 = eq(_T_1185, asSInt(UInt<1>(0h0)))
node _T_1187 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1188 = cvt(_T_1187)
node _T_1189 = and(_T_1188, asSInt(UInt<29>(0h10000000)))
node _T_1190 = asSInt(_T_1189)
node _T_1191 = eq(_T_1190, asSInt(UInt<1>(0h0)))
node _T_1192 = or(_T_1146, _T_1151)
node _T_1193 = or(_T_1192, _T_1156)
node _T_1194 = or(_T_1193, _T_1161)
node _T_1195 = or(_T_1194, _T_1166)
node _T_1196 = or(_T_1195, _T_1171)
node _T_1197 = or(_T_1196, _T_1176)
node _T_1198 = or(_T_1197, _T_1181)
node _T_1199 = or(_T_1198, _T_1186)
node _T_1200 = or(_T_1199, _T_1191)
node _T_1201 = and(_T_1141, _T_1200)
node _T_1202 = or(UInt<1>(0h0), _T_1201)
node _T_1203 = and(_WIRE_5, _T_1202)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(address_ok, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(legal_source, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1216 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90
node _T_1220 = eq(io.in.b.bits.mask, mask_1)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91
node _T_1224 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92
node _T_1228 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1228 :
node _T_1229 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1230 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1231 = and(_T_1229, _T_1230)
node _T_1232 = or(UInt<1>(0h0), _T_1231)
node _T_1233 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1234 = cvt(_T_1233)
node _T_1235 = and(_T_1234, asSInt(UInt<14>(0h2000)))
node _T_1236 = asSInt(_T_1235)
node _T_1237 = eq(_T_1236, asSInt(UInt<1>(0h0)))
node _T_1238 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1239 = cvt(_T_1238)
node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000)))
node _T_1241 = asSInt(_T_1240)
node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0)))
node _T_1243 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1244 = cvt(_T_1243)
node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000)))
node _T_1246 = asSInt(_T_1245)
node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0)))
node _T_1248 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1249 = cvt(_T_1248)
node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000)))
node _T_1251 = asSInt(_T_1250)
node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0)))
node _T_1253 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1254 = cvt(_T_1253)
node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000)))
node _T_1256 = asSInt(_T_1255)
node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0)))
node _T_1258 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1259 = cvt(_T_1258)
node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000)))
node _T_1261 = asSInt(_T_1260)
node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0)))
node _T_1263 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1264 = cvt(_T_1263)
node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000)))
node _T_1266 = asSInt(_T_1265)
node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0)))
node _T_1268 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1269 = cvt(_T_1268)
node _T_1270 = and(_T_1269, asSInt(UInt<27>(0h4000000)))
node _T_1271 = asSInt(_T_1270)
node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0)))
node _T_1273 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1274 = cvt(_T_1273)
node _T_1275 = and(_T_1274, asSInt(UInt<13>(0h1000)))
node _T_1276 = asSInt(_T_1275)
node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0)))
node _T_1278 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1279 = cvt(_T_1278)
node _T_1280 = and(_T_1279, asSInt(UInt<29>(0h10000000)))
node _T_1281 = asSInt(_T_1280)
node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0)))
node _T_1283 = or(_T_1237, _T_1242)
node _T_1284 = or(_T_1283, _T_1247)
node _T_1285 = or(_T_1284, _T_1252)
node _T_1286 = or(_T_1285, _T_1257)
node _T_1287 = or(_T_1286, _T_1262)
node _T_1288 = or(_T_1287, _T_1267)
node _T_1289 = or(_T_1288, _T_1272)
node _T_1290 = or(_T_1289, _T_1277)
node _T_1291 = or(_T_1290, _T_1282)
node _T_1292 = and(_T_1232, _T_1291)
node _T_1293 = or(UInt<1>(0h0), _T_1292)
node _T_1294 = and(UInt<1>(0h0), _T_1293)
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_93
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(address_ok, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(legal_source, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1307 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_97
node _T_1311 = eq(io.in.b.bits.mask, mask_1)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_98
node _T_1315 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_99
node _T_1319 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1321 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1322 = and(_T_1320, _T_1321)
node _T_1323 = or(UInt<1>(0h0), _T_1322)
node _T_1324 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1325 = cvt(_T_1324)
node _T_1326 = and(_T_1325, asSInt(UInt<14>(0h2000)))
node _T_1327 = asSInt(_T_1326)
node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0)))
node _T_1329 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1330 = cvt(_T_1329)
node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000)))
node _T_1332 = asSInt(_T_1331)
node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0)))
node _T_1334 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1335 = cvt(_T_1334)
node _T_1336 = and(_T_1335, asSInt(UInt<17>(0h10000)))
node _T_1337 = asSInt(_T_1336)
node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0)))
node _T_1339 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1340 = cvt(_T_1339)
node _T_1341 = and(_T_1340, asSInt(UInt<18>(0h2f000)))
node _T_1342 = asSInt(_T_1341)
node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0)))
node _T_1344 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1345 = cvt(_T_1344)
node _T_1346 = and(_T_1345, asSInt(UInt<17>(0h10000)))
node _T_1347 = asSInt(_T_1346)
node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0)))
node _T_1349 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1350 = cvt(_T_1349)
node _T_1351 = and(_T_1350, asSInt(UInt<13>(0h1000)))
node _T_1352 = asSInt(_T_1351)
node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0)))
node _T_1354 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1355 = cvt(_T_1354)
node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000)))
node _T_1357 = asSInt(_T_1356)
node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0)))
node _T_1359 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1360 = cvt(_T_1359)
node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000)))
node _T_1362 = asSInt(_T_1361)
node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0)))
node _T_1364 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1365 = cvt(_T_1364)
node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000)))
node _T_1367 = asSInt(_T_1366)
node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0)))
node _T_1369 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1370 = cvt(_T_1369)
node _T_1371 = and(_T_1370, asSInt(UInt<29>(0h10000000)))
node _T_1372 = asSInt(_T_1371)
node _T_1373 = eq(_T_1372, asSInt(UInt<1>(0h0)))
node _T_1374 = or(_T_1328, _T_1333)
node _T_1375 = or(_T_1374, _T_1338)
node _T_1376 = or(_T_1375, _T_1343)
node _T_1377 = or(_T_1376, _T_1348)
node _T_1378 = or(_T_1377, _T_1353)
node _T_1379 = or(_T_1378, _T_1358)
node _T_1380 = or(_T_1379, _T_1363)
node _T_1381 = or(_T_1380, _T_1368)
node _T_1382 = or(_T_1381, _T_1373)
node _T_1383 = and(_T_1323, _T_1382)
node _T_1384 = or(UInt<1>(0h0), _T_1383)
node _T_1385 = and(UInt<1>(0h0), _T_1384)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_100
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(address_ok, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(legal_source, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1395 = asUInt(reset)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
when _T_1396 :
node _T_1397 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1398 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_104
node _T_1402 = eq(io.in.b.bits.mask, mask_1)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_105
node _T_1406 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1406 :
node _T_1407 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1408 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1409 = and(_T_1407, _T_1408)
node _T_1410 = or(UInt<1>(0h0), _T_1409)
node _T_1411 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<14>(0h2000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1422 = cvt(_T_1421)
node _T_1423 = and(_T_1422, asSInt(UInt<17>(0h10000)))
node _T_1424 = asSInt(_T_1423)
node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0)))
node _T_1426 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1427 = cvt(_T_1426)
node _T_1428 = and(_T_1427, asSInt(UInt<18>(0h2f000)))
node _T_1429 = asSInt(_T_1428)
node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0)))
node _T_1431 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1432 = cvt(_T_1431)
node _T_1433 = and(_T_1432, asSInt(UInt<17>(0h10000)))
node _T_1434 = asSInt(_T_1433)
node _T_1435 = eq(_T_1434, asSInt(UInt<1>(0h0)))
node _T_1436 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1437 = cvt(_T_1436)
node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000)))
node _T_1439 = asSInt(_T_1438)
node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0)))
node _T_1441 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1442 = cvt(_T_1441)
node _T_1443 = and(_T_1442, asSInt(UInt<17>(0h10000)))
node _T_1444 = asSInt(_T_1443)
node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0)))
node _T_1446 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1447 = cvt(_T_1446)
node _T_1448 = and(_T_1447, asSInt(UInt<27>(0h4000000)))
node _T_1449 = asSInt(_T_1448)
node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0)))
node _T_1451 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1452 = cvt(_T_1451)
node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000)))
node _T_1454 = asSInt(_T_1453)
node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0)))
node _T_1456 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1457 = cvt(_T_1456)
node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000)))
node _T_1459 = asSInt(_T_1458)
node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0)))
node _T_1461 = or(_T_1415, _T_1420)
node _T_1462 = or(_T_1461, _T_1425)
node _T_1463 = or(_T_1462, _T_1430)
node _T_1464 = or(_T_1463, _T_1435)
node _T_1465 = or(_T_1464, _T_1440)
node _T_1466 = or(_T_1465, _T_1445)
node _T_1467 = or(_T_1466, _T_1450)
node _T_1468 = or(_T_1467, _T_1455)
node _T_1469 = or(_T_1468, _T_1460)
node _T_1470 = and(_T_1410, _T_1469)
node _T_1471 = or(UInt<1>(0h0), _T_1470)
node _T_1472 = and(UInt<1>(0h0), _T_1471)
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_106
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(address_ok, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(legal_source, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1485 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_110
node _T_1489 = not(mask_1)
node _T_1490 = and(io.in.b.bits.mask, _T_1489)
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111
node _T_1495 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1495 :
node _T_1496 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1497 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1498 = and(_T_1496, _T_1497)
node _T_1499 = or(UInt<1>(0h0), _T_1498)
node _T_1500 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1501 = cvt(_T_1500)
node _T_1502 = and(_T_1501, asSInt(UInt<14>(0h2000)))
node _T_1503 = asSInt(_T_1502)
node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0)))
node _T_1505 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1506 = cvt(_T_1505)
node _T_1507 = and(_T_1506, asSInt(UInt<13>(0h1000)))
node _T_1508 = asSInt(_T_1507)
node _T_1509 = eq(_T_1508, asSInt(UInt<1>(0h0)))
node _T_1510 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1511 = cvt(_T_1510)
node _T_1512 = and(_T_1511, asSInt(UInt<17>(0h10000)))
node _T_1513 = asSInt(_T_1512)
node _T_1514 = eq(_T_1513, asSInt(UInt<1>(0h0)))
node _T_1515 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1516 = cvt(_T_1515)
node _T_1517 = and(_T_1516, asSInt(UInt<18>(0h2f000)))
node _T_1518 = asSInt(_T_1517)
node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0)))
node _T_1520 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1521 = cvt(_T_1520)
node _T_1522 = and(_T_1521, asSInt(UInt<17>(0h10000)))
node _T_1523 = asSInt(_T_1522)
node _T_1524 = eq(_T_1523, asSInt(UInt<1>(0h0)))
node _T_1525 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1526 = cvt(_T_1525)
node _T_1527 = and(_T_1526, asSInt(UInt<13>(0h1000)))
node _T_1528 = asSInt(_T_1527)
node _T_1529 = eq(_T_1528, asSInt(UInt<1>(0h0)))
node _T_1530 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1531 = cvt(_T_1530)
node _T_1532 = and(_T_1531, asSInt(UInt<17>(0h10000)))
node _T_1533 = asSInt(_T_1532)
node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0)))
node _T_1535 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1536 = cvt(_T_1535)
node _T_1537 = and(_T_1536, asSInt(UInt<27>(0h4000000)))
node _T_1538 = asSInt(_T_1537)
node _T_1539 = eq(_T_1538, asSInt(UInt<1>(0h0)))
node _T_1540 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1541 = cvt(_T_1540)
node _T_1542 = and(_T_1541, asSInt(UInt<13>(0h1000)))
node _T_1543 = asSInt(_T_1542)
node _T_1544 = eq(_T_1543, asSInt(UInt<1>(0h0)))
node _T_1545 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1546 = cvt(_T_1545)
node _T_1547 = and(_T_1546, asSInt(UInt<29>(0h10000000)))
node _T_1548 = asSInt(_T_1547)
node _T_1549 = eq(_T_1548, asSInt(UInt<1>(0h0)))
node _T_1550 = or(_T_1504, _T_1509)
node _T_1551 = or(_T_1550, _T_1514)
node _T_1552 = or(_T_1551, _T_1519)
node _T_1553 = or(_T_1552, _T_1524)
node _T_1554 = or(_T_1553, _T_1529)
node _T_1555 = or(_T_1554, _T_1534)
node _T_1556 = or(_T_1555, _T_1539)
node _T_1557 = or(_T_1556, _T_1544)
node _T_1558 = or(_T_1557, _T_1549)
node _T_1559 = and(_T_1499, _T_1558)
node _T_1560 = or(UInt<1>(0h0), _T_1559)
node _T_1561 = and(UInt<1>(0h0), _T_1560)
node _T_1562 = asUInt(reset)
node _T_1563 = eq(_T_1562, UInt<1>(0h0))
when _T_1563 :
node _T_1564 = eq(_T_1561, UInt<1>(0h0))
when _T_1564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1561, UInt<1>(0h1), "") : assert_112
node _T_1565 = asUInt(reset)
node _T_1566 = eq(_T_1565, UInt<1>(0h0))
when _T_1566 :
node _T_1567 = eq(address_ok, UInt<1>(0h0))
when _T_1567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(legal_source, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1571 = asUInt(reset)
node _T_1572 = eq(_T_1571, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1574 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(_T_1574, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1574, UInt<1>(0h1), "") : assert_116
node _T_1578 = eq(io.in.b.bits.mask, mask_1)
node _T_1579 = asUInt(reset)
node _T_1580 = eq(_T_1579, UInt<1>(0h0))
when _T_1580 :
node _T_1581 = eq(_T_1578, UInt<1>(0h0))
when _T_1581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1578, UInt<1>(0h1), "") : assert_117
node _T_1582 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1582 :
node _T_1583 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1584 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1585 = and(_T_1583, _T_1584)
node _T_1586 = or(UInt<1>(0h0), _T_1585)
node _T_1587 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1588 = cvt(_T_1587)
node _T_1589 = and(_T_1588, asSInt(UInt<14>(0h2000)))
node _T_1590 = asSInt(_T_1589)
node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0)))
node _T_1592 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1593 = cvt(_T_1592)
node _T_1594 = and(_T_1593, asSInt(UInt<13>(0h1000)))
node _T_1595 = asSInt(_T_1594)
node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0)))
node _T_1597 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1598 = cvt(_T_1597)
node _T_1599 = and(_T_1598, asSInt(UInt<17>(0h10000)))
node _T_1600 = asSInt(_T_1599)
node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0)))
node _T_1602 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1603 = cvt(_T_1602)
node _T_1604 = and(_T_1603, asSInt(UInt<18>(0h2f000)))
node _T_1605 = asSInt(_T_1604)
node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0)))
node _T_1607 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1608 = cvt(_T_1607)
node _T_1609 = and(_T_1608, asSInt(UInt<17>(0h10000)))
node _T_1610 = asSInt(_T_1609)
node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0)))
node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1613 = cvt(_T_1612)
node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000)))
node _T_1615 = asSInt(_T_1614)
node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0)))
node _T_1617 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1618 = cvt(_T_1617)
node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000)))
node _T_1620 = asSInt(_T_1619)
node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0)))
node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1623 = cvt(_T_1622)
node _T_1624 = and(_T_1623, asSInt(UInt<27>(0h4000000)))
node _T_1625 = asSInt(_T_1624)
node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0)))
node _T_1627 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1628 = cvt(_T_1627)
node _T_1629 = and(_T_1628, asSInt(UInt<13>(0h1000)))
node _T_1630 = asSInt(_T_1629)
node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0)))
node _T_1632 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1633 = cvt(_T_1632)
node _T_1634 = and(_T_1633, asSInt(UInt<29>(0h10000000)))
node _T_1635 = asSInt(_T_1634)
node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0)))
node _T_1637 = or(_T_1591, _T_1596)
node _T_1638 = or(_T_1637, _T_1601)
node _T_1639 = or(_T_1638, _T_1606)
node _T_1640 = or(_T_1639, _T_1611)
node _T_1641 = or(_T_1640, _T_1616)
node _T_1642 = or(_T_1641, _T_1621)
node _T_1643 = or(_T_1642, _T_1626)
node _T_1644 = or(_T_1643, _T_1631)
node _T_1645 = or(_T_1644, _T_1636)
node _T_1646 = and(_T_1586, _T_1645)
node _T_1647 = or(UInt<1>(0h0), _T_1646)
node _T_1648 = and(UInt<1>(0h0), _T_1647)
node _T_1649 = asUInt(reset)
node _T_1650 = eq(_T_1649, UInt<1>(0h0))
when _T_1650 :
node _T_1651 = eq(_T_1648, UInt<1>(0h0))
when _T_1651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1648, UInt<1>(0h1), "") : assert_118
node _T_1652 = asUInt(reset)
node _T_1653 = eq(_T_1652, UInt<1>(0h0))
when _T_1653 :
node _T_1654 = eq(address_ok, UInt<1>(0h0))
when _T_1654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(legal_source, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1658 = asUInt(reset)
node _T_1659 = eq(_T_1658, UInt<1>(0h0))
when _T_1659 :
node _T_1660 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1661 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1662 = asUInt(reset)
node _T_1663 = eq(_T_1662, UInt<1>(0h0))
when _T_1663 :
node _T_1664 = eq(_T_1661, UInt<1>(0h0))
when _T_1664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1661, UInt<1>(0h1), "") : assert_122
node _T_1665 = eq(io.in.b.bits.mask, mask_1)
node _T_1666 = asUInt(reset)
node _T_1667 = eq(_T_1666, UInt<1>(0h0))
when _T_1667 :
node _T_1668 = eq(_T_1665, UInt<1>(0h0))
when _T_1668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1665, UInt<1>(0h1), "") : assert_123
node _T_1669 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1669 :
node _T_1670 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1671 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1672 = and(_T_1670, _T_1671)
node _T_1673 = or(UInt<1>(0h0), _T_1672)
node _T_1674 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1675 = cvt(_T_1674)
node _T_1676 = and(_T_1675, asSInt(UInt<14>(0h2000)))
node _T_1677 = asSInt(_T_1676)
node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0)))
node _T_1679 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1680 = cvt(_T_1679)
node _T_1681 = and(_T_1680, asSInt(UInt<13>(0h1000)))
node _T_1682 = asSInt(_T_1681)
node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0)))
node _T_1684 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1685 = cvt(_T_1684)
node _T_1686 = and(_T_1685, asSInt(UInt<17>(0h10000)))
node _T_1687 = asSInt(_T_1686)
node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0)))
node _T_1689 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1690 = cvt(_T_1689)
node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000)))
node _T_1692 = asSInt(_T_1691)
node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0)))
node _T_1694 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1695 = cvt(_T_1694)
node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000)))
node _T_1697 = asSInt(_T_1696)
node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0)))
node _T_1699 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1700 = cvt(_T_1699)
node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000)))
node _T_1702 = asSInt(_T_1701)
node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0)))
node _T_1704 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1705 = cvt(_T_1704)
node _T_1706 = and(_T_1705, asSInt(UInt<17>(0h10000)))
node _T_1707 = asSInt(_T_1706)
node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0)))
node _T_1709 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1710 = cvt(_T_1709)
node _T_1711 = and(_T_1710, asSInt(UInt<27>(0h4000000)))
node _T_1712 = asSInt(_T_1711)
node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0)))
node _T_1714 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1715 = cvt(_T_1714)
node _T_1716 = and(_T_1715, asSInt(UInt<13>(0h1000)))
node _T_1717 = asSInt(_T_1716)
node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0)))
node _T_1719 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1720 = cvt(_T_1719)
node _T_1721 = and(_T_1720, asSInt(UInt<29>(0h10000000)))
node _T_1722 = asSInt(_T_1721)
node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0)))
node _T_1724 = or(_T_1678, _T_1683)
node _T_1725 = or(_T_1724, _T_1688)
node _T_1726 = or(_T_1725, _T_1693)
node _T_1727 = or(_T_1726, _T_1698)
node _T_1728 = or(_T_1727, _T_1703)
node _T_1729 = or(_T_1728, _T_1708)
node _T_1730 = or(_T_1729, _T_1713)
node _T_1731 = or(_T_1730, _T_1718)
node _T_1732 = or(_T_1731, _T_1723)
node _T_1733 = and(_T_1673, _T_1732)
node _T_1734 = or(UInt<1>(0h0), _T_1733)
node _T_1735 = and(UInt<1>(0h0), _T_1734)
node _T_1736 = asUInt(reset)
node _T_1737 = eq(_T_1736, UInt<1>(0h0))
when _T_1737 :
node _T_1738 = eq(_T_1735, UInt<1>(0h0))
when _T_1738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1735, UInt<1>(0h1), "") : assert_124
node _T_1739 = asUInt(reset)
node _T_1740 = eq(_T_1739, UInt<1>(0h0))
when _T_1740 :
node _T_1741 = eq(address_ok, UInt<1>(0h0))
when _T_1741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1742 = asUInt(reset)
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
when _T_1743 :
node _T_1744 = eq(legal_source, UInt<1>(0h0))
when _T_1744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1745 = asUInt(reset)
node _T_1746 = eq(_T_1745, UInt<1>(0h0))
when _T_1746 :
node _T_1747 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1748 = eq(io.in.b.bits.mask, mask_1)
node _T_1749 = asUInt(reset)
node _T_1750 = eq(_T_1749, UInt<1>(0h0))
when _T_1750 :
node _T_1751 = eq(_T_1748, UInt<1>(0h0))
when _T_1751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1748, UInt<1>(0h1), "") : assert_128
node _T_1752 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1753 = asUInt(reset)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
when _T_1754 :
node _T_1755 = eq(_T_1752, UInt<1>(0h0))
when _T_1755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1752, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1756 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_130
node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_2 : UInt<1>[2]
connect _source_ok_WIRE_2[0], _source_ok_T_4
connect _source_ok_WIRE_2[1], _source_ok_T_5
node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _T_1760 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1763 = cvt(_T_1762)
node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0)))
node _T_1765 = asSInt(_T_1764)
node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0)))
node _T_1767 = or(_T_1761, _T_1766)
node _T_1768 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1769 = eq(_T_1768, UInt<1>(0h0))
node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1771 = cvt(_T_1770)
node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0)))
node _T_1773 = asSInt(_T_1772)
node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0)))
node _T_1775 = or(_T_1769, _T_1774)
node _T_1776 = and(_T_1767, _T_1775)
node _T_1777 = asUInt(reset)
node _T_1778 = eq(_T_1777, UInt<1>(0h0))
when _T_1778 :
node _T_1779 = eq(_T_1776, UInt<1>(0h0))
when _T_1779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1776, UInt<1>(0h1), "") : assert_131
node _T_1780 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1780 :
node _T_1781 = asUInt(reset)
node _T_1782 = eq(_T_1781, UInt<1>(0h0))
when _T_1782 :
node _T_1783 = eq(address_ok_1, UInt<1>(0h0))
when _T_1783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1784 = asUInt(reset)
node _T_1785 = eq(_T_1784, UInt<1>(0h0))
when _T_1785 :
node _T_1786 = eq(source_ok_2, UInt<1>(0h0))
when _T_1786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1787 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(_T_1787, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1787, UInt<1>(0h1), "") : assert_134
node _T_1791 = asUInt(reset)
node _T_1792 = eq(_T_1791, UInt<1>(0h0))
when _T_1792 :
node _T_1793 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1794 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1795 = asUInt(reset)
node _T_1796 = eq(_T_1795, UInt<1>(0h0))
when _T_1796 :
node _T_1797 = eq(_T_1794, UInt<1>(0h0))
when _T_1797 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1794, UInt<1>(0h1), "") : assert_136
node _T_1798 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1799 = asUInt(reset)
node _T_1800 = eq(_T_1799, UInt<1>(0h0))
when _T_1800 :
node _T_1801 = eq(_T_1798, UInt<1>(0h0))
when _T_1801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1798, UInt<1>(0h1), "") : assert_137
node _T_1802 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1802 :
node _T_1803 = asUInt(reset)
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
when _T_1804 :
node _T_1805 = eq(address_ok_1, UInt<1>(0h0))
when _T_1805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1806 = asUInt(reset)
node _T_1807 = eq(_T_1806, UInt<1>(0h0))
when _T_1807 :
node _T_1808 = eq(source_ok_2, UInt<1>(0h0))
when _T_1808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1809 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1810 = asUInt(reset)
node _T_1811 = eq(_T_1810, UInt<1>(0h0))
when _T_1811 :
node _T_1812 = eq(_T_1809, UInt<1>(0h0))
when _T_1812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1809, UInt<1>(0h1), "") : assert_140
node _T_1813 = asUInt(reset)
node _T_1814 = eq(_T_1813, UInt<1>(0h0))
when _T_1814 :
node _T_1815 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1816 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1817 = asUInt(reset)
node _T_1818 = eq(_T_1817, UInt<1>(0h0))
when _T_1818 :
node _T_1819 = eq(_T_1816, UInt<1>(0h0))
when _T_1819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1816, UInt<1>(0h1), "") : assert_142
node _T_1820 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1820 :
node _T_1821 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1822 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1823 = and(_T_1821, _T_1822)
node _T_1824 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1825 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1826 = or(_T_1824, _T_1825)
node _T_1827 = and(_T_1823, _T_1826)
node _T_1828 = or(UInt<1>(0h0), _T_1827)
node _T_1829 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1830 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1831 = cvt(_T_1830)
node _T_1832 = and(_T_1831, asSInt(UInt<14>(0h2000)))
node _T_1833 = asSInt(_T_1832)
node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0)))
node _T_1835 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1836 = cvt(_T_1835)
node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000)))
node _T_1838 = asSInt(_T_1837)
node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0)))
node _T_1840 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1841 = cvt(_T_1840)
node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000)))
node _T_1843 = asSInt(_T_1842)
node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0)))
node _T_1845 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1846 = cvt(_T_1845)
node _T_1847 = and(_T_1846, asSInt(UInt<18>(0h2f000)))
node _T_1848 = asSInt(_T_1847)
node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0)))
node _T_1850 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1851 = cvt(_T_1850)
node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000)))
node _T_1853 = asSInt(_T_1852)
node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0)))
node _T_1855 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1856 = cvt(_T_1855)
node _T_1857 = and(_T_1856, asSInt(UInt<13>(0h1000)))
node _T_1858 = asSInt(_T_1857)
node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0)))
node _T_1860 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1861 = cvt(_T_1860)
node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000)))
node _T_1863 = asSInt(_T_1862)
node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0)))
node _T_1865 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1866 = cvt(_T_1865)
node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000)))
node _T_1868 = asSInt(_T_1867)
node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0)))
node _T_1870 = or(_T_1834, _T_1839)
node _T_1871 = or(_T_1870, _T_1844)
node _T_1872 = or(_T_1871, _T_1849)
node _T_1873 = or(_T_1872, _T_1854)
node _T_1874 = or(_T_1873, _T_1859)
node _T_1875 = or(_T_1874, _T_1864)
node _T_1876 = or(_T_1875, _T_1869)
node _T_1877 = and(_T_1829, _T_1876)
node _T_1878 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1879 = or(UInt<1>(0h0), _T_1878)
node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1881 = cvt(_T_1880)
node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000)))
node _T_1883 = asSInt(_T_1882)
node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0)))
node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1886 = cvt(_T_1885)
node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000)))
node _T_1888 = asSInt(_T_1887)
node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0)))
node _T_1890 = or(_T_1884, _T_1889)
node _T_1891 = and(_T_1879, _T_1890)
node _T_1892 = or(UInt<1>(0h0), _T_1877)
node _T_1893 = or(_T_1892, _T_1891)
node _T_1894 = and(_T_1828, _T_1893)
node _T_1895 = asUInt(reset)
node _T_1896 = eq(_T_1895, UInt<1>(0h0))
when _T_1896 :
node _T_1897 = eq(_T_1894, UInt<1>(0h0))
when _T_1897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1894, UInt<1>(0h1), "") : assert_143
node _T_1898 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1899 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_6 : UInt<1>[2]
connect _WIRE_6[0], _T_1898
connect _WIRE_6[1], _T_1899
node _T_1900 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1901 = mux(_WIRE_6[0], _T_1900, UInt<1>(0h0))
node _T_1902 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1903 = or(_T_1901, _T_1902)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1903
node _T_1904 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1905 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1906 = and(_T_1904, _T_1905)
node _T_1907 = or(UInt<1>(0h0), _T_1906)
node _T_1908 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1909 = cvt(_T_1908)
node _T_1910 = and(_T_1909, asSInt(UInt<14>(0h2000)))
node _T_1911 = asSInt(_T_1910)
node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0)))
node _T_1913 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1914 = cvt(_T_1913)
node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000)))
node _T_1916 = asSInt(_T_1915)
node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0)))
node _T_1918 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1919 = cvt(_T_1918)
node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000)))
node _T_1921 = asSInt(_T_1920)
node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0)))
node _T_1923 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1924 = cvt(_T_1923)
node _T_1925 = and(_T_1924, asSInt(UInt<18>(0h2f000)))
node _T_1926 = asSInt(_T_1925)
node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0)))
node _T_1928 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1929 = cvt(_T_1928)
node _T_1930 = and(_T_1929, asSInt(UInt<17>(0h10000)))
node _T_1931 = asSInt(_T_1930)
node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0)))
node _T_1933 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1934 = cvt(_T_1933)
node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000)))
node _T_1936 = asSInt(_T_1935)
node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0)))
node _T_1938 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1939 = cvt(_T_1938)
node _T_1940 = and(_T_1939, asSInt(UInt<17>(0h10000)))
node _T_1941 = asSInt(_T_1940)
node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0)))
node _T_1943 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1944 = cvt(_T_1943)
node _T_1945 = and(_T_1944, asSInt(UInt<27>(0h4000000)))
node _T_1946 = asSInt(_T_1945)
node _T_1947 = eq(_T_1946, asSInt(UInt<1>(0h0)))
node _T_1948 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1949 = cvt(_T_1948)
node _T_1950 = and(_T_1949, asSInt(UInt<13>(0h1000)))
node _T_1951 = asSInt(_T_1950)
node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0)))
node _T_1953 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1954 = cvt(_T_1953)
node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000)))
node _T_1956 = asSInt(_T_1955)
node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0)))
node _T_1958 = or(_T_1912, _T_1917)
node _T_1959 = or(_T_1958, _T_1922)
node _T_1960 = or(_T_1959, _T_1927)
node _T_1961 = or(_T_1960, _T_1932)
node _T_1962 = or(_T_1961, _T_1937)
node _T_1963 = or(_T_1962, _T_1942)
node _T_1964 = or(_T_1963, _T_1947)
node _T_1965 = or(_T_1964, _T_1952)
node _T_1966 = or(_T_1965, _T_1957)
node _T_1967 = and(_T_1907, _T_1966)
node _T_1968 = or(UInt<1>(0h0), _T_1967)
node _T_1969 = and(_WIRE_7, _T_1968)
node _T_1970 = asUInt(reset)
node _T_1971 = eq(_T_1970, UInt<1>(0h0))
when _T_1971 :
node _T_1972 = eq(_T_1969, UInt<1>(0h0))
when _T_1972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1969, UInt<1>(0h1), "") : assert_144
node _T_1973 = asUInt(reset)
node _T_1974 = eq(_T_1973, UInt<1>(0h0))
when _T_1974 :
node _T_1975 = eq(source_ok_2, UInt<1>(0h0))
when _T_1975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1976 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1977 = asUInt(reset)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
when _T_1978 :
node _T_1979 = eq(_T_1976, UInt<1>(0h0))
when _T_1979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1976, UInt<1>(0h1), "") : assert_146
node _T_1980 = asUInt(reset)
node _T_1981 = eq(_T_1980, UInt<1>(0h0))
when _T_1981 :
node _T_1982 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1983 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1984 = asUInt(reset)
node _T_1985 = eq(_T_1984, UInt<1>(0h0))
when _T_1985 :
node _T_1986 = eq(_T_1983, UInt<1>(0h0))
when _T_1986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1983, UInt<1>(0h1), "") : assert_148
node _T_1987 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1988 = asUInt(reset)
node _T_1989 = eq(_T_1988, UInt<1>(0h0))
when _T_1989 :
node _T_1990 = eq(_T_1987, UInt<1>(0h0))
when _T_1990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1987, UInt<1>(0h1), "") : assert_149
node _T_1991 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1991 :
node _T_1992 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1993 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1994 = and(_T_1992, _T_1993)
node _T_1995 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1996 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1997 = or(_T_1995, _T_1996)
node _T_1998 = and(_T_1994, _T_1997)
node _T_1999 = or(UInt<1>(0h0), _T_1998)
node _T_2000 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2001 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2002 = cvt(_T_2001)
node _T_2003 = and(_T_2002, asSInt(UInt<14>(0h2000)))
node _T_2004 = asSInt(_T_2003)
node _T_2005 = eq(_T_2004, asSInt(UInt<1>(0h0)))
node _T_2006 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2007 = cvt(_T_2006)
node _T_2008 = and(_T_2007, asSInt(UInt<13>(0h1000)))
node _T_2009 = asSInt(_T_2008)
node _T_2010 = eq(_T_2009, asSInt(UInt<1>(0h0)))
node _T_2011 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2012 = cvt(_T_2011)
node _T_2013 = and(_T_2012, asSInt(UInt<17>(0h10000)))
node _T_2014 = asSInt(_T_2013)
node _T_2015 = eq(_T_2014, asSInt(UInt<1>(0h0)))
node _T_2016 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2017 = cvt(_T_2016)
node _T_2018 = and(_T_2017, asSInt(UInt<18>(0h2f000)))
node _T_2019 = asSInt(_T_2018)
node _T_2020 = eq(_T_2019, asSInt(UInt<1>(0h0)))
node _T_2021 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2022 = cvt(_T_2021)
node _T_2023 = and(_T_2022, asSInt(UInt<17>(0h10000)))
node _T_2024 = asSInt(_T_2023)
node _T_2025 = eq(_T_2024, asSInt(UInt<1>(0h0)))
node _T_2026 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2027 = cvt(_T_2026)
node _T_2028 = and(_T_2027, asSInt(UInt<13>(0h1000)))
node _T_2029 = asSInt(_T_2028)
node _T_2030 = eq(_T_2029, asSInt(UInt<1>(0h0)))
node _T_2031 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2032 = cvt(_T_2031)
node _T_2033 = and(_T_2032, asSInt(UInt<27>(0h4000000)))
node _T_2034 = asSInt(_T_2033)
node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0)))
node _T_2036 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2037 = cvt(_T_2036)
node _T_2038 = and(_T_2037, asSInt(UInt<13>(0h1000)))
node _T_2039 = asSInt(_T_2038)
node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0)))
node _T_2041 = or(_T_2005, _T_2010)
node _T_2042 = or(_T_2041, _T_2015)
node _T_2043 = or(_T_2042, _T_2020)
node _T_2044 = or(_T_2043, _T_2025)
node _T_2045 = or(_T_2044, _T_2030)
node _T_2046 = or(_T_2045, _T_2035)
node _T_2047 = or(_T_2046, _T_2040)
node _T_2048 = and(_T_2000, _T_2047)
node _T_2049 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2050 = or(UInt<1>(0h0), _T_2049)
node _T_2051 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2052 = cvt(_T_2051)
node _T_2053 = and(_T_2052, asSInt(UInt<17>(0h10000)))
node _T_2054 = asSInt(_T_2053)
node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0)))
node _T_2056 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2057 = cvt(_T_2056)
node _T_2058 = and(_T_2057, asSInt(UInt<29>(0h10000000)))
node _T_2059 = asSInt(_T_2058)
node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0)))
node _T_2061 = or(_T_2055, _T_2060)
node _T_2062 = and(_T_2050, _T_2061)
node _T_2063 = or(UInt<1>(0h0), _T_2048)
node _T_2064 = or(_T_2063, _T_2062)
node _T_2065 = and(_T_1999, _T_2064)
node _T_2066 = asUInt(reset)
node _T_2067 = eq(_T_2066, UInt<1>(0h0))
when _T_2067 :
node _T_2068 = eq(_T_2065, UInt<1>(0h0))
when _T_2068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2065, UInt<1>(0h1), "") : assert_150
node _T_2069 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2070 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_8 : UInt<1>[2]
connect _WIRE_8[0], _T_2069
connect _WIRE_8[1], _T_2070
node _T_2071 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2072 = mux(_WIRE_8[0], _T_2071, UInt<1>(0h0))
node _T_2073 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2074 = or(_T_2072, _T_2073)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2074
node _T_2075 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2076 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2077 = and(_T_2075, _T_2076)
node _T_2078 = or(UInt<1>(0h0), _T_2077)
node _T_2079 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2080 = cvt(_T_2079)
node _T_2081 = and(_T_2080, asSInt(UInt<14>(0h2000)))
node _T_2082 = asSInt(_T_2081)
node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0)))
node _T_2084 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2085 = cvt(_T_2084)
node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000)))
node _T_2087 = asSInt(_T_2086)
node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0)))
node _T_2089 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2090 = cvt(_T_2089)
node _T_2091 = and(_T_2090, asSInt(UInt<17>(0h10000)))
node _T_2092 = asSInt(_T_2091)
node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0)))
node _T_2094 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2095 = cvt(_T_2094)
node _T_2096 = and(_T_2095, asSInt(UInt<18>(0h2f000)))
node _T_2097 = asSInt(_T_2096)
node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0)))
node _T_2099 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2100 = cvt(_T_2099)
node _T_2101 = and(_T_2100, asSInt(UInt<17>(0h10000)))
node _T_2102 = asSInt(_T_2101)
node _T_2103 = eq(_T_2102, asSInt(UInt<1>(0h0)))
node _T_2104 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2105 = cvt(_T_2104)
node _T_2106 = and(_T_2105, asSInt(UInt<13>(0h1000)))
node _T_2107 = asSInt(_T_2106)
node _T_2108 = eq(_T_2107, asSInt(UInt<1>(0h0)))
node _T_2109 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2110 = cvt(_T_2109)
node _T_2111 = and(_T_2110, asSInt(UInt<17>(0h10000)))
node _T_2112 = asSInt(_T_2111)
node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0)))
node _T_2114 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2115 = cvt(_T_2114)
node _T_2116 = and(_T_2115, asSInt(UInt<27>(0h4000000)))
node _T_2117 = asSInt(_T_2116)
node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0)))
node _T_2119 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2120 = cvt(_T_2119)
node _T_2121 = and(_T_2120, asSInt(UInt<13>(0h1000)))
node _T_2122 = asSInt(_T_2121)
node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0)))
node _T_2124 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2125 = cvt(_T_2124)
node _T_2126 = and(_T_2125, asSInt(UInt<29>(0h10000000)))
node _T_2127 = asSInt(_T_2126)
node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0)))
node _T_2129 = or(_T_2083, _T_2088)
node _T_2130 = or(_T_2129, _T_2093)
node _T_2131 = or(_T_2130, _T_2098)
node _T_2132 = or(_T_2131, _T_2103)
node _T_2133 = or(_T_2132, _T_2108)
node _T_2134 = or(_T_2133, _T_2113)
node _T_2135 = or(_T_2134, _T_2118)
node _T_2136 = or(_T_2135, _T_2123)
node _T_2137 = or(_T_2136, _T_2128)
node _T_2138 = and(_T_2078, _T_2137)
node _T_2139 = or(UInt<1>(0h0), _T_2138)
node _T_2140 = and(_WIRE_9, _T_2139)
node _T_2141 = asUInt(reset)
node _T_2142 = eq(_T_2141, UInt<1>(0h0))
when _T_2142 :
node _T_2143 = eq(_T_2140, UInt<1>(0h0))
when _T_2143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2140, UInt<1>(0h1), "") : assert_151
node _T_2144 = asUInt(reset)
node _T_2145 = eq(_T_2144, UInt<1>(0h0))
when _T_2145 :
node _T_2146 = eq(source_ok_2, UInt<1>(0h0))
when _T_2146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2147 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2148 = asUInt(reset)
node _T_2149 = eq(_T_2148, UInt<1>(0h0))
when _T_2149 :
node _T_2150 = eq(_T_2147, UInt<1>(0h0))
when _T_2150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2147, UInt<1>(0h1), "") : assert_153
node _T_2151 = asUInt(reset)
node _T_2152 = eq(_T_2151, UInt<1>(0h0))
when _T_2152 :
node _T_2153 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2154 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2155 = asUInt(reset)
node _T_2156 = eq(_T_2155, UInt<1>(0h0))
when _T_2156 :
node _T_2157 = eq(_T_2154, UInt<1>(0h0))
when _T_2157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2154, UInt<1>(0h1), "") : assert_155
node _T_2158 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2158 :
node _T_2159 = asUInt(reset)
node _T_2160 = eq(_T_2159, UInt<1>(0h0))
when _T_2160 :
node _T_2161 = eq(address_ok_1, UInt<1>(0h0))
when _T_2161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2162 = asUInt(reset)
node _T_2163 = eq(_T_2162, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = eq(source_ok_2, UInt<1>(0h0))
when _T_2164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2165 = asUInt(reset)
node _T_2166 = eq(_T_2165, UInt<1>(0h0))
when _T_2166 :
node _T_2167 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2168 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2169 = asUInt(reset)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
when _T_2170 :
node _T_2171 = eq(_T_2168, UInt<1>(0h0))
when _T_2171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2168, UInt<1>(0h1), "") : assert_159
node _T_2172 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2173 = asUInt(reset)
node _T_2174 = eq(_T_2173, UInt<1>(0h0))
when _T_2174 :
node _T_2175 = eq(_T_2172, UInt<1>(0h0))
when _T_2175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2172, UInt<1>(0h1), "") : assert_160
node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2176 :
node _T_2177 = asUInt(reset)
node _T_2178 = eq(_T_2177, UInt<1>(0h0))
when _T_2178 :
node _T_2179 = eq(address_ok_1, UInt<1>(0h0))
when _T_2179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2180 = asUInt(reset)
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
when _T_2181 :
node _T_2182 = eq(source_ok_2, UInt<1>(0h0))
when _T_2182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2183 = asUInt(reset)
node _T_2184 = eq(_T_2183, UInt<1>(0h0))
when _T_2184 :
node _T_2185 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2187 = asUInt(reset)
node _T_2188 = eq(_T_2187, UInt<1>(0h0))
when _T_2188 :
node _T_2189 = eq(_T_2186, UInt<1>(0h0))
when _T_2189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2186, UInt<1>(0h1), "") : assert_164
node _T_2190 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2190 :
node _T_2191 = asUInt(reset)
node _T_2192 = eq(_T_2191, UInt<1>(0h0))
when _T_2192 :
node _T_2193 = eq(address_ok_1, UInt<1>(0h0))
when _T_2193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2194 = asUInt(reset)
node _T_2195 = eq(_T_2194, UInt<1>(0h0))
when _T_2195 :
node _T_2196 = eq(source_ok_2, UInt<1>(0h0))
when _T_2196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2197 = asUInt(reset)
node _T_2198 = eq(_T_2197, UInt<1>(0h0))
when _T_2198 :
node _T_2199 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2200 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2201 = asUInt(reset)
node _T_2202 = eq(_T_2201, UInt<1>(0h0))
when _T_2202 :
node _T_2203 = eq(_T_2200, UInt<1>(0h0))
when _T_2203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2200, UInt<1>(0h1), "") : assert_168
node _T_2204 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2205 = asUInt(reset)
node _T_2206 = eq(_T_2205, UInt<1>(0h0))
when _T_2206 :
node _T_2207 = eq(_T_2204, UInt<1>(0h0))
when _T_2207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2204, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2208 = asUInt(reset)
node _T_2209 = eq(_T_2208, UInt<1>(0h0))
when _T_2209 :
node _T_2210 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2211 = eq(a_first, UInt<1>(0h0))
node _T_2212 = and(io.in.a.valid, _T_2211)
when _T_2212 :
node _T_2213 = eq(io.in.a.bits.opcode, opcode)
node _T_2214 = asUInt(reset)
node _T_2215 = eq(_T_2214, UInt<1>(0h0))
when _T_2215 :
node _T_2216 = eq(_T_2213, UInt<1>(0h0))
when _T_2216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2213, UInt<1>(0h1), "") : assert_171
node _T_2217 = eq(io.in.a.bits.param, param)
node _T_2218 = asUInt(reset)
node _T_2219 = eq(_T_2218, UInt<1>(0h0))
when _T_2219 :
node _T_2220 = eq(_T_2217, UInt<1>(0h0))
when _T_2220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2217, UInt<1>(0h1), "") : assert_172
node _T_2221 = eq(io.in.a.bits.size, size)
node _T_2222 = asUInt(reset)
node _T_2223 = eq(_T_2222, UInt<1>(0h0))
when _T_2223 :
node _T_2224 = eq(_T_2221, UInt<1>(0h0))
when _T_2224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2221, UInt<1>(0h1), "") : assert_173
node _T_2225 = eq(io.in.a.bits.source, source)
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
node _T_2228 = eq(_T_2225, UInt<1>(0h0))
when _T_2228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2225, UInt<1>(0h1), "") : assert_174
node _T_2229 = eq(io.in.a.bits.address, address)
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
node _T_2232 = eq(_T_2229, UInt<1>(0h0))
when _T_2232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2229, UInt<1>(0h1), "") : assert_175
node _T_2233 = and(io.in.a.ready, io.in.a.valid)
node _T_2234 = and(_T_2233, a_first)
when _T_2234 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2235 = eq(d_first, UInt<1>(0h0))
node _T_2236 = and(io.in.d.valid, _T_2235)
when _T_2236 :
node _T_2237 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2238 = asUInt(reset)
node _T_2239 = eq(_T_2238, UInt<1>(0h0))
when _T_2239 :
node _T_2240 = eq(_T_2237, UInt<1>(0h0))
when _T_2240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2237, UInt<1>(0h1), "") : assert_176
node _T_2241 = eq(io.in.d.bits.param, param_1)
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
node _T_2244 = eq(_T_2241, UInt<1>(0h0))
when _T_2244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2241, UInt<1>(0h1), "") : assert_177
node _T_2245 = eq(io.in.d.bits.size, size_1)
node _T_2246 = asUInt(reset)
node _T_2247 = eq(_T_2246, UInt<1>(0h0))
when _T_2247 :
node _T_2248 = eq(_T_2245, UInt<1>(0h0))
when _T_2248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2245, UInt<1>(0h1), "") : assert_178
node _T_2249 = eq(io.in.d.bits.source, source_1)
node _T_2250 = asUInt(reset)
node _T_2251 = eq(_T_2250, UInt<1>(0h0))
when _T_2251 :
node _T_2252 = eq(_T_2249, UInt<1>(0h0))
when _T_2252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2249, UInt<1>(0h1), "") : assert_179
node _T_2253 = eq(io.in.d.bits.sink, sink)
node _T_2254 = asUInt(reset)
node _T_2255 = eq(_T_2254, UInt<1>(0h0))
when _T_2255 :
node _T_2256 = eq(_T_2253, UInt<1>(0h0))
when _T_2256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2253, UInt<1>(0h1), "") : assert_180
node _T_2257 = eq(io.in.d.bits.denied, denied)
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
node _T_2260 = eq(_T_2257, UInt<1>(0h0))
when _T_2260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2257, UInt<1>(0h1), "") : assert_181
node _T_2261 = and(io.in.d.ready, io.in.d.valid)
node _T_2262 = and(_T_2261, d_first)
when _T_2262 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2263 = eq(b_first, UInt<1>(0h0))
node _T_2264 = and(io.in.b.valid, _T_2263)
when _T_2264 :
node _T_2265 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2266 = asUInt(reset)
node _T_2267 = eq(_T_2266, UInt<1>(0h0))
when _T_2267 :
node _T_2268 = eq(_T_2265, UInt<1>(0h0))
when _T_2268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2265, UInt<1>(0h1), "") : assert_182
node _T_2269 = eq(io.in.b.bits.param, param_2)
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
node _T_2272 = eq(_T_2269, UInt<1>(0h0))
when _T_2272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2269, UInt<1>(0h1), "") : assert_183
node _T_2273 = eq(io.in.b.bits.size, size_2)
node _T_2274 = asUInt(reset)
node _T_2275 = eq(_T_2274, UInt<1>(0h0))
when _T_2275 :
node _T_2276 = eq(_T_2273, UInt<1>(0h0))
when _T_2276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2273, UInt<1>(0h1), "") : assert_184
node _T_2277 = eq(io.in.b.bits.source, source_2)
node _T_2278 = asUInt(reset)
node _T_2279 = eq(_T_2278, UInt<1>(0h0))
when _T_2279 :
node _T_2280 = eq(_T_2277, UInt<1>(0h0))
when _T_2280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2277, UInt<1>(0h1), "") : assert_185
node _T_2281 = eq(io.in.b.bits.address, address_1)
node _T_2282 = asUInt(reset)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
node _T_2284 = eq(_T_2281, UInt<1>(0h0))
when _T_2284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2281, UInt<1>(0h1), "") : assert_186
node _T_2285 = and(io.in.b.ready, io.in.b.valid)
node _T_2286 = and(_T_2285, b_first)
when _T_2286 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2287 = eq(c_first, UInt<1>(0h0))
node _T_2288 = and(io.in.c.valid, _T_2287)
when _T_2288 :
node _T_2289 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2290 = asUInt(reset)
node _T_2291 = eq(_T_2290, UInt<1>(0h0))
when _T_2291 :
node _T_2292 = eq(_T_2289, UInt<1>(0h0))
when _T_2292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2289, UInt<1>(0h1), "") : assert_187
node _T_2293 = eq(io.in.c.bits.param, param_3)
node _T_2294 = asUInt(reset)
node _T_2295 = eq(_T_2294, UInt<1>(0h0))
when _T_2295 :
node _T_2296 = eq(_T_2293, UInt<1>(0h0))
when _T_2296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2293, UInt<1>(0h1), "") : assert_188
node _T_2297 = eq(io.in.c.bits.size, size_3)
node _T_2298 = asUInt(reset)
node _T_2299 = eq(_T_2298, UInt<1>(0h0))
when _T_2299 :
node _T_2300 = eq(_T_2297, UInt<1>(0h0))
when _T_2300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2297, UInt<1>(0h1), "") : assert_189
node _T_2301 = eq(io.in.c.bits.source, source_3)
node _T_2302 = asUInt(reset)
node _T_2303 = eq(_T_2302, UInt<1>(0h0))
when _T_2303 :
node _T_2304 = eq(_T_2301, UInt<1>(0h0))
when _T_2304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2301, UInt<1>(0h1), "") : assert_190
node _T_2305 = eq(io.in.c.bits.address, address_2)
node _T_2306 = asUInt(reset)
node _T_2307 = eq(_T_2306, UInt<1>(0h0))
when _T_2307 :
node _T_2308 = eq(_T_2305, UInt<1>(0h0))
when _T_2308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2305, UInt<1>(0h1), "") : assert_191
node _T_2309 = and(io.in.c.ready, io.in.c.valid)
node _T_2310 = and(_T_2309, c_first)
when _T_2310 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2>
connect a_set, UInt<2>(0h0)
wire a_set_wo_ready : UInt<2>
connect a_set_wo_ready, UInt<2>(0h0)
wire a_opcodes_set : UInt<8>
connect a_opcodes_set, UInt<8>(0h0)
wire a_sizes_set : UInt<16>
connect a_sizes_set, UInt<16>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2311 = and(io.in.a.valid, a_first_1)
node _T_2312 = and(_T_2311, UInt<1>(0h1))
when _T_2312 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2313 = and(io.in.a.ready, io.in.a.valid)
node _T_2314 = and(_T_2313, a_first_1)
node _T_2315 = and(_T_2314, UInt<1>(0h1))
when _T_2315 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2316 = dshr(inflight, io.in.a.bits.source)
node _T_2317 = bits(_T_2316, 0, 0)
node _T_2318 = eq(_T_2317, UInt<1>(0h0))
node _T_2319 = asUInt(reset)
node _T_2320 = eq(_T_2319, UInt<1>(0h0))
when _T_2320 :
node _T_2321 = eq(_T_2318, UInt<1>(0h0))
when _T_2321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2318, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<2>
connect d_clr, UInt<2>(0h0)
wire d_clr_wo_ready : UInt<2>
connect d_clr_wo_ready, UInt<2>(0h0)
wire d_opcodes_clr : UInt<8>
connect d_opcodes_clr, UInt<8>(0h0)
wire d_sizes_clr : UInt<16>
connect d_sizes_clr, UInt<16>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2322 = and(io.in.d.valid, d_first_1)
node _T_2323 = and(_T_2322, UInt<1>(0h1))
node _T_2324 = eq(d_release_ack, UInt<1>(0h0))
node _T_2325 = and(_T_2323, _T_2324)
when _T_2325 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2326 = and(io.in.d.ready, io.in.d.valid)
node _T_2327 = and(_T_2326, d_first_1)
node _T_2328 = and(_T_2327, UInt<1>(0h1))
node _T_2329 = eq(d_release_ack, UInt<1>(0h0))
node _T_2330 = and(_T_2328, _T_2329)
when _T_2330 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2331 = and(io.in.d.valid, d_first_1)
node _T_2332 = and(_T_2331, UInt<1>(0h1))
node _T_2333 = eq(d_release_ack, UInt<1>(0h0))
node _T_2334 = and(_T_2332, _T_2333)
when _T_2334 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2335 = dshr(inflight, io.in.d.bits.source)
node _T_2336 = bits(_T_2335, 0, 0)
node _T_2337 = or(_T_2336, same_cycle_resp)
node _T_2338 = asUInt(reset)
node _T_2339 = eq(_T_2338, UInt<1>(0h0))
when _T_2339 :
node _T_2340 = eq(_T_2337, UInt<1>(0h0))
when _T_2340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2337, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2341 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2342 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2343 = or(_T_2341, _T_2342)
node _T_2344 = asUInt(reset)
node _T_2345 = eq(_T_2344, UInt<1>(0h0))
when _T_2345 :
node _T_2346 = eq(_T_2343, UInt<1>(0h0))
when _T_2346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2343, UInt<1>(0h1), "") : assert_194
node _T_2347 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2348 = asUInt(reset)
node _T_2349 = eq(_T_2348, UInt<1>(0h0))
when _T_2349 :
node _T_2350 = eq(_T_2347, UInt<1>(0h0))
when _T_2350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2347, UInt<1>(0h1), "") : assert_195
else :
node _T_2351 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2352 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2353 = or(_T_2351, _T_2352)
node _T_2354 = asUInt(reset)
node _T_2355 = eq(_T_2354, UInt<1>(0h0))
when _T_2355 :
node _T_2356 = eq(_T_2353, UInt<1>(0h0))
when _T_2356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2353, UInt<1>(0h1), "") : assert_196
node _T_2357 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2358 = asUInt(reset)
node _T_2359 = eq(_T_2358, UInt<1>(0h0))
when _T_2359 :
node _T_2360 = eq(_T_2357, UInt<1>(0h0))
when _T_2360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2357, UInt<1>(0h1), "") : assert_197
node _T_2361 = and(io.in.d.valid, d_first_1)
node _T_2362 = and(_T_2361, a_first_1)
node _T_2363 = and(_T_2362, io.in.a.valid)
node _T_2364 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2365 = and(_T_2363, _T_2364)
node _T_2366 = eq(d_release_ack, UInt<1>(0h0))
node _T_2367 = and(_T_2365, _T_2366)
when _T_2367 :
node _T_2368 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2369 = or(_T_2368, io.in.a.ready)
node _T_2370 = asUInt(reset)
node _T_2371 = eq(_T_2370, UInt<1>(0h0))
when _T_2371 :
node _T_2372 = eq(_T_2369, UInt<1>(0h0))
when _T_2372 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2369, UInt<1>(0h1), "") : assert_198
node _T_2373 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2374 = orr(a_set_wo_ready)
node _T_2375 = eq(_T_2374, UInt<1>(0h0))
node _T_2376 = or(_T_2373, _T_2375)
node _T_2377 = asUInt(reset)
node _T_2378 = eq(_T_2377, UInt<1>(0h0))
when _T_2378 :
node _T_2379 = eq(_T_2376, UInt<1>(0h0))
when _T_2379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2376, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_78
node _T_2380 = orr(inflight)
node _T_2381 = eq(_T_2380, UInt<1>(0h0))
node _T_2382 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2383 = or(_T_2381, _T_2382)
node _T_2384 = lt(watchdog, plusarg_reader.out)
node _T_2385 = or(_T_2383, _T_2384)
node _T_2386 = asUInt(reset)
node _T_2387 = eq(_T_2386, UInt<1>(0h0))
when _T_2387 :
node _T_2388 = eq(_T_2385, UInt<1>(0h0))
when _T_2388 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2385, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2389 = and(io.in.a.ready, io.in.a.valid)
node _T_2390 = and(io.in.d.ready, io.in.d.valid)
node _T_2391 = or(_T_2389, _T_2390)
when _T_2391 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2>
connect c_set, UInt<2>(0h0)
wire c_set_wo_ready : UInt<2>
connect c_set_wo_ready, UInt<2>(0h0)
wire c_opcodes_set : UInt<8>
connect c_opcodes_set, UInt<8>(0h0)
wire c_sizes_set : UInt<16>
connect c_sizes_set, UInt<16>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2392 = and(io.in.c.valid, c_first_1)
node _T_2393 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2394 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2395 = and(_T_2393, _T_2394)
node _T_2396 = and(_T_2392, _T_2395)
when _T_2396 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2397 = and(io.in.c.ready, io.in.c.valid)
node _T_2398 = and(_T_2397, c_first_1)
node _T_2399 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2400 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2401 = and(_T_2399, _T_2400)
node _T_2402 = and(_T_2398, _T_2401)
when _T_2402 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2403 = dshr(inflight_1, io.in.c.bits.source)
node _T_2404 = bits(_T_2403, 0, 0)
node _T_2405 = eq(_T_2404, UInt<1>(0h0))
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2>
connect d_clr_1, UInt<2>(0h0)
wire d_clr_wo_ready_1 : UInt<2>
connect d_clr_wo_ready_1, UInt<2>(0h0)
wire d_opcodes_clr_1 : UInt<8>
connect d_opcodes_clr_1, UInt<8>(0h0)
wire d_sizes_clr_1 : UInt<16>
connect d_sizes_clr_1, UInt<16>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2409 = and(io.in.d.valid, d_first_2)
node _T_2410 = and(_T_2409, UInt<1>(0h1))
node _T_2411 = and(_T_2410, d_release_ack_1)
when _T_2411 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2412 = and(io.in.d.ready, io.in.d.valid)
node _T_2413 = and(_T_2412, d_first_2)
node _T_2414 = and(_T_2413, UInt<1>(0h1))
node _T_2415 = and(_T_2414, d_release_ack_1)
when _T_2415 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2416 = and(io.in.d.valid, d_first_2)
node _T_2417 = and(_T_2416, UInt<1>(0h1))
node _T_2418 = and(_T_2417, d_release_ack_1)
when _T_2418 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2419 = dshr(inflight_1, io.in.d.bits.source)
node _T_2420 = bits(_T_2419, 0, 0)
node _T_2421 = or(_T_2420, same_cycle_resp_1)
node _T_2422 = asUInt(reset)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
when _T_2423 :
node _T_2424 = eq(_T_2421, UInt<1>(0h0))
when _T_2424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2421, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2425 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2426 = asUInt(reset)
node _T_2427 = eq(_T_2426, UInt<1>(0h0))
when _T_2427 :
node _T_2428 = eq(_T_2425, UInt<1>(0h0))
when _T_2428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2425, UInt<1>(0h1), "") : assert_203
else :
node _T_2429 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2430 = asUInt(reset)
node _T_2431 = eq(_T_2430, UInt<1>(0h0))
when _T_2431 :
node _T_2432 = eq(_T_2429, UInt<1>(0h0))
when _T_2432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2429, UInt<1>(0h1), "") : assert_204
node _T_2433 = and(io.in.d.valid, d_first_2)
node _T_2434 = and(_T_2433, c_first_1)
node _T_2435 = and(_T_2434, io.in.c.valid)
node _T_2436 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2437 = and(_T_2435, _T_2436)
node _T_2438 = and(_T_2437, d_release_ack_1)
node _T_2439 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2440 = and(_T_2438, _T_2439)
when _T_2440 :
node _T_2441 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2442 = or(_T_2441, io.in.c.ready)
node _T_2443 = asUInt(reset)
node _T_2444 = eq(_T_2443, UInt<1>(0h0))
when _T_2444 :
node _T_2445 = eq(_T_2442, UInt<1>(0h0))
when _T_2445 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2442, UInt<1>(0h1), "") : assert_205
node _T_2446 = orr(c_set_wo_ready)
when _T_2446 :
node _T_2447 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2448 = asUInt(reset)
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
when _T_2449 :
node _T_2450 = eq(_T_2447, UInt<1>(0h0))
when _T_2450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2447, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_79
node _T_2451 = orr(inflight_1)
node _T_2452 = eq(_T_2451, UInt<1>(0h0))
node _T_2453 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2454 = or(_T_2452, _T_2453)
node _T_2455 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2456 = or(_T_2454, _T_2455)
node _T_2457 = asUInt(reset)
node _T_2458 = eq(_T_2457, UInt<1>(0h0))
when _T_2458 :
node _T_2459 = eq(_T_2456, UInt<1>(0h0))
when _T_2459 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2456, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2460 = and(io.in.c.ready, io.in.c.valid)
node _T_2461 = and(io.in.d.ready, io.in.d.valid)
node _T_2462 = or(_T_2460, _T_2461)
when _T_2462 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2463 = and(io.in.d.ready, io.in.d.valid)
node _T_2464 = and(_T_2463, d_first_3)
node _T_2465 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2466 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2467 = eq(_T_2466, UInt<1>(0h0))
node _T_2468 = and(_T_2465, _T_2467)
node _T_2469 = and(_T_2464, _T_2468)
when _T_2469 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2470 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2471 = bits(_T_2470, 0, 0)
node _T_2472 = eq(_T_2471, UInt<1>(0h0))
node _T_2473 = asUInt(reset)
node _T_2474 = eq(_T_2473, UInt<1>(0h0))
when _T_2474 :
node _T_2475 = eq(_T_2472, UInt<1>(0h0))
when _T_2475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2472, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2476 = and(io.in.e.ready, io.in.e.valid)
node _T_2477 = and(_T_2476, UInt<1>(0h1))
node _T_2478 = and(_T_2477, UInt<1>(0h1))
when _T_2478 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2479 = or(d_set, inflight_2)
node _T_2480 = dshr(_T_2479, io.in.e.bits.sink)
node _T_2481 = bits(_T_2480, 0, 0)
node _T_2482 = asUInt(reset)
node _T_2483 = eq(_T_2482, UInt<1>(0h0))
when _T_2483 :
node _T_2484 = eq(_T_2481, UInt<1>(0h0))
when _T_2484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2481, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_80 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_81 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_39( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7]
wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34]
wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71]
assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71]
assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10]
wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31]
wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73]
wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73]
wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire _T_2389 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2389; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2389; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2463 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2463; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2463; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2463; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2463; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2460 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2460; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2460; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [15:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [1:0] a_set; // @[Monitor.scala:626:34]
wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [15:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99]
wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2315 = _T_2389 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2315 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2315 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2315 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2315 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_2315 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1:0] d_clr; // @[Monitor.scala:664:34]
wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46]
wire _T_2361 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2361 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2330 = _T_2463 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2330 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2330 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2330 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [1:0] c_set; // @[Monitor.scala:738:34]
wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [15:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2402 = _T_2460 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2402 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2402 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2402 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}]
assign c_opcodes_set = _T_2402 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}]
assign c_sizes_set = _T_2402 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [1:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2433 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2433 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire _T_2415 = _T_2463 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2415 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2415 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2415 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2469 = _T_2463 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35]
assign d_set = _T_2469 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2478 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35]
assign e_clr = _T_2478 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module DivUnit :
input clock : Clock
input reset : Reset
output io : { flip kill : UInt<1>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, ftq_info : { valid : UInt<1>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>}[2], pred_data : UInt<1>, imm_data : UInt<64>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}}
connect io.resp.bits.fflags.valid, UInt<1>(0h0)
invalidate io.resp.bits.fflags.bits
connect io.resp.bits.predicated, UInt<1>(0h0)
inst div of MulDiv
connect div.clock, clock
connect div.reset, reset
reg req : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock
node _T = and(io.req.ready, io.req.valid)
when _T :
node _req_valid_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _req_valid_T_1 = neq(_req_valid_T, UInt<1>(0h0))
node _req_valid_T_2 = or(_req_valid_T_1, io.kill)
node _req_valid_T_3 = eq(_req_valid_T_2, UInt<1>(0h0))
connect req.valid, _req_valid_T_3
wire req_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect req_bits_out, io.req.bits.uop
node _req_bits_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _req_bits_out_br_mask_T_1 = and(io.req.bits.uop.br_mask, _req_bits_out_br_mask_T)
connect req_bits_out.br_mask, _req_bits_out_br_mask_T_1
connect req.bits, req_bits_out
else :
node _req_valid_T_4 = and(io.brupdate.b1.mispredict_mask, req.bits.br_mask)
node _req_valid_T_5 = neq(_req_valid_T_4, UInt<1>(0h0))
node _req_valid_T_6 = or(_req_valid_T_5, io.kill)
node _req_valid_T_7 = eq(_req_valid_T_6, UInt<1>(0h0))
node _req_valid_T_8 = and(_req_valid_T_7, req.valid)
connect req.valid, _req_valid_T_8
wire req_bits_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect req_bits_out_1, req.bits
node _req_bits_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _req_bits_out_br_mask_T_3 = and(req.bits.br_mask, _req_bits_out_br_mask_T_2)
connect req_bits_out_1.br_mask, _req_bits_out_br_mask_T_3
connect req.bits, req_bits_out_1
node _T_1 = asUInt(reset)
when _T_1 :
connect req.valid, UInt<1>(0h0)
node _div_io_req_valid_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _div_io_req_valid_T_1 = neq(_div_io_req_valid_T, UInt<1>(0h0))
node _div_io_req_valid_T_2 = or(_div_io_req_valid_T_1, io.kill)
node _div_io_req_valid_T_3 = eq(_div_io_req_valid_T_2, UInt<1>(0h0))
node _div_io_req_valid_T_4 = and(io.req.valid, _div_io_req_valid_T_3)
connect div.io.req.valid, _div_io_req_valid_T_4
connect div.io.req.bits.dw, io.req.bits.uop.fcn_dw
connect div.io.req.bits.fn, io.req.bits.uop.fcn_op
connect div.io.req.bits.in1, io.req.bits.rs1_data
connect div.io.req.bits.in2, io.req.bits.rs2_data
invalidate div.io.req.bits.tag
node _io_req_ready_T = eq(req.valid, UInt<1>(0h0))
node _io_req_ready_T_1 = and(div.io.req.ready, _io_req_ready_T)
connect io.req.ready, _io_req_ready_T_1
node _div_io_kill_T = and(io.brupdate.b1.mispredict_mask, req.bits.br_mask)
node _div_io_kill_T_1 = neq(_div_io_kill_T, UInt<1>(0h0))
node _div_io_kill_T_2 = or(_div_io_kill_T_1, io.kill)
node _div_io_kill_T_3 = and(req.valid, _div_io_kill_T_2)
connect div.io.kill, _div_io_kill_T_3
node _io_resp_valid_T = and(div.io.resp.valid, req.valid)
connect io.resp.valid, _io_resp_valid_T
connect div.io.resp.ready, io.resp.ready
node _io_resp_valid_T_1 = and(div.io.resp.valid, req.valid)
connect io.resp.valid, _io_resp_valid_T_1
connect io.resp.bits.data, div.io.resp.bits.data
connect io.resp.bits.uop, req.bits
node _T_2 = and(io.resp.ready, io.resp.valid)
when _T_2 :
connect req.valid, UInt<1>(0h0) | module DivUnit( // @[functional-unit.scala:393:7]
input clock, // @[functional-unit.scala:393:7]
input reset, // @[functional-unit.scala:393:7]
input io_kill, // @[functional-unit.scala:105:14]
output io_req_ready, // @[functional-unit.scala:105:14]
input io_req_valid, // @[functional-unit.scala:105:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14]
input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14]
input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14]
input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14]
input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:105:14]
input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14]
input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14]
input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14]
input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14]
input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14]
input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14]
input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14]
input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14]
input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:105:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14]
input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14]
input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14]
input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14]
input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14]
input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14]
input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14]
input io_resp_ready, // @[functional-unit.scala:105:14]
output io_resp_valid, // @[functional-unit.scala:105:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14]
output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14]
output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14]
output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14]
output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14]
output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14]
output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14]
output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14]
output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14]
output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14]
output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14]
output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14]
output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14]
output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14]
output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14]
output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14]
output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14]
output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:105:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14]
input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:105:14]
);
wire _div_io_req_ready; // @[functional-unit.scala:399:19]
wire _div_io_resp_valid; // @[functional-unit.scala:399:19]
wire io_kill_0 = io_kill; // @[functional-unit.scala:393:7]
wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:393:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:393:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:393:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:393:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:393:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:393:7]
wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:393:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:393:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:393:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:393:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:393:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:393:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:393:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:393:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:393:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:393:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:393:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:393:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:393:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:393:7]
wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:393:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:393:7]
wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:393:7]
wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:393:7]
wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:393:7]
wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:393:7]
wire io_resp_ready_0 = io_resp_ready; // @[functional-unit.scala:393:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:393:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:393:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:393:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:393:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:393:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:393:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:393:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:393:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:393:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:393:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:393:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:393:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:393:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:393:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:393:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:393:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:393:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:393:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:393:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:393:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:393:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:393:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:393:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:393:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:393:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:393:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:393:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:393:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:393:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:393:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:393:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:393:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[functional-unit.scala:393:7]
wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:393:7]
wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[functional-unit.scala:105:14, :393:7]
wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[functional-unit.scala:105:14, :393:7]
wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[functional-unit.scala:105:14, :393:7]
wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[functional-unit.scala:105:14, :393:7]
wire [7:0] io_req_bits_ftq_info_0_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :393:7]
wire [7:0] io_req_bits_ftq_info_1_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :393:7]
wire [2:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:105:14, :393:7]
wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[functional-unit.scala:105:14, :393:7]
wire [2:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:105:14, :393:7]
wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[functional-unit.scala:105:14, :393:7]
wire io_req_bits_ftq_info_0_valid = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_valid = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:393:7]
wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:393:7]
wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:393:7]
wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:393:7]
wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:105:14, :393:7]
wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:105:14, :393:7]
wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:105:14, :393:7]
wire _io_req_ready_T_1; // @[functional-unit.scala:421:43]
wire [31:0] req_bits_out_inst = io_req_bits_uop_inst_0; // @[util.scala:104:23]
wire [31:0] req_bits_out_debug_inst = io_req_bits_uop_debug_inst_0; // @[util.scala:104:23]
wire req_bits_out_is_rvc = io_req_bits_uop_is_rvc_0; // @[util.scala:104:23]
wire [39:0] req_bits_out_debug_pc = io_req_bits_uop_debug_pc_0; // @[util.scala:104:23]
wire req_bits_out_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[util.scala:104:23]
wire req_bits_out_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[util.scala:104:23]
wire req_bits_out_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[util.scala:104:23]
wire req_bits_out_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[util.scala:104:23]
wire req_bits_out_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[util.scala:104:23]
wire req_bits_out_iw_issued = io_req_bits_uop_iw_issued_0; // @[util.scala:104:23]
wire req_bits_out_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[util.scala:104:23]
wire req_bits_out_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[util.scala:104:23]
wire req_bits_out_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:104:23]
wire req_bits_out_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:104:23]
wire req_bits_out_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[util.scala:104:23]
wire [3:0] req_bits_out_br_tag = io_req_bits_uop_br_tag_0; // @[util.scala:104:23]
wire [3:0] req_bits_out_br_type = io_req_bits_uop_br_type_0; // @[util.scala:104:23]
wire req_bits_out_is_sfb = io_req_bits_uop_is_sfb_0; // @[util.scala:104:23]
wire req_bits_out_is_fence = io_req_bits_uop_is_fence_0; // @[util.scala:104:23]
wire req_bits_out_is_fencei = io_req_bits_uop_is_fencei_0; // @[util.scala:104:23]
wire req_bits_out_is_sfence = io_req_bits_uop_is_sfence_0; // @[util.scala:104:23]
wire req_bits_out_is_amo = io_req_bits_uop_is_amo_0; // @[util.scala:104:23]
wire req_bits_out_is_eret = io_req_bits_uop_is_eret_0; // @[util.scala:104:23]
wire req_bits_out_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[util.scala:104:23]
wire req_bits_out_is_rocc = io_req_bits_uop_is_rocc_0; // @[util.scala:104:23]
wire req_bits_out_is_mov = io_req_bits_uop_is_mov_0; // @[util.scala:104:23]
wire [4:0] req_bits_out_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[util.scala:104:23]
wire req_bits_out_edge_inst = io_req_bits_uop_edge_inst_0; // @[util.scala:104:23]
wire [5:0] req_bits_out_pc_lob = io_req_bits_uop_pc_lob_0; // @[util.scala:104:23]
wire req_bits_out_taken = io_req_bits_uop_taken_0; // @[util.scala:104:23]
wire req_bits_out_imm_rename = io_req_bits_uop_imm_rename_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_imm_sel = io_req_bits_uop_imm_sel_0; // @[util.scala:104:23]
wire [4:0] req_bits_out_pimm = io_req_bits_uop_pimm_0; // @[util.scala:104:23]
wire [19:0] req_bits_out_imm_packed = io_req_bits_uop_imm_packed_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_op1_sel = io_req_bits_uop_op1_sel_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_op2_sel = io_req_bits_uop_op2_sel_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[util.scala:104:23]
wire req_bits_out_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[util.scala:104:23]
wire [6:0] req_bits_out_rob_idx = io_req_bits_uop_rob_idx_0; // @[util.scala:104:23]
wire [4:0] req_bits_out_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[util.scala:104:23]
wire [4:0] req_bits_out_stq_idx = io_req_bits_uop_stq_idx_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[util.scala:104:23]
wire [6:0] req_bits_out_pdst = io_req_bits_uop_pdst_0; // @[util.scala:104:23]
wire [6:0] req_bits_out_prs1 = io_req_bits_uop_prs1_0; // @[util.scala:104:23]
wire [6:0] req_bits_out_prs2 = io_req_bits_uop_prs2_0; // @[util.scala:104:23]
wire [6:0] req_bits_out_prs3 = io_req_bits_uop_prs3_0; // @[util.scala:104:23]
wire [4:0] req_bits_out_ppred = io_req_bits_uop_ppred_0; // @[util.scala:104:23]
wire req_bits_out_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[util.scala:104:23]
wire req_bits_out_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[util.scala:104:23]
wire req_bits_out_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[util.scala:104:23]
wire req_bits_out_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[util.scala:104:23]
wire [6:0] req_bits_out_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[util.scala:104:23]
wire req_bits_out_exception = io_req_bits_uop_exception_0; // @[util.scala:104:23]
wire [63:0] req_bits_out_exc_cause = io_req_bits_uop_exc_cause_0; // @[util.scala:104:23]
wire [4:0] req_bits_out_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_mem_size = io_req_bits_uop_mem_size_0; // @[util.scala:104:23]
wire req_bits_out_mem_signed = io_req_bits_uop_mem_signed_0; // @[util.scala:104:23]
wire req_bits_out_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[util.scala:104:23]
wire req_bits_out_uses_stq = io_req_bits_uop_uses_stq_0; // @[util.scala:104:23]
wire req_bits_out_is_unique = io_req_bits_uop_is_unique_0; // @[util.scala:104:23]
wire req_bits_out_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[util.scala:104:23]
wire req_bits_out_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[util.scala:104:23]
wire [5:0] req_bits_out_ldst = io_req_bits_uop_ldst_0; // @[util.scala:104:23]
wire [5:0] req_bits_out_lrs1 = io_req_bits_uop_lrs1_0; // @[util.scala:104:23]
wire [5:0] req_bits_out_lrs2 = io_req_bits_uop_lrs2_0; // @[util.scala:104:23]
wire [5:0] req_bits_out_lrs3 = io_req_bits_uop_lrs3_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[util.scala:104:23]
wire req_bits_out_frs3_en = io_req_bits_uop_frs3_en_0; // @[util.scala:104:23]
wire req_bits_out_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[util.scala:104:23]
wire [4:0] req_bits_out_fcn_op = io_req_bits_uop_fcn_op_0; // @[util.scala:104:23]
wire req_bits_out_fp_val = io_req_bits_uop_fp_val_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_fp_rm = io_req_bits_uop_fp_rm_0; // @[util.scala:104:23]
wire [1:0] req_bits_out_fp_typ = io_req_bits_uop_fp_typ_0; // @[util.scala:104:23]
wire req_bits_out_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[util.scala:104:23]
wire req_bits_out_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[util.scala:104:23]
wire req_bits_out_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[util.scala:104:23]
wire req_bits_out_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[util.scala:104:23]
wire req_bits_out_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[util.scala:104:23]
wire [2:0] req_bits_out_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[util.scala:104:23]
wire _io_resp_valid_T_1; // @[functional-unit.scala:429:44]
wire io_req_ready_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:393:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:393:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:393:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:393:7]
wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:393:7]
wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:393:7]
wire [3:0] io_resp_bits_uop_br_type_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:393:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_uop_pimm_0; // @[functional-unit.scala:393:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:393:7]
wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:393:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:393:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:393:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:393:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:393:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:393:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:393:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:393:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:393:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:393:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:393:7]
wire [4:0] io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:393:7]
wire [1:0] io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:393:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:393:7]
wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:393:7]
wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:393:7]
wire io_resp_valid_0; // @[functional-unit.scala:393:7]
reg req_valid; // @[functional-unit.scala:401:16]
reg [31:0] req_bits_inst; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_inst_0 = req_bits_inst; // @[functional-unit.scala:393:7, :401:16]
wire [31:0] req_bits_out_1_inst = req_bits_inst; // @[util.scala:104:23]
reg [31:0] req_bits_debug_inst; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_debug_inst_0 = req_bits_debug_inst; // @[functional-unit.scala:393:7, :401:16]
wire [31:0] req_bits_out_1_debug_inst = req_bits_debug_inst; // @[util.scala:104:23]
reg req_bits_is_rvc; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_rvc_0 = req_bits_is_rvc; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_rvc = req_bits_is_rvc; // @[util.scala:104:23]
reg [39:0] req_bits_debug_pc; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_debug_pc_0 = req_bits_debug_pc; // @[functional-unit.scala:393:7, :401:16]
wire [39:0] req_bits_out_1_debug_pc = req_bits_debug_pc; // @[util.scala:104:23]
reg req_bits_iq_type_0; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iq_type_0_0 = req_bits_iq_type_0; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iq_type_0 = req_bits_iq_type_0; // @[util.scala:104:23]
reg req_bits_iq_type_1; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iq_type_1_0 = req_bits_iq_type_1; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iq_type_1 = req_bits_iq_type_1; // @[util.scala:104:23]
reg req_bits_iq_type_2; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iq_type_2_0 = req_bits_iq_type_2; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iq_type_2 = req_bits_iq_type_2; // @[util.scala:104:23]
reg req_bits_iq_type_3; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iq_type_3_0 = req_bits_iq_type_3; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iq_type_3 = req_bits_iq_type_3; // @[util.scala:104:23]
reg req_bits_fu_code_0; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_0_0 = req_bits_fu_code_0; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_0 = req_bits_fu_code_0; // @[util.scala:104:23]
reg req_bits_fu_code_1; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_1_0 = req_bits_fu_code_1; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_1 = req_bits_fu_code_1; // @[util.scala:104:23]
reg req_bits_fu_code_2; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_2_0 = req_bits_fu_code_2; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_2 = req_bits_fu_code_2; // @[util.scala:104:23]
reg req_bits_fu_code_3; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_3_0 = req_bits_fu_code_3; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_3 = req_bits_fu_code_3; // @[util.scala:104:23]
reg req_bits_fu_code_4; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_4_0 = req_bits_fu_code_4; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_4 = req_bits_fu_code_4; // @[util.scala:104:23]
reg req_bits_fu_code_5; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_5_0 = req_bits_fu_code_5; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_5 = req_bits_fu_code_5; // @[util.scala:104:23]
reg req_bits_fu_code_6; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_6_0 = req_bits_fu_code_6; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_6 = req_bits_fu_code_6; // @[util.scala:104:23]
reg req_bits_fu_code_7; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_7_0 = req_bits_fu_code_7; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_7 = req_bits_fu_code_7; // @[util.scala:104:23]
reg req_bits_fu_code_8; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_8_0 = req_bits_fu_code_8; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_8 = req_bits_fu_code_8; // @[util.scala:104:23]
reg req_bits_fu_code_9; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fu_code_9_0 = req_bits_fu_code_9; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fu_code_9 = req_bits_fu_code_9; // @[util.scala:104:23]
reg req_bits_iw_issued; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_issued_0 = req_bits_iw_issued; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iw_issued = req_bits_iw_issued; // @[util.scala:104:23]
reg req_bits_iw_issued_partial_agen; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_issued_partial_agen_0 = req_bits_iw_issued_partial_agen; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iw_issued_partial_agen = req_bits_iw_issued_partial_agen; // @[util.scala:104:23]
reg req_bits_iw_issued_partial_dgen; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_issued_partial_dgen_0 = req_bits_iw_issued_partial_dgen; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iw_issued_partial_dgen = req_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
reg [2:0] req_bits_iw_p1_speculative_child; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_p1_speculative_child_0 = req_bits_iw_p1_speculative_child; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_iw_p1_speculative_child = req_bits_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] req_bits_iw_p2_speculative_child; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_p2_speculative_child_0 = req_bits_iw_p2_speculative_child; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_iw_p2_speculative_child = req_bits_iw_p2_speculative_child; // @[util.scala:104:23]
reg req_bits_iw_p1_bypass_hint; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_p1_bypass_hint_0 = req_bits_iw_p1_bypass_hint; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iw_p1_bypass_hint = req_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
reg req_bits_iw_p2_bypass_hint; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_p2_bypass_hint_0 = req_bits_iw_p2_bypass_hint; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iw_p2_bypass_hint = req_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
reg req_bits_iw_p3_bypass_hint; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_iw_p3_bypass_hint_0 = req_bits_iw_p3_bypass_hint; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_iw_p3_bypass_hint = req_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] req_bits_dis_col_sel; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_dis_col_sel_0 = req_bits_dis_col_sel; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_dis_col_sel = req_bits_dis_col_sel; // @[util.scala:104:23]
reg [15:0] req_bits_br_mask; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_br_mask_0 = req_bits_br_mask; // @[functional-unit.scala:393:7, :401:16]
reg [3:0] req_bits_br_tag; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_br_tag_0 = req_bits_br_tag; // @[functional-unit.scala:393:7, :401:16]
wire [3:0] req_bits_out_1_br_tag = req_bits_br_tag; // @[util.scala:104:23]
reg [3:0] req_bits_br_type; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_br_type_0 = req_bits_br_type; // @[functional-unit.scala:393:7, :401:16]
wire [3:0] req_bits_out_1_br_type = req_bits_br_type; // @[util.scala:104:23]
reg req_bits_is_sfb; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_sfb_0 = req_bits_is_sfb; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_sfb = req_bits_is_sfb; // @[util.scala:104:23]
reg req_bits_is_fence; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_fence_0 = req_bits_is_fence; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_fence = req_bits_is_fence; // @[util.scala:104:23]
reg req_bits_is_fencei; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_fencei_0 = req_bits_is_fencei; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_fencei = req_bits_is_fencei; // @[util.scala:104:23]
reg req_bits_is_sfence; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_sfence_0 = req_bits_is_sfence; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_sfence = req_bits_is_sfence; // @[util.scala:104:23]
reg req_bits_is_amo; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_amo_0 = req_bits_is_amo; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_amo = req_bits_is_amo; // @[util.scala:104:23]
reg req_bits_is_eret; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_eret_0 = req_bits_is_eret; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_eret = req_bits_is_eret; // @[util.scala:104:23]
reg req_bits_is_sys_pc2epc; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_sys_pc2epc_0 = req_bits_is_sys_pc2epc; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_sys_pc2epc = req_bits_is_sys_pc2epc; // @[util.scala:104:23]
reg req_bits_is_rocc; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_rocc_0 = req_bits_is_rocc; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_rocc = req_bits_is_rocc; // @[util.scala:104:23]
reg req_bits_is_mov; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_mov_0 = req_bits_is_mov; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_mov = req_bits_is_mov; // @[util.scala:104:23]
reg [4:0] req_bits_ftq_idx; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_ftq_idx_0 = req_bits_ftq_idx; // @[functional-unit.scala:393:7, :401:16]
wire [4:0] req_bits_out_1_ftq_idx = req_bits_ftq_idx; // @[util.scala:104:23]
reg req_bits_edge_inst; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_edge_inst_0 = req_bits_edge_inst; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_edge_inst = req_bits_edge_inst; // @[util.scala:104:23]
reg [5:0] req_bits_pc_lob; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_pc_lob_0 = req_bits_pc_lob; // @[functional-unit.scala:393:7, :401:16]
wire [5:0] req_bits_out_1_pc_lob = req_bits_pc_lob; // @[util.scala:104:23]
reg req_bits_taken; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_taken_0 = req_bits_taken; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_taken = req_bits_taken; // @[util.scala:104:23]
reg req_bits_imm_rename; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_imm_rename_0 = req_bits_imm_rename; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_imm_rename = req_bits_imm_rename; // @[util.scala:104:23]
reg [2:0] req_bits_imm_sel; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_imm_sel_0 = req_bits_imm_sel; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_imm_sel = req_bits_imm_sel; // @[util.scala:104:23]
reg [4:0] req_bits_pimm; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_pimm_0 = req_bits_pimm; // @[functional-unit.scala:393:7, :401:16]
wire [4:0] req_bits_out_1_pimm = req_bits_pimm; // @[util.scala:104:23]
reg [19:0] req_bits_imm_packed; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_imm_packed_0 = req_bits_imm_packed; // @[functional-unit.scala:393:7, :401:16]
wire [19:0] req_bits_out_1_imm_packed = req_bits_imm_packed; // @[util.scala:104:23]
reg [1:0] req_bits_op1_sel; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_op1_sel_0 = req_bits_op1_sel; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_op1_sel = req_bits_op1_sel; // @[util.scala:104:23]
reg [2:0] req_bits_op2_sel; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_op2_sel_0 = req_bits_op2_sel; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_op2_sel = req_bits_op2_sel; // @[util.scala:104:23]
reg req_bits_fp_ctrl_ldst; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_ldst_0 = req_bits_fp_ctrl_ldst; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_ldst = req_bits_fp_ctrl_ldst; // @[util.scala:104:23]
reg req_bits_fp_ctrl_wen; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_wen_0 = req_bits_fp_ctrl_wen; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_wen = req_bits_fp_ctrl_wen; // @[util.scala:104:23]
reg req_bits_fp_ctrl_ren1; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_ren1_0 = req_bits_fp_ctrl_ren1; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_ren1 = req_bits_fp_ctrl_ren1; // @[util.scala:104:23]
reg req_bits_fp_ctrl_ren2; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_ren2_0 = req_bits_fp_ctrl_ren2; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_ren2 = req_bits_fp_ctrl_ren2; // @[util.scala:104:23]
reg req_bits_fp_ctrl_ren3; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_ren3_0 = req_bits_fp_ctrl_ren3; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_ren3 = req_bits_fp_ctrl_ren3; // @[util.scala:104:23]
reg req_bits_fp_ctrl_swap12; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_swap12_0 = req_bits_fp_ctrl_swap12; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_swap12 = req_bits_fp_ctrl_swap12; // @[util.scala:104:23]
reg req_bits_fp_ctrl_swap23; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_swap23_0 = req_bits_fp_ctrl_swap23; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_swap23 = req_bits_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] req_bits_fp_ctrl_typeTagIn; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_typeTagIn_0 = req_bits_fp_ctrl_typeTagIn; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_fp_ctrl_typeTagIn = req_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] req_bits_fp_ctrl_typeTagOut; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_typeTagOut_0 = req_bits_fp_ctrl_typeTagOut; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_fp_ctrl_typeTagOut = req_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg req_bits_fp_ctrl_fromint; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_fromint_0 = req_bits_fp_ctrl_fromint; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_fromint = req_bits_fp_ctrl_fromint; // @[util.scala:104:23]
reg req_bits_fp_ctrl_toint; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_toint_0 = req_bits_fp_ctrl_toint; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_toint = req_bits_fp_ctrl_toint; // @[util.scala:104:23]
reg req_bits_fp_ctrl_fastpipe; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_fastpipe_0 = req_bits_fp_ctrl_fastpipe; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_fastpipe = req_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg req_bits_fp_ctrl_fma; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_fma_0 = req_bits_fp_ctrl_fma; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_fma = req_bits_fp_ctrl_fma; // @[util.scala:104:23]
reg req_bits_fp_ctrl_div; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_div_0 = req_bits_fp_ctrl_div; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_div = req_bits_fp_ctrl_div; // @[util.scala:104:23]
reg req_bits_fp_ctrl_sqrt; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_sqrt_0 = req_bits_fp_ctrl_sqrt; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_sqrt = req_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
reg req_bits_fp_ctrl_wflags; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_wflags_0 = req_bits_fp_ctrl_wflags; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_wflags = req_bits_fp_ctrl_wflags; // @[util.scala:104:23]
reg req_bits_fp_ctrl_vec; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_ctrl_vec_0 = req_bits_fp_ctrl_vec; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_ctrl_vec = req_bits_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] req_bits_rob_idx; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_rob_idx_0 = req_bits_rob_idx; // @[functional-unit.scala:393:7, :401:16]
wire [6:0] req_bits_out_1_rob_idx = req_bits_rob_idx; // @[util.scala:104:23]
reg [4:0] req_bits_ldq_idx; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_ldq_idx_0 = req_bits_ldq_idx; // @[functional-unit.scala:393:7, :401:16]
wire [4:0] req_bits_out_1_ldq_idx = req_bits_ldq_idx; // @[util.scala:104:23]
reg [4:0] req_bits_stq_idx; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_stq_idx_0 = req_bits_stq_idx; // @[functional-unit.scala:393:7, :401:16]
wire [4:0] req_bits_out_1_stq_idx = req_bits_stq_idx; // @[util.scala:104:23]
reg [1:0] req_bits_rxq_idx; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_rxq_idx_0 = req_bits_rxq_idx; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_rxq_idx = req_bits_rxq_idx; // @[util.scala:104:23]
reg [6:0] req_bits_pdst; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_pdst_0 = req_bits_pdst; // @[functional-unit.scala:393:7, :401:16]
wire [6:0] req_bits_out_1_pdst = req_bits_pdst; // @[util.scala:104:23]
reg [6:0] req_bits_prs1; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_prs1_0 = req_bits_prs1; // @[functional-unit.scala:393:7, :401:16]
wire [6:0] req_bits_out_1_prs1 = req_bits_prs1; // @[util.scala:104:23]
reg [6:0] req_bits_prs2; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_prs2_0 = req_bits_prs2; // @[functional-unit.scala:393:7, :401:16]
wire [6:0] req_bits_out_1_prs2 = req_bits_prs2; // @[util.scala:104:23]
reg [6:0] req_bits_prs3; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_prs3_0 = req_bits_prs3; // @[functional-unit.scala:393:7, :401:16]
wire [6:0] req_bits_out_1_prs3 = req_bits_prs3; // @[util.scala:104:23]
reg [4:0] req_bits_ppred; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_ppred_0 = req_bits_ppred; // @[functional-unit.scala:393:7, :401:16]
wire [4:0] req_bits_out_1_ppred = req_bits_ppred; // @[util.scala:104:23]
reg req_bits_prs1_busy; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_prs1_busy_0 = req_bits_prs1_busy; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_prs1_busy = req_bits_prs1_busy; // @[util.scala:104:23]
reg req_bits_prs2_busy; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_prs2_busy_0 = req_bits_prs2_busy; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_prs2_busy = req_bits_prs2_busy; // @[util.scala:104:23]
reg req_bits_prs3_busy; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_prs3_busy_0 = req_bits_prs3_busy; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_prs3_busy = req_bits_prs3_busy; // @[util.scala:104:23]
reg req_bits_ppred_busy; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_ppred_busy_0 = req_bits_ppred_busy; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_ppred_busy = req_bits_ppred_busy; // @[util.scala:104:23]
reg [6:0] req_bits_stale_pdst; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_stale_pdst_0 = req_bits_stale_pdst; // @[functional-unit.scala:393:7, :401:16]
wire [6:0] req_bits_out_1_stale_pdst = req_bits_stale_pdst; // @[util.scala:104:23]
reg req_bits_exception; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_exception_0 = req_bits_exception; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_exception = req_bits_exception; // @[util.scala:104:23]
reg [63:0] req_bits_exc_cause; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_exc_cause_0 = req_bits_exc_cause; // @[functional-unit.scala:393:7, :401:16]
wire [63:0] req_bits_out_1_exc_cause = req_bits_exc_cause; // @[util.scala:104:23]
reg [4:0] req_bits_mem_cmd; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_mem_cmd_0 = req_bits_mem_cmd; // @[functional-unit.scala:393:7, :401:16]
wire [4:0] req_bits_out_1_mem_cmd = req_bits_mem_cmd; // @[util.scala:104:23]
reg [1:0] req_bits_mem_size; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_mem_size_0 = req_bits_mem_size; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_mem_size = req_bits_mem_size; // @[util.scala:104:23]
reg req_bits_mem_signed; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_mem_signed_0 = req_bits_mem_signed; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_mem_signed = req_bits_mem_signed; // @[util.scala:104:23]
reg req_bits_uses_ldq; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_uses_ldq_0 = req_bits_uses_ldq; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_uses_ldq = req_bits_uses_ldq; // @[util.scala:104:23]
reg req_bits_uses_stq; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_uses_stq_0 = req_bits_uses_stq; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_uses_stq = req_bits_uses_stq; // @[util.scala:104:23]
reg req_bits_is_unique; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_is_unique_0 = req_bits_is_unique; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_is_unique = req_bits_is_unique; // @[util.scala:104:23]
reg req_bits_flush_on_commit; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_flush_on_commit_0 = req_bits_flush_on_commit; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_flush_on_commit = req_bits_flush_on_commit; // @[util.scala:104:23]
reg [2:0] req_bits_csr_cmd; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_csr_cmd_0 = req_bits_csr_cmd; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_csr_cmd = req_bits_csr_cmd; // @[util.scala:104:23]
reg req_bits_ldst_is_rs1; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_ldst_is_rs1_0 = req_bits_ldst_is_rs1; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_ldst_is_rs1 = req_bits_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] req_bits_ldst; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_ldst_0 = req_bits_ldst; // @[functional-unit.scala:393:7, :401:16]
wire [5:0] req_bits_out_1_ldst = req_bits_ldst; // @[util.scala:104:23]
reg [5:0] req_bits_lrs1; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_lrs1_0 = req_bits_lrs1; // @[functional-unit.scala:393:7, :401:16]
wire [5:0] req_bits_out_1_lrs1 = req_bits_lrs1; // @[util.scala:104:23]
reg [5:0] req_bits_lrs2; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_lrs2_0 = req_bits_lrs2; // @[functional-unit.scala:393:7, :401:16]
wire [5:0] req_bits_out_1_lrs2 = req_bits_lrs2; // @[util.scala:104:23]
reg [5:0] req_bits_lrs3; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_lrs3_0 = req_bits_lrs3; // @[functional-unit.scala:393:7, :401:16]
wire [5:0] req_bits_out_1_lrs3 = req_bits_lrs3; // @[util.scala:104:23]
reg [1:0] req_bits_dst_rtype; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_dst_rtype_0 = req_bits_dst_rtype; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_dst_rtype = req_bits_dst_rtype; // @[util.scala:104:23]
reg [1:0] req_bits_lrs1_rtype; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_lrs1_rtype_0 = req_bits_lrs1_rtype; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_lrs1_rtype = req_bits_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] req_bits_lrs2_rtype; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_lrs2_rtype_0 = req_bits_lrs2_rtype; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_lrs2_rtype = req_bits_lrs2_rtype; // @[util.scala:104:23]
reg req_bits_frs3_en; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_frs3_en_0 = req_bits_frs3_en; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_frs3_en = req_bits_frs3_en; // @[util.scala:104:23]
reg req_bits_fcn_dw; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fcn_dw_0 = req_bits_fcn_dw; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fcn_dw = req_bits_fcn_dw; // @[util.scala:104:23]
reg [4:0] req_bits_fcn_op; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fcn_op_0 = req_bits_fcn_op; // @[functional-unit.scala:393:7, :401:16]
wire [4:0] req_bits_out_1_fcn_op = req_bits_fcn_op; // @[util.scala:104:23]
reg req_bits_fp_val; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_val_0 = req_bits_fp_val; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_fp_val = req_bits_fp_val; // @[util.scala:104:23]
reg [2:0] req_bits_fp_rm; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_rm_0 = req_bits_fp_rm; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_fp_rm = req_bits_fp_rm; // @[util.scala:104:23]
reg [1:0] req_bits_fp_typ; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_fp_typ_0 = req_bits_fp_typ; // @[functional-unit.scala:393:7, :401:16]
wire [1:0] req_bits_out_1_fp_typ = req_bits_fp_typ; // @[util.scala:104:23]
reg req_bits_xcpt_pf_if; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_xcpt_pf_if_0 = req_bits_xcpt_pf_if; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_xcpt_pf_if = req_bits_xcpt_pf_if; // @[util.scala:104:23]
reg req_bits_xcpt_ae_if; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_xcpt_ae_if_0 = req_bits_xcpt_ae_if; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_xcpt_ae_if = req_bits_xcpt_ae_if; // @[util.scala:104:23]
reg req_bits_xcpt_ma_if; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_xcpt_ma_if_0 = req_bits_xcpt_ma_if; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_xcpt_ma_if = req_bits_xcpt_ma_if; // @[util.scala:104:23]
reg req_bits_bp_debug_if; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_bp_debug_if_0 = req_bits_bp_debug_if; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_bp_debug_if = req_bits_bp_debug_if; // @[util.scala:104:23]
reg req_bits_bp_xcpt_if; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_bp_xcpt_if_0 = req_bits_bp_xcpt_if; // @[functional-unit.scala:393:7, :401:16]
wire req_bits_out_1_bp_xcpt_if = req_bits_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] req_bits_debug_fsrc; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_debug_fsrc_0 = req_bits_debug_fsrc; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_debug_fsrc = req_bits_debug_fsrc; // @[util.scala:104:23]
reg [2:0] req_bits_debug_tsrc; // @[functional-unit.scala:401:16]
assign io_resp_bits_uop_debug_tsrc_0 = req_bits_debug_tsrc; // @[functional-unit.scala:393:7, :401:16]
wire [2:0] req_bits_out_1_debug_tsrc = req_bits_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _GEN = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:126:51]
wire [15:0] _req_valid_T; // @[util.scala:126:51]
assign _req_valid_T = _GEN; // @[util.scala:126:51]
wire [15:0] _div_io_req_valid_T; // @[util.scala:126:51]
assign _div_io_req_valid_T = _GEN; // @[util.scala:126:51]
wire _req_valid_T_1 = |_req_valid_T; // @[util.scala:126:{51,59}]
wire _req_valid_T_2 = _req_valid_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _req_valid_T_3 = ~_req_valid_T_2; // @[util.scala:61:61]
wire [15:0] _req_bits_out_br_mask_T_1; // @[util.scala:93:25]
wire [15:0] req_bits_out_br_mask; // @[util.scala:104:23]
wire [15:0] _req_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _req_bits_out_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _req_bits_out_br_mask_T; // @[util.scala:93:{25,27}]
assign req_bits_out_br_mask = _req_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire [15:0] _GEN_0 = io_brupdate_b1_mispredict_mask_0 & req_bits_br_mask; // @[util.scala:126:51]
wire [15:0] _req_valid_T_4; // @[util.scala:126:51]
assign _req_valid_T_4 = _GEN_0; // @[util.scala:126:51]
wire [15:0] _div_io_kill_T; // @[util.scala:126:51]
assign _div_io_kill_T = _GEN_0; // @[util.scala:126:51]
wire _req_valid_T_5 = |_req_valid_T_4; // @[util.scala:126:{51,59}]
wire _req_valid_T_6 = _req_valid_T_5 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _req_valid_T_7 = ~_req_valid_T_6; // @[util.scala:61:61]
wire _req_valid_T_8 = _req_valid_T_7 & req_valid; // @[functional-unit.scala:401:16, :407:{18,68}]
wire [15:0] _req_bits_out_br_mask_T_3; // @[util.scala:93:25]
wire [15:0] req_bits_out_1_br_mask; // @[util.scala:104:23]
wire [15:0] _req_bits_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _req_bits_out_br_mask_T_3 = req_bits_br_mask & _req_bits_out_br_mask_T_2; // @[util.scala:93:{25,27}]
assign req_bits_out_1_br_mask = _req_bits_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
wire _div_io_req_valid_T_1 = |_div_io_req_valid_T; // @[util.scala:126:{51,59}]
wire _div_io_req_valid_T_2 = _div_io_req_valid_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _div_io_req_valid_T_3 = ~_div_io_req_valid_T_2; // @[util.scala:61:61]
wire _div_io_req_valid_T_4 = io_req_valid_0 & _div_io_req_valid_T_3; // @[functional-unit.scala:393:7, :415:{39,42}]
wire _io_req_ready_T = ~req_valid; // @[functional-unit.scala:401:16, :421:46]
assign _io_req_ready_T_1 = _div_io_req_ready & _io_req_ready_T; // @[functional-unit.scala:399:19, :421:{43,46}]
assign io_req_ready_0 = _io_req_ready_T_1; // @[functional-unit.scala:393:7, :421:43]
wire _div_io_kill_T_1 = |_div_io_kill_T; // @[util.scala:126:{51,59}]
wire _div_io_kill_T_2 = _div_io_kill_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _div_io_kill_T_3 = req_valid & _div_io_kill_T_2; // @[util.scala:61:61]
wire _GEN_1 = _div_io_resp_valid & req_valid; // @[functional-unit.scala:399:19, :401:16, :427:44]
wire _io_resp_valid_T; // @[functional-unit.scala:427:44]
assign _io_resp_valid_T = _GEN_1; // @[functional-unit.scala:427:44]
assign _io_resp_valid_T_1 = _GEN_1; // @[functional-unit.scala:427:44, :429:44]
assign io_resp_valid_0 = _io_resp_valid_T_1; // @[functional-unit.scala:393:7, :429:44]
wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[functional-unit.scala:393:7]
req_valid <= ~(io_resp_ready_0 & io_resp_valid_0 | reset) & (_T ? _req_valid_T_3 : _req_valid_T_8); // @[Decoupled.scala:51:35]
req_bits_inst <= _T ? req_bits_out_inst : req_bits_out_1_inst; // @[Decoupled.scala:51:35]
req_bits_debug_inst <= _T ? req_bits_out_debug_inst : req_bits_out_1_debug_inst; // @[Decoupled.scala:51:35]
req_bits_is_rvc <= _T ? req_bits_out_is_rvc : req_bits_out_1_is_rvc; // @[Decoupled.scala:51:35]
req_bits_debug_pc <= _T ? req_bits_out_debug_pc : req_bits_out_1_debug_pc; // @[Decoupled.scala:51:35]
req_bits_iq_type_0 <= _T ? req_bits_out_iq_type_0 : req_bits_out_1_iq_type_0; // @[Decoupled.scala:51:35]
req_bits_iq_type_1 <= _T ? req_bits_out_iq_type_1 : req_bits_out_1_iq_type_1; // @[Decoupled.scala:51:35]
req_bits_iq_type_2 <= _T ? req_bits_out_iq_type_2 : req_bits_out_1_iq_type_2; // @[Decoupled.scala:51:35]
req_bits_iq_type_3 <= _T ? req_bits_out_iq_type_3 : req_bits_out_1_iq_type_3; // @[Decoupled.scala:51:35]
req_bits_fu_code_0 <= _T ? req_bits_out_fu_code_0 : req_bits_out_1_fu_code_0; // @[Decoupled.scala:51:35]
req_bits_fu_code_1 <= _T ? req_bits_out_fu_code_1 : req_bits_out_1_fu_code_1; // @[Decoupled.scala:51:35]
req_bits_fu_code_2 <= _T ? req_bits_out_fu_code_2 : req_bits_out_1_fu_code_2; // @[Decoupled.scala:51:35]
req_bits_fu_code_3 <= _T ? req_bits_out_fu_code_3 : req_bits_out_1_fu_code_3; // @[Decoupled.scala:51:35]
req_bits_fu_code_4 <= _T ? req_bits_out_fu_code_4 : req_bits_out_1_fu_code_4; // @[Decoupled.scala:51:35]
req_bits_fu_code_5 <= _T ? req_bits_out_fu_code_5 : req_bits_out_1_fu_code_5; // @[Decoupled.scala:51:35]
req_bits_fu_code_6 <= _T ? req_bits_out_fu_code_6 : req_bits_out_1_fu_code_6; // @[Decoupled.scala:51:35]
req_bits_fu_code_7 <= _T ? req_bits_out_fu_code_7 : req_bits_out_1_fu_code_7; // @[Decoupled.scala:51:35]
req_bits_fu_code_8 <= _T ? req_bits_out_fu_code_8 : req_bits_out_1_fu_code_8; // @[Decoupled.scala:51:35]
req_bits_fu_code_9 <= _T ? req_bits_out_fu_code_9 : req_bits_out_1_fu_code_9; // @[Decoupled.scala:51:35]
req_bits_iw_issued <= _T ? req_bits_out_iw_issued : req_bits_out_1_iw_issued; // @[Decoupled.scala:51:35]
req_bits_iw_issued_partial_agen <= _T ? req_bits_out_iw_issued_partial_agen : req_bits_out_1_iw_issued_partial_agen; // @[Decoupled.scala:51:35]
req_bits_iw_issued_partial_dgen <= _T ? req_bits_out_iw_issued_partial_dgen : req_bits_out_1_iw_issued_partial_dgen; // @[Decoupled.scala:51:35]
req_bits_iw_p1_speculative_child <= _T ? req_bits_out_iw_p1_speculative_child : req_bits_out_1_iw_p1_speculative_child; // @[Decoupled.scala:51:35]
req_bits_iw_p2_speculative_child <= _T ? req_bits_out_iw_p2_speculative_child : req_bits_out_1_iw_p2_speculative_child; // @[Decoupled.scala:51:35]
req_bits_iw_p1_bypass_hint <= _T ? req_bits_out_iw_p1_bypass_hint : req_bits_out_1_iw_p1_bypass_hint; // @[Decoupled.scala:51:35]
req_bits_iw_p2_bypass_hint <= _T ? req_bits_out_iw_p2_bypass_hint : req_bits_out_1_iw_p2_bypass_hint; // @[Decoupled.scala:51:35]
req_bits_iw_p3_bypass_hint <= _T ? req_bits_out_iw_p3_bypass_hint : req_bits_out_1_iw_p3_bypass_hint; // @[Decoupled.scala:51:35]
req_bits_dis_col_sel <= _T ? req_bits_out_dis_col_sel : req_bits_out_1_dis_col_sel; // @[Decoupled.scala:51:35]
req_bits_br_mask <= _T ? req_bits_out_br_mask : req_bits_out_1_br_mask; // @[Decoupled.scala:51:35]
req_bits_br_tag <= _T ? req_bits_out_br_tag : req_bits_out_1_br_tag; // @[Decoupled.scala:51:35]
req_bits_br_type <= _T ? req_bits_out_br_type : req_bits_out_1_br_type; // @[Decoupled.scala:51:35]
req_bits_is_sfb <= _T ? req_bits_out_is_sfb : req_bits_out_1_is_sfb; // @[Decoupled.scala:51:35]
req_bits_is_fence <= _T ? req_bits_out_is_fence : req_bits_out_1_is_fence; // @[Decoupled.scala:51:35]
req_bits_is_fencei <= _T ? req_bits_out_is_fencei : req_bits_out_1_is_fencei; // @[Decoupled.scala:51:35]
req_bits_is_sfence <= _T ? req_bits_out_is_sfence : req_bits_out_1_is_sfence; // @[Decoupled.scala:51:35]
req_bits_is_amo <= _T ? req_bits_out_is_amo : req_bits_out_1_is_amo; // @[Decoupled.scala:51:35]
req_bits_is_eret <= _T ? req_bits_out_is_eret : req_bits_out_1_is_eret; // @[Decoupled.scala:51:35]
req_bits_is_sys_pc2epc <= _T ? req_bits_out_is_sys_pc2epc : req_bits_out_1_is_sys_pc2epc; // @[Decoupled.scala:51:35]
req_bits_is_rocc <= _T ? req_bits_out_is_rocc : req_bits_out_1_is_rocc; // @[Decoupled.scala:51:35]
req_bits_is_mov <= _T ? req_bits_out_is_mov : req_bits_out_1_is_mov; // @[Decoupled.scala:51:35]
req_bits_ftq_idx <= _T ? req_bits_out_ftq_idx : req_bits_out_1_ftq_idx; // @[Decoupled.scala:51:35]
req_bits_edge_inst <= _T ? req_bits_out_edge_inst : req_bits_out_1_edge_inst; // @[Decoupled.scala:51:35]
req_bits_pc_lob <= _T ? req_bits_out_pc_lob : req_bits_out_1_pc_lob; // @[Decoupled.scala:51:35]
req_bits_taken <= _T ? req_bits_out_taken : req_bits_out_1_taken; // @[Decoupled.scala:51:35]
req_bits_imm_rename <= _T ? req_bits_out_imm_rename : req_bits_out_1_imm_rename; // @[Decoupled.scala:51:35]
req_bits_imm_sel <= _T ? req_bits_out_imm_sel : req_bits_out_1_imm_sel; // @[Decoupled.scala:51:35]
req_bits_pimm <= _T ? req_bits_out_pimm : req_bits_out_1_pimm; // @[Decoupled.scala:51:35]
req_bits_imm_packed <= _T ? req_bits_out_imm_packed : req_bits_out_1_imm_packed; // @[Decoupled.scala:51:35]
req_bits_op1_sel <= _T ? req_bits_out_op1_sel : req_bits_out_1_op1_sel; // @[Decoupled.scala:51:35]
req_bits_op2_sel <= _T ? req_bits_out_op2_sel : req_bits_out_1_op2_sel; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_ldst <= _T ? req_bits_out_fp_ctrl_ldst : req_bits_out_1_fp_ctrl_ldst; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_wen <= _T ? req_bits_out_fp_ctrl_wen : req_bits_out_1_fp_ctrl_wen; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_ren1 <= _T ? req_bits_out_fp_ctrl_ren1 : req_bits_out_1_fp_ctrl_ren1; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_ren2 <= _T ? req_bits_out_fp_ctrl_ren2 : req_bits_out_1_fp_ctrl_ren2; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_ren3 <= _T ? req_bits_out_fp_ctrl_ren3 : req_bits_out_1_fp_ctrl_ren3; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_swap12 <= _T ? req_bits_out_fp_ctrl_swap12 : req_bits_out_1_fp_ctrl_swap12; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_swap23 <= _T ? req_bits_out_fp_ctrl_swap23 : req_bits_out_1_fp_ctrl_swap23; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_typeTagIn <= _T ? req_bits_out_fp_ctrl_typeTagIn : req_bits_out_1_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_typeTagOut <= _T ? req_bits_out_fp_ctrl_typeTagOut : req_bits_out_1_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_fromint <= _T ? req_bits_out_fp_ctrl_fromint : req_bits_out_1_fp_ctrl_fromint; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_toint <= _T ? req_bits_out_fp_ctrl_toint : req_bits_out_1_fp_ctrl_toint; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_fastpipe <= _T ? req_bits_out_fp_ctrl_fastpipe : req_bits_out_1_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_fma <= _T ? req_bits_out_fp_ctrl_fma : req_bits_out_1_fp_ctrl_fma; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_div <= _T ? req_bits_out_fp_ctrl_div : req_bits_out_1_fp_ctrl_div; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_sqrt <= _T ? req_bits_out_fp_ctrl_sqrt : req_bits_out_1_fp_ctrl_sqrt; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_wflags <= _T ? req_bits_out_fp_ctrl_wflags : req_bits_out_1_fp_ctrl_wflags; // @[Decoupled.scala:51:35]
req_bits_fp_ctrl_vec <= _T ? req_bits_out_fp_ctrl_vec : req_bits_out_1_fp_ctrl_vec; // @[Decoupled.scala:51:35]
req_bits_rob_idx <= _T ? req_bits_out_rob_idx : req_bits_out_1_rob_idx; // @[Decoupled.scala:51:35]
req_bits_ldq_idx <= _T ? req_bits_out_ldq_idx : req_bits_out_1_ldq_idx; // @[Decoupled.scala:51:35]
req_bits_stq_idx <= _T ? req_bits_out_stq_idx : req_bits_out_1_stq_idx; // @[Decoupled.scala:51:35]
req_bits_rxq_idx <= _T ? req_bits_out_rxq_idx : req_bits_out_1_rxq_idx; // @[Decoupled.scala:51:35]
req_bits_pdst <= _T ? req_bits_out_pdst : req_bits_out_1_pdst; // @[Decoupled.scala:51:35]
req_bits_prs1 <= _T ? req_bits_out_prs1 : req_bits_out_1_prs1; // @[Decoupled.scala:51:35]
req_bits_prs2 <= _T ? req_bits_out_prs2 : req_bits_out_1_prs2; // @[Decoupled.scala:51:35]
req_bits_prs3 <= _T ? req_bits_out_prs3 : req_bits_out_1_prs3; // @[Decoupled.scala:51:35]
req_bits_ppred <= _T ? req_bits_out_ppred : req_bits_out_1_ppred; // @[Decoupled.scala:51:35]
req_bits_prs1_busy <= _T ? req_bits_out_prs1_busy : req_bits_out_1_prs1_busy; // @[Decoupled.scala:51:35]
req_bits_prs2_busy <= _T ? req_bits_out_prs2_busy : req_bits_out_1_prs2_busy; // @[Decoupled.scala:51:35]
req_bits_prs3_busy <= _T ? req_bits_out_prs3_busy : req_bits_out_1_prs3_busy; // @[Decoupled.scala:51:35]
req_bits_ppred_busy <= _T ? req_bits_out_ppred_busy : req_bits_out_1_ppred_busy; // @[Decoupled.scala:51:35]
req_bits_stale_pdst <= _T ? req_bits_out_stale_pdst : req_bits_out_1_stale_pdst; // @[Decoupled.scala:51:35]
req_bits_exception <= _T ? req_bits_out_exception : req_bits_out_1_exception; // @[Decoupled.scala:51:35]
req_bits_exc_cause <= _T ? req_bits_out_exc_cause : req_bits_out_1_exc_cause; // @[Decoupled.scala:51:35]
req_bits_mem_cmd <= _T ? req_bits_out_mem_cmd : req_bits_out_1_mem_cmd; // @[Decoupled.scala:51:35]
req_bits_mem_size <= _T ? req_bits_out_mem_size : req_bits_out_1_mem_size; // @[Decoupled.scala:51:35]
req_bits_mem_signed <= _T ? req_bits_out_mem_signed : req_bits_out_1_mem_signed; // @[Decoupled.scala:51:35]
req_bits_uses_ldq <= _T ? req_bits_out_uses_ldq : req_bits_out_1_uses_ldq; // @[Decoupled.scala:51:35]
req_bits_uses_stq <= _T ? req_bits_out_uses_stq : req_bits_out_1_uses_stq; // @[Decoupled.scala:51:35]
req_bits_is_unique <= _T ? req_bits_out_is_unique : req_bits_out_1_is_unique; // @[Decoupled.scala:51:35]
req_bits_flush_on_commit <= _T ? req_bits_out_flush_on_commit : req_bits_out_1_flush_on_commit; // @[Decoupled.scala:51:35]
req_bits_csr_cmd <= _T ? req_bits_out_csr_cmd : req_bits_out_1_csr_cmd; // @[Decoupled.scala:51:35]
req_bits_ldst_is_rs1 <= _T ? req_bits_out_ldst_is_rs1 : req_bits_out_1_ldst_is_rs1; // @[Decoupled.scala:51:35]
req_bits_ldst <= _T ? req_bits_out_ldst : req_bits_out_1_ldst; // @[Decoupled.scala:51:35]
req_bits_lrs1 <= _T ? req_bits_out_lrs1 : req_bits_out_1_lrs1; // @[Decoupled.scala:51:35]
req_bits_lrs2 <= _T ? req_bits_out_lrs2 : req_bits_out_1_lrs2; // @[Decoupled.scala:51:35]
req_bits_lrs3 <= _T ? req_bits_out_lrs3 : req_bits_out_1_lrs3; // @[Decoupled.scala:51:35]
req_bits_dst_rtype <= _T ? req_bits_out_dst_rtype : req_bits_out_1_dst_rtype; // @[Decoupled.scala:51:35]
req_bits_lrs1_rtype <= _T ? req_bits_out_lrs1_rtype : req_bits_out_1_lrs1_rtype; // @[Decoupled.scala:51:35]
req_bits_lrs2_rtype <= _T ? req_bits_out_lrs2_rtype : req_bits_out_1_lrs2_rtype; // @[Decoupled.scala:51:35]
req_bits_frs3_en <= _T ? req_bits_out_frs3_en : req_bits_out_1_frs3_en; // @[Decoupled.scala:51:35]
req_bits_fcn_dw <= _T ? req_bits_out_fcn_dw : req_bits_out_1_fcn_dw; // @[Decoupled.scala:51:35]
req_bits_fcn_op <= _T ? req_bits_out_fcn_op : req_bits_out_1_fcn_op; // @[Decoupled.scala:51:35]
req_bits_fp_val <= _T ? req_bits_out_fp_val : req_bits_out_1_fp_val; // @[Decoupled.scala:51:35]
req_bits_fp_rm <= _T ? req_bits_out_fp_rm : req_bits_out_1_fp_rm; // @[Decoupled.scala:51:35]
req_bits_fp_typ <= _T ? req_bits_out_fp_typ : req_bits_out_1_fp_typ; // @[Decoupled.scala:51:35]
req_bits_xcpt_pf_if <= _T ? req_bits_out_xcpt_pf_if : req_bits_out_1_xcpt_pf_if; // @[Decoupled.scala:51:35]
req_bits_xcpt_ae_if <= _T ? req_bits_out_xcpt_ae_if : req_bits_out_1_xcpt_ae_if; // @[Decoupled.scala:51:35]
req_bits_xcpt_ma_if <= _T ? req_bits_out_xcpt_ma_if : req_bits_out_1_xcpt_ma_if; // @[Decoupled.scala:51:35]
req_bits_bp_debug_if <= _T ? req_bits_out_bp_debug_if : req_bits_out_1_bp_debug_if; // @[Decoupled.scala:51:35]
req_bits_bp_xcpt_if <= _T ? req_bits_out_bp_xcpt_if : req_bits_out_1_bp_xcpt_if; // @[Decoupled.scala:51:35]
req_bits_debug_fsrc <= _T ? req_bits_out_debug_fsrc : req_bits_out_1_debug_fsrc; // @[Decoupled.scala:51:35]
req_bits_debug_tsrc <= _T ? req_bits_out_debug_tsrc : req_bits_out_1_debug_tsrc; // @[Decoupled.scala:51:35]
always @(posedge)
MulDiv div ( // @[functional-unit.scala:399:19]
.clock (clock),
.reset (reset),
.io_req_ready (_div_io_req_ready),
.io_req_valid (_div_io_req_valid_T_4), // @[functional-unit.scala:415:39]
.io_req_bits_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:393:7]
.io_req_bits_dw (io_req_bits_uop_fcn_dw_0), // @[functional-unit.scala:393:7]
.io_req_bits_in1 (io_req_bits_rs1_data_0), // @[functional-unit.scala:393:7]
.io_req_bits_in2 (io_req_bits_rs2_data_0), // @[functional-unit.scala:393:7]
.io_kill (_div_io_kill_T_3), // @[functional-unit.scala:424:37]
.io_resp_ready (io_resp_ready_0), // @[functional-unit.scala:393:7]
.io_resp_valid (_div_io_resp_valid),
.io_resp_bits_data (io_resp_bits_data_0)
); // @[functional-unit.scala:399:19]
assign io_req_ready = io_req_ready_0; // @[functional-unit.scala:393:7]
assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:393:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:393:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0)
node _source_ok_T = shr(io.in.a.bits.source, 12)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits = bits(_uncommonBits_T, 11, 0)
node _T_4 = shr(io.in.a.bits.source, 12)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<12>(0h80f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0)
node _T_24 = shr(io.in.a.bits.source, 12)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0)
node _T_86 = shr(io.in.a.bits.source, 12)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0)
node _T_152 = shr(io.in.a.bits.source, 12)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0)
node _T_199 = shr(io.in.a.bits.source, 12)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0)
node _T_240 = shr(io.in.a.bits.source, 12)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0)
node _T_283 = shr(io.in.a.bits.source, 12)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0)
node _T_321 = shr(io.in.a.bits.source, 12)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0)
node _T_359 = shr(io.in.a.bits.source, 12)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 12)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2064>
connect a_set, UInt<2064>(0h0)
wire a_set_wo_ready : UInt<2064>
connect a_set_wo_ready, UInt<2064>(0h0)
wire a_opcodes_set : UInt<8256>
connect a_opcodes_set, UInt<8256>(0h0)
wire a_sizes_set : UInt<8256>
connect a_sizes_set, UInt<8256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<2064>
connect d_clr, UInt<2064>(0h0)
wire d_clr_wo_ready : UInt<2064>
connect d_clr_wo_ready, UInt<2064>(0h0)
wire d_opcodes_clr : UInt<8256>
connect d_opcodes_clr, UInt<8256>(0h0)
wire d_sizes_clr : UInt<8256>
connect d_sizes_clr, UInt<8256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_103
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<12>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2064>
connect c_set, UInt<2064>(0h0)
wire c_set_wo_ready : UInt<2064>
connect c_set_wo_ready, UInt<2064>(0h0)
wire c_opcodes_set : UInt<8256>
connect c_opcodes_set, UInt<8256>(0h0)
wire c_sizes_set : UInt<8256>
connect c_sizes_set, UInt<8256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<12>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<12>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<12>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<12>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<12>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2064>
connect d_clr_1, UInt<2064>(0h0)
wire d_clr_wo_ready_1 : UInt<2064>
connect d_clr_wo_ready_1, UInt<2064>(0h0)
wire d_opcodes_clr_1 : UInt<8256>
connect d_opcodes_clr_1, UInt<8256>(0h0)
wire d_sizes_clr_1 : UInt<8256>
connect d_sizes_clr_1, UInt<8256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<12>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<12>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<12>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<12>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_104
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<12>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_50( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52]
wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79]
wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77]
wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35]
wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35]
wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34]
wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34]
wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34]
wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [2063:0] a_set; // @[Monitor.scala:626:34]
wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [2063:0] d_clr; // @[Monitor.scala:664:34]
wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [2063:0] d_clr_1; // @[Monitor.scala:774:34]
wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113]
wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s5k3z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_12
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s5k3z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s5k3z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_26 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_27 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a32d64s5k3z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [4:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_12 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s5k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s5k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (auto_out_d_bits_param),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (auto_out_d_bits_sink),
.io_enq_bits_denied (auto_out_d_bits_denied),
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_11 :
output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 63, 52)
node _rawIn_isZero_T = bits(rawIn_exp, 11, 9)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 64, 64)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 51, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_5
node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51)
node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0))
node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1)
connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig
connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp
connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign
connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RecFNToRecFN_11( // @[RecFNToRecFN.scala:44:5]
input [64:0] io_in, // @[RecFNToRecFN.scala:48:16]
input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out, // @[RecFNToRecFN.scala:48:16]
output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16]
);
wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_5 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_316 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_60
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_316( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_60 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_23 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_33
node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<4>(0h8))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _T_101 = and(_T_11, _T_24)
node _T_102 = and(_T_101, _T_37)
node _T_103 = and(_T_102, _T_50)
node _T_104 = and(_T_103, _T_63)
node _T_105 = and(_T_104, _T_76)
node _T_106 = and(_T_105, _T_84)
node _T_107 = and(_T_106, _T_92)
node _T_108 = and(_T_107, _T_100)
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_108, UInt<1>(0h1), "") : assert_1
node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_112 :
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_117 = shr(io.in.a.bits.source, 2)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_120 = and(_T_118, _T_119)
node _T_121 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_122 = and(_T_120, _T_121)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_123 = shr(io.in.a.bits.source, 2)
node _T_124 = eq(_T_123, UInt<1>(0h1))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_128 = and(_T_126, _T_127)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_129 = shr(io.in.a.bits.source, 2)
node _T_130 = eq(_T_129, UInt<2>(0h2))
node _T_131 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_132 = and(_T_130, _T_131)
node _T_133 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_134 = and(_T_132, _T_133)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_135 = shr(io.in.a.bits.source, 2)
node _T_136 = eq(_T_135, UInt<2>(0h3))
node _T_137 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_138 = and(_T_136, _T_137)
node _T_139 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_140 = and(_T_138, _T_139)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_141 = shr(io.in.a.bits.source, 2)
node _T_142 = eq(_T_141, UInt<4>(0h8))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_9, UInt<2>(0h2))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_116, _T_122)
node _T_151 = or(_T_150, _T_128)
node _T_152 = or(_T_151, _T_134)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_146)
node _T_155 = or(_T_154, _T_147)
node _T_156 = or(_T_155, _T_148)
node _T_157 = or(_T_156, _T_149)
node _T_158 = and(_T_115, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = and(_T_160, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = and(_T_159, _T_167)
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_168, UInt<1>(0h1), "") : assert_2
node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_173 = shr(io.in.a.bits.source, 2)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_176 = and(_T_174, _T_175)
node _T_177 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_178 = and(_T_176, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_179 = shr(io.in.a.bits.source, 2)
node _T_180 = eq(_T_179, UInt<1>(0h1))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_184 = and(_T_182, _T_183)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_185 = shr(io.in.a.bits.source, 2)
node _T_186 = eq(_T_185, UInt<2>(0h2))
node _T_187 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_188 = and(_T_186, _T_187)
node _T_189 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_190 = and(_T_188, _T_189)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_191 = shr(io.in.a.bits.source, 2)
node _T_192 = eq(_T_191, UInt<2>(0h3))
node _T_193 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_194 = and(_T_192, _T_193)
node _T_195 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_197 = shr(io.in.a.bits.source, 2)
node _T_198 = eq(_T_197, UInt<4>(0h8))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_14, UInt<2>(0h2))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_172
connect _WIRE[1], _T_178
connect _WIRE[2], _T_184
connect _WIRE[3], _T_190
connect _WIRE[4], _T_196
connect _WIRE[5], _T_202
connect _WIRE[6], _T_203
connect _WIRE[7], _T_204
connect _WIRE[8], _T_205
node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0))
node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_216 = or(_T_207, _T_208)
node _T_217 = or(_T_216, _T_209)
node _T_218 = or(_T_217, _T_210)
node _T_219 = or(_T_218, _T_211)
node _T_220 = or(_T_219, _T_212)
node _T_221 = or(_T_220, _T_213)
node _T_222 = or(_T_221, _T_214)
node _T_223 = or(_T_222, _T_215)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_223
node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_226 = and(_T_224, _T_225)
node _T_227 = or(UInt<1>(0h0), _T_226)
node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<17>(0h10000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = and(_T_227, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(_WIRE_1, _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_291 = shr(io.in.a.bits.source, 2)
node _T_292 = eq(_T_291, UInt<4>(0h8))
node _T_293 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_294 = and(_T_292, _T_293)
node _T_295 = leq(uncommonBits_19, UInt<2>(0h2))
node _T_296 = and(_T_294, _T_295)
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_300 = or(_T_266, _T_272)
node _T_301 = or(_T_300, _T_278)
node _T_302 = or(_T_301, _T_284)
node _T_303 = or(_T_302, _T_290)
node _T_304 = or(_T_303, _T_296)
node _T_305 = or(_T_304, _T_297)
node _T_306 = or(_T_305, _T_298)
node _T_307 = or(_T_306, _T_299)
node _T_308 = and(_T_265, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = and(_T_310, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = and(_T_309, _T_317)
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_318, UInt<1>(0h1), "") : assert_10
node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_323 = shr(io.in.a.bits.source, 2)
node _T_324 = eq(_T_323, UInt<1>(0h0))
node _T_325 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_326 = and(_T_324, _T_325)
node _T_327 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_328 = and(_T_326, _T_327)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_329 = shr(io.in.a.bits.source, 2)
node _T_330 = eq(_T_329, UInt<1>(0h1))
node _T_331 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_332 = and(_T_330, _T_331)
node _T_333 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_335 = shr(io.in.a.bits.source, 2)
node _T_336 = eq(_T_335, UInt<2>(0h2))
node _T_337 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_338 = and(_T_336, _T_337)
node _T_339 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_340 = and(_T_338, _T_339)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_341 = shr(io.in.a.bits.source, 2)
node _T_342 = eq(_T_341, UInt<2>(0h3))
node _T_343 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_344 = and(_T_342, _T_343)
node _T_345 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_346 = and(_T_344, _T_345)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_347 = shr(io.in.a.bits.source, 2)
node _T_348 = eq(_T_347, UInt<4>(0h8))
node _T_349 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_350 = and(_T_348, _T_349)
node _T_351 = leq(uncommonBits_24, UInt<2>(0h2))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_322
connect _WIRE_2[1], _T_328
connect _WIRE_2[2], _T_334
connect _WIRE_2[3], _T_340
connect _WIRE_2[4], _T_346
connect _WIRE_2[5], _T_352
connect _WIRE_2[6], _T_353
connect _WIRE_2[7], _T_354
connect _WIRE_2[8], _T_355
node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0))
node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_366 = or(_T_357, _T_358)
node _T_367 = or(_T_366, _T_359)
node _T_368 = or(_T_367, _T_360)
node _T_369 = or(_T_368, _T_361)
node _T_370 = or(_T_369, _T_362)
node _T_371 = or(_T_370, _T_363)
node _T_372 = or(_T_371, _T_364)
node _T_373 = or(_T_372, _T_365)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_373
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _T_377 = or(UInt<1>(0h0), _T_376)
node _T_378 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = and(_T_377, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = and(_WIRE_3, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_385, UInt<1>(0h1), "") : assert_11
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(source_ok, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_392, UInt<1>(0h1), "") : assert_13
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(is_aligned, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_399, UInt<1>(0h1), "") : assert_15
node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_403, UInt<1>(0h1), "") : assert_16
node _T_407 = not(io.in.a.bits.mask)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_408, UInt<1>(0h1), "") : assert_17
node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_413 = asUInt(reset)
node _T_414 = eq(_T_413, UInt<1>(0h0))
when _T_414 :
node _T_415 = eq(_T_412, UInt<1>(0h0))
when _T_415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_412, UInt<1>(0h1), "") : assert_18
node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_416 :
node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<1>(0h1))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h2))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_439 = shr(io.in.a.bits.source, 2)
node _T_440 = eq(_T_439, UInt<2>(0h3))
node _T_441 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_442 = and(_T_440, _T_441)
node _T_443 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_444 = and(_T_442, _T_443)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_445 = shr(io.in.a.bits.source, 2)
node _T_446 = eq(_T_445, UInt<4>(0h8))
node _T_447 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_448 = and(_T_446, _T_447)
node _T_449 = leq(uncommonBits_29, UInt<2>(0h2))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_454 = or(_T_420, _T_426)
node _T_455 = or(_T_454, _T_432)
node _T_456 = or(_T_455, _T_438)
node _T_457 = or(_T_456, _T_444)
node _T_458 = or(_T_457, _T_450)
node _T_459 = or(_T_458, _T_451)
node _T_460 = or(_T_459, _T_452)
node _T_461 = or(_T_460, _T_453)
node _T_462 = and(_T_419, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_463, UInt<1>(0h1), "") : assert_19
node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_469 = and(_T_467, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<17>(0h10000)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = and(_T_470, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_477, UInt<1>(0h1), "") : assert_20
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(source_ok, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(is_aligned, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_487, UInt<1>(0h1), "") : assert_23
node _T_491 = eq(io.in.a.bits.mask, mask)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_491, UInt<1>(0h1), "") : assert_24
node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_495, UInt<1>(0h1), "") : assert_25
node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_499 :
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_504 = shr(io.in.a.bits.source, 2)
node _T_505 = eq(_T_504, UInt<1>(0h0))
node _T_506 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_507 = and(_T_505, _T_506)
node _T_508 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_509 = and(_T_507, _T_508)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_510 = shr(io.in.a.bits.source, 2)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_516 = shr(io.in.a.bits.source, 2)
node _T_517 = eq(_T_516, UInt<2>(0h2))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<2>(0h3))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_528 = shr(io.in.a.bits.source, 2)
node _T_529 = eq(_T_528, UInt<4>(0h8))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_34, UInt<2>(0h2))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_537 = or(_T_503, _T_509)
node _T_538 = or(_T_537, _T_515)
node _T_539 = or(_T_538, _T_521)
node _T_540 = or(_T_539, _T_527)
node _T_541 = or(_T_540, _T_533)
node _T_542 = or(_T_541, _T_534)
node _T_543 = or(_T_542, _T_535)
node _T_544 = or(_T_543, _T_536)
node _T_545 = and(_T_502, _T_544)
node _T_546 = or(UInt<1>(0h0), _T_545)
node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_549 = and(_T_547, _T_548)
node _T_550 = or(UInt<1>(0h0), _T_549)
node _T_551 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_556)
node _T_558 = and(_T_546, _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_558, UInt<1>(0h1), "") : assert_26
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(source_ok, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(is_aligned, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_568, UInt<1>(0h1), "") : assert_29
node _T_572 = eq(io.in.a.bits.mask, mask)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_572, UInt<1>(0h1), "") : assert_30
node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_576 :
node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<1>(0h0))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<1>(0h1))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_593 = shr(io.in.a.bits.source, 2)
node _T_594 = eq(_T_593, UInt<2>(0h2))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_598 = and(_T_596, _T_597)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_599 = shr(io.in.a.bits.source, 2)
node _T_600 = eq(_T_599, UInt<2>(0h3))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_604 = and(_T_602, _T_603)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_605 = shr(io.in.a.bits.source, 2)
node _T_606 = eq(_T_605, UInt<4>(0h8))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_39, UInt<2>(0h2))
node _T_610 = and(_T_608, _T_609)
node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_614 = or(_T_580, _T_586)
node _T_615 = or(_T_614, _T_592)
node _T_616 = or(_T_615, _T_598)
node _T_617 = or(_T_616, _T_604)
node _T_618 = or(_T_617, _T_610)
node _T_619 = or(_T_618, _T_611)
node _T_620 = or(_T_619, _T_612)
node _T_621 = or(_T_620, _T_613)
node _T_622 = and(_T_579, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<17>(0h10000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = and(_T_627, _T_632)
node _T_634 = or(UInt<1>(0h0), _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_635, UInt<1>(0h1), "") : assert_31
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(source_ok, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(is_aligned, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_645, UInt<1>(0h1), "") : assert_34
node _T_649 = not(mask)
node _T_650 = and(io.in.a.bits.mask, _T_649)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_651, UInt<1>(0h1), "") : assert_35
node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_655 :
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<1>(0h1))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<2>(0h2))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_678 = shr(io.in.a.bits.source, 2)
node _T_679 = eq(_T_678, UInt<2>(0h3))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_683 = and(_T_681, _T_682)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_684 = shr(io.in.a.bits.source, 2)
node _T_685 = eq(_T_684, UInt<4>(0h8))
node _T_686 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_687 = and(_T_685, _T_686)
node _T_688 = leq(uncommonBits_44, UInt<2>(0h2))
node _T_689 = and(_T_687, _T_688)
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_693 = or(_T_659, _T_665)
node _T_694 = or(_T_693, _T_671)
node _T_695 = or(_T_694, _T_677)
node _T_696 = or(_T_695, _T_683)
node _T_697 = or(_T_696, _T_689)
node _T_698 = or(_T_697, _T_690)
node _T_699 = or(_T_698, _T_691)
node _T_700 = or(_T_699, _T_692)
node _T_701 = and(_T_658, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_701)
node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_705 = cvt(_T_704)
node _T_706 = and(_T_705, asSInt(UInt<17>(0h10000)))
node _T_707 = asSInt(_T_706)
node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0)))
node _T_709 = and(_T_703, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = and(_T_702, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_711, UInt<1>(0h1), "") : assert_36
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_721, UInt<1>(0h1), "") : assert_39
node _T_725 = eq(io.in.a.bits.mask, mask)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_725, UInt<1>(0h1), "") : assert_40
node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_729 :
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_740 = shr(io.in.a.bits.source, 2)
node _T_741 = eq(_T_740, UInt<1>(0h1))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<2>(0h2))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<2>(0h3))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<4>(0h8))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_49, UInt<2>(0h2))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_767 = or(_T_733, _T_739)
node _T_768 = or(_T_767, _T_745)
node _T_769 = or(_T_768, _T_751)
node _T_770 = or(_T_769, _T_757)
node _T_771 = or(_T_770, _T_763)
node _T_772 = or(_T_771, _T_764)
node _T_773 = or(_T_772, _T_765)
node _T_774 = or(_T_773, _T_766)
node _T_775 = and(_T_732, _T_774)
node _T_776 = or(UInt<1>(0h0), _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_783)
node _T_785 = and(_T_776, _T_784)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_785, UInt<1>(0h1), "") : assert_41
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(source_ok, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(is_aligned, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_795, UInt<1>(0h1), "") : assert_44
node _T_799 = eq(io.in.a.bits.mask, mask)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_799, UInt<1>(0h1), "") : assert_45
node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_803 :
node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_806 = and(_T_804, _T_805)
node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<1>(0h0))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_814 = shr(io.in.a.bits.source, 2)
node _T_815 = eq(_T_814, UInt<1>(0h1))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_819 = and(_T_817, _T_818)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_820 = shr(io.in.a.bits.source, 2)
node _T_821 = eq(_T_820, UInt<2>(0h2))
node _T_822 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_823 = and(_T_821, _T_822)
node _T_824 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_825 = and(_T_823, _T_824)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_826 = shr(io.in.a.bits.source, 2)
node _T_827 = eq(_T_826, UInt<2>(0h3))
node _T_828 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_829 = and(_T_827, _T_828)
node _T_830 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_831 = and(_T_829, _T_830)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_832 = shr(io.in.a.bits.source, 2)
node _T_833 = eq(_T_832, UInt<4>(0h8))
node _T_834 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_835 = and(_T_833, _T_834)
node _T_836 = leq(uncommonBits_54, UInt<2>(0h2))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_841 = or(_T_807, _T_813)
node _T_842 = or(_T_841, _T_819)
node _T_843 = or(_T_842, _T_825)
node _T_844 = or(_T_843, _T_831)
node _T_845 = or(_T_844, _T_837)
node _T_846 = or(_T_845, _T_838)
node _T_847 = or(_T_846, _T_839)
node _T_848 = or(_T_847, _T_840)
node _T_849 = and(_T_806, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_852 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<17>(0h10000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = and(_T_851, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = and(_T_850, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_859, UInt<1>(0h1), "") : assert_46
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(source_ok, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(is_aligned, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_869, UInt<1>(0h1), "") : assert_49
node _T_873 = eq(io.in.a.bits.mask, mask)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_873, UInt<1>(0h1), "") : assert_50
node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_877, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_881, UInt<1>(0h1), "") : assert_52
node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_42 = shr(io.in.d.bits.source, 2)
node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0))
node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_48 = shr(io.in.d.bits.source, 2)
node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1))
node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_54 = shr(io.in.d.bits.source, 2)
node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2))
node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_60 = shr(io.in.d.bits.source, 2)
node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3))
node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_66 = shr(io.in.d.bits.source, 2)
node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8))
node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2))
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23))
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_41
connect _source_ok_WIRE_1[1], _source_ok_T_47
connect _source_ok_WIRE_1[2], _source_ok_T_53
connect _source_ok_WIRE_1[3], _source_ok_T_59
connect _source_ok_WIRE_1[4], _source_ok_T_65
connect _source_ok_WIRE_1[5], _source_ok_T_71
connect _source_ok_WIRE_1[6], _source_ok_T_72
connect _source_ok_WIRE_1[7], _source_ok_T_73
connect _source_ok_WIRE_1[8], _source_ok_T_74
node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_885 :
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok_1, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_889, UInt<1>(0h1), "") : assert_54
node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_893, UInt<1>(0h1), "") : assert_55
node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_897, UInt<1>(0h1), "") : assert_56
node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_901, UInt<1>(0h1), "") : assert_57
node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_905 :
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok_1, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(sink_ok, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_912, UInt<1>(0h1), "") : assert_60
node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_916, UInt<1>(0h1), "") : assert_61
node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_920, UInt<1>(0h1), "") : assert_62
node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_924, UInt<1>(0h1), "") : assert_63
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(UInt<1>(0h0), _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_929, UInt<1>(0h1), "") : assert_64
node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_933 :
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(source_ok_1, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(sink_ok, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_940, UInt<1>(0h1), "") : assert_67
node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_944, UInt<1>(0h1), "") : assert_68
node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_948, UInt<1>(0h1), "") : assert_69
node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_953 = or(_T_952, io.in.d.bits.corrupt)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_953, UInt<1>(0h1), "") : assert_70
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = or(UInt<1>(0h0), _T_957)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_958, UInt<1>(0h1), "") : assert_71
node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_962 :
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(source_ok_1, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_966, UInt<1>(0h1), "") : assert_73
node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_970, UInt<1>(0h1), "") : assert_74
node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_975, UInt<1>(0h1), "") : assert_75
node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_979 :
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok_1, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_983, UInt<1>(0h1), "") : assert_77
node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_988 = or(_T_987, io.in.d.bits.corrupt)
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_988, UInt<1>(0h1), "") : assert_78
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(UInt<1>(0h0), _T_992)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_993, UInt<1>(0h1), "") : assert_79
node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_997 :
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(source_ok_1, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81
node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82
node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1010 = or(UInt<1>(0h0), _T_1009)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<26>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1026 = eq(a_first, UInt<1>(0h0))
node _T_1027 = and(io.in.a.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.a.bits.opcode, opcode)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87
node _T_1032 = eq(io.in.a.bits.param, param)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88
node _T_1036 = eq(io.in.a.bits.size, size)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89
node _T_1040 = eq(io.in.a.bits.source, source)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90
node _T_1044 = eq(io.in.a.bits.address, address)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91
node _T_1048 = and(io.in.a.ready, io.in.a.valid)
node _T_1049 = and(_T_1048, a_first)
when _T_1049 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1050 = eq(d_first, UInt<1>(0h0))
node _T_1051 = and(io.in.d.valid, _T_1050)
when _T_1051 :
node _T_1052 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92
node _T_1056 = eq(io.in.d.bits.param, param_1)
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93
node _T_1060 = eq(io.in.d.bits.size, size_1)
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94
node _T_1064 = eq(io.in.d.bits.source, source_1)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95
node _T_1068 = eq(io.in.d.bits.sink, sink)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96
node _T_1072 = eq(io.in.d.bits.denied, denied)
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97
node _T_1076 = and(io.in.d.ready, io.in.d.valid)
node _T_1077 = and(_T_1076, d_first)
when _T_1077 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1078 = and(io.in.a.valid, a_first_1)
node _T_1079 = and(_T_1078, UInt<1>(0h1))
when _T_1079 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1080 = and(io.in.a.ready, io.in.a.valid)
node _T_1081 = and(_T_1080, a_first_1)
node _T_1082 = and(_T_1081, UInt<1>(0h1))
when _T_1082 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1083 = dshr(inflight, io.in.a.bits.source)
node _T_1084 = bits(_T_1083, 0, 0)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1089 = and(io.in.d.valid, d_first_1)
node _T_1090 = and(_T_1089, UInt<1>(0h1))
node _T_1091 = eq(d_release_ack, UInt<1>(0h0))
node _T_1092 = and(_T_1090, _T_1091)
when _T_1092 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1093 = and(io.in.d.ready, io.in.d.valid)
node _T_1094 = and(_T_1093, d_first_1)
node _T_1095 = and(_T_1094, UInt<1>(0h1))
node _T_1096 = eq(d_release_ack, UInt<1>(0h0))
node _T_1097 = and(_T_1095, _T_1096)
when _T_1097 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1098 = and(io.in.d.valid, d_first_1)
node _T_1099 = and(_T_1098, UInt<1>(0h1))
node _T_1100 = eq(d_release_ack, UInt<1>(0h0))
node _T_1101 = and(_T_1099, _T_1100)
when _T_1101 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1102 = dshr(inflight, io.in.d.bits.source)
node _T_1103 = bits(_T_1102, 0, 0)
node _T_1104 = or(_T_1103, same_cycle_resp)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1110 = or(_T_1108, _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100
node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101
else :
node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1120 = or(_T_1118, _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102
node _T_1124 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103
node _T_1128 = and(io.in.d.valid, d_first_1)
node _T_1129 = and(_T_1128, a_first_1)
node _T_1130 = and(_T_1129, io.in.a.valid)
node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1132 = and(_T_1130, _T_1131)
node _T_1133 = eq(d_release_ack, UInt<1>(0h0))
node _T_1134 = and(_T_1132, _T_1133)
when _T_1134 :
node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1136 = or(_T_1135, io.in.a.ready)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_46
node _T_1140 = orr(inflight)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1143 = or(_T_1141, _T_1142)
node _T_1144 = lt(watchdog, plusarg_reader.out)
node _T_1145 = or(_T_1143, _T_1144)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1149 = and(io.in.a.ready, io.in.a.valid)
node _T_1150 = and(io.in.d.ready, io.in.d.valid)
node _T_1151 = or(_T_1149, _T_1150)
when _T_1151 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1152 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1153 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1154 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = and(_T_1152, _T_1155)
when _T_1156 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1157 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1158 = and(_T_1157, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1159 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1160 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1161 = and(_T_1159, _T_1160)
node _T_1162 = and(_T_1158, _T_1161)
when _T_1162 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1163 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1164 = bits(_T_1163, 0, 0)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1169 = and(io.in.d.valid, d_first_2)
node _T_1170 = and(_T_1169, UInt<1>(0h1))
node _T_1171 = and(_T_1170, d_release_ack_1)
when _T_1171 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1172 = and(io.in.d.ready, io.in.d.valid)
node _T_1173 = and(_T_1172, d_first_2)
node _T_1174 = and(_T_1173, UInt<1>(0h1))
node _T_1175 = and(_T_1174, d_release_ack_1)
when _T_1175 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1176 = and(io.in.d.valid, d_first_2)
node _T_1177 = and(_T_1176, UInt<1>(0h1))
node _T_1178 = and(_T_1177, d_release_ack_1)
when _T_1178 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1179 = dshr(inflight_1, io.in.d.bits.source)
node _T_1180 = bits(_T_1179, 0, 0)
node _T_1181 = or(_T_1180, same_cycle_resp_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1185 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_108
else :
node _T_1189 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_109
node _T_1193 = and(io.in.d.valid, d_first_2)
node _T_1194 = and(_T_1193, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1195 = and(_T_1194, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1196 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1197 = and(_T_1195, _T_1196)
node _T_1198 = and(_T_1197, d_release_ack_1)
node _T_1199 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1200 = and(_T_1198, _T_1199)
when _T_1200 :
node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<26>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1202 = or(_T_1201, _WIRE_27.ready)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_47
node _T_1206 = orr(inflight_1)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
node _T_1208 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1209 = or(_T_1207, _T_1208)
node _T_1210 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1211 = or(_T_1209, _T_1210)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<26>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1215 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1216 = and(io.in.d.ready, io.in.d.valid)
node _T_1217 = or(_T_1215, _T_1216)
when _T_1217 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_23( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_230 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_230( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_Phit_18 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
wire sink_ready : UInt<1>
connect sink_ready, UInt<1>(0h1)
reg mem : { phit : UInt<32>}[8], clock
node _widx_T = asAsyncReset(reset)
node _widx_T_1 = and(io.enq.ready, io.enq.valid)
node _widx_T_2 = eq(sink_ready, UInt<1>(0h0))
wire widx_incremented : UInt<4>
regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0)
connect widx_widx_bin, widx_incremented
node _widx_incremented_T = add(widx_widx_bin, _widx_T_1)
node _widx_incremented_T_1 = tail(_widx_incremented_T, 1)
node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1)
connect widx_incremented, _widx_incremented_T_2
node _widx_T_3 = shr(widx_incremented, 1)
node widx = xor(widx_incremented, _widx_T_3)
inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_36
connect ridx_ridx_gray.clock, clock
connect ridx_ridx_gray.reset, reset
connect ridx_ridx_gray.io.d, io.async.ridx
wire ridx : UInt<4>
connect ridx, ridx_ridx_gray.io.q
node _ready_T = xor(ridx, UInt<4>(0hc))
node _ready_T_1 = neq(widx, _ready_T)
node ready = and(sink_ready, _ready_T_1)
node _index_T = bits(io.async.widx, 2, 0)
node _index_T_1 = bits(io.async.widx, 3, 3)
node _index_T_2 = shl(_index_T_1, 2)
node index = xor(_index_T, _index_T_2)
node _T = and(io.enq.ready, io.enq.valid)
when _T :
connect mem[index], io.enq.bits
node _ready_reg_T = asAsyncReset(reset)
regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0)
connect ready_reg, ready
node _io_enq_ready_T = and(ready_reg, sink_ready)
connect io.enq.ready, _io_enq_ready_T
node _widx_reg_T = asAsyncReset(reset)
regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0)
connect widx_gray, widx
connect io.async.widx, widx_gray
connect io.async.mem, mem
inst source_valid_0 of AsyncValidSync_168
inst source_valid_1 of AsyncValidSync_169
inst sink_extend of AsyncValidSync_170
inst sink_valid of AsyncValidSync_171
node _source_valid_0_reset_T = asUInt(reset)
node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1)
node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2)
connect source_valid_0.reset, _source_valid_0_reset_T_3
node _source_valid_1_reset_T = asUInt(reset)
node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1)
node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2)
connect source_valid_1.reset, _source_valid_1_reset_T_3
node _sink_extend_reset_T = asUInt(reset)
node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1)
node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2)
connect sink_extend.reset, _sink_extend_reset_T_3
node _sink_valid_reset_T = asAsyncReset(reset)
connect sink_valid.reset, _sink_valid_reset_T
connect source_valid_0.clock, clock
connect source_valid_1.clock, clock
connect sink_extend.clock, clock
connect sink_valid.clock, clock
connect source_valid_0.io.in, UInt<1>(0h1)
connect source_valid_1.io.in, source_valid_0.io.out
connect io.async.safe.widx_valid, source_valid_1.io.out
connect sink_extend.io.in, io.async.safe.ridx_valid
connect sink_valid.io.in, sink_extend.io.out
connect sink_ready, sink_valid.io.out
node _io_async_safe_source_reset_n_T = asUInt(reset)
node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0))
connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 | module AsyncQueueSource_Phit_18( // @[AsyncQueue.scala:70:7]
input clock, // @[AsyncQueue.scala:70:7]
input reset, // @[AsyncQueue.scala:70:7]
output io_enq_ready, // @[AsyncQueue.scala:73:14]
input io_enq_valid, // @[AsyncQueue.scala:73:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:73:14]
input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14]
input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14]
input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14]
);
wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30]
wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7]
wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7]
wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7]
wire _widx_T = reset; // @[AsyncQueue.scala:83:30]
wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35]
wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34]
wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36]
wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36]
wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36]
wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35]
wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34]
wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29]
wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27]
wire io_enq_ready_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_0_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_1_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_2_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_3_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_4_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_5_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_6_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_7_phit_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7]
wire sink_ready; // @[AsyncQueue.scala:81:28]
reg [31:0] mem_0_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_phit_0 = mem_0_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_1_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_phit_0 = mem_1_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_2_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_phit_0 = mem_2_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_3_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_phit_0 = mem_3_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_4_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_phit_0 = mem_4_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_5_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_phit_0 = mem_5_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_6_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_phit_0 = mem_6_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_7_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_phit_0 = mem_7_phit; // @[AsyncQueue.scala:70:7, :82:16]
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77]
wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]
assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] ridx; // @[ShiftReg.scala:48:24]
wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24]
wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}]
wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}]
wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52]
wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}]
reg ready_reg; // @[AsyncQueue.scala:90:56]
assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29]
assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29]
reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55]
assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55]
wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46]
wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}]
wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}]
wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46]
wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}]
wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}]
wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46]
wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}]
wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}]
assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}]
assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27]
always @(posedge clock) begin // @[AsyncQueue.scala:70:7]
if (_widx_T_1 & index == 3'h0) // @[Decoupled.scala:51:35]
mem_0_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h1) // @[Decoupled.scala:51:35]
mem_1_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h2) // @[Decoupled.scala:51:35]
mem_2_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h3) // @[Decoupled.scala:51:35]
mem_3_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h4) // @[Decoupled.scala:51:35]
mem_4_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h5) // @[Decoupled.scala:51:35]
mem_5_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h6) // @[Decoupled.scala:51:35]
mem_6_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & (&index)) // @[Decoupled.scala:51:35]
mem_7_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
always @(posedge)
always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30]
if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30]
widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:70:7]
widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35]
if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35]
ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56]
else // @[AsyncQueue.scala:70:7]
ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56]
always @(posedge, posedge)
always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34]
if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34]
widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55]
else // @[AsyncQueue.scala:70:7]
widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PE_446 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_190
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_446( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_190 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_14 :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.conf, UInt<1>(0h0)
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn_14( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [35:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [35:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [35:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [35:0] f4_idx_REG; // @[loop.scala:92:35]
reg [35:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a14d64s5k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_6
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a14d64s5k1z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a14d64s5k1z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<14>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<14>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<14>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a14d64s5k1z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_d_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [13:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [13:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_6 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a14d64s5k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a14d64s5k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module CoherenceManagerWrapper :
output auto : { coupler_to_bus_named_mbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coherent_jbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip l2_ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coh_clock_groups_in : { member : { coh_0 : { clock : Clock, reset : Reset}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst coh_clock_groups of ClockGroupAggregator_coh
inst clockGroup of ClockGroup_5
inst fixedClockNode of FixedClockBroadcast_1
inst broadcast of BundleBridgeNexus_NoOutput_5
inst l2 of InclusiveCache
connect l2.clock, childClock
connect l2.reset, childReset
inst filter of TLFilter
connect filter.clock, childClock
connect filter.reset, childReset
inst InclusiveCache_inner_TLBuffer of TLBuffer_a32d64s6k3z3c
connect InclusiveCache_inner_TLBuffer.clock, childClock
connect InclusiveCache_inner_TLBuffer.reset, childReset
inst InclusiveCache_outer_TLBuffer of TLBuffer_a32d64s3k3z3c
connect InclusiveCache_outer_TLBuffer.clock, childClock
connect InclusiveCache_outer_TLBuffer.reset, childReset
inst cork of TLCacheCork
connect cork.clock, childClock
connect cork.reset, childReset
inst coherent_jbar of TLJbar
connect coherent_jbar.clock, childClock
connect coherent_jbar.reset, childReset
inst binder of BankBinder
connect binder.clock, childClock
connect binder.reset, childReset
inst coupler_to_bus_named_mbus of TLInterconnectCoupler_coh_to_bus_named_mbus
connect coupler_to_bus_named_mbus.clock, childClock
connect coupler_to_bus_named_mbus.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
connect clockGroup.auto.in, coh_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out
connect InclusiveCache_outer_TLBuffer.auto.in, l2.auto.out
connect InclusiveCache_inner_TLBuffer.auto.in, filter.auto.anon_out
connect l2.auto.in, InclusiveCache_inner_TLBuffer.auto.out
connect cork.auto.in, InclusiveCache_outer_TLBuffer.auto.out
connect binder.auto.in, cork.auto.out
connect filter.auto.anon_in, coherent_jbar.auto.anon_out
connect coupler_to_bus_named_mbus.auto.widget_anon_in, binder.auto.out
connect coh_clock_groups.auto.in, auto.coh_clock_groups_in
connect l2.auto.ctrls_ctrl_in, auto.l2_ctrls_ctrl_in
connect coherent_jbar.auto.anon_in, auto.coherent_jbar_anon_in
connect coupler_to_bus_named_mbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_mbus_bus_xing_out.d
connect auto.coupler_to_bus_named_mbus_bus_xing_out.a.bits, coupler_to_bus_named_mbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_mbus_bus_xing_out.a.valid, coupler_to_bus_named_mbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_mbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_mbus_bus_xing_out.a.ready
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset
extmodule plusarg_reader_76 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_77 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9]
input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [5:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28]
wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28]
wire [3:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28]
wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28]
wire _cork_auto_out_a_valid; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26]
wire [3:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26]
wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26]
wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26]
wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26]
wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26]
wire _cork_auto_out_d_ready; // @[Configs.scala:120:26]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69]
wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69]
wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69]
wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69]
wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69]
wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69]
wire _l2_auto_in_a_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_b_valid; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24]
wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24]
wire _l2_auto_in_c_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_d_valid; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24]
wire [5:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24]
wire [63:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24]
wire [5:0] auto_coherent_jbar_anon_in_b_bits_source = 6'h20; // @[ClockDomain.scala:14:9]
wire [5:0] filter_auto_anon_in_b_bits_source = 6'h20; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_b_bits_source = 6'h20; // @[Filter.scala:60:9]
wire [5:0] filter_anonOut_b_bits_source = 6'h20; // @[MixedNode.scala:542:17]
wire [5:0] filter_anonIn_b_bits_source = 6'h20; // @[MixedNode.scala:551:17]
wire [5:0] coherent_jbar_auto_anon_in_b_bits_source = 6'h20; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_out_b_bits_source = 6'h20; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_b_bits_source = 6'h20; // @[MixedNode.scala:542:17]
wire [5:0] coherent_jbar_anonIn_b_bits_source = 6'h20; // @[MixedNode.scala:551:17]
wire [5:0] coherent_jbar_in_0_b_bits_source = 6'h20; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar__anonIn_b_bits_source_T = 6'h20; // @[Xbar.scala:156:69]
wire [5:0] coherent_jbar_out_0_b_bits_source = 6'h20; // @[Xbar.scala:216:19]
wire [5:0] coherent_jbar__requestBOI_uncommonBits_T = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] coherent_jbar_requestBOI_uncommonBits = 6'h20; // @[Parameters.scala:52:56]
wire [5:0] coherent_jbar_portsBIO_filtered_0_bits_source = 6'h20; // @[Xbar.scala:352:24]
wire [7:0] auto_coherent_jbar_anon_in_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9]
wire [7:0] filter_auto_anon_in_b_bits_mask = 8'hFF; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_b_bits_mask = 8'hFF; // @[Filter.scala:60:9]
wire [7:0] filter_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_auto_anon_in_b_bits_mask = 8'hFF; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_out_b_bits_mask = 8'hFF; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] coherent_jbar_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_in_0_b_bits_mask = 8'hFF; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_out_0_b_bits_mask = 8'hFF; // @[Xbar.scala:216:19]
wire [7:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [63:0] auto_coherent_jbar_anon_in_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] filter_auto_anon_in_b_bits_data = 64'h0; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_b_bits_data = 64'h0; // @[Filter.scala:60:9]
wire [63:0] filter_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_auto_anon_in_b_bits_data = 64'h0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_out_b_bits_data = 64'h0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] coherent_jbar_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_in_0_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_out_0_b_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] coherent_jbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28]
wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24]
wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] coherent_jbar_beatsBO_decode = 3'h7; // @[Edges.scala:220:59]
wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9]
wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9]
wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [5:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [5:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [7:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [7:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [63:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [5:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [5:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [63:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [5:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [5:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [5:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [63:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9]
assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9]
assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9]
assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9]
assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9]
assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9]
assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [5:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire [5:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [2:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata ? coherent_jbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata ? coherent_jbar_beatsCI_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata ? coherent_jbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
InclusiveCache l2 ( // @[Configs.scala:93:24]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0),
.auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0),
.auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0),
.auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0),
.auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0),
.auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0),
.auto_in_a_ready (_l2_auto_in_a_ready),
.auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69]
.auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69]
.auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69]
.auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69]
.auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69]
.auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69]
.auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69]
.auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69]
.auto_in_b_valid (_l2_auto_in_b_valid),
.auto_in_b_bits_param (_l2_auto_in_b_bits_param),
.auto_in_b_bits_address (_l2_auto_in_b_bits_address),
.auto_in_c_ready (_l2_auto_in_c_ready),
.auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69]
.auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69]
.auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69]
.auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69]
.auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69]
.auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69]
.auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69]
.auto_in_d_valid (_l2_auto_in_d_valid),
.auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_l2_auto_in_d_bits_param),
.auto_in_d_bits_size (_l2_auto_in_d_bits_size),
.auto_in_d_bits_source (_l2_auto_in_d_bits_source),
.auto_in_d_bits_sink (_l2_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_l2_auto_in_d_bits_denied),
.auto_in_d_bits_data (_l2_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt),
.auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69]
.auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69]
.auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9]
.auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid),
.auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode),
.auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param),
.auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size),
.auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source),
.auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address),
.auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask),
.auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data),
.auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt),
.auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9]
.auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid),
.auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode),
.auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param),
.auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size),
.auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source),
.auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address),
.auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data),
.auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt),
.auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready),
.auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9]
.auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9]
.auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9]
.auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9]
.auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9]
.auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9]
.auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9]
.auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9]
.auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9]
.auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid),
.auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink)
); // @[Configs.scala:93:24]
TLBuffer_a32d64s6k3z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (filter_auto_anon_out_a_ready),
.auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9]
.auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9]
.auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9]
.auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9]
.auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9]
.auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9]
.auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9]
.auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9]
.auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9]
.auto_in_b_valid (filter_auto_anon_out_b_valid),
.auto_in_b_bits_param (filter_auto_anon_out_b_bits_param),
.auto_in_b_bits_address (filter_auto_anon_out_b_bits_address),
.auto_in_c_ready (filter_auto_anon_out_c_ready),
.auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9]
.auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9]
.auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9]
.auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9]
.auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9]
.auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9]
.auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9]
.auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9]
.auto_in_d_valid (filter_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (filter_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (filter_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (filter_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (filter_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt),
.auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9]
.auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9]
.auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24]
.auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt),
.auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready),
.auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24]
.auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24]
.auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24]
.auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24]
.auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid),
.auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode),
.auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param),
.auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size),
.auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source),
.auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address),
.auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data),
.auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt),
.auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready),
.auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24]
.auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24]
.auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24]
.auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24]
.auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24]
.auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24]
.auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24]
.auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24]
.auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24]
.auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid),
.auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink)
); // @[Parameters.scala:56:69]
TLCacheCork cork ( // @[Configs.scala:120:26]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready),
.auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9]
.auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9]
.auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9]
.auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9]
.auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9]
.auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9]
.auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9]
.auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready),
.auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9]
.auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9]
.auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9]
.auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9]
.auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9]
.auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9]
.auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9]
.auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid),
.auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode),
.auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param),
.auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size),
.auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source),
.auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink),
.auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied),
.auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data),
.auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt),
.auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9]
.auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9]
.auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28]
.auto_out_a_valid (_cork_auto_out_a_valid),
.auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_cork_auto_out_a_bits_param),
.auto_out_a_bits_size (_cork_auto_out_a_bits_size),
.auto_out_a_bits_source (_cork_auto_out_a_bits_source),
.auto_out_a_bits_address (_cork_auto_out_a_bits_address),
.auto_out_a_bits_mask (_cork_auto_out_a_bits_mask),
.auto_out_a_bits_data (_cork_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt),
.auto_out_d_ready (_cork_auto_out_d_ready),
.auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28]
.auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28]
.auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28]
.auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28]
.auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28]
.auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28]
.auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28]
.auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28]
.auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28]
); // @[Configs.scala:120:26]
BankBinder binder ( // @[BankBinder.scala:71:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_binder_auto_in_a_ready),
.auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26]
.auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26]
.auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26]
.auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26]
.auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26]
.auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26]
.auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26]
.auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26]
.auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26]
.auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26]
.auto_in_d_valid (_binder_auto_in_d_valid),
.auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_binder_auto_in_d_bits_param),
.auto_in_d_bits_size (_binder_auto_in_d_bits_size),
.auto_in_d_bits_source (_binder_auto_in_d_bits_source),
.auto_in_d_bits_sink (_binder_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_binder_auto_in_d_bits_denied),
.auto_in_d_bits_data (_binder_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt),
.auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid),
.auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode),
.auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param),
.auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size),
.auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source),
.auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address),
.auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask),
.auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt),
.auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready),
.auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7]
); // @[BankBinder.scala:71:28]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_240 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_240( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ITLB :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>}
invalidate io.ptw.customCSRs.csrs[0].sdata
invalidate io.ptw.customCSRs.csrs[0].set
invalidate io.ptw.customCSRs.csrs[0].stall
invalidate io.ptw.customCSRs.csrs[0].value
invalidate io.ptw.customCSRs.csrs[0].wdata
invalidate io.ptw.customCSRs.csrs[0].wen
invalidate io.ptw.customCSRs.csrs[0].ren
invalidate io.ptw.customCSRs.csrs[1].sdata
invalidate io.ptw.customCSRs.csrs[1].set
invalidate io.ptw.customCSRs.csrs[1].stall
invalidate io.ptw.customCSRs.csrs[1].value
invalidate io.ptw.customCSRs.csrs[1].wdata
invalidate io.ptw.customCSRs.csrs[1].wen
invalidate io.ptw.customCSRs.csrs[1].ren
invalidate io.ptw.customCSRs.csrs[2].sdata
invalidate io.ptw.customCSRs.csrs[2].set
invalidate io.ptw.customCSRs.csrs[2].stall
invalidate io.ptw.customCSRs.csrs[2].value
invalidate io.ptw.customCSRs.csrs[2].wdata
invalidate io.ptw.customCSRs.csrs[2].wen
invalidate io.ptw.customCSRs.csrs[2].ren
invalidate io.ptw.customCSRs.csrs[3].sdata
invalidate io.ptw.customCSRs.csrs[3].set
invalidate io.ptw.customCSRs.csrs[3].stall
invalidate io.ptw.customCSRs.csrs[3].value
invalidate io.ptw.customCSRs.csrs[3].wdata
invalidate io.ptw.customCSRs.csrs[3].wen
invalidate io.ptw.customCSRs.csrs[3].ren
node vpn = bits(io.req.bits.vaddr, 32, 12)
reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock
reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock
reg special_entry : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
reg r_refill_tag : UInt<21>, clock
reg r_superpage_repl_addr : UInt<2>, clock
reg r_sectored_repl_addr : UInt<3>, clock
reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock
reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock
reg r_vstage1_en : UInt<1>, clock
reg r_stage2_en : UInt<1>, clock
reg r_need_gpa : UInt<1>, clock
reg r_gpa_valid : UInt<1>, clock
reg r_gpa : UInt<33>, clock
reg r_gpa_vpn : UInt<21>, clock
reg r_gpa_is_pte : UInt<1>, clock
node priv_v = and(UInt<1>(0h0), io.req.bits.v)
node priv_s = bits(io.req.bits.prv, 0, 0)
node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1))
node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
node _stage1_en_T = bits(satp.mode, 3, 3)
node stage1_en = and(UInt<1>(0h0), _stage1_en_T)
node _vstage1_en_T = and(UInt<1>(0h0), priv_v)
node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3)
node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1)
node _stage2_en_T = and(UInt<1>(0h0), priv_v)
node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3)
node stage2_en = and(_stage2_en_T, _stage2_en_T_1)
node _vm_enabled_T = or(stage1_en, stage2_en)
node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm)
node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2)
regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1)
node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T)
node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2)
node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0)
node do_refill = and(UInt<1>(0h0), io.ptw.resp.valid)
node _invalidate_refill_T = eq(state, UInt<2>(0h1))
node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3))
node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1)
node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid)
node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1))
wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _mpu_ppn_WIRE_1 : UInt<42>
connect _mpu_ppn_WIRE_1, special_entry.data[0]
node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0)
connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1
node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1)
connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2
node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2)
connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3
node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3)
connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4
node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4)
connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5
node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5)
connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6
node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6)
connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7
node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7)
connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8
node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8)
connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9
node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9)
connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10
node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10)
connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11
node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11)
connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12
node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12)
connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13
node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13)
connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14
node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14)
connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15
node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15)
connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16
node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16)
connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17
node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17)
connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18
node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18)
connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19
node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19)
connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20
node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20)
connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21
node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21)
connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22
node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22)
connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23
inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_28
connect mpu_ppn_barrier.clock, clock
connect mpu_ppn_barrier.reset, reset
connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage
connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c
connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff
connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa
connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal
connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp
connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr
connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px
connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw
connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr
connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx
connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw
connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr
connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx
connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw
connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf
connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf
connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2
connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final
connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw
connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g
connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u
connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn
node _mpu_ppn_T_24 = shr(io.req.bits.vaddr, 12)
node _mpu_ppn_T_25 = mux(_mpu_ppn_T, mpu_ppn_barrier.io.y.ppn, _mpu_ppn_T_24)
node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_25)
node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0)
node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T)
node _mpu_priv_T = or(do_refill, io.req.bits.passthrough)
node _mpu_priv_T_1 = and(UInt<1>(0h0), _mpu_priv_T)
node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv)
node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2)
inst pmp of PMPChecker_s2
connect pmp.clock, clock
connect pmp.reset, reset
connect pmp.io.addr, mpu_physaddr
connect pmp.io.size, io.req.bits.size
connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask
connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr
connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r
connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w
connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x
connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a
connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res
connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l
connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask
connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr
connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r
connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w
connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x
connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a
connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res
connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l
connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask
connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr
connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r
connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w
connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x
connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a
connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res
connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l
connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask
connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr
connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r
connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w
connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x
connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a
connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res
connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l
connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask
connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr
connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r
connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w
connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x
connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a
connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res
connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l
connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask
connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr
connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r
connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w
connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x
connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a
connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res
connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l
connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask
connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr
connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r
connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w
connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x
connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a
connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res
connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l
connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask
connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr
connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r
connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w
connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x
connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a
connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res
connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l
connect pmp.io.prv, mpu_priv
inst pma of PMAChecker_2
connect pma.clock, clock
connect pma.reset, reset
connect pma.io.paddr, mpu_physaddr
node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1))
node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_1 = cvt(_homogeneous_T)
node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000)))
node _homogeneous_T_3 = asSInt(_homogeneous_T_2)
node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0)))
node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_6 = cvt(_homogeneous_T_5)
node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_8 = asSInt(_homogeneous_T_7)
node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0)))
node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_11 = cvt(_homogeneous_T_10)
node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_13 = asSInt(_homogeneous_T_12)
node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0)))
node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000))
node _homogeneous_T_16 = cvt(_homogeneous_T_15)
node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000)))
node _homogeneous_T_18 = asSInt(_homogeneous_T_17)
node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0)))
node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000))
node _homogeneous_T_21 = cvt(_homogeneous_T_20)
node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_23 = asSInt(_homogeneous_T_22)
node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0)))
node _homogeneous_T_25 = xor(mpu_physaddr, UInt<28>(0hc000000))
node _homogeneous_T_26 = cvt(_homogeneous_T_25)
node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<27>(0h4000000)))
node _homogeneous_T_28 = asSInt(_homogeneous_T_27)
node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0)))
node _homogeneous_T_30 = xor(mpu_physaddr, UInt<29>(0h10020000))
node _homogeneous_T_31 = cvt(_homogeneous_T_30)
node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_33 = asSInt(_homogeneous_T_32)
node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0)))
node _homogeneous_T_35 = xor(mpu_physaddr, UInt<31>(0h60000000))
node _homogeneous_T_36 = cvt(_homogeneous_T_35)
node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<30>(0h20000000)))
node _homogeneous_T_38 = asSInt(_homogeneous_T_37)
node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0)))
node _homogeneous_T_40 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_41 = cvt(_homogeneous_T_40)
node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<15>(0h4000)))
node _homogeneous_T_43 = asSInt(_homogeneous_T_42)
node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0)))
node _homogeneous_T_45 = or(UInt<1>(0h0), _homogeneous_T_4)
node _homogeneous_T_46 = or(_homogeneous_T_45, _homogeneous_T_9)
node _homogeneous_T_47 = or(_homogeneous_T_46, _homogeneous_T_14)
node _homogeneous_T_48 = or(_homogeneous_T_47, _homogeneous_T_19)
node _homogeneous_T_49 = or(_homogeneous_T_48, _homogeneous_T_24)
node _homogeneous_T_50 = or(_homogeneous_T_49, _homogeneous_T_29)
node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_34)
node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_39)
node homogeneous = or(_homogeneous_T_52, _homogeneous_T_44)
node _homogeneous_T_53 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_54 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_55 = cvt(_homogeneous_T_54)
node _homogeneous_T_56 = and(_homogeneous_T_55, asSInt(UInt<33>(0hd8110000)))
node _homogeneous_T_57 = asSInt(_homogeneous_T_56)
node _homogeneous_T_58 = eq(_homogeneous_T_57, asSInt(UInt<1>(0h0)))
node _homogeneous_T_59 = or(UInt<1>(0h0), _homogeneous_T_58)
node _homogeneous_T_60 = eq(_homogeneous_T_59, UInt<1>(0h0))
node _homogeneous_T_61 = xor(mpu_physaddr, UInt<13>(0h1000))
node _homogeneous_T_62 = cvt(_homogeneous_T_61)
node _homogeneous_T_63 = and(_homogeneous_T_62, asSInt(UInt<33>(0hda113000)))
node _homogeneous_T_64 = asSInt(_homogeneous_T_63)
node _homogeneous_T_65 = eq(_homogeneous_T_64, asSInt(UInt<1>(0h0)))
node _homogeneous_T_66 = xor(mpu_physaddr, UInt<21>(0h100000))
node _homogeneous_T_67 = cvt(_homogeneous_T_66)
node _homogeneous_T_68 = and(_homogeneous_T_67, asSInt(UInt<33>(0hda103000)))
node _homogeneous_T_69 = asSInt(_homogeneous_T_68)
node _homogeneous_T_70 = eq(_homogeneous_T_69, asSInt(UInt<1>(0h0)))
node _homogeneous_T_71 = xor(mpu_physaddr, UInt<26>(0h2000000))
node _homogeneous_T_72 = cvt(_homogeneous_T_71)
node _homogeneous_T_73 = and(_homogeneous_T_72, asSInt(UInt<33>(0hda110000)))
node _homogeneous_T_74 = asSInt(_homogeneous_T_73)
node _homogeneous_T_75 = eq(_homogeneous_T_74, asSInt(UInt<1>(0h0)))
node _homogeneous_T_76 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_77 = cvt(_homogeneous_T_76)
node _homogeneous_T_78 = and(_homogeneous_T_77, asSInt(UInt<33>(0hd8000000)))
node _homogeneous_T_79 = asSInt(_homogeneous_T_78)
node _homogeneous_T_80 = eq(_homogeneous_T_79, asSInt(UInt<1>(0h0)))
node _homogeneous_T_81 = xor(mpu_physaddr, UInt<29>(0h10000000))
node _homogeneous_T_82 = cvt(_homogeneous_T_81)
node _homogeneous_T_83 = and(_homogeneous_T_82, asSInt(UInt<33>(0hda113000)))
node _homogeneous_T_84 = asSInt(_homogeneous_T_83)
node _homogeneous_T_85 = eq(_homogeneous_T_84, asSInt(UInt<1>(0h0)))
node _homogeneous_T_86 = or(UInt<1>(0h0), _homogeneous_T_65)
node _homogeneous_T_87 = or(_homogeneous_T_86, _homogeneous_T_70)
node _homogeneous_T_88 = or(_homogeneous_T_87, _homogeneous_T_75)
node _homogeneous_T_89 = or(_homogeneous_T_88, _homogeneous_T_80)
node _homogeneous_T_90 = or(_homogeneous_T_89, _homogeneous_T_85)
node _homogeneous_T_91 = eq(_homogeneous_T_90, UInt<1>(0h0))
node _homogeneous_T_92 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_93 = cvt(_homogeneous_T_92)
node _homogeneous_T_94 = and(_homogeneous_T_93, asSInt(UInt<33>(0hd8110000)))
node _homogeneous_T_95 = asSInt(_homogeneous_T_94)
node _homogeneous_T_96 = eq(_homogeneous_T_95, asSInt(UInt<1>(0h0)))
node _homogeneous_T_97 = xor(mpu_physaddr, UInt<31>(0h40000000))
node _homogeneous_T_98 = cvt(_homogeneous_T_97)
node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0hc0000000)))
node _homogeneous_T_100 = asSInt(_homogeneous_T_99)
node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0)))
node _homogeneous_T_102 = or(UInt<1>(0h0), _homogeneous_T_96)
node _homogeneous_T_103 = or(_homogeneous_T_102, _homogeneous_T_101)
node _homogeneous_T_104 = eq(_homogeneous_T_103, UInt<1>(0h0))
node _homogeneous_T_105 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_106 = cvt(_homogeneous_T_105)
node _homogeneous_T_107 = and(_homogeneous_T_106, asSInt(UInt<33>(0hd8110000)))
node _homogeneous_T_108 = asSInt(_homogeneous_T_107)
node _homogeneous_T_109 = eq(_homogeneous_T_108, asSInt(UInt<1>(0h0)))
node _homogeneous_T_110 = xor(mpu_physaddr, UInt<31>(0h40000000))
node _homogeneous_T_111 = cvt(_homogeneous_T_110)
node _homogeneous_T_112 = and(_homogeneous_T_111, asSInt(UInt<33>(0hc0000000)))
node _homogeneous_T_113 = asSInt(_homogeneous_T_112)
node _homogeneous_T_114 = eq(_homogeneous_T_113, asSInt(UInt<1>(0h0)))
node _homogeneous_T_115 = or(UInt<1>(0h0), _homogeneous_T_109)
node _homogeneous_T_116 = or(_homogeneous_T_115, _homogeneous_T_114)
node _homogeneous_T_117 = eq(_homogeneous_T_116, UInt<1>(0h0))
node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3))
node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0))
node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1)
node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000)))
node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3)
node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0)))
node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5)
node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T)
node prot_r = and(_prot_r_T_1, pmp.io.r)
node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T)
node prot_w = and(_prot_w_T_1, pmp.io.w)
node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T)
node prot_x = and(_prot_x_T_1, pmp.io.x)
node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2])
node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3])
node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _sector_hits_T_4 = shr(_sector_hits_T_3, 2)
node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0))
node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v)
node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6)
node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7)
node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2])
node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3])
node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _sector_hits_T_12 = shr(_sector_hits_T_11, 2)
node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0))
node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v)
node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14)
node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15)
node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2])
node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3])
node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _sector_hits_T_20 = shr(_sector_hits_T_19, 2)
node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0))
node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v)
node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22)
node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23)
node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2])
node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3])
node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _sector_hits_T_28 = shr(_sector_hits_T_27, 2)
node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0))
node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v)
node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30)
node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31)
node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2])
node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3])
node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _sector_hits_T_36 = shr(_sector_hits_T_35, 2)
node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0))
node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v)
node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38)
node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39)
node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2])
node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3])
node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _sector_hits_T_44 = shr(_sector_hits_T_43, 2)
node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0))
node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v)
node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46)
node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47)
node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2])
node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3])
node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _sector_hits_T_52 = shr(_sector_hits_T_51, 2)
node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0))
node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v)
node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54)
node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55)
node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2])
node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3])
node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _sector_hits_T_60 = shr(_sector_hits_T_59, 2)
node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0))
node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v)
node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62)
node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63)
node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_1 = shr(_superpage_hits_T, 0)
node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0))
node _superpage_hits_T_3 = eq(superpage_entries[0].tag_v, priv_v)
node _superpage_hits_T_4 = and(_superpage_hits_T_2, _superpage_hits_T_3)
node superpage_hits_0 = and(superpage_entries[0].valid[0], _superpage_hits_T_4)
node _superpage_hits_T_5 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_6 = shr(_superpage_hits_T_5, 0)
node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0))
node _superpage_hits_T_8 = eq(superpage_entries[1].tag_v, priv_v)
node _superpage_hits_T_9 = and(_superpage_hits_T_7, _superpage_hits_T_8)
node superpage_hits_1 = and(superpage_entries[1].valid[0], _superpage_hits_T_9)
node _superpage_hits_T_10 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_11 = shr(_superpage_hits_T_10, 0)
node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0))
node _superpage_hits_T_13 = eq(superpage_entries[2].tag_v, priv_v)
node _superpage_hits_T_14 = and(_superpage_hits_T_12, _superpage_hits_T_13)
node superpage_hits_2 = and(superpage_entries[2].valid[0], _superpage_hits_T_14)
node _superpage_hits_T_15 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_16 = shr(_superpage_hits_T_15, 0)
node _superpage_hits_T_17 = eq(_superpage_hits_T_16, UInt<1>(0h0))
node _superpage_hits_T_18 = eq(superpage_entries[3].tag_v, priv_v)
node _superpage_hits_T_19 = and(_superpage_hits_T_17, _superpage_hits_T_18)
node superpage_hits_3 = and(superpage_entries[3].valid[0], _superpage_hits_T_19)
node hitsVec_idx = bits(vpn, 1, 0)
node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn)
node _hitsVec_T_1 = shr(_hitsVec_T, 2)
node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0))
node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v)
node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3)
node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4)
node hitsVec_0 = and(vm_enabled, _hitsVec_T_5)
node hitsVec_idx_1 = bits(vpn, 1, 0)
node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _hitsVec_T_7 = shr(_hitsVec_T_6, 2)
node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0))
node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v)
node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9)
node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10)
node hitsVec_1 = and(vm_enabled, _hitsVec_T_11)
node hitsVec_idx_2 = bits(vpn, 1, 0)
node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _hitsVec_T_13 = shr(_hitsVec_T_12, 2)
node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0))
node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v)
node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15)
node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16)
node hitsVec_2 = and(vm_enabled, _hitsVec_T_17)
node hitsVec_idx_3 = bits(vpn, 1, 0)
node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _hitsVec_T_19 = shr(_hitsVec_T_18, 2)
node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0))
node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v)
node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21)
node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22)
node hitsVec_3 = and(vm_enabled, _hitsVec_T_23)
node hitsVec_idx_4 = bits(vpn, 1, 0)
node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _hitsVec_T_25 = shr(_hitsVec_T_24, 2)
node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0))
node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v)
node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27)
node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28)
node hitsVec_4 = and(vm_enabled, _hitsVec_T_29)
node hitsVec_idx_5 = bits(vpn, 1, 0)
node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _hitsVec_T_31 = shr(_hitsVec_T_30, 2)
node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0))
node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v)
node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33)
node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34)
node hitsVec_5 = and(vm_enabled, _hitsVec_T_35)
node hitsVec_idx_6 = bits(vpn, 1, 0)
node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _hitsVec_T_37 = shr(_hitsVec_T_36, 2)
node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0))
node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v)
node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39)
node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40)
node hitsVec_6 = and(vm_enabled, _hitsVec_T_41)
node hitsVec_idx_7 = bits(vpn, 1, 0)
node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _hitsVec_T_43 = shr(_hitsVec_T_42, 2)
node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0))
node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v)
node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45)
node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46)
node hitsVec_7 = and(vm_enabled, _hitsVec_T_47)
node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_49 = shr(_hitsVec_T_48, 0)
node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0))
node _hitsVec_T_51 = eq(superpage_entries[0].tag_v, priv_v)
node _hitsVec_T_52 = and(_hitsVec_T_50, _hitsVec_T_51)
node _hitsVec_T_53 = and(superpage_entries[0].valid[0], _hitsVec_T_52)
node hitsVec_8 = and(vm_enabled, _hitsVec_T_53)
node _hitsVec_T_54 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_55 = shr(_hitsVec_T_54, 0)
node _hitsVec_T_56 = eq(_hitsVec_T_55, UInt<1>(0h0))
node _hitsVec_T_57 = eq(superpage_entries[1].tag_v, priv_v)
node _hitsVec_T_58 = and(_hitsVec_T_56, _hitsVec_T_57)
node _hitsVec_T_59 = and(superpage_entries[1].valid[0], _hitsVec_T_58)
node hitsVec_9 = and(vm_enabled, _hitsVec_T_59)
node _hitsVec_T_60 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_61 = shr(_hitsVec_T_60, 0)
node _hitsVec_T_62 = eq(_hitsVec_T_61, UInt<1>(0h0))
node _hitsVec_T_63 = eq(superpage_entries[2].tag_v, priv_v)
node _hitsVec_T_64 = and(_hitsVec_T_62, _hitsVec_T_63)
node _hitsVec_T_65 = and(superpage_entries[2].valid[0], _hitsVec_T_64)
node hitsVec_10 = and(vm_enabled, _hitsVec_T_65)
node _hitsVec_T_66 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_67 = shr(_hitsVec_T_66, 0)
node _hitsVec_T_68 = eq(_hitsVec_T_67, UInt<1>(0h0))
node _hitsVec_T_69 = eq(superpage_entries[3].tag_v, priv_v)
node _hitsVec_T_70 = and(_hitsVec_T_68, _hitsVec_T_69)
node _hitsVec_T_71 = and(superpage_entries[3].valid[0], _hitsVec_T_70)
node hitsVec_11 = and(vm_enabled, _hitsVec_T_71)
node _hitsVec_T_72 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_73 = shr(_hitsVec_T_72, 0)
node _hitsVec_T_74 = eq(_hitsVec_T_73, UInt<1>(0h0))
node _hitsVec_T_75 = eq(special_entry.tag_v, priv_v)
node _hitsVec_T_76 = and(_hitsVec_T_74, _hitsVec_T_75)
node _hitsVec_T_77 = and(special_entry.valid[0], _hitsVec_T_76)
node hitsVec_12 = and(vm_enabled, _hitsVec_T_77)
node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1)
node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0)
node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4)
node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3)
node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo)
node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7)
node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6)
node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9)
node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11)
node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo)
node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo)
node real_hits = cat(real_hits_hi, real_hits_lo)
node _hits_T = eq(vm_enabled, UInt<1>(0h0))
node hits = cat(_hits_T, real_hits)
when do_refill :
node refill_v = or(r_vstage1_en, r_stage2_en)
wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
connect newEntry.ppn, io.ptw.resp.bits.pte.ppn
connect newEntry.c, cacheable
connect newEntry.u, io.ptw.resp.bits.pte.u
node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v)
connect newEntry.g, _newEntry_g_T
connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw
connect newEntry.ae_final, io.ptw.resp.bits.ae_final
node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte)
node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en)
connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1
connect newEntry.pf, io.ptw.resp.bits.pf
connect newEntry.gf, io.ptw.resp.bits.gf
connect newEntry.hr, io.ptw.resp.bits.hr
connect newEntry.hw, io.ptw.resp.bits.hw
connect newEntry.hx, io.ptw.resp.bits.hx
node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T)
node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1)
node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2)
node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r)
connect newEntry.sr, _newEntry_sr_T_5
node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T)
node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1)
node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2)
node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w)
node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d)
connect newEntry.sw, _newEntry_sw_T_6
node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T)
node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1)
node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2)
node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x)
connect newEntry.sx, _newEntry_sx_T_5
connect newEntry.pr, prot_r
connect newEntry.pw, prot_w
connect newEntry.px, prot_x
connect newEntry.ppp, pma.io.resp.pp
connect newEntry.pal, pma.io.resp.al
connect newEntry.paa, pma.io.resp.aa
connect newEntry.eff, pma.io.resp.eff
connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage
node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
when _T_1 :
connect special_entry.tag_vpn, r_refill_tag
connect special_entry.tag_v, refill_v
node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0)
connect special_entry.level, _special_entry_level_T
connect special_entry.valid[0], UInt<1>(0h1)
node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff)
node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo)
node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp)
node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw)
node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo)
node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo)
node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw)
node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw)
node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo)
node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g)
node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo)
node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo)
node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo)
connect special_entry.data[0], _special_entry_data_0_T
else :
node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2))
when _T_2 :
node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0))
node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr)
node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0))
when _T_3 :
connect superpage_entries[0].tag_vpn, r_refill_tag
connect superpage_entries[0].tag_v, refill_v
node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[0].level, _superpage_entries_0_level_T
connect superpage_entries[0].valid[0], UInt<1>(0h1)
node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo)
node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo)
node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo)
node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo)
node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo)
node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo)
node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo)
connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T
when invalidate_refill :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1))
when _T_4 :
connect superpage_entries[1].tag_vpn, r_refill_tag
connect superpage_entries[1].tag_v, refill_v
node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[1].level, _superpage_entries_1_level_T
connect superpage_entries[1].valid[0], UInt<1>(0h1)
node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo)
node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo)
node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo)
node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo)
node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo)
node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo)
node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo)
connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T
when invalidate_refill :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2))
when _T_5 :
connect superpage_entries[2].tag_vpn, r_refill_tag
connect superpage_entries[2].tag_v, refill_v
node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[2].level, _superpage_entries_2_level_T
connect superpage_entries[2].valid[0], UInt<1>(0h1)
node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo)
node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo)
node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo)
node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo)
node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo)
node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo)
node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo)
connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T
when invalidate_refill :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3))
when _T_6 :
connect superpage_entries[3].tag_vpn, r_refill_tag
connect superpage_entries[3].tag_v, refill_v
node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[3].level, _superpage_entries_3_level_T
connect superpage_entries[3].valid[0], UInt<1>(0h1)
node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo)
node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo)
node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo)
node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo)
node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo)
node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo)
node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo)
connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T
when invalidate_refill :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
node _T_7 = eq(waddr_1, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_8 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][0].tag_vpn, r_refill_tag
connect sectored_entries[0][0].tag_v, refill_v
connect sectored_entries[0][0].level, UInt<2>(0h0)
node idx = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][0].valid[idx], UInt<1>(0h1)
node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo)
node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo)
node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo)
node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo)
node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo)
node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo)
node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo)
connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T
when invalidate_refill :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_9 = eq(waddr_1, UInt<1>(0h1))
when _T_9 :
node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_10 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].tag_vpn, r_refill_tag
connect sectored_entries[0][1].tag_v, refill_v
connect sectored_entries[0][1].level, UInt<2>(0h0)
node idx_1 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1)
node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo)
node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo)
node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo)
node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo)
node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo)
node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo)
node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo)
connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T
when invalidate_refill :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_11 = eq(waddr_1, UInt<2>(0h2))
when _T_11 :
node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_12 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].tag_vpn, r_refill_tag
connect sectored_entries[0][2].tag_v, refill_v
connect sectored_entries[0][2].level, UInt<2>(0h0)
node idx_2 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1)
node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo)
node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo)
node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo)
node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo)
node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo)
node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo)
node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo)
connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T
when invalidate_refill :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_13 = eq(waddr_1, UInt<2>(0h3))
when _T_13 :
node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_14 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].tag_vpn, r_refill_tag
connect sectored_entries[0][3].tag_v, refill_v
connect sectored_entries[0][3].level, UInt<2>(0h0)
node idx_3 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1)
node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo)
node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo)
node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo)
node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo)
node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo)
node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo)
node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo)
connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T
when invalidate_refill :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_15 = eq(waddr_1, UInt<3>(0h4))
when _T_15 :
node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_16 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].tag_vpn, r_refill_tag
connect sectored_entries[0][4].tag_v, refill_v
connect sectored_entries[0][4].level, UInt<2>(0h0)
node idx_4 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1)
node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo)
node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo)
node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo)
node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo)
node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo)
node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo)
node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo)
connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T
when invalidate_refill :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_17 = eq(waddr_1, UInt<3>(0h5))
when _T_17 :
node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_18 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].tag_vpn, r_refill_tag
connect sectored_entries[0][5].tag_v, refill_v
connect sectored_entries[0][5].level, UInt<2>(0h0)
node idx_5 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1)
node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo)
node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo)
node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo)
node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo)
node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo)
node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo)
node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo)
connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T
when invalidate_refill :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_19 = eq(waddr_1, UInt<3>(0h6))
when _T_19 :
node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_20 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].tag_vpn, r_refill_tag
connect sectored_entries[0][6].tag_v, refill_v
connect sectored_entries[0][6].level, UInt<2>(0h0)
node idx_6 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1)
node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo)
node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo)
node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo)
node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo)
node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo)
node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo)
node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo)
connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T
when invalidate_refill :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_21 = eq(waddr_1, UInt<3>(0h7))
when _T_21 :
node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_22 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].tag_vpn, r_refill_tag
connect sectored_entries[0][7].tag_v, refill_v
connect sectored_entries[0][7].level, UInt<2>(0h0)
node idx_7 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1)
node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo)
node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo)
node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo)
node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo)
node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo)
node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo)
node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo)
connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T
when invalidate_refill :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect r_gpa_valid, io.ptw.resp.bits.gpa.valid
connect r_gpa, io.ptw.resp.bits.gpa.bits
connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte
node _entries_T = bits(vpn, 1, 0)
wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_1 : UInt<42>
connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T]
node _entries_T_1 = bits(_entries_WIRE_1, 0, 0)
connect _entries_WIRE.fragmented_superpage, _entries_T_1
node _entries_T_2 = bits(_entries_WIRE_1, 1, 1)
connect _entries_WIRE.c, _entries_T_2
node _entries_T_3 = bits(_entries_WIRE_1, 2, 2)
connect _entries_WIRE.eff, _entries_T_3
node _entries_T_4 = bits(_entries_WIRE_1, 3, 3)
connect _entries_WIRE.paa, _entries_T_4
node _entries_T_5 = bits(_entries_WIRE_1, 4, 4)
connect _entries_WIRE.pal, _entries_T_5
node _entries_T_6 = bits(_entries_WIRE_1, 5, 5)
connect _entries_WIRE.ppp, _entries_T_6
node _entries_T_7 = bits(_entries_WIRE_1, 6, 6)
connect _entries_WIRE.pr, _entries_T_7
node _entries_T_8 = bits(_entries_WIRE_1, 7, 7)
connect _entries_WIRE.px, _entries_T_8
node _entries_T_9 = bits(_entries_WIRE_1, 8, 8)
connect _entries_WIRE.pw, _entries_T_9
node _entries_T_10 = bits(_entries_WIRE_1, 9, 9)
connect _entries_WIRE.hr, _entries_T_10
node _entries_T_11 = bits(_entries_WIRE_1, 10, 10)
connect _entries_WIRE.hx, _entries_T_11
node _entries_T_12 = bits(_entries_WIRE_1, 11, 11)
connect _entries_WIRE.hw, _entries_T_12
node _entries_T_13 = bits(_entries_WIRE_1, 12, 12)
connect _entries_WIRE.sr, _entries_T_13
node _entries_T_14 = bits(_entries_WIRE_1, 13, 13)
connect _entries_WIRE.sx, _entries_T_14
node _entries_T_15 = bits(_entries_WIRE_1, 14, 14)
connect _entries_WIRE.sw, _entries_T_15
node _entries_T_16 = bits(_entries_WIRE_1, 15, 15)
connect _entries_WIRE.gf, _entries_T_16
node _entries_T_17 = bits(_entries_WIRE_1, 16, 16)
connect _entries_WIRE.pf, _entries_T_17
node _entries_T_18 = bits(_entries_WIRE_1, 17, 17)
connect _entries_WIRE.ae_stage2, _entries_T_18
node _entries_T_19 = bits(_entries_WIRE_1, 18, 18)
connect _entries_WIRE.ae_final, _entries_T_19
node _entries_T_20 = bits(_entries_WIRE_1, 19, 19)
connect _entries_WIRE.ae_ptw, _entries_T_20
node _entries_T_21 = bits(_entries_WIRE_1, 20, 20)
connect _entries_WIRE.g, _entries_T_21
node _entries_T_22 = bits(_entries_WIRE_1, 21, 21)
connect _entries_WIRE.u, _entries_T_22
node _entries_T_23 = bits(_entries_WIRE_1, 41, 22)
connect _entries_WIRE.ppn, _entries_T_23
inst entries_barrier of OptimizationBarrier_TLBEntryData_29
connect entries_barrier.clock, clock
connect entries_barrier.reset, reset
connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage
connect entries_barrier.io.x.c, _entries_WIRE.c
connect entries_barrier.io.x.eff, _entries_WIRE.eff
connect entries_barrier.io.x.paa, _entries_WIRE.paa
connect entries_barrier.io.x.pal, _entries_WIRE.pal
connect entries_barrier.io.x.ppp, _entries_WIRE.ppp
connect entries_barrier.io.x.pr, _entries_WIRE.pr
connect entries_barrier.io.x.px, _entries_WIRE.px
connect entries_barrier.io.x.pw, _entries_WIRE.pw
connect entries_barrier.io.x.hr, _entries_WIRE.hr
connect entries_barrier.io.x.hx, _entries_WIRE.hx
connect entries_barrier.io.x.hw, _entries_WIRE.hw
connect entries_barrier.io.x.sr, _entries_WIRE.sr
connect entries_barrier.io.x.sx, _entries_WIRE.sx
connect entries_barrier.io.x.sw, _entries_WIRE.sw
connect entries_barrier.io.x.gf, _entries_WIRE.gf
connect entries_barrier.io.x.pf, _entries_WIRE.pf
connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2
connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final
connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw
connect entries_barrier.io.x.g, _entries_WIRE.g
connect entries_barrier.io.x.u, _entries_WIRE.u
connect entries_barrier.io.x.ppn, _entries_WIRE.ppn
node _entries_T_24 = bits(vpn, 1, 0)
wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_3 : UInt<42>
connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24]
node _entries_T_25 = bits(_entries_WIRE_3, 0, 0)
connect _entries_WIRE_2.fragmented_superpage, _entries_T_25
node _entries_T_26 = bits(_entries_WIRE_3, 1, 1)
connect _entries_WIRE_2.c, _entries_T_26
node _entries_T_27 = bits(_entries_WIRE_3, 2, 2)
connect _entries_WIRE_2.eff, _entries_T_27
node _entries_T_28 = bits(_entries_WIRE_3, 3, 3)
connect _entries_WIRE_2.paa, _entries_T_28
node _entries_T_29 = bits(_entries_WIRE_3, 4, 4)
connect _entries_WIRE_2.pal, _entries_T_29
node _entries_T_30 = bits(_entries_WIRE_3, 5, 5)
connect _entries_WIRE_2.ppp, _entries_T_30
node _entries_T_31 = bits(_entries_WIRE_3, 6, 6)
connect _entries_WIRE_2.pr, _entries_T_31
node _entries_T_32 = bits(_entries_WIRE_3, 7, 7)
connect _entries_WIRE_2.px, _entries_T_32
node _entries_T_33 = bits(_entries_WIRE_3, 8, 8)
connect _entries_WIRE_2.pw, _entries_T_33
node _entries_T_34 = bits(_entries_WIRE_3, 9, 9)
connect _entries_WIRE_2.hr, _entries_T_34
node _entries_T_35 = bits(_entries_WIRE_3, 10, 10)
connect _entries_WIRE_2.hx, _entries_T_35
node _entries_T_36 = bits(_entries_WIRE_3, 11, 11)
connect _entries_WIRE_2.hw, _entries_T_36
node _entries_T_37 = bits(_entries_WIRE_3, 12, 12)
connect _entries_WIRE_2.sr, _entries_T_37
node _entries_T_38 = bits(_entries_WIRE_3, 13, 13)
connect _entries_WIRE_2.sx, _entries_T_38
node _entries_T_39 = bits(_entries_WIRE_3, 14, 14)
connect _entries_WIRE_2.sw, _entries_T_39
node _entries_T_40 = bits(_entries_WIRE_3, 15, 15)
connect _entries_WIRE_2.gf, _entries_T_40
node _entries_T_41 = bits(_entries_WIRE_3, 16, 16)
connect _entries_WIRE_2.pf, _entries_T_41
node _entries_T_42 = bits(_entries_WIRE_3, 17, 17)
connect _entries_WIRE_2.ae_stage2, _entries_T_42
node _entries_T_43 = bits(_entries_WIRE_3, 18, 18)
connect _entries_WIRE_2.ae_final, _entries_T_43
node _entries_T_44 = bits(_entries_WIRE_3, 19, 19)
connect _entries_WIRE_2.ae_ptw, _entries_T_44
node _entries_T_45 = bits(_entries_WIRE_3, 20, 20)
connect _entries_WIRE_2.g, _entries_T_45
node _entries_T_46 = bits(_entries_WIRE_3, 21, 21)
connect _entries_WIRE_2.u, _entries_T_46
node _entries_T_47 = bits(_entries_WIRE_3, 41, 22)
connect _entries_WIRE_2.ppn, _entries_T_47
inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_30
connect entries_barrier_1.clock, clock
connect entries_barrier_1.reset, reset
connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage
connect entries_barrier_1.io.x.c, _entries_WIRE_2.c
connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff
connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa
connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal
connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp
connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr
connect entries_barrier_1.io.x.px, _entries_WIRE_2.px
connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw
connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr
connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx
connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw
connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr
connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx
connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw
connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf
connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf
connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2
connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final
connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw
connect entries_barrier_1.io.x.g, _entries_WIRE_2.g
connect entries_barrier_1.io.x.u, _entries_WIRE_2.u
connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn
node _entries_T_48 = bits(vpn, 1, 0)
wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_5 : UInt<42>
connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48]
node _entries_T_49 = bits(_entries_WIRE_5, 0, 0)
connect _entries_WIRE_4.fragmented_superpage, _entries_T_49
node _entries_T_50 = bits(_entries_WIRE_5, 1, 1)
connect _entries_WIRE_4.c, _entries_T_50
node _entries_T_51 = bits(_entries_WIRE_5, 2, 2)
connect _entries_WIRE_4.eff, _entries_T_51
node _entries_T_52 = bits(_entries_WIRE_5, 3, 3)
connect _entries_WIRE_4.paa, _entries_T_52
node _entries_T_53 = bits(_entries_WIRE_5, 4, 4)
connect _entries_WIRE_4.pal, _entries_T_53
node _entries_T_54 = bits(_entries_WIRE_5, 5, 5)
connect _entries_WIRE_4.ppp, _entries_T_54
node _entries_T_55 = bits(_entries_WIRE_5, 6, 6)
connect _entries_WIRE_4.pr, _entries_T_55
node _entries_T_56 = bits(_entries_WIRE_5, 7, 7)
connect _entries_WIRE_4.px, _entries_T_56
node _entries_T_57 = bits(_entries_WIRE_5, 8, 8)
connect _entries_WIRE_4.pw, _entries_T_57
node _entries_T_58 = bits(_entries_WIRE_5, 9, 9)
connect _entries_WIRE_4.hr, _entries_T_58
node _entries_T_59 = bits(_entries_WIRE_5, 10, 10)
connect _entries_WIRE_4.hx, _entries_T_59
node _entries_T_60 = bits(_entries_WIRE_5, 11, 11)
connect _entries_WIRE_4.hw, _entries_T_60
node _entries_T_61 = bits(_entries_WIRE_5, 12, 12)
connect _entries_WIRE_4.sr, _entries_T_61
node _entries_T_62 = bits(_entries_WIRE_5, 13, 13)
connect _entries_WIRE_4.sx, _entries_T_62
node _entries_T_63 = bits(_entries_WIRE_5, 14, 14)
connect _entries_WIRE_4.sw, _entries_T_63
node _entries_T_64 = bits(_entries_WIRE_5, 15, 15)
connect _entries_WIRE_4.gf, _entries_T_64
node _entries_T_65 = bits(_entries_WIRE_5, 16, 16)
connect _entries_WIRE_4.pf, _entries_T_65
node _entries_T_66 = bits(_entries_WIRE_5, 17, 17)
connect _entries_WIRE_4.ae_stage2, _entries_T_66
node _entries_T_67 = bits(_entries_WIRE_5, 18, 18)
connect _entries_WIRE_4.ae_final, _entries_T_67
node _entries_T_68 = bits(_entries_WIRE_5, 19, 19)
connect _entries_WIRE_4.ae_ptw, _entries_T_68
node _entries_T_69 = bits(_entries_WIRE_5, 20, 20)
connect _entries_WIRE_4.g, _entries_T_69
node _entries_T_70 = bits(_entries_WIRE_5, 21, 21)
connect _entries_WIRE_4.u, _entries_T_70
node _entries_T_71 = bits(_entries_WIRE_5, 41, 22)
connect _entries_WIRE_4.ppn, _entries_T_71
inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_31
connect entries_barrier_2.clock, clock
connect entries_barrier_2.reset, reset
connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage
connect entries_barrier_2.io.x.c, _entries_WIRE_4.c
connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff
connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa
connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal
connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp
connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr
connect entries_barrier_2.io.x.px, _entries_WIRE_4.px
connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw
connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr
connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx
connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw
connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr
connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx
connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw
connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf
connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf
connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2
connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final
connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw
connect entries_barrier_2.io.x.g, _entries_WIRE_4.g
connect entries_barrier_2.io.x.u, _entries_WIRE_4.u
connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn
node _entries_T_72 = bits(vpn, 1, 0)
wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_7 : UInt<42>
connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72]
node _entries_T_73 = bits(_entries_WIRE_7, 0, 0)
connect _entries_WIRE_6.fragmented_superpage, _entries_T_73
node _entries_T_74 = bits(_entries_WIRE_7, 1, 1)
connect _entries_WIRE_6.c, _entries_T_74
node _entries_T_75 = bits(_entries_WIRE_7, 2, 2)
connect _entries_WIRE_6.eff, _entries_T_75
node _entries_T_76 = bits(_entries_WIRE_7, 3, 3)
connect _entries_WIRE_6.paa, _entries_T_76
node _entries_T_77 = bits(_entries_WIRE_7, 4, 4)
connect _entries_WIRE_6.pal, _entries_T_77
node _entries_T_78 = bits(_entries_WIRE_7, 5, 5)
connect _entries_WIRE_6.ppp, _entries_T_78
node _entries_T_79 = bits(_entries_WIRE_7, 6, 6)
connect _entries_WIRE_6.pr, _entries_T_79
node _entries_T_80 = bits(_entries_WIRE_7, 7, 7)
connect _entries_WIRE_6.px, _entries_T_80
node _entries_T_81 = bits(_entries_WIRE_7, 8, 8)
connect _entries_WIRE_6.pw, _entries_T_81
node _entries_T_82 = bits(_entries_WIRE_7, 9, 9)
connect _entries_WIRE_6.hr, _entries_T_82
node _entries_T_83 = bits(_entries_WIRE_7, 10, 10)
connect _entries_WIRE_6.hx, _entries_T_83
node _entries_T_84 = bits(_entries_WIRE_7, 11, 11)
connect _entries_WIRE_6.hw, _entries_T_84
node _entries_T_85 = bits(_entries_WIRE_7, 12, 12)
connect _entries_WIRE_6.sr, _entries_T_85
node _entries_T_86 = bits(_entries_WIRE_7, 13, 13)
connect _entries_WIRE_6.sx, _entries_T_86
node _entries_T_87 = bits(_entries_WIRE_7, 14, 14)
connect _entries_WIRE_6.sw, _entries_T_87
node _entries_T_88 = bits(_entries_WIRE_7, 15, 15)
connect _entries_WIRE_6.gf, _entries_T_88
node _entries_T_89 = bits(_entries_WIRE_7, 16, 16)
connect _entries_WIRE_6.pf, _entries_T_89
node _entries_T_90 = bits(_entries_WIRE_7, 17, 17)
connect _entries_WIRE_6.ae_stage2, _entries_T_90
node _entries_T_91 = bits(_entries_WIRE_7, 18, 18)
connect _entries_WIRE_6.ae_final, _entries_T_91
node _entries_T_92 = bits(_entries_WIRE_7, 19, 19)
connect _entries_WIRE_6.ae_ptw, _entries_T_92
node _entries_T_93 = bits(_entries_WIRE_7, 20, 20)
connect _entries_WIRE_6.g, _entries_T_93
node _entries_T_94 = bits(_entries_WIRE_7, 21, 21)
connect _entries_WIRE_6.u, _entries_T_94
node _entries_T_95 = bits(_entries_WIRE_7, 41, 22)
connect _entries_WIRE_6.ppn, _entries_T_95
inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_32
connect entries_barrier_3.clock, clock
connect entries_barrier_3.reset, reset
connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage
connect entries_barrier_3.io.x.c, _entries_WIRE_6.c
connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff
connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa
connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal
connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp
connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr
connect entries_barrier_3.io.x.px, _entries_WIRE_6.px
connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw
connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr
connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx
connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw
connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr
connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx
connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw
connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf
connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf
connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2
connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final
connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw
connect entries_barrier_3.io.x.g, _entries_WIRE_6.g
connect entries_barrier_3.io.x.u, _entries_WIRE_6.u
connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn
node _entries_T_96 = bits(vpn, 1, 0)
wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_9 : UInt<42>
connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96]
node _entries_T_97 = bits(_entries_WIRE_9, 0, 0)
connect _entries_WIRE_8.fragmented_superpage, _entries_T_97
node _entries_T_98 = bits(_entries_WIRE_9, 1, 1)
connect _entries_WIRE_8.c, _entries_T_98
node _entries_T_99 = bits(_entries_WIRE_9, 2, 2)
connect _entries_WIRE_8.eff, _entries_T_99
node _entries_T_100 = bits(_entries_WIRE_9, 3, 3)
connect _entries_WIRE_8.paa, _entries_T_100
node _entries_T_101 = bits(_entries_WIRE_9, 4, 4)
connect _entries_WIRE_8.pal, _entries_T_101
node _entries_T_102 = bits(_entries_WIRE_9, 5, 5)
connect _entries_WIRE_8.ppp, _entries_T_102
node _entries_T_103 = bits(_entries_WIRE_9, 6, 6)
connect _entries_WIRE_8.pr, _entries_T_103
node _entries_T_104 = bits(_entries_WIRE_9, 7, 7)
connect _entries_WIRE_8.px, _entries_T_104
node _entries_T_105 = bits(_entries_WIRE_9, 8, 8)
connect _entries_WIRE_8.pw, _entries_T_105
node _entries_T_106 = bits(_entries_WIRE_9, 9, 9)
connect _entries_WIRE_8.hr, _entries_T_106
node _entries_T_107 = bits(_entries_WIRE_9, 10, 10)
connect _entries_WIRE_8.hx, _entries_T_107
node _entries_T_108 = bits(_entries_WIRE_9, 11, 11)
connect _entries_WIRE_8.hw, _entries_T_108
node _entries_T_109 = bits(_entries_WIRE_9, 12, 12)
connect _entries_WIRE_8.sr, _entries_T_109
node _entries_T_110 = bits(_entries_WIRE_9, 13, 13)
connect _entries_WIRE_8.sx, _entries_T_110
node _entries_T_111 = bits(_entries_WIRE_9, 14, 14)
connect _entries_WIRE_8.sw, _entries_T_111
node _entries_T_112 = bits(_entries_WIRE_9, 15, 15)
connect _entries_WIRE_8.gf, _entries_T_112
node _entries_T_113 = bits(_entries_WIRE_9, 16, 16)
connect _entries_WIRE_8.pf, _entries_T_113
node _entries_T_114 = bits(_entries_WIRE_9, 17, 17)
connect _entries_WIRE_8.ae_stage2, _entries_T_114
node _entries_T_115 = bits(_entries_WIRE_9, 18, 18)
connect _entries_WIRE_8.ae_final, _entries_T_115
node _entries_T_116 = bits(_entries_WIRE_9, 19, 19)
connect _entries_WIRE_8.ae_ptw, _entries_T_116
node _entries_T_117 = bits(_entries_WIRE_9, 20, 20)
connect _entries_WIRE_8.g, _entries_T_117
node _entries_T_118 = bits(_entries_WIRE_9, 21, 21)
connect _entries_WIRE_8.u, _entries_T_118
node _entries_T_119 = bits(_entries_WIRE_9, 41, 22)
connect _entries_WIRE_8.ppn, _entries_T_119
inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_33
connect entries_barrier_4.clock, clock
connect entries_barrier_4.reset, reset
connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage
connect entries_barrier_4.io.x.c, _entries_WIRE_8.c
connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff
connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa
connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal
connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp
connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr
connect entries_barrier_4.io.x.px, _entries_WIRE_8.px
connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw
connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr
connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx
connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw
connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr
connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx
connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw
connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf
connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf
connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2
connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final
connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw
connect entries_barrier_4.io.x.g, _entries_WIRE_8.g
connect entries_barrier_4.io.x.u, _entries_WIRE_8.u
connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn
node _entries_T_120 = bits(vpn, 1, 0)
wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_11 : UInt<42>
connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120]
node _entries_T_121 = bits(_entries_WIRE_11, 0, 0)
connect _entries_WIRE_10.fragmented_superpage, _entries_T_121
node _entries_T_122 = bits(_entries_WIRE_11, 1, 1)
connect _entries_WIRE_10.c, _entries_T_122
node _entries_T_123 = bits(_entries_WIRE_11, 2, 2)
connect _entries_WIRE_10.eff, _entries_T_123
node _entries_T_124 = bits(_entries_WIRE_11, 3, 3)
connect _entries_WIRE_10.paa, _entries_T_124
node _entries_T_125 = bits(_entries_WIRE_11, 4, 4)
connect _entries_WIRE_10.pal, _entries_T_125
node _entries_T_126 = bits(_entries_WIRE_11, 5, 5)
connect _entries_WIRE_10.ppp, _entries_T_126
node _entries_T_127 = bits(_entries_WIRE_11, 6, 6)
connect _entries_WIRE_10.pr, _entries_T_127
node _entries_T_128 = bits(_entries_WIRE_11, 7, 7)
connect _entries_WIRE_10.px, _entries_T_128
node _entries_T_129 = bits(_entries_WIRE_11, 8, 8)
connect _entries_WIRE_10.pw, _entries_T_129
node _entries_T_130 = bits(_entries_WIRE_11, 9, 9)
connect _entries_WIRE_10.hr, _entries_T_130
node _entries_T_131 = bits(_entries_WIRE_11, 10, 10)
connect _entries_WIRE_10.hx, _entries_T_131
node _entries_T_132 = bits(_entries_WIRE_11, 11, 11)
connect _entries_WIRE_10.hw, _entries_T_132
node _entries_T_133 = bits(_entries_WIRE_11, 12, 12)
connect _entries_WIRE_10.sr, _entries_T_133
node _entries_T_134 = bits(_entries_WIRE_11, 13, 13)
connect _entries_WIRE_10.sx, _entries_T_134
node _entries_T_135 = bits(_entries_WIRE_11, 14, 14)
connect _entries_WIRE_10.sw, _entries_T_135
node _entries_T_136 = bits(_entries_WIRE_11, 15, 15)
connect _entries_WIRE_10.gf, _entries_T_136
node _entries_T_137 = bits(_entries_WIRE_11, 16, 16)
connect _entries_WIRE_10.pf, _entries_T_137
node _entries_T_138 = bits(_entries_WIRE_11, 17, 17)
connect _entries_WIRE_10.ae_stage2, _entries_T_138
node _entries_T_139 = bits(_entries_WIRE_11, 18, 18)
connect _entries_WIRE_10.ae_final, _entries_T_139
node _entries_T_140 = bits(_entries_WIRE_11, 19, 19)
connect _entries_WIRE_10.ae_ptw, _entries_T_140
node _entries_T_141 = bits(_entries_WIRE_11, 20, 20)
connect _entries_WIRE_10.g, _entries_T_141
node _entries_T_142 = bits(_entries_WIRE_11, 21, 21)
connect _entries_WIRE_10.u, _entries_T_142
node _entries_T_143 = bits(_entries_WIRE_11, 41, 22)
connect _entries_WIRE_10.ppn, _entries_T_143
inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_34
connect entries_barrier_5.clock, clock
connect entries_barrier_5.reset, reset
connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage
connect entries_barrier_5.io.x.c, _entries_WIRE_10.c
connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff
connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa
connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal
connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp
connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr
connect entries_barrier_5.io.x.px, _entries_WIRE_10.px
connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw
connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr
connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx
connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw
connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr
connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx
connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw
connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf
connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf
connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2
connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final
connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw
connect entries_barrier_5.io.x.g, _entries_WIRE_10.g
connect entries_barrier_5.io.x.u, _entries_WIRE_10.u
connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn
node _entries_T_144 = bits(vpn, 1, 0)
wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_13 : UInt<42>
connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144]
node _entries_T_145 = bits(_entries_WIRE_13, 0, 0)
connect _entries_WIRE_12.fragmented_superpage, _entries_T_145
node _entries_T_146 = bits(_entries_WIRE_13, 1, 1)
connect _entries_WIRE_12.c, _entries_T_146
node _entries_T_147 = bits(_entries_WIRE_13, 2, 2)
connect _entries_WIRE_12.eff, _entries_T_147
node _entries_T_148 = bits(_entries_WIRE_13, 3, 3)
connect _entries_WIRE_12.paa, _entries_T_148
node _entries_T_149 = bits(_entries_WIRE_13, 4, 4)
connect _entries_WIRE_12.pal, _entries_T_149
node _entries_T_150 = bits(_entries_WIRE_13, 5, 5)
connect _entries_WIRE_12.ppp, _entries_T_150
node _entries_T_151 = bits(_entries_WIRE_13, 6, 6)
connect _entries_WIRE_12.pr, _entries_T_151
node _entries_T_152 = bits(_entries_WIRE_13, 7, 7)
connect _entries_WIRE_12.px, _entries_T_152
node _entries_T_153 = bits(_entries_WIRE_13, 8, 8)
connect _entries_WIRE_12.pw, _entries_T_153
node _entries_T_154 = bits(_entries_WIRE_13, 9, 9)
connect _entries_WIRE_12.hr, _entries_T_154
node _entries_T_155 = bits(_entries_WIRE_13, 10, 10)
connect _entries_WIRE_12.hx, _entries_T_155
node _entries_T_156 = bits(_entries_WIRE_13, 11, 11)
connect _entries_WIRE_12.hw, _entries_T_156
node _entries_T_157 = bits(_entries_WIRE_13, 12, 12)
connect _entries_WIRE_12.sr, _entries_T_157
node _entries_T_158 = bits(_entries_WIRE_13, 13, 13)
connect _entries_WIRE_12.sx, _entries_T_158
node _entries_T_159 = bits(_entries_WIRE_13, 14, 14)
connect _entries_WIRE_12.sw, _entries_T_159
node _entries_T_160 = bits(_entries_WIRE_13, 15, 15)
connect _entries_WIRE_12.gf, _entries_T_160
node _entries_T_161 = bits(_entries_WIRE_13, 16, 16)
connect _entries_WIRE_12.pf, _entries_T_161
node _entries_T_162 = bits(_entries_WIRE_13, 17, 17)
connect _entries_WIRE_12.ae_stage2, _entries_T_162
node _entries_T_163 = bits(_entries_WIRE_13, 18, 18)
connect _entries_WIRE_12.ae_final, _entries_T_163
node _entries_T_164 = bits(_entries_WIRE_13, 19, 19)
connect _entries_WIRE_12.ae_ptw, _entries_T_164
node _entries_T_165 = bits(_entries_WIRE_13, 20, 20)
connect _entries_WIRE_12.g, _entries_T_165
node _entries_T_166 = bits(_entries_WIRE_13, 21, 21)
connect _entries_WIRE_12.u, _entries_T_166
node _entries_T_167 = bits(_entries_WIRE_13, 41, 22)
connect _entries_WIRE_12.ppn, _entries_T_167
inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_35
connect entries_barrier_6.clock, clock
connect entries_barrier_6.reset, reset
connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage
connect entries_barrier_6.io.x.c, _entries_WIRE_12.c
connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff
connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa
connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal
connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp
connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr
connect entries_barrier_6.io.x.px, _entries_WIRE_12.px
connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw
connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr
connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx
connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw
connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr
connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx
connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw
connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf
connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf
connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2
connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final
connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw
connect entries_barrier_6.io.x.g, _entries_WIRE_12.g
connect entries_barrier_6.io.x.u, _entries_WIRE_12.u
connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn
node _entries_T_168 = bits(vpn, 1, 0)
wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_15 : UInt<42>
connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168]
node _entries_T_169 = bits(_entries_WIRE_15, 0, 0)
connect _entries_WIRE_14.fragmented_superpage, _entries_T_169
node _entries_T_170 = bits(_entries_WIRE_15, 1, 1)
connect _entries_WIRE_14.c, _entries_T_170
node _entries_T_171 = bits(_entries_WIRE_15, 2, 2)
connect _entries_WIRE_14.eff, _entries_T_171
node _entries_T_172 = bits(_entries_WIRE_15, 3, 3)
connect _entries_WIRE_14.paa, _entries_T_172
node _entries_T_173 = bits(_entries_WIRE_15, 4, 4)
connect _entries_WIRE_14.pal, _entries_T_173
node _entries_T_174 = bits(_entries_WIRE_15, 5, 5)
connect _entries_WIRE_14.ppp, _entries_T_174
node _entries_T_175 = bits(_entries_WIRE_15, 6, 6)
connect _entries_WIRE_14.pr, _entries_T_175
node _entries_T_176 = bits(_entries_WIRE_15, 7, 7)
connect _entries_WIRE_14.px, _entries_T_176
node _entries_T_177 = bits(_entries_WIRE_15, 8, 8)
connect _entries_WIRE_14.pw, _entries_T_177
node _entries_T_178 = bits(_entries_WIRE_15, 9, 9)
connect _entries_WIRE_14.hr, _entries_T_178
node _entries_T_179 = bits(_entries_WIRE_15, 10, 10)
connect _entries_WIRE_14.hx, _entries_T_179
node _entries_T_180 = bits(_entries_WIRE_15, 11, 11)
connect _entries_WIRE_14.hw, _entries_T_180
node _entries_T_181 = bits(_entries_WIRE_15, 12, 12)
connect _entries_WIRE_14.sr, _entries_T_181
node _entries_T_182 = bits(_entries_WIRE_15, 13, 13)
connect _entries_WIRE_14.sx, _entries_T_182
node _entries_T_183 = bits(_entries_WIRE_15, 14, 14)
connect _entries_WIRE_14.sw, _entries_T_183
node _entries_T_184 = bits(_entries_WIRE_15, 15, 15)
connect _entries_WIRE_14.gf, _entries_T_184
node _entries_T_185 = bits(_entries_WIRE_15, 16, 16)
connect _entries_WIRE_14.pf, _entries_T_185
node _entries_T_186 = bits(_entries_WIRE_15, 17, 17)
connect _entries_WIRE_14.ae_stage2, _entries_T_186
node _entries_T_187 = bits(_entries_WIRE_15, 18, 18)
connect _entries_WIRE_14.ae_final, _entries_T_187
node _entries_T_188 = bits(_entries_WIRE_15, 19, 19)
connect _entries_WIRE_14.ae_ptw, _entries_T_188
node _entries_T_189 = bits(_entries_WIRE_15, 20, 20)
connect _entries_WIRE_14.g, _entries_T_189
node _entries_T_190 = bits(_entries_WIRE_15, 21, 21)
connect _entries_WIRE_14.u, _entries_T_190
node _entries_T_191 = bits(_entries_WIRE_15, 41, 22)
connect _entries_WIRE_14.ppn, _entries_T_191
inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_36
connect entries_barrier_7.clock, clock
connect entries_barrier_7.reset, reset
connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage
connect entries_barrier_7.io.x.c, _entries_WIRE_14.c
connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff
connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa
connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal
connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp
connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr
connect entries_barrier_7.io.x.px, _entries_WIRE_14.px
connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw
connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr
connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx
connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw
connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr
connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx
connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw
connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf
connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf
connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2
connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final
connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw
connect entries_barrier_7.io.x.g, _entries_WIRE_14.g
connect entries_barrier_7.io.x.u, _entries_WIRE_14.u
connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn
wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_17 : UInt<42>
connect _entries_WIRE_17, superpage_entries[0].data[0]
node _entries_T_192 = bits(_entries_WIRE_17, 0, 0)
connect _entries_WIRE_16.fragmented_superpage, _entries_T_192
node _entries_T_193 = bits(_entries_WIRE_17, 1, 1)
connect _entries_WIRE_16.c, _entries_T_193
node _entries_T_194 = bits(_entries_WIRE_17, 2, 2)
connect _entries_WIRE_16.eff, _entries_T_194
node _entries_T_195 = bits(_entries_WIRE_17, 3, 3)
connect _entries_WIRE_16.paa, _entries_T_195
node _entries_T_196 = bits(_entries_WIRE_17, 4, 4)
connect _entries_WIRE_16.pal, _entries_T_196
node _entries_T_197 = bits(_entries_WIRE_17, 5, 5)
connect _entries_WIRE_16.ppp, _entries_T_197
node _entries_T_198 = bits(_entries_WIRE_17, 6, 6)
connect _entries_WIRE_16.pr, _entries_T_198
node _entries_T_199 = bits(_entries_WIRE_17, 7, 7)
connect _entries_WIRE_16.px, _entries_T_199
node _entries_T_200 = bits(_entries_WIRE_17, 8, 8)
connect _entries_WIRE_16.pw, _entries_T_200
node _entries_T_201 = bits(_entries_WIRE_17, 9, 9)
connect _entries_WIRE_16.hr, _entries_T_201
node _entries_T_202 = bits(_entries_WIRE_17, 10, 10)
connect _entries_WIRE_16.hx, _entries_T_202
node _entries_T_203 = bits(_entries_WIRE_17, 11, 11)
connect _entries_WIRE_16.hw, _entries_T_203
node _entries_T_204 = bits(_entries_WIRE_17, 12, 12)
connect _entries_WIRE_16.sr, _entries_T_204
node _entries_T_205 = bits(_entries_WIRE_17, 13, 13)
connect _entries_WIRE_16.sx, _entries_T_205
node _entries_T_206 = bits(_entries_WIRE_17, 14, 14)
connect _entries_WIRE_16.sw, _entries_T_206
node _entries_T_207 = bits(_entries_WIRE_17, 15, 15)
connect _entries_WIRE_16.gf, _entries_T_207
node _entries_T_208 = bits(_entries_WIRE_17, 16, 16)
connect _entries_WIRE_16.pf, _entries_T_208
node _entries_T_209 = bits(_entries_WIRE_17, 17, 17)
connect _entries_WIRE_16.ae_stage2, _entries_T_209
node _entries_T_210 = bits(_entries_WIRE_17, 18, 18)
connect _entries_WIRE_16.ae_final, _entries_T_210
node _entries_T_211 = bits(_entries_WIRE_17, 19, 19)
connect _entries_WIRE_16.ae_ptw, _entries_T_211
node _entries_T_212 = bits(_entries_WIRE_17, 20, 20)
connect _entries_WIRE_16.g, _entries_T_212
node _entries_T_213 = bits(_entries_WIRE_17, 21, 21)
connect _entries_WIRE_16.u, _entries_T_213
node _entries_T_214 = bits(_entries_WIRE_17, 41, 22)
connect _entries_WIRE_16.ppn, _entries_T_214
inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_37
connect entries_barrier_8.clock, clock
connect entries_barrier_8.reset, reset
connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage
connect entries_barrier_8.io.x.c, _entries_WIRE_16.c
connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff
connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa
connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal
connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp
connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr
connect entries_barrier_8.io.x.px, _entries_WIRE_16.px
connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw
connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr
connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx
connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw
connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr
connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx
connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw
connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf
connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf
connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2
connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final
connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw
connect entries_barrier_8.io.x.g, _entries_WIRE_16.g
connect entries_barrier_8.io.x.u, _entries_WIRE_16.u
connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn
wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_19 : UInt<42>
connect _entries_WIRE_19, superpage_entries[1].data[0]
node _entries_T_215 = bits(_entries_WIRE_19, 0, 0)
connect _entries_WIRE_18.fragmented_superpage, _entries_T_215
node _entries_T_216 = bits(_entries_WIRE_19, 1, 1)
connect _entries_WIRE_18.c, _entries_T_216
node _entries_T_217 = bits(_entries_WIRE_19, 2, 2)
connect _entries_WIRE_18.eff, _entries_T_217
node _entries_T_218 = bits(_entries_WIRE_19, 3, 3)
connect _entries_WIRE_18.paa, _entries_T_218
node _entries_T_219 = bits(_entries_WIRE_19, 4, 4)
connect _entries_WIRE_18.pal, _entries_T_219
node _entries_T_220 = bits(_entries_WIRE_19, 5, 5)
connect _entries_WIRE_18.ppp, _entries_T_220
node _entries_T_221 = bits(_entries_WIRE_19, 6, 6)
connect _entries_WIRE_18.pr, _entries_T_221
node _entries_T_222 = bits(_entries_WIRE_19, 7, 7)
connect _entries_WIRE_18.px, _entries_T_222
node _entries_T_223 = bits(_entries_WIRE_19, 8, 8)
connect _entries_WIRE_18.pw, _entries_T_223
node _entries_T_224 = bits(_entries_WIRE_19, 9, 9)
connect _entries_WIRE_18.hr, _entries_T_224
node _entries_T_225 = bits(_entries_WIRE_19, 10, 10)
connect _entries_WIRE_18.hx, _entries_T_225
node _entries_T_226 = bits(_entries_WIRE_19, 11, 11)
connect _entries_WIRE_18.hw, _entries_T_226
node _entries_T_227 = bits(_entries_WIRE_19, 12, 12)
connect _entries_WIRE_18.sr, _entries_T_227
node _entries_T_228 = bits(_entries_WIRE_19, 13, 13)
connect _entries_WIRE_18.sx, _entries_T_228
node _entries_T_229 = bits(_entries_WIRE_19, 14, 14)
connect _entries_WIRE_18.sw, _entries_T_229
node _entries_T_230 = bits(_entries_WIRE_19, 15, 15)
connect _entries_WIRE_18.gf, _entries_T_230
node _entries_T_231 = bits(_entries_WIRE_19, 16, 16)
connect _entries_WIRE_18.pf, _entries_T_231
node _entries_T_232 = bits(_entries_WIRE_19, 17, 17)
connect _entries_WIRE_18.ae_stage2, _entries_T_232
node _entries_T_233 = bits(_entries_WIRE_19, 18, 18)
connect _entries_WIRE_18.ae_final, _entries_T_233
node _entries_T_234 = bits(_entries_WIRE_19, 19, 19)
connect _entries_WIRE_18.ae_ptw, _entries_T_234
node _entries_T_235 = bits(_entries_WIRE_19, 20, 20)
connect _entries_WIRE_18.g, _entries_T_235
node _entries_T_236 = bits(_entries_WIRE_19, 21, 21)
connect _entries_WIRE_18.u, _entries_T_236
node _entries_T_237 = bits(_entries_WIRE_19, 41, 22)
connect _entries_WIRE_18.ppn, _entries_T_237
inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_38
connect entries_barrier_9.clock, clock
connect entries_barrier_9.reset, reset
connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage
connect entries_barrier_9.io.x.c, _entries_WIRE_18.c
connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff
connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa
connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal
connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp
connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr
connect entries_barrier_9.io.x.px, _entries_WIRE_18.px
connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw
connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr
connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx
connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw
connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr
connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx
connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw
connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf
connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf
connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2
connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final
connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw
connect entries_barrier_9.io.x.g, _entries_WIRE_18.g
connect entries_barrier_9.io.x.u, _entries_WIRE_18.u
connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn
wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_21 : UInt<42>
connect _entries_WIRE_21, superpage_entries[2].data[0]
node _entries_T_238 = bits(_entries_WIRE_21, 0, 0)
connect _entries_WIRE_20.fragmented_superpage, _entries_T_238
node _entries_T_239 = bits(_entries_WIRE_21, 1, 1)
connect _entries_WIRE_20.c, _entries_T_239
node _entries_T_240 = bits(_entries_WIRE_21, 2, 2)
connect _entries_WIRE_20.eff, _entries_T_240
node _entries_T_241 = bits(_entries_WIRE_21, 3, 3)
connect _entries_WIRE_20.paa, _entries_T_241
node _entries_T_242 = bits(_entries_WIRE_21, 4, 4)
connect _entries_WIRE_20.pal, _entries_T_242
node _entries_T_243 = bits(_entries_WIRE_21, 5, 5)
connect _entries_WIRE_20.ppp, _entries_T_243
node _entries_T_244 = bits(_entries_WIRE_21, 6, 6)
connect _entries_WIRE_20.pr, _entries_T_244
node _entries_T_245 = bits(_entries_WIRE_21, 7, 7)
connect _entries_WIRE_20.px, _entries_T_245
node _entries_T_246 = bits(_entries_WIRE_21, 8, 8)
connect _entries_WIRE_20.pw, _entries_T_246
node _entries_T_247 = bits(_entries_WIRE_21, 9, 9)
connect _entries_WIRE_20.hr, _entries_T_247
node _entries_T_248 = bits(_entries_WIRE_21, 10, 10)
connect _entries_WIRE_20.hx, _entries_T_248
node _entries_T_249 = bits(_entries_WIRE_21, 11, 11)
connect _entries_WIRE_20.hw, _entries_T_249
node _entries_T_250 = bits(_entries_WIRE_21, 12, 12)
connect _entries_WIRE_20.sr, _entries_T_250
node _entries_T_251 = bits(_entries_WIRE_21, 13, 13)
connect _entries_WIRE_20.sx, _entries_T_251
node _entries_T_252 = bits(_entries_WIRE_21, 14, 14)
connect _entries_WIRE_20.sw, _entries_T_252
node _entries_T_253 = bits(_entries_WIRE_21, 15, 15)
connect _entries_WIRE_20.gf, _entries_T_253
node _entries_T_254 = bits(_entries_WIRE_21, 16, 16)
connect _entries_WIRE_20.pf, _entries_T_254
node _entries_T_255 = bits(_entries_WIRE_21, 17, 17)
connect _entries_WIRE_20.ae_stage2, _entries_T_255
node _entries_T_256 = bits(_entries_WIRE_21, 18, 18)
connect _entries_WIRE_20.ae_final, _entries_T_256
node _entries_T_257 = bits(_entries_WIRE_21, 19, 19)
connect _entries_WIRE_20.ae_ptw, _entries_T_257
node _entries_T_258 = bits(_entries_WIRE_21, 20, 20)
connect _entries_WIRE_20.g, _entries_T_258
node _entries_T_259 = bits(_entries_WIRE_21, 21, 21)
connect _entries_WIRE_20.u, _entries_T_259
node _entries_T_260 = bits(_entries_WIRE_21, 41, 22)
connect _entries_WIRE_20.ppn, _entries_T_260
inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_39
connect entries_barrier_10.clock, clock
connect entries_barrier_10.reset, reset
connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage
connect entries_barrier_10.io.x.c, _entries_WIRE_20.c
connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff
connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa
connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal
connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp
connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr
connect entries_barrier_10.io.x.px, _entries_WIRE_20.px
connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw
connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr
connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx
connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw
connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr
connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx
connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw
connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf
connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf
connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2
connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final
connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw
connect entries_barrier_10.io.x.g, _entries_WIRE_20.g
connect entries_barrier_10.io.x.u, _entries_WIRE_20.u
connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn
wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_23 : UInt<42>
connect _entries_WIRE_23, superpage_entries[3].data[0]
node _entries_T_261 = bits(_entries_WIRE_23, 0, 0)
connect _entries_WIRE_22.fragmented_superpage, _entries_T_261
node _entries_T_262 = bits(_entries_WIRE_23, 1, 1)
connect _entries_WIRE_22.c, _entries_T_262
node _entries_T_263 = bits(_entries_WIRE_23, 2, 2)
connect _entries_WIRE_22.eff, _entries_T_263
node _entries_T_264 = bits(_entries_WIRE_23, 3, 3)
connect _entries_WIRE_22.paa, _entries_T_264
node _entries_T_265 = bits(_entries_WIRE_23, 4, 4)
connect _entries_WIRE_22.pal, _entries_T_265
node _entries_T_266 = bits(_entries_WIRE_23, 5, 5)
connect _entries_WIRE_22.ppp, _entries_T_266
node _entries_T_267 = bits(_entries_WIRE_23, 6, 6)
connect _entries_WIRE_22.pr, _entries_T_267
node _entries_T_268 = bits(_entries_WIRE_23, 7, 7)
connect _entries_WIRE_22.px, _entries_T_268
node _entries_T_269 = bits(_entries_WIRE_23, 8, 8)
connect _entries_WIRE_22.pw, _entries_T_269
node _entries_T_270 = bits(_entries_WIRE_23, 9, 9)
connect _entries_WIRE_22.hr, _entries_T_270
node _entries_T_271 = bits(_entries_WIRE_23, 10, 10)
connect _entries_WIRE_22.hx, _entries_T_271
node _entries_T_272 = bits(_entries_WIRE_23, 11, 11)
connect _entries_WIRE_22.hw, _entries_T_272
node _entries_T_273 = bits(_entries_WIRE_23, 12, 12)
connect _entries_WIRE_22.sr, _entries_T_273
node _entries_T_274 = bits(_entries_WIRE_23, 13, 13)
connect _entries_WIRE_22.sx, _entries_T_274
node _entries_T_275 = bits(_entries_WIRE_23, 14, 14)
connect _entries_WIRE_22.sw, _entries_T_275
node _entries_T_276 = bits(_entries_WIRE_23, 15, 15)
connect _entries_WIRE_22.gf, _entries_T_276
node _entries_T_277 = bits(_entries_WIRE_23, 16, 16)
connect _entries_WIRE_22.pf, _entries_T_277
node _entries_T_278 = bits(_entries_WIRE_23, 17, 17)
connect _entries_WIRE_22.ae_stage2, _entries_T_278
node _entries_T_279 = bits(_entries_WIRE_23, 18, 18)
connect _entries_WIRE_22.ae_final, _entries_T_279
node _entries_T_280 = bits(_entries_WIRE_23, 19, 19)
connect _entries_WIRE_22.ae_ptw, _entries_T_280
node _entries_T_281 = bits(_entries_WIRE_23, 20, 20)
connect _entries_WIRE_22.g, _entries_T_281
node _entries_T_282 = bits(_entries_WIRE_23, 21, 21)
connect _entries_WIRE_22.u, _entries_T_282
node _entries_T_283 = bits(_entries_WIRE_23, 41, 22)
connect _entries_WIRE_22.ppn, _entries_T_283
inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_40
connect entries_barrier_11.clock, clock
connect entries_barrier_11.reset, reset
connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage
connect entries_barrier_11.io.x.c, _entries_WIRE_22.c
connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff
connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa
connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal
connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp
connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr
connect entries_barrier_11.io.x.px, _entries_WIRE_22.px
connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw
connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr
connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx
connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw
connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr
connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx
connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw
connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf
connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf
connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2
connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final
connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw
connect entries_barrier_11.io.x.g, _entries_WIRE_22.g
connect entries_barrier_11.io.x.u, _entries_WIRE_22.u
connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn
wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_25 : UInt<42>
connect _entries_WIRE_25, special_entry.data[0]
node _entries_T_284 = bits(_entries_WIRE_25, 0, 0)
connect _entries_WIRE_24.fragmented_superpage, _entries_T_284
node _entries_T_285 = bits(_entries_WIRE_25, 1, 1)
connect _entries_WIRE_24.c, _entries_T_285
node _entries_T_286 = bits(_entries_WIRE_25, 2, 2)
connect _entries_WIRE_24.eff, _entries_T_286
node _entries_T_287 = bits(_entries_WIRE_25, 3, 3)
connect _entries_WIRE_24.paa, _entries_T_287
node _entries_T_288 = bits(_entries_WIRE_25, 4, 4)
connect _entries_WIRE_24.pal, _entries_T_288
node _entries_T_289 = bits(_entries_WIRE_25, 5, 5)
connect _entries_WIRE_24.ppp, _entries_T_289
node _entries_T_290 = bits(_entries_WIRE_25, 6, 6)
connect _entries_WIRE_24.pr, _entries_T_290
node _entries_T_291 = bits(_entries_WIRE_25, 7, 7)
connect _entries_WIRE_24.px, _entries_T_291
node _entries_T_292 = bits(_entries_WIRE_25, 8, 8)
connect _entries_WIRE_24.pw, _entries_T_292
node _entries_T_293 = bits(_entries_WIRE_25, 9, 9)
connect _entries_WIRE_24.hr, _entries_T_293
node _entries_T_294 = bits(_entries_WIRE_25, 10, 10)
connect _entries_WIRE_24.hx, _entries_T_294
node _entries_T_295 = bits(_entries_WIRE_25, 11, 11)
connect _entries_WIRE_24.hw, _entries_T_295
node _entries_T_296 = bits(_entries_WIRE_25, 12, 12)
connect _entries_WIRE_24.sr, _entries_T_296
node _entries_T_297 = bits(_entries_WIRE_25, 13, 13)
connect _entries_WIRE_24.sx, _entries_T_297
node _entries_T_298 = bits(_entries_WIRE_25, 14, 14)
connect _entries_WIRE_24.sw, _entries_T_298
node _entries_T_299 = bits(_entries_WIRE_25, 15, 15)
connect _entries_WIRE_24.gf, _entries_T_299
node _entries_T_300 = bits(_entries_WIRE_25, 16, 16)
connect _entries_WIRE_24.pf, _entries_T_300
node _entries_T_301 = bits(_entries_WIRE_25, 17, 17)
connect _entries_WIRE_24.ae_stage2, _entries_T_301
node _entries_T_302 = bits(_entries_WIRE_25, 18, 18)
connect _entries_WIRE_24.ae_final, _entries_T_302
node _entries_T_303 = bits(_entries_WIRE_25, 19, 19)
connect _entries_WIRE_24.ae_ptw, _entries_T_303
node _entries_T_304 = bits(_entries_WIRE_25, 20, 20)
connect _entries_WIRE_24.g, _entries_T_304
node _entries_T_305 = bits(_entries_WIRE_25, 21, 21)
connect _entries_WIRE_24.u, _entries_T_305
node _entries_T_306 = bits(_entries_WIRE_25, 41, 22)
connect _entries_WIRE_24.ppn, _entries_T_306
inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_41
connect entries_barrier_12.clock, clock
connect entries_barrier_12.reset, reset
connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage
connect entries_barrier_12.io.x.c, _entries_WIRE_24.c
connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff
connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa
connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal
connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp
connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr
connect entries_barrier_12.io.x.px, _entries_WIRE_24.px
connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw
connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr
connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx
connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw
connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr
connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx
connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw
connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf
connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf
connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2
connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final
connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw
connect entries_barrier_12.io.x.g, _entries_WIRE_24.g
connect entries_barrier_12.io.x.u, _entries_WIRE_24.u
connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn
node _ppn_T = eq(vm_enabled, UInt<1>(0h0))
node _ppn_T_1 = bits(vpn, 19, 0)
node _ppn_T_2 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0))
node _ppn_T_3 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0))
node _ppn_T_4 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0))
node _ppn_T_5 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0))
node _ppn_T_6 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0))
node _ppn_T_7 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0))
node _ppn_T_8 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0))
node _ppn_T_9 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0))
node _ppn_T_10 = mux(hitsVec_8, entries_barrier_8.io.y.ppn, UInt<1>(0h0))
node _ppn_T_11 = mux(hitsVec_9, entries_barrier_9.io.y.ppn, UInt<1>(0h0))
node _ppn_T_12 = mux(hitsVec_10, entries_barrier_10.io.y.ppn, UInt<1>(0h0))
node _ppn_T_13 = mux(hitsVec_11, entries_barrier_11.io.y.ppn, UInt<1>(0h0))
node _ppn_T_14 = mux(hitsVec_12, entries_barrier_12.io.y.ppn, UInt<1>(0h0))
node _ppn_T_15 = mux(_ppn_T, _ppn_T_1, UInt<1>(0h0))
node _ppn_T_16 = or(_ppn_T_2, _ppn_T_3)
node _ppn_T_17 = or(_ppn_T_16, _ppn_T_4)
node _ppn_T_18 = or(_ppn_T_17, _ppn_T_5)
node _ppn_T_19 = or(_ppn_T_18, _ppn_T_6)
node _ppn_T_20 = or(_ppn_T_19, _ppn_T_7)
node _ppn_T_21 = or(_ppn_T_20, _ppn_T_8)
node _ppn_T_22 = or(_ppn_T_21, _ppn_T_9)
node _ppn_T_23 = or(_ppn_T_22, _ppn_T_10)
node _ppn_T_24 = or(_ppn_T_23, _ppn_T_11)
node _ppn_T_25 = or(_ppn_T_24, _ppn_T_12)
node _ppn_T_26 = or(_ppn_T_25, _ppn_T_13)
node _ppn_T_27 = or(_ppn_T_26, _ppn_T_14)
node _ppn_T_28 = or(_ppn_T_27, _ppn_T_15)
wire ppn : UInt<20>
connect ppn, _ppn_T_28
node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw)
node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw)
node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw)
node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw)
node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo)
node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw)
node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw)
node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw)
node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw)
node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo)
node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo)
node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo)
node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T)
node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final)
node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final)
node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final)
node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final)
node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo)
node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final)
node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final)
node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final)
node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final)
node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo)
node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo)
node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo)
node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T)
node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf)
node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf)
node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf)
node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf)
node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo)
node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf)
node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf)
node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf)
node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf)
node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo)
node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo)
node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo)
node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T)
node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf)
node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf)
node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf)
node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf)
node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo)
node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf)
node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf)
node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf)
node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf)
node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo)
node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo)
node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo)
node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T)
node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0))
node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum)
node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo)
node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo)
node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo)
node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo)
node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0))
node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1)
node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1)
node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1)
node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1)
node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4)
node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0))
node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6)
node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo)
node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo)
node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo)
node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo)
node _priv_x_ok_T_1 = not(_priv_x_ok_T)
node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1)
node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1)
node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1)
node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1)
node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2)
node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0))
node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0))
node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0))
node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2)
node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2)
node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2)
node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2)
node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo)
node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2)
node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2)
node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2)
node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2)
node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo)
node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo)
node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo)
node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3)
node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4)
node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0))
node mxr = or(io.ptw.status.mxr, _mxr_T)
node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr)
node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr)
node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr)
node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr)
node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo)
node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr)
node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr)
node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr)
node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr)
node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo)
node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo)
node _r_array_T = cat(r_array_hi, r_array_lo)
node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx)
node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx)
node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1)
node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx)
node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1)
node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1)
node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1)
node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0))
node _r_array_T_3 = or(_r_array_T, _r_array_T_2)
node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3)
node _r_array_T_5 = or(_r_array_T_4, stage1_bypass)
node r_array = cat(UInt<1>(0h1), _r_array_T_5)
node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw)
node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw)
node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw)
node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw)
node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo)
node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw)
node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw)
node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw)
node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw)
node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo)
node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo)
node _w_array_T = cat(w_array_hi, w_array_lo)
node _w_array_T_1 = and(priv_rw_ok, _w_array_T)
node _w_array_T_2 = or(_w_array_T_1, stage1_bypass)
node w_array = cat(UInt<1>(0h1), _w_array_T_2)
node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx)
node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx)
node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo)
node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx)
node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo)
node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo)
node _x_array_T = cat(x_array_hi, x_array_lo)
node _x_array_T_1 = and(priv_x_ok, _x_array_T)
node _x_array_T_2 = or(_x_array_T_1, stage1_bypass)
node x_array = cat(UInt<1>(0h1), _x_array_T_2)
node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0))
node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0))
node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr)
node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr)
node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr)
node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr)
node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo)
node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr)
node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr)
node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr)
node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr)
node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo)
node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo)
node _hr_array_T = cat(hr_array_hi, hr_array_lo)
node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx)
node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx)
node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1)
node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx)
node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1)
node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1)
node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1)
node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0))
node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2)
node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass)
node hr_array = cat(UInt<1>(0h1), _hr_array_T_4)
node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw)
node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw)
node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw)
node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw)
node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo)
node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw)
node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw)
node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw)
node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw)
node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo)
node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo)
node _hw_array_T = cat(hw_array_hi, hw_array_lo)
node _hw_array_T_1 = or(_hw_array_T, stage2_bypass)
node hw_array = cat(UInt<1>(0h1), _hw_array_T_1)
node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx)
node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx)
node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo)
node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx)
node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo)
node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo)
node _hx_array_T = cat(hx_array_hi, hx_array_lo)
node _hx_array_T_1 = or(_hx_array_T, stage2_bypass)
node hx_array = cat(UInt<1>(0h1), _hx_array_T_1)
node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0))
node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr)
node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr)
node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr)
node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr)
node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo)
node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr)
node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr)
node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr)
node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr)
node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo)
node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo)
node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1)
node _pr_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pr_array_T_4 = not(_pr_array_T_3)
node pr_array = and(_pr_array_T_2, _pr_array_T_4)
node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0))
node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw)
node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw)
node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw)
node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw)
node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo)
node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw)
node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw)
node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw)
node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw)
node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo)
node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo)
node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1)
node _pw_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pw_array_T_4 = not(_pw_array_T_3)
node pw_array = and(_pw_array_T_2, _pw_array_T_4)
node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0))
node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px)
node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px)
node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px)
node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px)
node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo)
node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px)
node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px)
node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px)
node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px)
node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo)
node _px_array_T_1 = cat(px_array_hi, px_array_lo)
node _px_array_T_2 = cat(_px_array_T, _px_array_T_1)
node _px_array_T_3 = or(ptw_ae_array, final_ae_array)
node _px_array_T_4 = not(_px_array_T_3)
node px_array = and(_px_array_T_2, _px_array_T_4)
node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0))
node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff)
node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff)
node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff)
node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff)
node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo)
node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff)
node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff)
node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff)
node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff)
node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo)
node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo)
node eff_array = cat(_eff_array_T, _eff_array_T_1)
node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0))
node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c)
node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c)
node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo)
node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c)
node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c)
node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo)
node _c_array_T_1 = cat(c_array_hi, c_array_lo)
node c_array = cat(_c_array_T, _c_array_T_1)
node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0))
node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp)
node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp)
node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp)
node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp)
node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo)
node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp)
node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp)
node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp)
node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp)
node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo)
node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo)
node ppp_array = cat(_ppp_array_T, _ppp_array_T_1)
node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0))
node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa)
node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa)
node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa)
node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa)
node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo)
node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa)
node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa)
node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa)
node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa)
node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo)
node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo)
node paa_array = cat(_paa_array_T, _paa_array_T_1)
node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0))
node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal)
node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal)
node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal)
node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal)
node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo)
node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal)
node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal)
node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal)
node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal)
node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo)
node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo)
node pal_array = cat(_pal_array_T, _pal_array_T_1)
node ppp_array_if_cached = or(ppp_array, c_array)
node paa_array_if_cached = or(paa_array, c_array)
node pal_array_if_cached = or(pal_array, c_array)
node _prefetchable_array_T = and(cacheable, homogeneous)
node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1)
node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c)
node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c)
node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo)
node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c)
node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c)
node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo)
node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo)
node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2)
node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size)
node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1))
node _misaligned_T_2 = tail(_misaligned_T_1, 1)
node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2)
node misaligned = orr(_misaligned_T_3)
node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1)
node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2)
node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1)
node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2)
node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3)
node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6)
node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1)
node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2)
node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3)
node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4)
node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8)
node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0))
node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10))
node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1)
node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2)
node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3)
node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8)
node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9)
node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10)
node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15)
node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16)
node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17)
node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18)
node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22)
node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23)
node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10))
node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T)
node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1))
node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1)
node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3)
node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6)
node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7)
node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8)
node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13)
node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14)
node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15)
node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16)
node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20)
node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21)
node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5))
node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17))
node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1)
node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2)
node lrscAllowed = mux(UInt<1>(0h1), UInt<1>(0h0), c_array)
node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0))
node _ae_array_T_1 = not(lrscAllowed)
node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0))
node ae_array = or(_ae_array_T, _ae_array_T_2)
node _ae_ld_array_T = not(pr_array)
node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T)
node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0))
node _ae_st_array_T = not(pw_array)
node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T)
node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0))
node _ae_st_array_T_3 = not(ppp_array_if_cached)
node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0))
node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4)
node _ae_st_array_T_6 = not(pal_array_if_cached)
node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0))
node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7)
node _ae_st_array_T_9 = not(paa_array_if_cached)
node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0))
node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10)
node _must_alloc_array_T = not(ppp_array)
node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0))
node _must_alloc_array_T_2 = not(pal_array)
node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0))
node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3)
node _must_alloc_array_T_5 = not(paa_array)
node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0))
node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6)
node _must_alloc_array_T_8 = not(UInt<14>(0h0))
node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0))
node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9)
node _pf_ld_array_T = mux(cmd_readx, x_array, r_array)
node _pf_ld_array_T_1 = not(_pf_ld_array_T)
node _pf_ld_array_T_2 = not(ptw_ae_array)
node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2)
node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array)
node _pf_ld_array_T_5 = not(ptw_gf_array)
node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5)
node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0))
node _pf_st_array_T = not(w_array)
node _pf_st_array_T_1 = not(ptw_ae_array)
node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1)
node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array)
node _pf_st_array_T_4 = not(ptw_gf_array)
node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4)
node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0))
node _pf_inst_array_T = not(x_array)
node _pf_inst_array_T_1 = not(ptw_ae_array)
node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1)
node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array)
node _pf_inst_array_T_4 = not(ptw_gf_array)
node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4)
node _gf_ld_array_T = and(priv_v, cmd_read)
node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array)
node _gf_ld_array_T_2 = not(_gf_ld_array_T_1)
node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array)
node _gf_ld_array_T_4 = not(ptw_ae_array)
node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4)
node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0))
node _gf_st_array_T = and(priv_v, cmd_write_perms)
node _gf_st_array_T_1 = not(hw_array)
node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array)
node _gf_st_array_T_3 = not(ptw_ae_array)
node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3)
node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0))
node _gf_inst_array_T = not(hx_array)
node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array)
node _gf_inst_array_T_2 = not(ptw_ae_array)
node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2)
node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0))
node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn)
node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T)
node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0))
node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0))
node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0))
node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4)
node _gpa_hits_T = bits(gf_inst_array, 12, 0)
node _gpa_hits_T_1 = not(_gpa_hits_T)
node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1)
node tlb_hit_if_not_gpa_miss = orr(real_hits)
node _tlb_hit_T = and(real_hits, gpa_hits)
node tlb_hit = orr(_tlb_hit_T)
node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0))
node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T)
node _tlb_miss_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2)
node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0))
node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
wire _state_vec_WIRE : UInt<7>[1]
connect _state_vec_WIRE[0], UInt<7>(0h0)
regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE
regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _T_23 = and(io.req.valid, vm_enabled)
when _T_23 :
node _T_24 = or(sector_hits_0, sector_hits_1)
node _T_25 = or(_T_24, sector_hits_2)
node _T_26 = or(_T_25, sector_hits_3)
node _T_27 = or(_T_26, sector_hits_4)
node _T_28 = or(_T_27, sector_hits_5)
node _T_29 = or(_T_28, sector_hits_6)
node _T_30 = or(_T_29, sector_hits_7)
when _T_30 :
node lo_lo = cat(sector_hits_1, sector_hits_0)
node lo_hi = cat(sector_hits_3, sector_hits_2)
node lo = cat(lo_hi, lo_lo)
node hi_lo = cat(sector_hits_5, sector_hits_4)
node hi_hi = cat(sector_hits_7, sector_hits_6)
node hi = cat(hi_hi, hi_lo)
node _T_31 = cat(hi, lo)
node hi_1 = bits(_T_31, 7, 4)
node lo_1 = bits(_T_31, 3, 0)
node _T_32 = orr(hi_1)
node _T_33 = or(hi_1, lo_1)
node hi_2 = bits(_T_33, 3, 2)
node lo_2 = bits(_T_33, 1, 0)
node _T_34 = orr(hi_2)
node _T_35 = or(hi_2, lo_2)
node _T_36 = bits(_T_35, 1, 1)
node _T_37 = cat(_T_34, _T_36)
node _T_38 = cat(_T_32, _T_37)
node state_vec_0_touch_way_sized = bits(_T_38, 2, 0)
node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2)
node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0))
node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3)
node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0)
node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1)
node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0))
node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0)
node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0)
node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0))
node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3)
node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0)
node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0))
node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1)
node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4)
node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8)
node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9)
node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1)
node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0))
node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0)
node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0)
node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0))
node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14)
node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0)
node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0))
node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2)
node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15)
node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19)
node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state)
node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10)
node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21)
connect state_vec[0], _state_vec_0_T_22
node _T_39 = or(superpage_hits_0, superpage_hits_1)
node _T_40 = or(_T_39, superpage_hits_2)
node _T_41 = or(_T_40, superpage_hits_3)
when _T_41 :
node lo_3 = cat(superpage_hits_1, superpage_hits_0)
node hi_3 = cat(superpage_hits_3, superpage_hits_2)
node _T_42 = cat(hi_3, lo_3)
node hi_4 = bits(_T_42, 3, 2)
node lo_4 = bits(_T_42, 1, 0)
node _T_43 = orr(hi_4)
node _T_44 = or(hi_4, lo_4)
node _T_45 = bits(_T_44, 1, 1)
node _T_46 = cat(_T_43, _T_45)
node state_reg_touch_way_sized = bits(_T_46, 1, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg_1, 1, 1)
node state_reg_right_subtree_state = bits(state_reg_1, 0, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0))
node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2)
node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0)
node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0))
node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state)
node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3)
node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7)
connect state_reg_1, _state_reg_T_8
node _multipleHits_T = bits(real_hits, 5, 0)
node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0)
node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0)
node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0)
node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1)
node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0)
node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0)
node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1)
node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0)
node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne)
node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne)
node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7)
node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1)
node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo)
node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1)
node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9)
node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3)
node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0)
node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0)
node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1)
node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0)
node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0)
node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1)
node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0)
node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2)
node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2)
node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16)
node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3)
node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1)
node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3)
node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18)
node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4)
node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2)
node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4)
node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20)
node _multipleHits_T_21 = bits(real_hits, 12, 6)
node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0)
node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0)
node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0)
node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1)
node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0)
node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0)
node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1)
node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0)
node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5)
node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5)
node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28)
node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6)
node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3)
node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6)
node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30)
node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3)
node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0)
node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0)
node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0)
node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1)
node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0)
node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7)
node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7)
node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36)
node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2)
node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0)
node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0)
node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1)
node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0)
node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8)
node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8)
node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41)
node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9)
node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4)
node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9)
node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43)
node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10)
node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5)
node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10)
node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45)
node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6)
node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11)
node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
node _io_resp_pf_ld_T = and(UInt<1>(0h0), cmd_read)
node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits)
node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1)
node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2)
connect io.resp.pf.ld, _io_resp_pf_ld_T_3
node _io_resp_pf_st_T = and(UInt<1>(0h0), cmd_write_perms)
node _io_resp_pf_st_T_1 = and(pf_st_array, hits)
node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1)
node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2)
connect io.resp.pf.st, _io_resp_pf_st_T_3
node _io_resp_pf_inst_T = and(pf_inst_array, hits)
node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T)
node _io_resp_pf_inst_T_2 = or(UInt<1>(0h0), _io_resp_pf_inst_T_1)
connect io.resp.pf.inst, _io_resp_pf_inst_T_2
node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read)
node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits)
node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1)
node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2)
connect io.resp.gf.ld, _io_resp_gf_ld_T_3
node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms)
node _io_resp_gf_st_T_1 = and(gf_st_array, hits)
node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1)
node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2)
connect io.resp.gf.st, _io_resp_gf_st_T_3
node _io_resp_gf_inst_T = and(gf_inst_array, hits)
node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T)
node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1)
connect io.resp.gf.inst, _io_resp_gf_inst_T_2
node _io_resp_ae_ld_T = and(ae_ld_array, hits)
node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T)
connect io.resp.ae.ld, _io_resp_ae_ld_T_1
node _io_resp_ae_st_T = and(ae_st_array, hits)
node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T)
connect io.resp.ae.st, _io_resp_ae_st_T_1
node _io_resp_ae_inst_T = not(px_array)
node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits)
node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1)
connect io.resp.ae.inst, _io_resp_ae_inst_T_2
node _io_resp_ma_ld_T = and(misaligned, cmd_read)
connect io.resp.ma.ld, _io_resp_ma_ld_T
node _io_resp_ma_st_T = and(misaligned, cmd_write)
connect io.resp.ma.st, _io_resp_ma_st_T
connect io.resp.ma.inst, UInt<1>(0h0)
node _io_resp_cacheable_T = and(c_array, hits)
node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T)
connect io.resp.cacheable, _io_resp_cacheable_T_1
node _io_resp_must_alloc_T = and(must_alloc_array, hits)
node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T)
connect io.resp.must_alloc, _io_resp_must_alloc_T_1
node _io_resp_prefetchable_T = and(prefetchable_array, hits)
node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T)
node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1))
connect io.resp.prefetchable, _io_resp_prefetchable_T_2
node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch)
node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss)
node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits)
connect io.resp.miss, _io_resp_miss_T_2
node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0)
node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T)
connect io.resp.paddr, _io_resp_paddr_T_1
connect io.resp.size, io.req.bits.size
connect io.resp.cmd, io.req.bits.cmd
node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte)
connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T
node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0))
node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn)
node _io_resp_gpa_page_T_2 = shr(r_gpa, 12)
node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2)
node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0)
node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0)
node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1)
node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset)
connect io.resp.gpa, _io_resp_gpa_T
node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1))
connect io.ptw.req.valid, _io_ptw_req_valid_T
node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0))
connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T
connect io.ptw.req.bits.bits.addr, r_refill_tag
connect io.ptw.req.bits.bits.vstage1, r_vstage1_en
connect io.ptw.req.bits.bits.stage2, r_stage2_en
connect io.ptw.req.bits.bits.need_gpa, r_need_gpa | module ITLB( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
input io_req_valid, // @[TLB.scala:320:14]
input [33:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [33:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [32:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_bits_valid, // @[TLB.scala:320:14]
output [20:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_vstage1, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_stage2, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [32:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_debug, // @[TLB.scala:320:14]
input io_ptw_gstatus_cease, // @[TLB.scala:320:14]
input io_ptw_gstatus_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14]
input io_ptw_gstatus_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14]
input io_ptw_gstatus_v, // @[TLB.scala:320:14]
input io_ptw_gstatus_sd, // @[TLB.scala:320:14]
input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpv, // @[TLB.scala:320:14]
input io_ptw_gstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_mbe, // @[TLB.scala:320:14]
input io_ptw_gstatus_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14]
input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14]
input io_ptw_gstatus_tsr, // @[TLB.scala:320:14]
input io_ptw_gstatus_tw, // @[TLB.scala:320:14]
input io_ptw_gstatus_tvm, // @[TLB.scala:320:14]
input io_ptw_gstatus_mxr, // @[TLB.scala:320:14]
input io_ptw_gstatus_sum, // @[TLB.scala:320:14]
input io_ptw_gstatus_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14]
input io_ptw_gstatus_spp, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpie, // @[TLB.scala:320:14]
input io_ptw_gstatus_ube, // @[TLB.scala:320:14]
input io_ptw_gstatus_spie, // @[TLB.scala:320:14]
input io_ptw_gstatus_upie, // @[TLB.scala:320:14]
input io_ptw_gstatus_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_hie, // @[TLB.scala:320:14]
input io_ptw_gstatus_sie, // @[TLB.scala:320:14]
input io_ptw_gstatus_uie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_value, // @[TLB.scala:320:14]
input io_kill // @[TLB.scala:320:14]
);
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [33:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [32:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [32:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7]
wire io_kill_0 = io_kill; // @[TLB.scala:318:7]
wire [41:0] _mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77]
wire [20:0] io_ptw_req_bits_bits_addr_0 = 21'h0; // @[TLB.scala:318:7, :339:29]
wire [20:0] _io_resp_gpa_page_T_2 = 21'h0; // @[TLB.scala:339:29, :657:58]
wire [11:0] _io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47]
wire [13:0] hits = 14'h2000; // @[TLB.scala:442:17]
wire [19:0] _ppn_T_2 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_3 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_4 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_5 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_6 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_7 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_8 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_9 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_10 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_11 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_12 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_13 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_14 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_16 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_17 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_18 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_19 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_20 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_21 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_22 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_23 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_24 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_25 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_26 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_27 = 20'h0; // @[Mux.scala:30:73]
wire [3:0] _misaligned_T = 4'h4; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = 5'h3; // @[TLB.scala:550:69]
wire [3:0] _misaligned_T_2 = 4'h3; // @[TLB.scala:550:69]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _ae_array_T_1 = 14'h3FFF; // @[TLB.scala:583:19]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [12:0] _stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [6:0] real_hits_hi = 7'h0; // @[package.scala:45:27]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [6:0] _multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39]
wire [13:0] lrscAllowed = 14'h0; // @[TLB.scala:580:24]
wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8]
wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8]
wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8]
wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53]
wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8]
wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53]
wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8]
wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53]
wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8]
wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8]
wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43]
wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8]
wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43]
wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8]
wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46]
wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33]
wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_resp_size = 2'h2; // @[TLB.scala:318:7]
wire [12:0] real_hits = 13'h0; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = 13'h0; // @[TLB.scala:513:23]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _r_array_T_2 = 13'h0; // @[TLB.scala:520:74]
wire [12:0] _hr_array_T_2 = 13'h0; // @[TLB.scala:524:60]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [12:0] _tlb_hit_T = 13'h0; // @[TLB.scala:611:28]
wire [2:0] real_hits_lo_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] waddr_1 = 3'h0; // @[TLB.scala:485:22]
wire [2:0] state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38]
wire [2:0] _multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] _multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39]
wire [2:0] _multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37]
wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [5:0] real_hits_lo = 6'h0; // @[package.scala:45:27]
wire [5:0] _multipleHits_T = 6'h0; // @[Misc.scala:181:37]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14]
wire [1:0] io_ptw_status_sxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] special_entry_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] waddr = 2'h0; // @[TLB.scala:477:22]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_1 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_2 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_3 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_4 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_5 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_6 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_7 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] _c_array_T = 2'h0; // @[TLB.scala:537:25]
wire [1:0] _prefetchable_array_T_1 = 2'h0; // @[TLB.scala:547:59]
wire [1:0] _multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37]
wire [1:0] _multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7, :320:14]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7, :320:14]
wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [43:0] satp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [3:0] io_ptw_ptbr_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] satp_mode = 4'h0; // @[TLB.scala:373:17]
wire [3:0] real_hits_hi_hi = 4'h0; // @[package.scala:45:27]
wire [3:0] _multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39]
wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7]
wire io_resp_miss = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_valid = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1_0 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2_0 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_tsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_tw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_tvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mxr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sum = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mprv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_spp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_spie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire priv_uses_vm = 1'h0; // @[TLB.scala:372:27]
wire _stage1_en_T = 1'h0; // @[TLB.scala:374:41]
wire stage1_en = 1'h0; // @[TLB.scala:374:29]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vm_enabled_T = 1'h0; // @[TLB.scala:399:31]
wire _vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45]
wire vm_enabled = 1'h0; // @[TLB.scala:399:61]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire do_refill = 1'h0; // @[TLB.scala:408:29]
wire _invalidate_refill_T = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59]
wire _mpu_ppn_T = 1'h0; // @[TLB.scala:413:32]
wire _mpu_priv_T = 1'h0; // @[TLB.scala:415:52]
wire _mpu_priv_T_1 = 1'h0; // @[TLB.scala:415:38]
wire cacheable = 1'h0; // @[TLB.scala:425:41]
wire _sector_hits_T = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_8 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_16 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_24 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_32 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_40 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_48 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_56 = 1'h0; // @[package.scala:81:59]
wire superpage_hits_0 = 1'h0; // @[TLB.scala:188:18]
wire superpage_hits_1 = 1'h0; // @[TLB.scala:188:18]
wire superpage_hits_2 = 1'h0; // @[TLB.scala:188:18]
wire superpage_hits_3 = 1'h0; // @[TLB.scala:188:18]
wire _hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_0 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_1 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_2 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_3 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_4 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_5 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_6 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_7 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_53 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_8 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_59 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_9 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_65 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_10 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_71 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_11 = 1'h0; // @[TLB.scala:440:44]
wire hitsVec_12 = 1'h0; // @[TLB.scala:440:44]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_c = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire sum = 1'h0; // @[TLB.scala:510:16]
wire _priv_rw_ok_T = 1'h0; // @[TLB.scala:513:24]
wire _priv_rw_ok_T_1 = 1'h0; // @[TLB.scala:513:32]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire mxr = 1'h0; // @[TLB.scala:518:31]
wire _prefetchable_array_T = 1'h0; // @[TLB.scala:547:43]
wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33]
wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40]
wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43]
wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41]
wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32]
wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49]
wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42]
wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66]
wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59]
wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44]
wire cmd_write = 1'h0; // @[Consts.scala:90:76]
wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60]
wire tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43]
wire tlb_hit = 1'h0; // @[TLB.scala:611:40]
wire _tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29]
wire _tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53]
wire tlb_miss = 1'h0; // @[TLB.scala:613:64]
wire state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38]
wire state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38]
wire state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38]
wire _multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits = 1'h0; // @[Misc.scala:183:49]
wire _io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28]
wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72]
wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41]
wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31]
wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51]
wire _io_resp_miss_T = 1'h0; // @[TLB.scala:651:29]
wire _io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52]
wire _io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire _io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29]
wire [1:0] io_req_bits_prv = 2'h3; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv = 2'h3; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv = 2'h3; // @[TLB.scala:318:7]
wire io_req_ready = 1'h1; // @[TLB.scala:318:7]
wire priv_s = 1'h1; // @[TLB.scala:370:20]
wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64]
wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81]
wire _homogeneous_T_53 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_3 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_8 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_18 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_51 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_57 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_63 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_69 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_75 = 1'h1; // @[TLB.scala:174:105]
wire _hits_T = 1'h1; // @[TLB.scala:442:18]
wire _ppn_T = 1'h1; // @[TLB.scala:502:30]
wire _stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _cmd_read_T = 1'h1; // @[package.scala:16:47]
wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59]
wire cmd_read = 1'h1; // @[Consts.scala:89:68]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56]
wire _tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67]
wire _io_req_ready_T = 1'h1; // @[TLB.scala:631:25]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [33:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire invalidate_refill = io_sfence_valid_0; // @[TLB.scala:318:7, :410:88]
wire _io_ptw_req_bits_valid_T; // @[TLB.scala:663:28]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [33:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid_0; // @[TLB.scala:318:7]
wire [20:0] vpn = io_req_bits_vaddr_0[32:12]; // @[TLB.scala:318:7, :335:30]
wire [20:0] _sector_hits_T_3 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_11 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_19 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_27 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_35 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_43 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_51 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_59 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T_5 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T_10 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T_15 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_6 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_12 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_18 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_24 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_30 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_36 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_42 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_48 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_54 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_60 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_66 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_72 = vpn; // @[TLB.scala:174:61, :335:30]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [21:0] _mpu_ppn_T_24 = io_req_bits_vaddr_0[33:12]; // @[TLB.scala:318:7, :413:146]
wire [21:0] _mpu_ppn_T_25 = _mpu_ppn_T_24; // @[TLB.scala:413:{20,146}]
wire [21:0] mpu_ppn = _mpu_ppn_T_25; // @[TLB.scala:412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [33:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [33:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [33:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h3}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_2; // @[TLB.scala:415:{27,103}]
wire [34:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_2 = _homogeneous_T_1 & 35'h7FFFFE000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_45 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [33:0] _homogeneous_T_5 = {mpu_physaddr[33:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_7 = _homogeneous_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN = {mpu_physaddr[33:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_54; // @[Parameters.scala:137:31]
assign _homogeneous_T_54 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_92; // @[Parameters.scala:137:31]
assign _homogeneous_T_92 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_105; // @[Parameters.scala:137:31]
assign _homogeneous_T_105 = _GEN; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_12 = _homogeneous_T_11 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_0 = {mpu_physaddr[33:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_15; // @[Parameters.scala:137:31]
assign _homogeneous_T_15 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_66; // @[Parameters.scala:137:31]
assign _homogeneous_T_66 = _GEN_0; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_17 = _homogeneous_T_16 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_1 = {mpu_physaddr[33:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_20; // @[Parameters.scala:137:31]
assign _homogeneous_T_20 = _GEN_1; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_71; // @[Parameters.scala:137:31]
assign _homogeneous_T_71 = _GEN_1; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_22 = _homogeneous_T_21 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_25 = {mpu_physaddr[33:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_27 = _homogeneous_T_26 & 35'h7FC000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_30 = {mpu_physaddr[33:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_32 = _homogeneous_T_31 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_35 = {mpu_physaddr[33:31], mpu_physaddr[30:0] ^ 31'h60000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_37 = _homogeneous_T_36 & 35'h7E0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_40 = {mpu_physaddr[33:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [34:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_42 = _homogeneous_T_41 & 35'h7FFFFC000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_46 = _homogeneous_T_45 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_47 = _homogeneous_T_46 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_48 = _homogeneous_T_47 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_49 = _homogeneous_T_48 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_50 = _homogeneous_T_49 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_52 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire [34:0] _homogeneous_T_55 = {1'h0, _homogeneous_T_54}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_56 = _homogeneous_T_55 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_57 = _homogeneous_T_56; // @[Parameters.scala:137:46]
wire _homogeneous_T_58 = _homogeneous_T_57 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_59 = _homogeneous_T_58; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_60 = ~_homogeneous_T_59; // @[TLBPermissions.scala:87:{22,66}]
wire [33:0] _homogeneous_T_61 = {mpu_physaddr[33:13], mpu_physaddr[12:0] ^ 13'h1000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_62 = {1'h0, _homogeneous_T_61}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_63 = _homogeneous_T_62 & 35'hDA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_64 = _homogeneous_T_63; // @[Parameters.scala:137:46]
wire _homogeneous_T_65 = _homogeneous_T_64 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_86 = _homogeneous_T_65; // @[TLBPermissions.scala:87:66]
wire [34:0] _homogeneous_T_67 = {1'h0, _homogeneous_T_66}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_68 = _homogeneous_T_67 & 35'hDA103000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_69 = _homogeneous_T_68; // @[Parameters.scala:137:46]
wire _homogeneous_T_70 = _homogeneous_T_69 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _homogeneous_T_72 = {1'h0, _homogeneous_T_71}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_73 = _homogeneous_T_72 & 35'hDA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_74 = _homogeneous_T_73; // @[Parameters.scala:137:46]
wire _homogeneous_T_75 = _homogeneous_T_74 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_76 = {mpu_physaddr[33:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_77 = {1'h0, _homogeneous_T_76}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_78 = _homogeneous_T_77 & 35'hD8000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_79 = _homogeneous_T_78; // @[Parameters.scala:137:46]
wire _homogeneous_T_80 = _homogeneous_T_79 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_81 = {mpu_physaddr[33:29], mpu_physaddr[28:0] ^ 29'h10000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_82 = {1'h0, _homogeneous_T_81}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_83 = _homogeneous_T_82 & 35'hDA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_84 = _homogeneous_T_83; // @[Parameters.scala:137:46]
wire _homogeneous_T_85 = _homogeneous_T_84 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_87 = _homogeneous_T_86 | _homogeneous_T_70; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_88 = _homogeneous_T_87 | _homogeneous_T_75; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_89 = _homogeneous_T_88 | _homogeneous_T_80; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_90 = _homogeneous_T_89 | _homogeneous_T_85; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_91 = ~_homogeneous_T_90; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] _homogeneous_T_93 = {1'h0, _homogeneous_T_92}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_94 = _homogeneous_T_93 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_95 = _homogeneous_T_94; // @[Parameters.scala:137:46]
wire _homogeneous_T_96 = _homogeneous_T_95 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_102 = _homogeneous_T_96; // @[TLBPermissions.scala:87:66]
wire [33:0] _GEN_2 = {mpu_physaddr[33:31], mpu_physaddr[30:0] ^ 31'h40000000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_110; // @[Parameters.scala:137:31]
assign _homogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_99 = _homogeneous_T_98 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_103 = _homogeneous_T_102 | _homogeneous_T_101; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_104 = ~_homogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] _homogeneous_T_106 = {1'h0, _homogeneous_T_105}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_107 = _homogeneous_T_106 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_108 = _homogeneous_T_107; // @[Parameters.scala:137:46]
wire _homogeneous_T_109 = _homogeneous_T_108 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_115 = _homogeneous_T_109; // @[TLBPermissions.scala:87:66]
wire [34:0] _homogeneous_T_111 = {1'h0, _homogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_112 = _homogeneous_T_111 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_113 = _homogeneous_T_112; // @[Parameters.scala:137:46]
wire _homogeneous_T_114 = _homogeneous_T_113 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_116 = _homogeneous_T_115 | _homogeneous_T_114; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_117 = ~_homogeneous_T_116; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [34:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _sector_hits_T_1 = _sector_hits_T; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_4 = _sector_hits_T_3[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_12 = _sector_hits_T_11[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_20 = _sector_hits_T_19[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_28 = _sector_hits_T_27[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_36 = _sector_hits_T_35[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_44 = _sector_hits_T_43[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_52 = _sector_hits_T_51[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_60 = _sector_hits_T_59[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire [20:0] _superpage_hits_T_1 = _superpage_hits_T; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_4 = _superpage_hits_T_2 & _superpage_hits_T_3; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _superpage_hits_T_6 = _superpage_hits_T_5; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_9 = _superpage_hits_T_7 & _superpage_hits_T_8; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _superpage_hits_T_11 = _superpage_hits_T_10; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_14 = _superpage_hits_T_12 & _superpage_hits_T_13; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _superpage_hits_T_16 = _superpage_hits_T_15; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_17 = _superpage_hits_T_16 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_19 = _superpage_hits_T_17 & _superpage_hits_T_18; // @[TLB.scala:174:{86,95,105}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [18:0] _hitsVec_T_1 = _hitsVec_T[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_7 = _hitsVec_T_6[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_13 = _hitsVec_T_12[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_19 = _hitsVec_T_18[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_25 = _hitsVec_T_24[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_31 = _hitsVec_T_30[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_37 = _hitsVec_T_36[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_43 = _hitsVec_T_42[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_49 = _hitsVec_T_48; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_52 = _hitsVec_T_50 & _hitsVec_T_51; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_55 = _hitsVec_T_54; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_56 = _hitsVec_T_55 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_58 = _hitsVec_T_56 & _hitsVec_T_57; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_61 = _hitsVec_T_60; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_62 = _hitsVec_T_61 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_64 = _hitsVec_T_62 & _hitsVec_T_63; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_67 = _hitsVec_T_66; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_68 = _hitsVec_T_67 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_70 = _hitsVec_T_68 & _hitsVec_T_69; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_73 = _hitsVec_T_72; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_74 = _hitsVec_T_73 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_76 = _hitsVec_T_74 & _hitsVec_T_75; // @[TLB.scala:174:{86,95,105}]
wire _hitsVec_T_77 = _hitsVec_T_76; // @[TLB.scala:174:95, :188:18]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_ae_stage2; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
assign newEntry_ae_stage2 = _newEntry_ae_stage2_T_1; // @[TLB.scala:449:24, :456:84]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_3 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [1:0] _GEN_4 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_5 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_6 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_7 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_8 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [20:0] _GEN_9 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire [19:0] _ppn_T_1 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_15 = _ppn_T_1; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_28 = _ppn_T_15; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_28; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire [1:0] _GEN_10 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_11 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_12 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_13 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] _GEN_14 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_14; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_14; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = _priv_rw_ok_T_5; // @[TLB.scala:513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_6; // @[TLB.scala:513:{70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [12:0] priv_x_ok = _priv_x_ok_T_1; // @[TLB.scala:516:{22,31}]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_15 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_15; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_15; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_16 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_16; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_16; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_17 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_17; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_17; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_18 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_18; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_18; // @[package.scala:45:27]
wire [1:0] _GEN_19 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_19; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_19; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_20 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_20; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_20; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_21 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_21; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_21; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_22 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_22; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_22; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_23 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_23; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_23; // @[package.scala:45:27]
wire [1:0] _GEN_24 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_24; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_24; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_25 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_25; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_25; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_25; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _GEN_26 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_26; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_26; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_27 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_27; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_27; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_28 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_28; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_28; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_29 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_29; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_29; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {2'h0, _c_array_T_1}; // @[package.scala:45:27]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {2'h0, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [33:0] _misaligned_T_3 = {32'h0, io_req_bits_vaddr_0[1:0]}; // @[TLB.scala:318:7, :550:39]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = vpn == 21'h0; // @[TLB.scala:335:30, :339:29, :606:73]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire [1:0] lo_lo = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_lo = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = ~state_vec_0_set_left_older_1 & _state_vec_0_T_3; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 & _state_vec_0_T_7; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? 3'h0 : _state_vec_0_T_9; // @[Replacement.scala:196:33, :202:12, :203:16]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = ~state_vec_0_set_left_older_2 & _state_vec_0_T_14; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 & _state_vec_0_T_18; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] lo_3 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_3 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = ~state_reg_set_left_older & _state_reg_T_2; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older & _state_reg_T_6; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & 14'h2000; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & 14'h2000; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = _io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & 14'h2000; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
wire [13:0] _io_resp_cacheable_T = c_array & 14'h2000; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & 14'h2000; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [21:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [21:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign _io_ptw_req_bits_valid_T = ~io_kill_0; // @[TLB.scala:318:7, :663:28]
assign io_ptw_req_bits_valid_0 = _io_ptw_req_bits_valid_T; // @[TLB.scala:318:7, :663:28]
OptimizationBarrier_TLBEntryData_28 mpu_ppn_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77]
.io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77]
.io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77]
.io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77]
.io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77]
.io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77]
.io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77]
.io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77]
.io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77]
.io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77]
.io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77]
.io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77]
.io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77]
.io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77]
.io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77]
.io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77]
.io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77]
.io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage) // @[TLB.scala:170:77]
); // @[package.scala:267:25]
PMPChecker_s2 pmp ( // @[TLB.scala:416:19]
.clock (clock),
.reset (reset),
.io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14]
.io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7]
.io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7]
.io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7]
.io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7]
.io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7]
.io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7]
.io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7]
.io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7]
.io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7]
.io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15]
.io_r (_pmp_io_r),
.io_w (_pmp_io_w),
.io_x (_pmp_io_x)
); // @[TLB.scala:416:19]
PMAChecker_2 pma ( // @[TLB.scala:422:19]
.clock (clock),
.reset (reset),
.io_paddr (mpu_physaddr), // @[TLB.scala:414:25]
.io_resp_r (_pma_io_resp_r),
.io_resp_w (_pma_io_resp_w),
.io_resp_pp (_pma_io_resp_pp),
.io_resp_al (_pma_io_resp_al),
.io_resp_aa (_pma_io_resp_aa),
.io_resp_x (_pma_io_resp_x),
.io_resp_eff (_pma_io_resp_eff)
); // @[TLB.scala:422:19]
assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24]
assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24]
assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24]
assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24]
OptimizationBarrier_TLBEntryData_29 entries_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_io_y_u),
.io_y_ae_ptw (_entries_barrier_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2),
.io_y_pf (_entries_barrier_io_y_pf),
.io_y_gf (_entries_barrier_io_y_gf),
.io_y_sw (_entries_barrier_io_y_sw),
.io_y_sx (_entries_barrier_io_y_sx),
.io_y_sr (_entries_barrier_io_y_sr),
.io_y_hw (_entries_barrier_io_y_hw),
.io_y_hx (_entries_barrier_io_y_hx),
.io_y_hr (_entries_barrier_io_y_hr),
.io_y_pw (_entries_barrier_io_y_pw),
.io_y_px (_entries_barrier_io_y_px),
.io_y_pr (_entries_barrier_io_y_pr),
.io_y_ppp (_entries_barrier_io_y_ppp),
.io_y_pal (_entries_barrier_io_y_pal),
.io_y_paa (_entries_barrier_io_y_paa),
.io_y_eff (_entries_barrier_io_y_eff),
.io_y_c (_entries_barrier_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_30 entries_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_1_io_y_u),
.io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_1_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2),
.io_y_pf (_entries_barrier_1_io_y_pf),
.io_y_gf (_entries_barrier_1_io_y_gf),
.io_y_sw (_entries_barrier_1_io_y_sw),
.io_y_sx (_entries_barrier_1_io_y_sx),
.io_y_sr (_entries_barrier_1_io_y_sr),
.io_y_hw (_entries_barrier_1_io_y_hw),
.io_y_hx (_entries_barrier_1_io_y_hx),
.io_y_hr (_entries_barrier_1_io_y_hr),
.io_y_pw (_entries_barrier_1_io_y_pw),
.io_y_px (_entries_barrier_1_io_y_px),
.io_y_pr (_entries_barrier_1_io_y_pr),
.io_y_ppp (_entries_barrier_1_io_y_ppp),
.io_y_pal (_entries_barrier_1_io_y_pal),
.io_y_paa (_entries_barrier_1_io_y_paa),
.io_y_eff (_entries_barrier_1_io_y_eff),
.io_y_c (_entries_barrier_1_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_31 entries_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_2_io_y_u),
.io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_2_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2),
.io_y_pf (_entries_barrier_2_io_y_pf),
.io_y_gf (_entries_barrier_2_io_y_gf),
.io_y_sw (_entries_barrier_2_io_y_sw),
.io_y_sx (_entries_barrier_2_io_y_sx),
.io_y_sr (_entries_barrier_2_io_y_sr),
.io_y_hw (_entries_barrier_2_io_y_hw),
.io_y_hx (_entries_barrier_2_io_y_hx),
.io_y_hr (_entries_barrier_2_io_y_hr),
.io_y_pw (_entries_barrier_2_io_y_pw),
.io_y_px (_entries_barrier_2_io_y_px),
.io_y_pr (_entries_barrier_2_io_y_pr),
.io_y_ppp (_entries_barrier_2_io_y_ppp),
.io_y_pal (_entries_barrier_2_io_y_pal),
.io_y_paa (_entries_barrier_2_io_y_paa),
.io_y_eff (_entries_barrier_2_io_y_eff),
.io_y_c (_entries_barrier_2_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_32 entries_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_3_io_y_u),
.io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_3_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2),
.io_y_pf (_entries_barrier_3_io_y_pf),
.io_y_gf (_entries_barrier_3_io_y_gf),
.io_y_sw (_entries_barrier_3_io_y_sw),
.io_y_sx (_entries_barrier_3_io_y_sx),
.io_y_sr (_entries_barrier_3_io_y_sr),
.io_y_hw (_entries_barrier_3_io_y_hw),
.io_y_hx (_entries_barrier_3_io_y_hx),
.io_y_hr (_entries_barrier_3_io_y_hr),
.io_y_pw (_entries_barrier_3_io_y_pw),
.io_y_px (_entries_barrier_3_io_y_px),
.io_y_pr (_entries_barrier_3_io_y_pr),
.io_y_ppp (_entries_barrier_3_io_y_ppp),
.io_y_pal (_entries_barrier_3_io_y_pal),
.io_y_paa (_entries_barrier_3_io_y_paa),
.io_y_eff (_entries_barrier_3_io_y_eff),
.io_y_c (_entries_barrier_3_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_33 entries_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_4_io_y_u),
.io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_4_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2),
.io_y_pf (_entries_barrier_4_io_y_pf),
.io_y_gf (_entries_barrier_4_io_y_gf),
.io_y_sw (_entries_barrier_4_io_y_sw),
.io_y_sx (_entries_barrier_4_io_y_sx),
.io_y_sr (_entries_barrier_4_io_y_sr),
.io_y_hw (_entries_barrier_4_io_y_hw),
.io_y_hx (_entries_barrier_4_io_y_hx),
.io_y_hr (_entries_barrier_4_io_y_hr),
.io_y_pw (_entries_barrier_4_io_y_pw),
.io_y_px (_entries_barrier_4_io_y_px),
.io_y_pr (_entries_barrier_4_io_y_pr),
.io_y_ppp (_entries_barrier_4_io_y_ppp),
.io_y_pal (_entries_barrier_4_io_y_pal),
.io_y_paa (_entries_barrier_4_io_y_paa),
.io_y_eff (_entries_barrier_4_io_y_eff),
.io_y_c (_entries_barrier_4_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_34 entries_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_5_io_y_u),
.io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_5_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2),
.io_y_pf (_entries_barrier_5_io_y_pf),
.io_y_gf (_entries_barrier_5_io_y_gf),
.io_y_sw (_entries_barrier_5_io_y_sw),
.io_y_sx (_entries_barrier_5_io_y_sx),
.io_y_sr (_entries_barrier_5_io_y_sr),
.io_y_hw (_entries_barrier_5_io_y_hw),
.io_y_hx (_entries_barrier_5_io_y_hx),
.io_y_hr (_entries_barrier_5_io_y_hr),
.io_y_pw (_entries_barrier_5_io_y_pw),
.io_y_px (_entries_barrier_5_io_y_px),
.io_y_pr (_entries_barrier_5_io_y_pr),
.io_y_ppp (_entries_barrier_5_io_y_ppp),
.io_y_pal (_entries_barrier_5_io_y_pal),
.io_y_paa (_entries_barrier_5_io_y_paa),
.io_y_eff (_entries_barrier_5_io_y_eff),
.io_y_c (_entries_barrier_5_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_35 entries_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_12_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_12_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_12_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_12_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_12_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_12_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_12_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_12_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_12_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_12_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_12_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_12_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_12_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_12_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_12_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_12_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_12_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_12_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_12_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_12_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_12_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_12_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_12_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_6_io_y_u),
.io_y_ae_ptw (_entries_barrier_6_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_6_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_6_io_y_ae_stage2),
.io_y_pf (_entries_barrier_6_io_y_pf),
.io_y_gf (_entries_barrier_6_io_y_gf),
.io_y_sw (_entries_barrier_6_io_y_sw),
.io_y_sx (_entries_barrier_6_io_y_sx),
.io_y_sr (_entries_barrier_6_io_y_sr),
.io_y_hw (_entries_barrier_6_io_y_hw),
.io_y_hx (_entries_barrier_6_io_y_hx),
.io_y_hr (_entries_barrier_6_io_y_hr),
.io_y_pw (_entries_barrier_6_io_y_pw),
.io_y_px (_entries_barrier_6_io_y_px),
.io_y_pr (_entries_barrier_6_io_y_pr),
.io_y_ppp (_entries_barrier_6_io_y_ppp),
.io_y_pal (_entries_barrier_6_io_y_pal),
.io_y_paa (_entries_barrier_6_io_y_paa),
.io_y_eff (_entries_barrier_6_io_y_eff),
.io_y_c (_entries_barrier_6_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_36 entries_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_14_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_14_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_14_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_14_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_14_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_14_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_14_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_14_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_14_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_14_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_14_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_14_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_14_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_14_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_14_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_14_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_14_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_14_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_14_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_14_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_14_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_14_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_14_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_7_io_y_u),
.io_y_ae_ptw (_entries_barrier_7_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_7_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_7_io_y_ae_stage2),
.io_y_pf (_entries_barrier_7_io_y_pf),
.io_y_gf (_entries_barrier_7_io_y_gf),
.io_y_sw (_entries_barrier_7_io_y_sw),
.io_y_sx (_entries_barrier_7_io_y_sx),
.io_y_sr (_entries_barrier_7_io_y_sr),
.io_y_hw (_entries_barrier_7_io_y_hw),
.io_y_hx (_entries_barrier_7_io_y_hx),
.io_y_hr (_entries_barrier_7_io_y_hr),
.io_y_pw (_entries_barrier_7_io_y_pw),
.io_y_px (_entries_barrier_7_io_y_px),
.io_y_pr (_entries_barrier_7_io_y_pr),
.io_y_ppp (_entries_barrier_7_io_y_ppp),
.io_y_pal (_entries_barrier_7_io_y_pal),
.io_y_paa (_entries_barrier_7_io_y_paa),
.io_y_eff (_entries_barrier_7_io_y_eff),
.io_y_c (_entries_barrier_7_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_37 entries_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_16_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_16_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_16_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_16_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_16_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_16_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_16_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_16_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_16_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_16_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_16_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_16_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_16_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_16_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_16_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_16_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_16_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_16_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_16_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_16_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_16_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_16_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_16_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_8_io_y_u),
.io_y_ae_ptw (_entries_barrier_8_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_8_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_8_io_y_ae_stage2),
.io_y_pf (_entries_barrier_8_io_y_pf),
.io_y_gf (_entries_barrier_8_io_y_gf),
.io_y_sw (_entries_barrier_8_io_y_sw),
.io_y_sx (_entries_barrier_8_io_y_sx),
.io_y_sr (_entries_barrier_8_io_y_sr),
.io_y_hw (_entries_barrier_8_io_y_hw),
.io_y_hx (_entries_barrier_8_io_y_hx),
.io_y_hr (_entries_barrier_8_io_y_hr),
.io_y_pw (_entries_barrier_8_io_y_pw),
.io_y_px (_entries_barrier_8_io_y_px),
.io_y_pr (_entries_barrier_8_io_y_pr),
.io_y_ppp (_entries_barrier_8_io_y_ppp),
.io_y_pal (_entries_barrier_8_io_y_pal),
.io_y_paa (_entries_barrier_8_io_y_paa),
.io_y_eff (_entries_barrier_8_io_y_eff),
.io_y_c (_entries_barrier_8_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_38 entries_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_18_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_18_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_18_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_18_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_18_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_18_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_18_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_18_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_18_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_18_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_18_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_18_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_18_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_18_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_18_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_18_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_18_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_18_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_18_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_18_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_18_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_18_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_18_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_9_io_y_u),
.io_y_ae_ptw (_entries_barrier_9_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_9_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_9_io_y_ae_stage2),
.io_y_pf (_entries_barrier_9_io_y_pf),
.io_y_gf (_entries_barrier_9_io_y_gf),
.io_y_sw (_entries_barrier_9_io_y_sw),
.io_y_sx (_entries_barrier_9_io_y_sx),
.io_y_sr (_entries_barrier_9_io_y_sr),
.io_y_hw (_entries_barrier_9_io_y_hw),
.io_y_hx (_entries_barrier_9_io_y_hx),
.io_y_hr (_entries_barrier_9_io_y_hr),
.io_y_pw (_entries_barrier_9_io_y_pw),
.io_y_px (_entries_barrier_9_io_y_px),
.io_y_pr (_entries_barrier_9_io_y_pr),
.io_y_ppp (_entries_barrier_9_io_y_ppp),
.io_y_pal (_entries_barrier_9_io_y_pal),
.io_y_paa (_entries_barrier_9_io_y_paa),
.io_y_eff (_entries_barrier_9_io_y_eff),
.io_y_c (_entries_barrier_9_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_39 entries_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_20_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_20_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_20_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_20_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_20_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_20_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_20_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_20_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_20_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_20_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_20_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_20_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_20_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_20_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_20_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_20_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_20_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_20_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_20_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_20_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_20_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_20_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_20_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_10_io_y_u),
.io_y_ae_ptw (_entries_barrier_10_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_10_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_10_io_y_ae_stage2),
.io_y_pf (_entries_barrier_10_io_y_pf),
.io_y_gf (_entries_barrier_10_io_y_gf),
.io_y_sw (_entries_barrier_10_io_y_sw),
.io_y_sx (_entries_barrier_10_io_y_sx),
.io_y_sr (_entries_barrier_10_io_y_sr),
.io_y_hw (_entries_barrier_10_io_y_hw),
.io_y_hx (_entries_barrier_10_io_y_hx),
.io_y_hr (_entries_barrier_10_io_y_hr),
.io_y_pw (_entries_barrier_10_io_y_pw),
.io_y_px (_entries_barrier_10_io_y_px),
.io_y_pr (_entries_barrier_10_io_y_pr),
.io_y_ppp (_entries_barrier_10_io_y_ppp),
.io_y_pal (_entries_barrier_10_io_y_pal),
.io_y_paa (_entries_barrier_10_io_y_paa),
.io_y_eff (_entries_barrier_10_io_y_eff),
.io_y_c (_entries_barrier_10_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_40 entries_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_22_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_22_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_22_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_22_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_22_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_22_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_22_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_22_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_22_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_22_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_22_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_22_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_22_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_22_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_22_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_22_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_22_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_22_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_22_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_22_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_22_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_22_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_22_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_11_io_y_u),
.io_y_ae_ptw (_entries_barrier_11_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_11_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_11_io_y_ae_stage2),
.io_y_pf (_entries_barrier_11_io_y_pf),
.io_y_gf (_entries_barrier_11_io_y_gf),
.io_y_sw (_entries_barrier_11_io_y_sw),
.io_y_sx (_entries_barrier_11_io_y_sx),
.io_y_sr (_entries_barrier_11_io_y_sr),
.io_y_hw (_entries_barrier_11_io_y_hw),
.io_y_hx (_entries_barrier_11_io_y_hx),
.io_y_hr (_entries_barrier_11_io_y_hr),
.io_y_pw (_entries_barrier_11_io_y_pw),
.io_y_px (_entries_barrier_11_io_y_px),
.io_y_pr (_entries_barrier_11_io_y_pr),
.io_y_ppp (_entries_barrier_11_io_y_ppp),
.io_y_pal (_entries_barrier_11_io_y_pal),
.io_y_paa (_entries_barrier_11_io_y_paa),
.io_y_eff (_entries_barrier_11_io_y_eff),
.io_y_c (_entries_barrier_11_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_41 entries_barrier_12 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_24_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_24_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_24_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_24_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_24_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_24_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_24_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_24_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_24_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_24_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_24_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_24_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_24_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_24_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_24_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_24_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_24_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_24_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_24_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_24_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_24_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_24_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_24_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_12_io_y_u),
.io_y_ae_ptw (_entries_barrier_12_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_12_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_12_io_y_ae_stage2),
.io_y_pf (_entries_barrier_12_io_y_pf),
.io_y_gf (_entries_barrier_12_io_y_gf),
.io_y_sw (_entries_barrier_12_io_y_sw),
.io_y_sx (_entries_barrier_12_io_y_sx),
.io_y_sr (_entries_barrier_12_io_y_sr),
.io_y_hw (_entries_barrier_12_io_y_hw),
.io_y_hx (_entries_barrier_12_io_y_hx),
.io_y_hr (_entries_barrier_12_io_y_hr)
); // @[package.scala:267:25]
assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7]
assign io_resp_gpa = io_resp_gpa_0; // @[TLB.scala:318:7]
assign io_resp_pf_ld = io_resp_pf_ld_0; // @[TLB.scala:318:7]
assign io_resp_pf_inst = io_resp_pf_inst_0; // @[TLB.scala:318:7]
assign io_resp_ae_ld = io_resp_ae_ld_0; // @[TLB.scala:318:7]
assign io_resp_ae_inst = io_resp_ae_inst_0; // @[TLB.scala:318:7]
assign io_resp_ma_ld = io_resp_ma_ld_0; // @[TLB.scala:318:7]
assign io_resp_cacheable = io_resp_cacheable_0; // @[TLB.scala:318:7]
assign io_resp_prefetchable = io_resp_prefetchable_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_valid = io_ptw_req_bits_valid_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_vstage1 = io_ptw_req_bits_bits_vstage1_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_stage2 = io_ptw_req_bits_bits_stage2_0; // @[TLB.scala:318:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_133 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}}
inst input_buffer of InputBuffer_133
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
connect input_buffer.io.deq[8].ready, UInt<1>(0h0)
connect input_buffer.io.deq[9].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter10_RouteComputerReq_27
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[8], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[9], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[8], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[9], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_9 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_9 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_10 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_10 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_11 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_11 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_12 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_12 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_13 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_13 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_14 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_14 :
connect states[7].g, UInt<3>(0h2)
node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1))
connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T
connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id
connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node
connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id
connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node
connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id
connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8)
node _T_15 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid)
when _T_15 :
connect states[8].g, UInt<3>(0h2)
node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1))
connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T
connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id
connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node
connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id
connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node
connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id
connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9)
node _T_16 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid)
when _T_16 :
connect states[9].g, UInt<3>(0h2)
node _T_17 = and(io.router_req.ready, io.router_req.valid)
when _T_17 :
node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_30 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id)
when _T_30 :
connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_31 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id)
when _T_31 :
connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<10>, clock, reset, UInt<10>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}[10]
wire vcalloc_vals : UInt<1>[10]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5])
node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8])
node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5])
node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16)
node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17)
node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18)
node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0))
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34)
node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35)
node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36)
node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37)
node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38)
node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39)
node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40)
node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41)
node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43)
node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_32 = and(io.router_req.ready, io.router_req.valid)
when _T_32 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_33 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_34 = or(_T_33, vcalloc_vals[2])
node _T_35 = or(_T_34, vcalloc_vals[3])
node _T_36 = or(_T_35, vcalloc_vals[4])
node _T_37 = or(_T_36, vcalloc_vals[5])
node _T_38 = or(_T_37, vcalloc_vals[6])
node _T_39 = or(_T_38, vcalloc_vals[7])
node _T_40 = or(_T_39, vcalloc_vals[8])
node _T_41 = or(_T_40, vcalloc_vals[9])
when _T_41 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = not(UInt<9>(0h0))
node _mask_T_12 = not(UInt<10>(0h0))
node _mask_T_13 = bits(vcalloc_sel, 0, 0)
node _mask_T_14 = bits(vcalloc_sel, 1, 1)
node _mask_T_15 = bits(vcalloc_sel, 2, 2)
node _mask_T_16 = bits(vcalloc_sel, 3, 3)
node _mask_T_17 = bits(vcalloc_sel, 4, 4)
node _mask_T_18 = bits(vcalloc_sel, 5, 5)
node _mask_T_19 = bits(vcalloc_sel, 6, 6)
node _mask_T_20 = bits(vcalloc_sel, 7, 7)
node _mask_T_21 = bits(vcalloc_sel, 8, 8)
node _mask_T_22 = bits(vcalloc_sel, 9, 9)
node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0))
node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0))
node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0))
node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0))
node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0))
node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0))
node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0))
node _mask_T_33 = or(_mask_T_23, _mask_T_24)
node _mask_T_34 = or(_mask_T_33, _mask_T_25)
node _mask_T_35 = or(_mask_T_34, _mask_T_26)
node _mask_T_36 = or(_mask_T_35, _mask_T_27)
node _mask_T_37 = or(_mask_T_36, _mask_T_28)
node _mask_T_38 = or(_mask_T_37, _mask_T_29)
node _mask_T_39 = or(_mask_T_38, _mask_T_30)
node _mask_T_40 = or(_mask_T_39, _mask_T_31)
node _mask_T_41 = or(_mask_T_40, _mask_T_32)
wire _mask_WIRE : UInt<10>
connect _mask_WIRE, _mask_T_41
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8])
node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8)
node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10]
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15)
node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16)
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18)
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30)
node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31)
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33)
node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35)
node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36)
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50)
node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51)
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75)
node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90)
node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91)
node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92)
node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93)
node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94)
node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106)
node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107)
node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108)
node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109)
node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110)
node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111)
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125)
node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126)
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150)
node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151)
node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165)
node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166)
node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167)
node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168)
node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169)
node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170)
node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180
connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182)
node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183)
node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184)
node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185)
node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186)
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199
connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[10]
node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201)
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218
connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225)
node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226)
node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227)
node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_237
connect _io_vcalloc_req_bits_WIRE_13[1], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240)
node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241)
node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242)
node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243)
node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244)
node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245)
node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246)
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_256
connect _io_vcalloc_req_bits_WIRE_13[2], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258)
node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259)
node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260)
node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261)
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_275
connect _io_vcalloc_req_bits_WIRE_13[3], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_294
connect _io_vcalloc_req_bits_WIRE_13[4], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300)
node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301)
node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302)
node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303)
node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_313
connect _io_vcalloc_req_bits_WIRE_13[5], _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315)
node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316)
node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317)
node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318)
node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319)
node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320)
node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321)
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_332
connect _io_vcalloc_req_bits_WIRE_13[6], _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334)
node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335)
node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336)
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_351
connect _io_vcalloc_req_bits_WIRE_13[7], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360)
node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_370
connect _io_vcalloc_req_bits_WIRE_13[8], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375)
node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376)
node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377)
node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378)
node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379)
node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_389
connect _io_vcalloc_req_bits_WIRE_13[9], _io_vcalloc_req_bits_WIRE_23
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>[10]
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391)
node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392)
node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393)
node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394)
node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395)
node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396)
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_408
connect _io_vcalloc_req_bits_WIRE_24[0], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_409 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_410 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_411 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_412 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_410)
node _io_vcalloc_req_bits_T_420 = or(_io_vcalloc_req_bits_T_419, _io_vcalloc_req_bits_T_411)
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_420, _io_vcalloc_req_bits_T_412)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_413)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_418)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_24[1], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_437 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_443 = or(_io_vcalloc_req_bits_T_442, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_444 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_435)
node _io_vcalloc_req_bits_T_445 = or(_io_vcalloc_req_bits_T_444, _io_vcalloc_req_bits_T_436)
node _io_vcalloc_req_bits_T_446 = or(_io_vcalloc_req_bits_T_445, _io_vcalloc_req_bits_T_437)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_446
connect _io_vcalloc_req_bits_WIRE_24[2], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_452 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_453 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_454 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_455 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_456 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_447, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_458 = or(_io_vcalloc_req_bits_T_457, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_459 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_450)
node _io_vcalloc_req_bits_T_460 = or(_io_vcalloc_req_bits_T_459, _io_vcalloc_req_bits_T_451)
node _io_vcalloc_req_bits_T_461 = or(_io_vcalloc_req_bits_T_460, _io_vcalloc_req_bits_T_452)
node _io_vcalloc_req_bits_T_462 = or(_io_vcalloc_req_bits_T_461, _io_vcalloc_req_bits_T_453)
node _io_vcalloc_req_bits_T_463 = or(_io_vcalloc_req_bits_T_462, _io_vcalloc_req_bits_T_454)
node _io_vcalloc_req_bits_T_464 = or(_io_vcalloc_req_bits_T_463, _io_vcalloc_req_bits_T_455)
node _io_vcalloc_req_bits_T_465 = or(_io_vcalloc_req_bits_T_464, _io_vcalloc_req_bits_T_456)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_465
connect _io_vcalloc_req_bits_WIRE_24[3], _io_vcalloc_req_bits_WIRE_28
node _io_vcalloc_req_bits_T_466 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_467 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_468 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_469 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_470 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_471 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_472 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_467)
node _io_vcalloc_req_bits_T_477 = or(_io_vcalloc_req_bits_T_476, _io_vcalloc_req_bits_T_468)
node _io_vcalloc_req_bits_T_478 = or(_io_vcalloc_req_bits_T_477, _io_vcalloc_req_bits_T_469)
node _io_vcalloc_req_bits_T_479 = or(_io_vcalloc_req_bits_T_478, _io_vcalloc_req_bits_T_470)
node _io_vcalloc_req_bits_T_480 = or(_io_vcalloc_req_bits_T_479, _io_vcalloc_req_bits_T_471)
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_480, _io_vcalloc_req_bits_T_472)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_473)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_475)
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_484
connect _io_vcalloc_req_bits_WIRE_24[4], _io_vcalloc_req_bits_WIRE_29
node _io_vcalloc_req_bits_T_485 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_486 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_487 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_486)
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_495, _io_vcalloc_req_bits_T_487)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_488)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_503 = or(_io_vcalloc_req_bits_T_502, _io_vcalloc_req_bits_T_494)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_503
connect _io_vcalloc_req_bits_WIRE_24[5], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_512 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_513 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_504, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_518 = or(_io_vcalloc_req_bits_T_517, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_519 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_510)
node _io_vcalloc_req_bits_T_520 = or(_io_vcalloc_req_bits_T_519, _io_vcalloc_req_bits_T_511)
node _io_vcalloc_req_bits_T_521 = or(_io_vcalloc_req_bits_T_520, _io_vcalloc_req_bits_T_512)
node _io_vcalloc_req_bits_T_522 = or(_io_vcalloc_req_bits_T_521, _io_vcalloc_req_bits_T_513)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_522
connect _io_vcalloc_req_bits_WIRE_24[6], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_527 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_528 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_529 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_530 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_531 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_532 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_533 = or(_io_vcalloc_req_bits_T_523, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_534 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_525)
node _io_vcalloc_req_bits_T_535 = or(_io_vcalloc_req_bits_T_534, _io_vcalloc_req_bits_T_526)
node _io_vcalloc_req_bits_T_536 = or(_io_vcalloc_req_bits_T_535, _io_vcalloc_req_bits_T_527)
node _io_vcalloc_req_bits_T_537 = or(_io_vcalloc_req_bits_T_536, _io_vcalloc_req_bits_T_528)
node _io_vcalloc_req_bits_T_538 = or(_io_vcalloc_req_bits_T_537, _io_vcalloc_req_bits_T_529)
node _io_vcalloc_req_bits_T_539 = or(_io_vcalloc_req_bits_T_538, _io_vcalloc_req_bits_T_530)
node _io_vcalloc_req_bits_T_540 = or(_io_vcalloc_req_bits_T_539, _io_vcalloc_req_bits_T_531)
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_540, _io_vcalloc_req_bits_T_532)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_541
connect _io_vcalloc_req_bits_WIRE_24[7], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_542 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_543 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_544 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_545 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_546 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_547 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_543)
node _io_vcalloc_req_bits_T_553 = or(_io_vcalloc_req_bits_T_552, _io_vcalloc_req_bits_T_544)
node _io_vcalloc_req_bits_T_554 = or(_io_vcalloc_req_bits_T_553, _io_vcalloc_req_bits_T_545)
node _io_vcalloc_req_bits_T_555 = or(_io_vcalloc_req_bits_T_554, _io_vcalloc_req_bits_T_546)
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_555, _io_vcalloc_req_bits_T_547)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_548)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_551)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_560
connect _io_vcalloc_req_bits_WIRE_24[8], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_561 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_562 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_562)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_563)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_578 = or(_io_vcalloc_req_bits_T_577, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_579 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_579
connect _io_vcalloc_req_bits_WIRE_24[9], _io_vcalloc_req_bits_WIRE_34
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_24
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_586 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_587 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_588 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_589 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_580, _io_vcalloc_req_bits_T_581)
node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_582)
node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_583)
node _io_vcalloc_req_bits_T_593 = or(_io_vcalloc_req_bits_T_592, _io_vcalloc_req_bits_T_584)
node _io_vcalloc_req_bits_T_594 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_585)
node _io_vcalloc_req_bits_T_595 = or(_io_vcalloc_req_bits_T_594, _io_vcalloc_req_bits_T_586)
node _io_vcalloc_req_bits_T_596 = or(_io_vcalloc_req_bits_T_595, _io_vcalloc_req_bits_T_587)
node _io_vcalloc_req_bits_T_597 = or(_io_vcalloc_req_bits_T_596, _io_vcalloc_req_bits_T_588)
node _io_vcalloc_req_bits_T_598 = or(_io_vcalloc_req_bits_T_597, _io_vcalloc_req_bits_T_589)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_598
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_35
wire _io_vcalloc_req_bits_WIRE_36 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}
node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_601 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_602 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_603 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_604 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_605 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_606 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_607 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_609 = or(_io_vcalloc_req_bits_T_599, _io_vcalloc_req_bits_T_600)
node _io_vcalloc_req_bits_T_610 = or(_io_vcalloc_req_bits_T_609, _io_vcalloc_req_bits_T_601)
node _io_vcalloc_req_bits_T_611 = or(_io_vcalloc_req_bits_T_610, _io_vcalloc_req_bits_T_602)
node _io_vcalloc_req_bits_T_612 = or(_io_vcalloc_req_bits_T_611, _io_vcalloc_req_bits_T_603)
node _io_vcalloc_req_bits_T_613 = or(_io_vcalloc_req_bits_T_612, _io_vcalloc_req_bits_T_604)
node _io_vcalloc_req_bits_T_614 = or(_io_vcalloc_req_bits_T_613, _io_vcalloc_req_bits_T_605)
node _io_vcalloc_req_bits_T_615 = or(_io_vcalloc_req_bits_T_614, _io_vcalloc_req_bits_T_606)
node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_615, _io_vcalloc_req_bits_T_607)
node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_608)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_617
connect _io_vcalloc_req_bits_WIRE_36.egress_node_id, _io_vcalloc_req_bits_WIRE_37
node _io_vcalloc_req_bits_T_618 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_619 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_620 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_621 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_622 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_628 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_619)
node _io_vcalloc_req_bits_T_629 = or(_io_vcalloc_req_bits_T_628, _io_vcalloc_req_bits_T_620)
node _io_vcalloc_req_bits_T_630 = or(_io_vcalloc_req_bits_T_629, _io_vcalloc_req_bits_T_621)
node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_630, _io_vcalloc_req_bits_T_622)
node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_623)
node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_624)
node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_625)
node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_626)
node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_627)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_636
connect _io_vcalloc_req_bits_WIRE_36.egress_node, _io_vcalloc_req_bits_WIRE_38
node _io_vcalloc_req_bits_T_637 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_646 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_637, _io_vcalloc_req_bits_T_638)
node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_639)
node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_640)
node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_641)
node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_642)
node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_643)
node _io_vcalloc_req_bits_T_653 = or(_io_vcalloc_req_bits_T_652, _io_vcalloc_req_bits_T_644)
node _io_vcalloc_req_bits_T_654 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_645)
node _io_vcalloc_req_bits_T_655 = or(_io_vcalloc_req_bits_T_654, _io_vcalloc_req_bits_T_646)
wire _io_vcalloc_req_bits_WIRE_39 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_655
connect _io_vcalloc_req_bits_WIRE_36.ingress_node_id, _io_vcalloc_req_bits_WIRE_39
node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_661 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_662 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_663 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_664 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_665 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_656, _io_vcalloc_req_bits_T_657)
node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_658)
node _io_vcalloc_req_bits_T_668 = or(_io_vcalloc_req_bits_T_667, _io_vcalloc_req_bits_T_659)
node _io_vcalloc_req_bits_T_669 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_660)
node _io_vcalloc_req_bits_T_670 = or(_io_vcalloc_req_bits_T_669, _io_vcalloc_req_bits_T_661)
node _io_vcalloc_req_bits_T_671 = or(_io_vcalloc_req_bits_T_670, _io_vcalloc_req_bits_T_662)
node _io_vcalloc_req_bits_T_672 = or(_io_vcalloc_req_bits_T_671, _io_vcalloc_req_bits_T_663)
node _io_vcalloc_req_bits_T_673 = or(_io_vcalloc_req_bits_T_672, _io_vcalloc_req_bits_T_664)
node _io_vcalloc_req_bits_T_674 = or(_io_vcalloc_req_bits_T_673, _io_vcalloc_req_bits_T_665)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_674
connect _io_vcalloc_req_bits_WIRE_36.ingress_node, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_676 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_677 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_678 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_679 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_680 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_681 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_682 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_685 = or(_io_vcalloc_req_bits_T_675, _io_vcalloc_req_bits_T_676)
node _io_vcalloc_req_bits_T_686 = or(_io_vcalloc_req_bits_T_685, _io_vcalloc_req_bits_T_677)
node _io_vcalloc_req_bits_T_687 = or(_io_vcalloc_req_bits_T_686, _io_vcalloc_req_bits_T_678)
node _io_vcalloc_req_bits_T_688 = or(_io_vcalloc_req_bits_T_687, _io_vcalloc_req_bits_T_679)
node _io_vcalloc_req_bits_T_689 = or(_io_vcalloc_req_bits_T_688, _io_vcalloc_req_bits_T_680)
node _io_vcalloc_req_bits_T_690 = or(_io_vcalloc_req_bits_T_689, _io_vcalloc_req_bits_T_681)
node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_690, _io_vcalloc_req_bits_T_682)
node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_683)
node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_684)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_693
connect _io_vcalloc_req_bits_WIRE_36.vnet_id, _io_vcalloc_req_bits_WIRE_41
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_36
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`0`[8]
invalidate vcalloc_reqs[0].vc_sel.`0`[9]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[5]
invalidate vcalloc_reqs[0].vc_sel.`1`[6]
invalidate vcalloc_reqs[0].vc_sel.`1`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[8]
invalidate vcalloc_reqs[0].vc_sel.`1`[9]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[3]
invalidate vcalloc_reqs[0].vc_sel.`2`[4]
invalidate vcalloc_reqs[0].vc_sel.`2`[5]
invalidate vcalloc_reqs[0].vc_sel.`2`[6]
invalidate vcalloc_reqs[0].vc_sel.`2`[7]
invalidate vcalloc_reqs[0].vc_sel.`2`[8]
invalidate vcalloc_reqs[0].vc_sel.`2`[9]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`0`[3]
invalidate vcalloc_reqs[1].vc_sel.`0`[4]
invalidate vcalloc_reqs[1].vc_sel.`0`[5]
invalidate vcalloc_reqs[1].vc_sel.`0`[6]
invalidate vcalloc_reqs[1].vc_sel.`0`[7]
invalidate vcalloc_reqs[1].vc_sel.`0`[8]
invalidate vcalloc_reqs[1].vc_sel.`0`[9]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[3]
invalidate vcalloc_reqs[1].vc_sel.`1`[4]
invalidate vcalloc_reqs[1].vc_sel.`1`[5]
invalidate vcalloc_reqs[1].vc_sel.`1`[6]
invalidate vcalloc_reqs[1].vc_sel.`1`[7]
invalidate vcalloc_reqs[1].vc_sel.`1`[8]
invalidate vcalloc_reqs[1].vc_sel.`1`[9]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[2]
invalidate vcalloc_reqs[1].vc_sel.`2`[3]
invalidate vcalloc_reqs[1].vc_sel.`2`[4]
invalidate vcalloc_reqs[1].vc_sel.`2`[5]
invalidate vcalloc_reqs[1].vc_sel.`2`[6]
invalidate vcalloc_reqs[1].vc_sel.`2`[7]
invalidate vcalloc_reqs[1].vc_sel.`2`[8]
invalidate vcalloc_reqs[1].vc_sel.`2`[9]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_42 = bits(vcalloc_sel, 2, 2)
node _T_43 = and(vcalloc_vals[2], _T_42)
node _T_44 = and(_T_43, io.vcalloc_req.ready)
when _T_44 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_45 = bits(vcalloc_sel, 3, 3)
node _T_46 = and(vcalloc_vals[3], _T_45)
node _T_47 = and(_T_46, io.vcalloc_req.ready)
when _T_47 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_48 = bits(vcalloc_sel, 4, 4)
node _T_49 = and(vcalloc_vals[4], _T_48)
node _T_50 = and(_T_49, io.vcalloc_req.ready)
when _T_50 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_51 = bits(vcalloc_sel, 5, 5)
node _T_52 = and(vcalloc_vals[5], _T_51)
node _T_53 = and(_T_52, io.vcalloc_req.ready)
when _T_53 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_54 = bits(vcalloc_sel, 6, 6)
node _T_55 = and(vcalloc_vals[6], _T_54)
node _T_56 = and(_T_55, io.vcalloc_req.ready)
when _T_56 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_57 = bits(vcalloc_sel, 7, 7)
node _T_58 = and(vcalloc_vals[7], _T_57)
node _T_59 = and(_T_58, io.vcalloc_req.ready)
when _T_59 :
connect states[7].g, UInt<3>(0h3)
node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2))
node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1)
connect vcalloc_vals[8], _vcalloc_vals_8_T_2
connect vcalloc_reqs[8].in_vc, UInt<4>(0h8)
connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0`
connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1`
connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2`
connect vcalloc_reqs[8].flow, states[8].flow
node _T_60 = bits(vcalloc_sel, 8, 8)
node _T_61 = and(vcalloc_vals[8], _T_60)
node _T_62 = and(_T_61, io.vcalloc_req.ready)
when _T_62 :
connect states[8].g, UInt<3>(0h3)
node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2))
node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1)
connect vcalloc_vals[9], _vcalloc_vals_9_T_2
connect vcalloc_reqs[9].in_vc, UInt<4>(0h9)
connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0`
connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1`
connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2`
connect vcalloc_reqs[9].flow, states[9].flow
node _T_63 = bits(vcalloc_sel, 9, 9)
node _T_64 = and(vcalloc_vals[9], _T_63)
node _T_65 = and(_T_64, io.vcalloc_req.ready)
when _T_65 :
connect states[9].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0)
node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5)
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9])
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0)
node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0)
node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13)
node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0)
node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15)
node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0)
node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready)
node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_19
node _T_66 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_66 :
node _T_67 = bits(vcalloc_sel, 0, 0)
when _T_67 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_68 = eq(states[0].g, UInt<3>(0h2))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_68, UInt<1>(0h1), "") : assert_3
node _T_72 = bits(vcalloc_sel, 1, 1)
when _T_72 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_73 = eq(states[1].g, UInt<3>(0h2))
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_73, UInt<1>(0h1), "") : assert_4
node _T_77 = bits(vcalloc_sel, 2, 2)
when _T_77 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
node _T_78 = eq(states[2].g, UInt<3>(0h2))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_78, UInt<1>(0h1), "") : assert_5
node _T_82 = bits(vcalloc_sel, 3, 3)
when _T_82 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].g, UInt<3>(0h3)
node _T_83 = eq(states[3].g, UInt<3>(0h2))
node _T_84 = asUInt(reset)
node _T_85 = eq(_T_84, UInt<1>(0h0))
when _T_85 :
node _T_86 = eq(_T_83, UInt<1>(0h0))
when _T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_83, UInt<1>(0h1), "") : assert_6
node _T_87 = bits(vcalloc_sel, 4, 4)
when _T_87 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].g, UInt<3>(0h3)
node _T_88 = eq(states[4].g, UInt<3>(0h2))
node _T_89 = asUInt(reset)
node _T_90 = eq(_T_89, UInt<1>(0h0))
when _T_90 :
node _T_91 = eq(_T_88, UInt<1>(0h0))
when _T_91 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_88, UInt<1>(0h1), "") : assert_7
node _T_92 = bits(vcalloc_sel, 5, 5)
when _T_92 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].g, UInt<3>(0h3)
node _T_93 = eq(states[5].g, UInt<3>(0h2))
node _T_94 = asUInt(reset)
node _T_95 = eq(_T_94, UInt<1>(0h0))
when _T_95 :
node _T_96 = eq(_T_93, UInt<1>(0h0))
when _T_96 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_93, UInt<1>(0h1), "") : assert_8
node _T_97 = bits(vcalloc_sel, 6, 6)
when _T_97 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].g, UInt<3>(0h3)
node _T_98 = eq(states[6].g, UInt<3>(0h2))
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_98, UInt<1>(0h1), "") : assert_9
node _T_102 = bits(vcalloc_sel, 7, 7)
when _T_102 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].g, UInt<3>(0h3)
node _T_103 = eq(states[7].g, UInt<3>(0h2))
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_103, UInt<1>(0h1), "") : assert_10
node _T_107 = bits(vcalloc_sel, 8, 8)
when _T_107 :
connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[8].g, UInt<3>(0h3)
node _T_108 = eq(states[8].g, UInt<3>(0h2))
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11
assert(clock, _T_108, UInt<1>(0h1), "") : assert_11
node _T_112 = bits(vcalloc_sel, 9, 9)
when _T_112 :
connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[9].g, UInt<3>(0h3)
node _T_113 = eq(states[9].g, UInt<3>(0h2))
node _T_114 = asUInt(reset)
node _T_115 = eq(_T_114, UInt<1>(0h0))
when _T_115 :
node _T_116 = eq(_T_113, UInt<1>(0h0))
when _T_116 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12
assert(clock, _T_113, UInt<1>(0h1), "") : assert_12
inst salloc_arb of SwitchArbiter_348
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[8]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[9]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[8]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[9]
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[8]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[9]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[8]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[9]
node credit_available_lo_lo = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_hi = cat(states[2].vc_sel.`0`[4], states[2].vc_sel.`0`[3])
node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[2].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[2].vc_sel.`0`[6], states[2].vc_sel.`0`[5])
node credit_available_hi_hi_hi = cat(states[2].vc_sel.`0`[9], states[2].vc_sel.`0`[8])
node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[2].vc_sel.`0`[7])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_hi_1 = cat(states[2].vc_sel.`1`[4], states[2].vc_sel.`1`[3])
node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, states[2].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[2].vc_sel.`1`[6], states[2].vc_sel.`1`[5])
node credit_available_hi_hi_hi_1 = cat(states[2].vc_sel.`1`[9], states[2].vc_sel.`1`[8])
node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, states[2].vc_sel.`1`[7])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_hi_2 = cat(states[2].vc_sel.`2`[4], states[2].vc_sel.`2`[3])
node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[2].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[2].vc_sel.`2`[6], states[2].vc_sel.`2`[5])
node credit_available_hi_hi_hi_2 = cat(states[2].vc_sel.`2`[9], states[2].vc_sel.`2`[8])
node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[2].vc_sel.`2`[7])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1)
node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T)
node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7])
node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, io.out_credit_available.`1`[2])
node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_4 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, io.out_credit_available.`1`[7])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`2`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`2`[7])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5)
node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5)
node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[8], states[2].vc_sel.`0`[8]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[9], states[2].vc_sel.`0`[9]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[8], states[2].vc_sel.`1`[8]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[9], states[2].vc_sel.`1`[9]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[8], states[2].vc_sel.`2`[8]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[9], states[2].vc_sel.`2`[9]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_117 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_118 = and(_T_117, input_buffer.io.deq[2].bits.tail)
when _T_118 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_6 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_hi_6 = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3])
node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_6, states[3].vc_sel.`0`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5])
node credit_available_hi_hi_hi_6 = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8])
node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_6, states[3].vc_sel.`0`[7])
node credit_available_hi_8 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_6)
node credit_available_lo_lo_7 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_hi_7 = cat(states[3].vc_sel.`1`[4], states[3].vc_sel.`1`[3])
node credit_available_lo_hi_7 = cat(credit_available_lo_hi_hi_7, states[3].vc_sel.`1`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(states[3].vc_sel.`1`[6], states[3].vc_sel.`1`[5])
node credit_available_hi_hi_hi_7 = cat(states[3].vc_sel.`1`[9], states[3].vc_sel.`1`[8])
node credit_available_hi_hi_7 = cat(credit_available_hi_hi_hi_7, states[3].vc_sel.`1`[7])
node credit_available_hi_9 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_10 = cat(credit_available_hi_9, credit_available_lo_7)
node credit_available_lo_lo_8 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_hi_8 = cat(states[3].vc_sel.`2`[4], states[3].vc_sel.`2`[3])
node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_8, states[3].vc_sel.`2`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[3].vc_sel.`2`[6], states[3].vc_sel.`2`[5])
node credit_available_hi_hi_hi_8 = cat(states[3].vc_sel.`2`[9], states[3].vc_sel.`2`[8])
node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_8, states[3].vc_sel.`2`[7])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_8)
node credit_available_hi_11 = cat(_credit_available_T_11, _credit_available_T_10)
node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_9)
node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_9 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2])
node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_9 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7])
node credit_available_hi_12 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_9)
node credit_available_lo_lo_10 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_10 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_10, io.out_credit_available.`1`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_10 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_10, io.out_credit_available.`1`[7])
node credit_available_hi_13 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_10)
node credit_available_lo_lo_11 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_11 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`2`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_11 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`2`[7])
node credit_available_hi_14 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_11)
node credit_available_hi_15 = cat(_credit_available_T_15, _credit_available_T_14)
node _credit_available_T_16 = cat(credit_available_hi_15, _credit_available_T_13)
node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16)
node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_1)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[8], states[3].vc_sel.`1`[8]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[9], states[3].vc_sel.`1`[9]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[8], states[3].vc_sel.`2`[8]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[9], states[3].vc_sel.`2`[9]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_119 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_120 = and(_T_119, input_buffer.io.deq[3].bits.tail)
when _T_120 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_12 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_hi_12 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3])
node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_12, states[4].vc_sel.`0`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5])
node credit_available_hi_hi_hi_12 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8])
node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_12, states[4].vc_sel.`0`[7])
node credit_available_hi_16 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_18 = cat(credit_available_hi_16, credit_available_lo_12)
node credit_available_lo_lo_13 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_hi_13 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3])
node credit_available_lo_hi_13 = cat(credit_available_lo_hi_hi_13, states[4].vc_sel.`1`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(states[4].vc_sel.`1`[6], states[4].vc_sel.`1`[5])
node credit_available_hi_hi_hi_13 = cat(states[4].vc_sel.`1`[9], states[4].vc_sel.`1`[8])
node credit_available_hi_hi_13 = cat(credit_available_hi_hi_hi_13, states[4].vc_sel.`1`[7])
node credit_available_hi_17 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_19 = cat(credit_available_hi_17, credit_available_lo_13)
node credit_available_lo_lo_14 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_hi_14 = cat(states[4].vc_sel.`2`[4], states[4].vc_sel.`2`[3])
node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_14, states[4].vc_sel.`2`[2])
node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(states[4].vc_sel.`2`[6], states[4].vc_sel.`2`[5])
node credit_available_hi_hi_hi_14 = cat(states[4].vc_sel.`2`[9], states[4].vc_sel.`2`[8])
node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_14, states[4].vc_sel.`2`[7])
node credit_available_hi_18 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_20 = cat(credit_available_hi_18, credit_available_lo_14)
node credit_available_hi_19 = cat(_credit_available_T_20, _credit_available_T_19)
node _credit_available_T_21 = cat(credit_available_hi_19, _credit_available_T_18)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_15 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_15 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7])
node credit_available_hi_20 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_15)
node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_16 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_16 = cat(credit_available_lo_hi_hi_16, io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_16 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_16 = cat(credit_available_hi_hi_hi_16, io.out_credit_available.`1`[7])
node credit_available_hi_21 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_16)
node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_17 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_17 = cat(credit_available_lo_hi_hi_17, io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_17 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_17 = cat(credit_available_hi_hi_hi_17, io.out_credit_available.`2`[7])
node credit_available_hi_22 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_17)
node credit_available_hi_23 = cat(_credit_available_T_24, _credit_available_T_23)
node _credit_available_T_25 = cat(credit_available_hi_23, _credit_available_T_22)
node _credit_available_T_26 = and(_credit_available_T_21, _credit_available_T_25)
node credit_available_2 = neq(_credit_available_T_26, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_2)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[8], states[4].vc_sel.`1`[8]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[9], states[4].vc_sel.`1`[9]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[8], states[4].vc_sel.`2`[8]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[9], states[4].vc_sel.`2`[9]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_121 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_122 = and(_T_121, input_buffer.io.deq[4].bits.tail)
when _T_122 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_18 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_hi_18 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3])
node credit_available_lo_hi_18 = cat(credit_available_lo_hi_hi_18, states[5].vc_sel.`0`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5])
node credit_available_hi_hi_hi_18 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8])
node credit_available_hi_hi_18 = cat(credit_available_hi_hi_hi_18, states[5].vc_sel.`0`[7])
node credit_available_hi_24 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_27 = cat(credit_available_hi_24, credit_available_lo_18)
node credit_available_lo_lo_19 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_hi_19 = cat(states[5].vc_sel.`1`[4], states[5].vc_sel.`1`[3])
node credit_available_lo_hi_19 = cat(credit_available_lo_hi_hi_19, states[5].vc_sel.`1`[2])
node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[5].vc_sel.`1`[6], states[5].vc_sel.`1`[5])
node credit_available_hi_hi_hi_19 = cat(states[5].vc_sel.`1`[9], states[5].vc_sel.`1`[8])
node credit_available_hi_hi_19 = cat(credit_available_hi_hi_hi_19, states[5].vc_sel.`1`[7])
node credit_available_hi_25 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_28 = cat(credit_available_hi_25, credit_available_lo_19)
node credit_available_lo_lo_20 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_hi_20 = cat(states[5].vc_sel.`2`[4], states[5].vc_sel.`2`[3])
node credit_available_lo_hi_20 = cat(credit_available_lo_hi_hi_20, states[5].vc_sel.`2`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(states[5].vc_sel.`2`[6], states[5].vc_sel.`2`[5])
node credit_available_hi_hi_hi_20 = cat(states[5].vc_sel.`2`[9], states[5].vc_sel.`2`[8])
node credit_available_hi_hi_20 = cat(credit_available_hi_hi_hi_20, states[5].vc_sel.`2`[7])
node credit_available_hi_26 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_29 = cat(credit_available_hi_26, credit_available_lo_20)
node credit_available_hi_27 = cat(_credit_available_T_29, _credit_available_T_28)
node _credit_available_T_30 = cat(credit_available_hi_27, _credit_available_T_27)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_21 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_21 = cat(credit_available_lo_hi_hi_21, io.out_credit_available.`0`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_21 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_21 = cat(credit_available_hi_hi_hi_21, io.out_credit_available.`0`[7])
node credit_available_hi_28 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_31 = cat(credit_available_hi_28, credit_available_lo_21)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_22 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_22 = cat(credit_available_lo_hi_hi_22, io.out_credit_available.`1`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_22 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_22 = cat(credit_available_hi_hi_hi_22, io.out_credit_available.`1`[7])
node credit_available_hi_29 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_32 = cat(credit_available_hi_29, credit_available_lo_22)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_23 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_23 = cat(credit_available_lo_hi_hi_23, io.out_credit_available.`2`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_23 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_23 = cat(credit_available_hi_hi_hi_23, io.out_credit_available.`2`[7])
node credit_available_hi_30 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_23)
node credit_available_hi_31 = cat(_credit_available_T_33, _credit_available_T_32)
node _credit_available_T_34 = cat(credit_available_hi_31, _credit_available_T_31)
node _credit_available_T_35 = and(_credit_available_T_30, _credit_available_T_34)
node credit_available_3 = neq(_credit_available_T_35, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_3)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[8], states[5].vc_sel.`1`[8]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[9], states[5].vc_sel.`1`[9]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[8], states[5].vc_sel.`2`[8]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[9], states[5].vc_sel.`2`[9]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_123 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_124 = and(_T_123, input_buffer.io.deq[5].bits.tail)
when _T_124 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_24 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_hi_24 = cat(states[6].vc_sel.`0`[4], states[6].vc_sel.`0`[3])
node credit_available_lo_hi_24 = cat(credit_available_lo_hi_hi_24, states[6].vc_sel.`0`[2])
node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[6].vc_sel.`0`[6], states[6].vc_sel.`0`[5])
node credit_available_hi_hi_hi_24 = cat(states[6].vc_sel.`0`[9], states[6].vc_sel.`0`[8])
node credit_available_hi_hi_24 = cat(credit_available_hi_hi_hi_24, states[6].vc_sel.`0`[7])
node credit_available_hi_32 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_36 = cat(credit_available_hi_32, credit_available_lo_24)
node credit_available_lo_lo_25 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_hi_25 = cat(states[6].vc_sel.`1`[4], states[6].vc_sel.`1`[3])
node credit_available_lo_hi_25 = cat(credit_available_lo_hi_hi_25, states[6].vc_sel.`1`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[6].vc_sel.`1`[6], states[6].vc_sel.`1`[5])
node credit_available_hi_hi_hi_25 = cat(states[6].vc_sel.`1`[9], states[6].vc_sel.`1`[8])
node credit_available_hi_hi_25 = cat(credit_available_hi_hi_hi_25, states[6].vc_sel.`1`[7])
node credit_available_hi_33 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_37 = cat(credit_available_hi_33, credit_available_lo_25)
node credit_available_lo_lo_26 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_hi_26 = cat(states[6].vc_sel.`2`[4], states[6].vc_sel.`2`[3])
node credit_available_lo_hi_26 = cat(credit_available_lo_hi_hi_26, states[6].vc_sel.`2`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[6].vc_sel.`2`[6], states[6].vc_sel.`2`[5])
node credit_available_hi_hi_hi_26 = cat(states[6].vc_sel.`2`[9], states[6].vc_sel.`2`[8])
node credit_available_hi_hi_26 = cat(credit_available_hi_hi_hi_26, states[6].vc_sel.`2`[7])
node credit_available_hi_34 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_38 = cat(credit_available_hi_34, credit_available_lo_26)
node credit_available_hi_35 = cat(_credit_available_T_38, _credit_available_T_37)
node _credit_available_T_39 = cat(credit_available_hi_35, _credit_available_T_36)
node credit_available_lo_lo_27 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_27 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_27 = cat(credit_available_lo_hi_hi_27, io.out_credit_available.`0`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_27 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_27 = cat(credit_available_hi_hi_hi_27, io.out_credit_available.`0`[7])
node credit_available_hi_36 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_40 = cat(credit_available_hi_36, credit_available_lo_27)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_28 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_28 = cat(credit_available_lo_hi_hi_28, io.out_credit_available.`1`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_28 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_28 = cat(credit_available_hi_hi_hi_28, io.out_credit_available.`1`[7])
node credit_available_hi_37 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_41 = cat(credit_available_hi_37, credit_available_lo_28)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_29 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_29 = cat(credit_available_lo_hi_hi_29, io.out_credit_available.`2`[2])
node credit_available_lo_29 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_29 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_29 = cat(credit_available_hi_hi_hi_29, io.out_credit_available.`2`[7])
node credit_available_hi_38 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_42 = cat(credit_available_hi_38, credit_available_lo_29)
node credit_available_hi_39 = cat(_credit_available_T_42, _credit_available_T_41)
node _credit_available_T_43 = cat(credit_available_hi_39, _credit_available_T_40)
node _credit_available_T_44 = and(_credit_available_T_39, _credit_available_T_43)
node credit_available_4 = neq(_credit_available_T_44, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_4)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[8], states[6].vc_sel.`0`[8]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[9], states[6].vc_sel.`0`[9]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[8], states[6].vc_sel.`1`[8]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[9], states[6].vc_sel.`1`[9]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[8], states[6].vc_sel.`2`[8]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[9], states[6].vc_sel.`2`[9]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_125 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_126 = and(_T_125, input_buffer.io.deq[6].bits.tail)
when _T_126 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_30 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_hi_30 = cat(states[7].vc_sel.`0`[4], states[7].vc_sel.`0`[3])
node credit_available_lo_hi_30 = cat(credit_available_lo_hi_hi_30, states[7].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(states[7].vc_sel.`0`[6], states[7].vc_sel.`0`[5])
node credit_available_hi_hi_hi_30 = cat(states[7].vc_sel.`0`[9], states[7].vc_sel.`0`[8])
node credit_available_hi_hi_30 = cat(credit_available_hi_hi_hi_30, states[7].vc_sel.`0`[7])
node credit_available_hi_40 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_45 = cat(credit_available_hi_40, credit_available_lo_30)
node credit_available_lo_lo_31 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_hi_31 = cat(states[7].vc_sel.`1`[4], states[7].vc_sel.`1`[3])
node credit_available_lo_hi_31 = cat(credit_available_lo_hi_hi_31, states[7].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(states[7].vc_sel.`1`[6], states[7].vc_sel.`1`[5])
node credit_available_hi_hi_hi_31 = cat(states[7].vc_sel.`1`[9], states[7].vc_sel.`1`[8])
node credit_available_hi_hi_31 = cat(credit_available_hi_hi_hi_31, states[7].vc_sel.`1`[7])
node credit_available_hi_41 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_46 = cat(credit_available_hi_41, credit_available_lo_31)
node credit_available_lo_lo_32 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_hi_32 = cat(states[7].vc_sel.`2`[4], states[7].vc_sel.`2`[3])
node credit_available_lo_hi_32 = cat(credit_available_lo_hi_hi_32, states[7].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[7].vc_sel.`2`[6], states[7].vc_sel.`2`[5])
node credit_available_hi_hi_hi_32 = cat(states[7].vc_sel.`2`[9], states[7].vc_sel.`2`[8])
node credit_available_hi_hi_32 = cat(credit_available_hi_hi_hi_32, states[7].vc_sel.`2`[7])
node credit_available_hi_42 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_47 = cat(credit_available_hi_42, credit_available_lo_32)
node credit_available_hi_43 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_43, _credit_available_T_45)
node credit_available_lo_lo_33 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_33 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_33 = cat(credit_available_lo_hi_hi_33, io.out_credit_available.`0`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_33 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_33 = cat(credit_available_hi_hi_hi_33, io.out_credit_available.`0`[7])
node credit_available_hi_44 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_49 = cat(credit_available_hi_44, credit_available_lo_33)
node credit_available_lo_lo_34 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_34 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_34 = cat(credit_available_lo_hi_hi_34, io.out_credit_available.`1`[2])
node credit_available_lo_34 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_34 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_34 = cat(credit_available_hi_hi_hi_34, io.out_credit_available.`1`[7])
node credit_available_hi_45 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_50 = cat(credit_available_hi_45, credit_available_lo_34)
node credit_available_lo_lo_35 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_35 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_35 = cat(credit_available_lo_hi_hi_35, io.out_credit_available.`2`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_35 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_35 = cat(credit_available_hi_hi_hi_35, io.out_credit_available.`2`[7])
node credit_available_hi_46 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_51 = cat(credit_available_hi_46, credit_available_lo_35)
node credit_available_hi_47 = cat(_credit_available_T_51, _credit_available_T_50)
node _credit_available_T_52 = cat(credit_available_hi_47, _credit_available_T_49)
node _credit_available_T_53 = and(_credit_available_T_48, _credit_available_T_52)
node credit_available_5 = neq(_credit_available_T_53, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_5)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[8], states[7].vc_sel.`0`[8]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[9], states[7].vc_sel.`0`[9]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[8], states[7].vc_sel.`1`[8]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[9], states[7].vc_sel.`1`[9]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[8], states[7].vc_sel.`2`[8]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[9], states[7].vc_sel.`2`[9]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_127 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_128 = and(_T_127, input_buffer.io.deq[7].bits.tail)
when _T_128 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node credit_available_lo_lo_36 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0])
node credit_available_lo_hi_hi_36 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3])
node credit_available_lo_hi_36 = cat(credit_available_lo_hi_hi_36, states[8].vc_sel.`0`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5])
node credit_available_hi_hi_hi_36 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8])
node credit_available_hi_hi_36 = cat(credit_available_hi_hi_hi_36, states[8].vc_sel.`0`[7])
node credit_available_hi_48 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_54 = cat(credit_available_hi_48, credit_available_lo_36)
node credit_available_lo_lo_37 = cat(states[8].vc_sel.`1`[1], states[8].vc_sel.`1`[0])
node credit_available_lo_hi_hi_37 = cat(states[8].vc_sel.`1`[4], states[8].vc_sel.`1`[3])
node credit_available_lo_hi_37 = cat(credit_available_lo_hi_hi_37, states[8].vc_sel.`1`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(states[8].vc_sel.`1`[6], states[8].vc_sel.`1`[5])
node credit_available_hi_hi_hi_37 = cat(states[8].vc_sel.`1`[9], states[8].vc_sel.`1`[8])
node credit_available_hi_hi_37 = cat(credit_available_hi_hi_hi_37, states[8].vc_sel.`1`[7])
node credit_available_hi_49 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_55 = cat(credit_available_hi_49, credit_available_lo_37)
node credit_available_lo_lo_38 = cat(states[8].vc_sel.`2`[1], states[8].vc_sel.`2`[0])
node credit_available_lo_hi_hi_38 = cat(states[8].vc_sel.`2`[4], states[8].vc_sel.`2`[3])
node credit_available_lo_hi_38 = cat(credit_available_lo_hi_hi_38, states[8].vc_sel.`2`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(states[8].vc_sel.`2`[6], states[8].vc_sel.`2`[5])
node credit_available_hi_hi_hi_38 = cat(states[8].vc_sel.`2`[9], states[8].vc_sel.`2`[8])
node credit_available_hi_hi_38 = cat(credit_available_hi_hi_hi_38, states[8].vc_sel.`2`[7])
node credit_available_hi_50 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_56 = cat(credit_available_hi_50, credit_available_lo_38)
node credit_available_hi_51 = cat(_credit_available_T_56, _credit_available_T_55)
node _credit_available_T_57 = cat(credit_available_hi_51, _credit_available_T_54)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_39 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_39 = cat(credit_available_lo_hi_hi_39, io.out_credit_available.`0`[2])
node credit_available_lo_39 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_39 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_39 = cat(credit_available_hi_hi_hi_39, io.out_credit_available.`0`[7])
node credit_available_hi_52 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_58 = cat(credit_available_hi_52, credit_available_lo_39)
node credit_available_lo_lo_40 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_40 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_40 = cat(credit_available_lo_hi_hi_40, io.out_credit_available.`1`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_40 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_40 = cat(credit_available_hi_hi_hi_40, io.out_credit_available.`1`[7])
node credit_available_hi_53 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_59 = cat(credit_available_hi_53, credit_available_lo_40)
node credit_available_lo_lo_41 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_41 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_41 = cat(credit_available_lo_hi_hi_41, io.out_credit_available.`2`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_41 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_41 = cat(credit_available_hi_hi_hi_41, io.out_credit_available.`2`[7])
node credit_available_hi_54 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_60 = cat(credit_available_hi_54, credit_available_lo_41)
node credit_available_hi_55 = cat(_credit_available_T_60, _credit_available_T_59)
node _credit_available_T_61 = cat(credit_available_hi_55, _credit_available_T_58)
node _credit_available_T_62 = and(_credit_available_T_57, _credit_available_T_61)
node credit_available_6 = neq(_credit_available_T_62, UInt<1>(0h0))
node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3))
node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_6)
node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid)
connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2
connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[1], states[8].vc_sel.`1`[1]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[2], states[8].vc_sel.`1`[2]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[3], states[8].vc_sel.`1`[3]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[4], states[8].vc_sel.`1`[4]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[5], states[8].vc_sel.`1`[5]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[6], states[8].vc_sel.`1`[6]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[7], states[8].vc_sel.`1`[7]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[8], states[8].vc_sel.`1`[8]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[9], states[8].vc_sel.`1`[9]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[1], states[8].vc_sel.`2`[1]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[2], states[8].vc_sel.`2`[2]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[3], states[8].vc_sel.`2`[3]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[4], states[8].vc_sel.`2`[4]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[5], states[8].vc_sel.`2`[5]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[6], states[8].vc_sel.`2`[6]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[7], states[8].vc_sel.`2`[7]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[8], states[8].vc_sel.`2`[8]
connect salloc_arb.io.in[8].bits.vc_sel.`2`[9], states[8].vc_sel.`2`[9]
connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail
node _T_129 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid)
node _T_130 = and(_T_129, input_buffer.io.deq[8].bits.tail)
when _T_130 :
connect states[8].g, UInt<3>(0h0)
connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready
node credit_available_lo_lo_42 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0])
node credit_available_lo_hi_hi_42 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3])
node credit_available_lo_hi_42 = cat(credit_available_lo_hi_hi_42, states[9].vc_sel.`0`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5])
node credit_available_hi_hi_hi_42 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8])
node credit_available_hi_hi_42 = cat(credit_available_hi_hi_hi_42, states[9].vc_sel.`0`[7])
node credit_available_hi_56 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_63 = cat(credit_available_hi_56, credit_available_lo_42)
node credit_available_lo_lo_43 = cat(states[9].vc_sel.`1`[1], states[9].vc_sel.`1`[0])
node credit_available_lo_hi_hi_43 = cat(states[9].vc_sel.`1`[4], states[9].vc_sel.`1`[3])
node credit_available_lo_hi_43 = cat(credit_available_lo_hi_hi_43, states[9].vc_sel.`1`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[9].vc_sel.`1`[6], states[9].vc_sel.`1`[5])
node credit_available_hi_hi_hi_43 = cat(states[9].vc_sel.`1`[9], states[9].vc_sel.`1`[8])
node credit_available_hi_hi_43 = cat(credit_available_hi_hi_hi_43, states[9].vc_sel.`1`[7])
node credit_available_hi_57 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_64 = cat(credit_available_hi_57, credit_available_lo_43)
node credit_available_lo_lo_44 = cat(states[9].vc_sel.`2`[1], states[9].vc_sel.`2`[0])
node credit_available_lo_hi_hi_44 = cat(states[9].vc_sel.`2`[4], states[9].vc_sel.`2`[3])
node credit_available_lo_hi_44 = cat(credit_available_lo_hi_hi_44, states[9].vc_sel.`2`[2])
node credit_available_lo_44 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(states[9].vc_sel.`2`[6], states[9].vc_sel.`2`[5])
node credit_available_hi_hi_hi_44 = cat(states[9].vc_sel.`2`[9], states[9].vc_sel.`2`[8])
node credit_available_hi_hi_44 = cat(credit_available_hi_hi_hi_44, states[9].vc_sel.`2`[7])
node credit_available_hi_58 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_65 = cat(credit_available_hi_58, credit_available_lo_44)
node credit_available_hi_59 = cat(_credit_available_T_65, _credit_available_T_64)
node _credit_available_T_66 = cat(credit_available_hi_59, _credit_available_T_63)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_45 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_45 = cat(credit_available_lo_hi_hi_45, io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_45 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_45 = cat(credit_available_hi_hi_hi_45, io.out_credit_available.`0`[7])
node credit_available_hi_60 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_67 = cat(credit_available_hi_60, credit_available_lo_45)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_46 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_46 = cat(credit_available_lo_hi_hi_46, io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_46 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_46 = cat(credit_available_hi_hi_hi_46, io.out_credit_available.`1`[7])
node credit_available_hi_61 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_68 = cat(credit_available_hi_61, credit_available_lo_46)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_hi_47 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_lo_hi_47 = cat(credit_available_lo_hi_hi_47, io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5])
node credit_available_hi_hi_hi_47 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8])
node credit_available_hi_hi_47 = cat(credit_available_hi_hi_hi_47, io.out_credit_available.`2`[7])
node credit_available_hi_62 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_69 = cat(credit_available_hi_62, credit_available_lo_47)
node credit_available_hi_63 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_63, _credit_available_T_67)
node _credit_available_T_71 = and(_credit_available_T_66, _credit_available_T_70)
node credit_available_7 = neq(_credit_available_T_71, UInt<1>(0h0))
node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3))
node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_7)
node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid)
connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2
connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[1], states[9].vc_sel.`1`[1]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[2], states[9].vc_sel.`1`[2]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[3], states[9].vc_sel.`1`[3]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[4], states[9].vc_sel.`1`[4]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[5], states[9].vc_sel.`1`[5]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[6], states[9].vc_sel.`1`[6]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[7], states[9].vc_sel.`1`[7]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[8], states[9].vc_sel.`1`[8]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[9], states[9].vc_sel.`1`[9]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[1], states[9].vc_sel.`2`[1]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[2], states[9].vc_sel.`2`[2]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[3], states[9].vc_sel.`2`[3]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[4], states[9].vc_sel.`2`[4]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[5], states[9].vc_sel.`2`[5]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[6], states[9].vc_sel.`2`[6]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[7], states[9].vc_sel.`2`[7]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[8], states[9].vc_sel.`2`[8]
connect salloc_arb.io.in[9].bits.vc_sel.`2`[9], states[9].vc_sel.`2`[9]
connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail
node _T_131 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid)
node _T_132 = and(_T_131, input_buffer.io.deq[9].bits.tail)
when _T_132 :
connect states[9].g, UInt<3>(0h0)
connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16)
node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0)
node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0)
node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31)
node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0)
node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33)
node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0)
node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35)
node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_37
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14)
node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15)
node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16)
node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17)
node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18)
node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19)
node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29
node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_31
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2)
node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0)
node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2)
node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2)
node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1)
node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6)
node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7)
node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
wire vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}
wire _vc_sel_WIRE : UInt<1>[10]
node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13)
node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14)
node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15)
node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16)
node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18)
node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_28
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30)
node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31)
node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32)
node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33)
node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34)
node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35)
node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36)
node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_47
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49)
node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50)
node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51)
node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_66
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73)
node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74)
node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75)
node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_85
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88)
node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89)
node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90)
node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91)
node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92)
node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93)
node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94)
node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_104
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106)
node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107)
node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108)
node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109)
node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110)
node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111)
node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_123
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125)
node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126)
node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_142
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148)
node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149)
node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150)
node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151)
node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_161
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163)
node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164)
node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165)
node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166)
node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167)
node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168)
node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169)
node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170)
node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_180
connect _vc_sel_WIRE[8], _vc_sel_WIRE_9
node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182)
node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183)
node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184)
node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185)
node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186)
node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_199
connect _vc_sel_WIRE[9], _vc_sel_WIRE_10
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_11 : UInt<1>[10]
node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201)
node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208)
node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_218
connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12
node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223)
node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224)
node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225)
node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226)
node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227)
node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_237
connect _vc_sel_WIRE_11[1], _vc_sel_WIRE_13
node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239)
node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240)
node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241)
node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242)
node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243)
node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244)
node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245)
node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246)
node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_256
connect _vc_sel_WIRE_11[2], _vc_sel_WIRE_14
node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258)
node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259)
node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260)
node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261)
node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_275
connect _vc_sel_WIRE_11[3], _vc_sel_WIRE_15
node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283)
node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284)
node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_294
connect _vc_sel_WIRE_11[4], _vc_sel_WIRE_16
node _vc_sel_T_295 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_301 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_302 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_303 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_304 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_305 = or(_vc_sel_T_295, _vc_sel_T_296)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_297)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_298)
node _vc_sel_T_308 = or(_vc_sel_T_307, _vc_sel_T_299)
node _vc_sel_T_309 = or(_vc_sel_T_308, _vc_sel_T_300)
node _vc_sel_T_310 = or(_vc_sel_T_309, _vc_sel_T_301)
node _vc_sel_T_311 = or(_vc_sel_T_310, _vc_sel_T_302)
node _vc_sel_T_312 = or(_vc_sel_T_311, _vc_sel_T_303)
node _vc_sel_T_313 = or(_vc_sel_T_312, _vc_sel_T_304)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_313
connect _vc_sel_WIRE_11[5], _vc_sel_WIRE_17
node _vc_sel_T_314 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_316 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_317 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_318 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_319 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_320 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_321 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_322 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_323 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_324 = or(_vc_sel_T_314, _vc_sel_T_315)
node _vc_sel_T_325 = or(_vc_sel_T_324, _vc_sel_T_316)
node _vc_sel_T_326 = or(_vc_sel_T_325, _vc_sel_T_317)
node _vc_sel_T_327 = or(_vc_sel_T_326, _vc_sel_T_318)
node _vc_sel_T_328 = or(_vc_sel_T_327, _vc_sel_T_319)
node _vc_sel_T_329 = or(_vc_sel_T_328, _vc_sel_T_320)
node _vc_sel_T_330 = or(_vc_sel_T_329, _vc_sel_T_321)
node _vc_sel_T_331 = or(_vc_sel_T_330, _vc_sel_T_322)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_323)
wire _vc_sel_WIRE_18 : UInt<1>
connect _vc_sel_WIRE_18, _vc_sel_T_332
connect _vc_sel_WIRE_11[6], _vc_sel_WIRE_18
node _vc_sel_T_333 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_334 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_335 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_336 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_337 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_338 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_343 = or(_vc_sel_T_333, _vc_sel_T_334)
node _vc_sel_T_344 = or(_vc_sel_T_343, _vc_sel_T_335)
node _vc_sel_T_345 = or(_vc_sel_T_344, _vc_sel_T_336)
node _vc_sel_T_346 = or(_vc_sel_T_345, _vc_sel_T_337)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_338)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_339)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_340)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_341)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_342)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_351
connect _vc_sel_WIRE_11[7], _vc_sel_WIRE_19
node _vc_sel_T_352 = mux(_vc_sel_T, states[0].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_353 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_361 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_362 = or(_vc_sel_T_352, _vc_sel_T_353)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_354)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_355)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_356)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_357)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_358)
node _vc_sel_T_368 = or(_vc_sel_T_367, _vc_sel_T_359)
node _vc_sel_T_369 = or(_vc_sel_T_368, _vc_sel_T_360)
node _vc_sel_T_370 = or(_vc_sel_T_369, _vc_sel_T_361)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_370
connect _vc_sel_WIRE_11[8], _vc_sel_WIRE_20
node _vc_sel_T_371 = mux(_vc_sel_T, states[0].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_376 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_377 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_378 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_379 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_380 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_381 = or(_vc_sel_T_371, _vc_sel_T_372)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_373)
node _vc_sel_T_383 = or(_vc_sel_T_382, _vc_sel_T_374)
node _vc_sel_T_384 = or(_vc_sel_T_383, _vc_sel_T_375)
node _vc_sel_T_385 = or(_vc_sel_T_384, _vc_sel_T_376)
node _vc_sel_T_386 = or(_vc_sel_T_385, _vc_sel_T_377)
node _vc_sel_T_387 = or(_vc_sel_T_386, _vc_sel_T_378)
node _vc_sel_T_388 = or(_vc_sel_T_387, _vc_sel_T_379)
node _vc_sel_T_389 = or(_vc_sel_T_388, _vc_sel_T_380)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_389
connect _vc_sel_WIRE_11[9], _vc_sel_WIRE_21
connect vc_sel.`1`, _vc_sel_WIRE_11
wire _vc_sel_WIRE_22 : UInt<1>[10]
node _vc_sel_T_390 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_391 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_392 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_393 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_394 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_395 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_396 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_397 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_398 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_400 = or(_vc_sel_T_390, _vc_sel_T_391)
node _vc_sel_T_401 = or(_vc_sel_T_400, _vc_sel_T_392)
node _vc_sel_T_402 = or(_vc_sel_T_401, _vc_sel_T_393)
node _vc_sel_T_403 = or(_vc_sel_T_402, _vc_sel_T_394)
node _vc_sel_T_404 = or(_vc_sel_T_403, _vc_sel_T_395)
node _vc_sel_T_405 = or(_vc_sel_T_404, _vc_sel_T_396)
node _vc_sel_T_406 = or(_vc_sel_T_405, _vc_sel_T_397)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_398)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_399)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_408
connect _vc_sel_WIRE_22[0], _vc_sel_WIRE_23
node _vc_sel_T_409 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_410 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_411 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_412 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_413 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_419 = or(_vc_sel_T_409, _vc_sel_T_410)
node _vc_sel_T_420 = or(_vc_sel_T_419, _vc_sel_T_411)
node _vc_sel_T_421 = or(_vc_sel_T_420, _vc_sel_T_412)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_413)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_414)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_415)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_416)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_417)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_418)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_427
connect _vc_sel_WIRE_22[1], _vc_sel_WIRE_24
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_436 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_437 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_438 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_430)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_431)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_432)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_433)
node _vc_sel_T_443 = or(_vc_sel_T_442, _vc_sel_T_434)
node _vc_sel_T_444 = or(_vc_sel_T_443, _vc_sel_T_435)
node _vc_sel_T_445 = or(_vc_sel_T_444, _vc_sel_T_436)
node _vc_sel_T_446 = or(_vc_sel_T_445, _vc_sel_T_437)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_446
connect _vc_sel_WIRE_22[2], _vc_sel_WIRE_25
node _vc_sel_T_447 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_451 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_452 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_453 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_454 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_455 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_456 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_457 = or(_vc_sel_T_447, _vc_sel_T_448)
node _vc_sel_T_458 = or(_vc_sel_T_457, _vc_sel_T_449)
node _vc_sel_T_459 = or(_vc_sel_T_458, _vc_sel_T_450)
node _vc_sel_T_460 = or(_vc_sel_T_459, _vc_sel_T_451)
node _vc_sel_T_461 = or(_vc_sel_T_460, _vc_sel_T_452)
node _vc_sel_T_462 = or(_vc_sel_T_461, _vc_sel_T_453)
node _vc_sel_T_463 = or(_vc_sel_T_462, _vc_sel_T_454)
node _vc_sel_T_464 = or(_vc_sel_T_463, _vc_sel_T_455)
node _vc_sel_T_465 = or(_vc_sel_T_464, _vc_sel_T_456)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_465
connect _vc_sel_WIRE_22[3], _vc_sel_WIRE_26
node _vc_sel_T_466 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_467 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_468 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_469 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_470 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_471 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_472 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_473 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_476 = or(_vc_sel_T_466, _vc_sel_T_467)
node _vc_sel_T_477 = or(_vc_sel_T_476, _vc_sel_T_468)
node _vc_sel_T_478 = or(_vc_sel_T_477, _vc_sel_T_469)
node _vc_sel_T_479 = or(_vc_sel_T_478, _vc_sel_T_470)
node _vc_sel_T_480 = or(_vc_sel_T_479, _vc_sel_T_471)
node _vc_sel_T_481 = or(_vc_sel_T_480, _vc_sel_T_472)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_473)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_474)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_475)
wire _vc_sel_WIRE_27 : UInt<1>
connect _vc_sel_WIRE_27, _vc_sel_T_484
connect _vc_sel_WIRE_22[4], _vc_sel_WIRE_27
node _vc_sel_T_485 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_486 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_487 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_488 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_489 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_490 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_491 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_492 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_493 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_494 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_495 = or(_vc_sel_T_485, _vc_sel_T_486)
node _vc_sel_T_496 = or(_vc_sel_T_495, _vc_sel_T_487)
node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_488)
node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_489)
node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_490)
node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_491)
node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_492)
node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_493)
node _vc_sel_T_503 = or(_vc_sel_T_502, _vc_sel_T_494)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_503
connect _vc_sel_WIRE_22[5], _vc_sel_WIRE_28
node _vc_sel_T_504 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_505 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_506 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_507 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_508 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_509 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_510 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_511 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_512 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_513 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_514 = or(_vc_sel_T_504, _vc_sel_T_505)
node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_506)
node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_507)
node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_508)
node _vc_sel_T_518 = or(_vc_sel_T_517, _vc_sel_T_509)
node _vc_sel_T_519 = or(_vc_sel_T_518, _vc_sel_T_510)
node _vc_sel_T_520 = or(_vc_sel_T_519, _vc_sel_T_511)
node _vc_sel_T_521 = or(_vc_sel_T_520, _vc_sel_T_512)
node _vc_sel_T_522 = or(_vc_sel_T_521, _vc_sel_T_513)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_522
connect _vc_sel_WIRE_22[6], _vc_sel_WIRE_29
node _vc_sel_T_523 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_524 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_525 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_526 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_527 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_528 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_529 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_530 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_531 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_532 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_533 = or(_vc_sel_T_523, _vc_sel_T_524)
node _vc_sel_T_534 = or(_vc_sel_T_533, _vc_sel_T_525)
node _vc_sel_T_535 = or(_vc_sel_T_534, _vc_sel_T_526)
node _vc_sel_T_536 = or(_vc_sel_T_535, _vc_sel_T_527)
node _vc_sel_T_537 = or(_vc_sel_T_536, _vc_sel_T_528)
node _vc_sel_T_538 = or(_vc_sel_T_537, _vc_sel_T_529)
node _vc_sel_T_539 = or(_vc_sel_T_538, _vc_sel_T_530)
node _vc_sel_T_540 = or(_vc_sel_T_539, _vc_sel_T_531)
node _vc_sel_T_541 = or(_vc_sel_T_540, _vc_sel_T_532)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_541
connect _vc_sel_WIRE_22[7], _vc_sel_WIRE_30
node _vc_sel_T_542 = mux(_vc_sel_T, states[0].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_543 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_544 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_545 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_546 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_547 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_548 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_549 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_550 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_551 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[8], UInt<1>(0h0))
node _vc_sel_T_552 = or(_vc_sel_T_542, _vc_sel_T_543)
node _vc_sel_T_553 = or(_vc_sel_T_552, _vc_sel_T_544)
node _vc_sel_T_554 = or(_vc_sel_T_553, _vc_sel_T_545)
node _vc_sel_T_555 = or(_vc_sel_T_554, _vc_sel_T_546)
node _vc_sel_T_556 = or(_vc_sel_T_555, _vc_sel_T_547)
node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_548)
node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_549)
node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_550)
node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_551)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_560
connect _vc_sel_WIRE_22[8], _vc_sel_WIRE_31
node _vc_sel_T_561 = mux(_vc_sel_T, states[0].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_562 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_563 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_564 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_565 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_566 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_567 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_568 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_569 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_570 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[9], UInt<1>(0h0))
node _vc_sel_T_571 = or(_vc_sel_T_561, _vc_sel_T_562)
node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_563)
node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_564)
node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_565)
node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_566)
node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_567)
node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_568)
node _vc_sel_T_578 = or(_vc_sel_T_577, _vc_sel_T_569)
node _vc_sel_T_579 = or(_vc_sel_T_578, _vc_sel_T_570)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_579
connect _vc_sel_WIRE_22[9], _vc_sel_WIRE_32
connect vc_sel.`2`, _vc_sel_WIRE_22
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8])
node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9])
node _channel_oh_T_8 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[2])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[3])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[4])
node _channel_oh_T_12 = or(_channel_oh_T_11, vc_sel.`1`[5])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`1`[6])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`1`[7])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`1`[8])
node channel_oh_1 = or(_channel_oh_T_15, vc_sel.`1`[9])
node _channel_oh_T_16 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[2])
node _channel_oh_T_18 = or(_channel_oh_T_17, vc_sel.`2`[3])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`2`[4])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`2`[5])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`2`[6])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`2`[7])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`2`[8])
node channel_oh_2 = or(_channel_oh_T_23, vc_sel.`2`[9])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3])
node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5])
node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8])
node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8)
node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2)
node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0)
node _virt_channel_T_5 = orr(virt_channel_hi_3)
node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3)
node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1)
node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7)
node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8)
node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3])
node virt_channel_lo_hi_1 = cat(virt_channel_lo_hi_hi_1, vc_sel.`1`[2])
node virt_channel_lo_4 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[6], vc_sel.`1`[5])
node virt_channel_hi_hi_hi_1 = cat(vc_sel.`1`[9], vc_sel.`1`[8])
node virt_channel_hi_hi_1 = cat(virt_channel_hi_hi_hi_1, vc_sel.`1`[7])
node virt_channel_hi_4 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_11 = cat(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_11, 9, 8)
node virt_channel_lo_5 = bits(_virt_channel_T_11, 7, 0)
node _virt_channel_T_12 = orr(virt_channel_hi_5)
node _virt_channel_T_13 = or(virt_channel_hi_5, virt_channel_lo_5)
node virt_channel_hi_6 = bits(_virt_channel_T_13, 7, 4)
node virt_channel_lo_6 = bits(_virt_channel_T_13, 3, 0)
node _virt_channel_T_14 = orr(virt_channel_hi_6)
node _virt_channel_T_15 = or(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_15, 3, 2)
node virt_channel_lo_7 = bits(_virt_channel_T_15, 1, 0)
node _virt_channel_T_16 = orr(virt_channel_hi_7)
node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_7)
node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1)
node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18)
node _virt_channel_T_20 = cat(_virt_channel_T_14, _virt_channel_T_19)
node _virt_channel_T_21 = cat(_virt_channel_T_12, _virt_channel_T_20)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3])
node virt_channel_lo_hi_2 = cat(virt_channel_lo_hi_hi_2, vc_sel.`2`[2])
node virt_channel_lo_8 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[6], vc_sel.`2`[5])
node virt_channel_hi_hi_hi_2 = cat(vc_sel.`2`[9], vc_sel.`2`[8])
node virt_channel_hi_hi_2 = cat(virt_channel_hi_hi_hi_2, vc_sel.`2`[7])
node virt_channel_hi_8 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_22 = cat(virt_channel_hi_8, virt_channel_lo_8)
node virt_channel_hi_9 = bits(_virt_channel_T_22, 9, 8)
node virt_channel_lo_9 = bits(_virt_channel_T_22, 7, 0)
node _virt_channel_T_23 = orr(virt_channel_hi_9)
node _virt_channel_T_24 = or(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = cat(_virt_channel_T_23, _virt_channel_T_31)
node _virt_channel_T_33 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_1, _virt_channel_T_21, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_2, _virt_channel_T_32, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_33, _virt_channel_T_34)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_35)
wire virt_channel : UInt<4>
connect virt_channel, _virt_channel_T_37
node _T_133 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_133 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15)
node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16)
node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17)
node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18)
node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15)
node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16)
node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17)
node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18)
node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15)
node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16)
node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17)
node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18)
node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15)
node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16)
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18)
node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30)
node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31)
node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32)
node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33)
node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34)
node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35)
node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36)
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49)
node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50)
node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51)
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75)
node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87)
node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88)
node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89)
node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90)
node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91)
node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92)
node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93)
node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94)
node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`0`[8]
invalidate states[0].vc_sel.`0`[9]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`1`[3]
invalidate states[0].vc_sel.`1`[4]
invalidate states[0].vc_sel.`1`[5]
invalidate states[0].vc_sel.`1`[6]
invalidate states[0].vc_sel.`1`[7]
invalidate states[0].vc_sel.`1`[8]
invalidate states[0].vc_sel.`1`[9]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`2`[3]
invalidate states[0].vc_sel.`2`[4]
invalidate states[0].vc_sel.`2`[5]
invalidate states[0].vc_sel.`2`[6]
invalidate states[0].vc_sel.`2`[7]
invalidate states[0].vc_sel.`2`[8]
invalidate states[0].vc_sel.`2`[9]
invalidate states[0].g
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`0`[3]
invalidate states[1].vc_sel.`0`[4]
invalidate states[1].vc_sel.`0`[5]
invalidate states[1].vc_sel.`0`[6]
invalidate states[1].vc_sel.`0`[7]
invalidate states[1].vc_sel.`0`[8]
invalidate states[1].vc_sel.`0`[9]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`1`[3]
invalidate states[1].vc_sel.`1`[4]
invalidate states[1].vc_sel.`1`[5]
invalidate states[1].vc_sel.`1`[6]
invalidate states[1].vc_sel.`1`[7]
invalidate states[1].vc_sel.`1`[8]
invalidate states[1].vc_sel.`1`[9]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`2`[2]
invalidate states[1].vc_sel.`2`[3]
invalidate states[1].vc_sel.`2`[4]
invalidate states[1].vc_sel.`2`[5]
invalidate states[1].vc_sel.`2`[6]
invalidate states[1].vc_sel.`2`[7]
invalidate states[1].vc_sel.`2`[8]
invalidate states[1].vc_sel.`2`[9]
invalidate states[1].g
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[6], UInt<1>(0h0)
connect states[2].vc_sel.`0`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[8], UInt<1>(0h0)
connect states[2].vc_sel.`0`[9], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`1`[3], UInt<1>(0h0)
connect states[2].vc_sel.`1`[4], UInt<1>(0h0)
connect states[2].vc_sel.`1`[5], UInt<1>(0h0)
connect states[2].vc_sel.`1`[6], UInt<1>(0h0)
connect states[2].vc_sel.`1`[7], UInt<1>(0h0)
connect states[2].vc_sel.`1`[8], UInt<1>(0h0)
connect states[2].vc_sel.`1`[9], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[2].vc_sel.`2`[1], UInt<1>(0h0)
connect states[2].vc_sel.`2`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[6], UInt<1>(0h0)
connect states[3].vc_sel.`0`[7], UInt<1>(0h0)
connect states[3].vc_sel.`0`[8], UInt<1>(0h0)
connect states[3].vc_sel.`0`[9], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[1], UInt<1>(0h0)
connect states[3].vc_sel.`1`[2], UInt<1>(0h0)
connect states[3].vc_sel.`1`[3], UInt<1>(0h0)
connect states[3].vc_sel.`1`[4], UInt<1>(0h0)
connect states[3].vc_sel.`1`[5], UInt<1>(0h0)
connect states[3].vc_sel.`1`[6], UInt<1>(0h0)
connect states[3].vc_sel.`1`[7], UInt<1>(0h0)
connect states[3].vc_sel.`1`[8], UInt<1>(0h0)
connect states[3].vc_sel.`1`[9], UInt<1>(0h0)
connect states[3].vc_sel.`2`[0], UInt<1>(0h0)
connect states[3].vc_sel.`2`[1], UInt<1>(0h0)
connect states[3].vc_sel.`2`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[4].vc_sel.`0`[8], UInt<1>(0h0)
connect states[4].vc_sel.`0`[9], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[4], UInt<1>(0h0)
connect states[4].vc_sel.`1`[5], UInt<1>(0h0)
connect states[4].vc_sel.`1`[6], UInt<1>(0h0)
connect states[4].vc_sel.`1`[7], UInt<1>(0h0)
connect states[4].vc_sel.`1`[8], UInt<1>(0h0)
connect states[4].vc_sel.`1`[9], UInt<1>(0h0)
connect states[4].vc_sel.`2`[0], UInt<1>(0h0)
connect states[4].vc_sel.`2`[1], UInt<1>(0h0)
connect states[4].vc_sel.`2`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`0`[8], UInt<1>(0h0)
connect states[5].vc_sel.`0`[9], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`1`[3], UInt<1>(0h0)
connect states[5].vc_sel.`1`[4], UInt<1>(0h0)
connect states[5].vc_sel.`1`[5], UInt<1>(0h0)
connect states[5].vc_sel.`1`[6], UInt<1>(0h0)
connect states[5].vc_sel.`1`[7], UInt<1>(0h0)
connect states[5].vc_sel.`1`[8], UInt<1>(0h0)
connect states[5].vc_sel.`1`[9], UInt<1>(0h0)
connect states[5].vc_sel.`2`[0], UInt<1>(0h0)
connect states[5].vc_sel.`2`[1], UInt<1>(0h0)
connect states[5].vc_sel.`2`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`0`[8], UInt<1>(0h0)
connect states[6].vc_sel.`0`[9], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`1`[3], UInt<1>(0h0)
connect states[6].vc_sel.`1`[4], UInt<1>(0h0)
connect states[6].vc_sel.`1`[5], UInt<1>(0h0)
connect states[6].vc_sel.`1`[6], UInt<1>(0h0)
connect states[6].vc_sel.`1`[7], UInt<1>(0h0)
connect states[6].vc_sel.`1`[8], UInt<1>(0h0)
connect states[6].vc_sel.`1`[9], UInt<1>(0h0)
connect states[6].vc_sel.`2`[0], UInt<1>(0h0)
connect states[6].vc_sel.`2`[1], UInt<1>(0h0)
connect states[6].vc_sel.`2`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`0`[8], UInt<1>(0h0)
connect states[7].vc_sel.`0`[9], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`1`[3], UInt<1>(0h0)
connect states[7].vc_sel.`1`[4], UInt<1>(0h0)
connect states[7].vc_sel.`1`[5], UInt<1>(0h0)
connect states[7].vc_sel.`1`[6], UInt<1>(0h0)
connect states[7].vc_sel.`1`[7], UInt<1>(0h0)
connect states[7].vc_sel.`1`[8], UInt<1>(0h0)
connect states[7].vc_sel.`1`[9], UInt<1>(0h0)
connect states[7].vc_sel.`2`[0], UInt<1>(0h0)
connect states[7].vc_sel.`2`[1], UInt<1>(0h0)
connect states[7].vc_sel.`2`[2], UInt<1>(0h0)
connect states[8].vc_sel.`0`[0], UInt<1>(0h0)
connect states[8].vc_sel.`0`[1], UInt<1>(0h0)
connect states[8].vc_sel.`0`[2], UInt<1>(0h0)
connect states[8].vc_sel.`0`[3], UInt<1>(0h0)
connect states[8].vc_sel.`0`[4], UInt<1>(0h0)
connect states[8].vc_sel.`0`[5], UInt<1>(0h0)
connect states[8].vc_sel.`0`[6], UInt<1>(0h0)
connect states[8].vc_sel.`0`[7], UInt<1>(0h0)
connect states[8].vc_sel.`0`[8], UInt<1>(0h0)
connect states[8].vc_sel.`0`[9], UInt<1>(0h0)
connect states[8].vc_sel.`1`[0], UInt<1>(0h0)
connect states[8].vc_sel.`1`[1], UInt<1>(0h0)
connect states[8].vc_sel.`1`[2], UInt<1>(0h0)
connect states[8].vc_sel.`1`[3], UInt<1>(0h0)
connect states[8].vc_sel.`1`[4], UInt<1>(0h0)
connect states[8].vc_sel.`1`[5], UInt<1>(0h0)
connect states[8].vc_sel.`1`[6], UInt<1>(0h0)
connect states[8].vc_sel.`1`[7], UInt<1>(0h0)
connect states[8].vc_sel.`1`[8], UInt<1>(0h0)
connect states[8].vc_sel.`1`[9], UInt<1>(0h0)
connect states[8].vc_sel.`2`[0], UInt<1>(0h0)
connect states[8].vc_sel.`2`[1], UInt<1>(0h0)
connect states[8].vc_sel.`2`[2], UInt<1>(0h0)
connect states[9].vc_sel.`0`[0], UInt<1>(0h0)
connect states[9].vc_sel.`0`[1], UInt<1>(0h0)
connect states[9].vc_sel.`0`[2], UInt<1>(0h0)
connect states[9].vc_sel.`0`[3], UInt<1>(0h0)
connect states[9].vc_sel.`0`[4], UInt<1>(0h0)
connect states[9].vc_sel.`0`[5], UInt<1>(0h0)
connect states[9].vc_sel.`0`[6], UInt<1>(0h0)
connect states[9].vc_sel.`0`[7], UInt<1>(0h0)
connect states[9].vc_sel.`0`[8], UInt<1>(0h0)
connect states[9].vc_sel.`0`[9], UInt<1>(0h0)
connect states[9].vc_sel.`1`[0], UInt<1>(0h0)
connect states[9].vc_sel.`1`[1], UInt<1>(0h0)
connect states[9].vc_sel.`1`[2], UInt<1>(0h0)
connect states[9].vc_sel.`1`[3], UInt<1>(0h0)
connect states[9].vc_sel.`1`[4], UInt<1>(0h0)
connect states[9].vc_sel.`1`[5], UInt<1>(0h0)
connect states[9].vc_sel.`1`[6], UInt<1>(0h0)
connect states[9].vc_sel.`1`[7], UInt<1>(0h0)
connect states[9].vc_sel.`1`[8], UInt<1>(0h0)
connect states[9].vc_sel.`1`[9], UInt<1>(0h0)
connect states[9].vc_sel.`2`[0], UInt<1>(0h0)
connect states[9].vc_sel.`2`[1], UInt<1>(0h0)
connect states[9].vc_sel.`2`[2], UInt<1>(0h0)
node _T_134 = asUInt(reset)
when _T_134 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0)
connect states[8].g, UInt<3>(0h0)
connect states[9].g, UInt<3>(0h0) | module InputUnit_133( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_8, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_9, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_8, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_9, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_8, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_9, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [9:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_9; // @[InputUnit.scala:266:32]
wire vcalloc_vals_8; // @[InputUnit.scala:266:32]
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_8_g; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_9_g; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [9:0] mask; // @[InputUnit.scala:250:21]
wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, 2'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_2 ? 20'h1000 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_6 ? 20'h10000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71]
wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7 | vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_40 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_40( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_100 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}}
wire _in_flight_WIRE : UInt<1>[5]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = or(_T_17, _T_24)
node _T_26 = or(_T_10, _T_25)
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_26, UInt<1>(0h1), "") : assert_2
node _T_30 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_31 = or(_T_30, UInt<1>(0h0))
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
node _T_34 = eq(_T_31, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_31, UInt<1>(0h1), "") : assert_3
node _T_35 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_36 = or(_T_35, UInt<1>(0h0))
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_36, UInt<1>(0h1), "") : assert_4
node _T_40 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_41 = or(_T_40, UInt<1>(0h0))
node _T_42 = asUInt(reset)
node _T_43 = eq(_T_42, UInt<1>(0h0))
when _T_43 :
node _T_44 = eq(_T_41, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_41, UInt<1>(0h1), "") : assert_5 | module NoCMonitor_100( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h4; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_prcibus_i1_o2_a21d64s7k1z3u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_66
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect anonIn, auto.anon_in
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 6, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<21>(0h0)
connect _WIRE_30.bits.source, UInt<7>(0h0)
connect _WIRE_30.bits.size, UInt<3>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.address, UInt<21>(0h0)
connect _WIRE_32.bits.source, UInt<7>(0h0)
connect _WIRE_32.bits.size, UInt<3>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<21>(0h0)
connect _WIRE_34.bits.source, UInt<7>(0h0)
connect _WIRE_34.bits.size, UInt<3>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.address, UInt<21>(0h0)
connect _WIRE_36.bits.source, UInt<7>(0h0)
connect _WIRE_36.bits.size, UInt<3>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.ready, UInt<1>(0h1)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<21>(0h0)
connect _WIRE_38.bits.source, UInt<7>(0h0)
connect _WIRE_38.bits.size, UInt<3>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.ready, UInt<1>(0h1)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.valid, UInt<1>(0h0)
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<21>(0h0)
connect _WIRE_48.bits.source, UInt<7>(0h0)
connect _WIRE_48.bits.size, UInt<3>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<21>(0h0)
connect _WIRE_50.bits.source, UInt<7>(0h0)
connect _WIRE_50.bits.size, UInt<3>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<21>(0h0)
connect _WIRE_52.bits.source, UInt<7>(0h0)
connect _WIRE_52.bits.size, UInt<3>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<21>(0h0)
connect _WIRE_54.bits.source, UInt<7>(0h0)
connect _WIRE_54.bits.size, UInt<3>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.address, UInt<21>(0h0)
connect _WIRE_56.bits.source, UInt<7>(0h0)
connect _WIRE_56.bits.size, UInt<3>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<21>(0h0)
connect _WIRE_58.bits.source, UInt<7>(0h0)
connect _WIRE_58.bits.size, UInt<3>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.address, UInt<21>(0h0)
connect _WIRE_60.bits.source, UInt<7>(0h0)
connect _WIRE_60.bits.size, UInt<3>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<21>(0h0)
connect _WIRE_62.bits.source, UInt<7>(0h0)
connect _WIRE_62.bits.size, UInt<3>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.address, UInt<21>(0h0)
connect _addressC_WIRE.bits.source, UInt<7>(0h0)
connect _addressC_WIRE.bits.size, UInt<3>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<18>(0h10000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<18>(0h10000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<21>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 6, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 7)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<7>(0h7f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<21>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 6, 0)
node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 7)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<7>(0h7f))
node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 6, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 7)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<7>(0h7f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 6, 0)
node _requestDOI_T_5 = shr(out[1].d.bits.source, 7)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<7>(0h7f))
node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9)
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<21>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_2.bits.address, UInt<21>(0h0)
connect _beatsBO_WIRE_2.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_2.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_2.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits
connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid
connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<21>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<21>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready
wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_2.bits.address, UInt<21>(0h0)
connect _portsBIO_WIRE_2.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_2.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_2.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits
connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid
connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<21>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1)
wire _portsCOI_WIRE_2 : UInt<1>
connect _portsCOI_WIRE_2, _portsCOI_T_2
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect out[0].d.ready, portsDIO_filtered[0].ready
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect out[1].d.ready, portsDIO_filtered_1[0].ready
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1)
wire _portsEOI_WIRE_2 : UInt<1>
connect _portsEOI_WIRE_2, _portsEOI_T_2
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2
connect out[0].a, portsAOI_filtered[0]
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.address, UInt<21>(0h0)
connect _WIRE_72.bits.source, UInt<7>(0h0)
connect _WIRE_72.bits.size, UInt<3>(0h0)
connect _WIRE_72.bits.param, UInt<3>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_74.bits.sink, UInt<1>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect out[1].a, portsAOI_filtered[1]
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.address, UInt<21>(0h0)
connect _WIRE_76.bits.source, UInt<7>(0h0)
connect _WIRE_76.bits.size, UInt<3>(0h0)
connect _WIRE_76.bits.param, UInt<3>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_78.bits.sink, UInt<1>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
invalidate _WIRE_79.bits.sink
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_80.bits.corrupt, UInt<1>(0h0)
connect _WIRE_80.bits.data, UInt<64>(0h0)
connect _WIRE_80.bits.mask, UInt<8>(0h0)
connect _WIRE_80.bits.address, UInt<21>(0h0)
connect _WIRE_80.bits.source, UInt<7>(0h0)
connect _WIRE_80.bits.size, UInt<3>(0h0)
connect _WIRE_80.bits.param, UInt<2>(0h0)
connect _WIRE_80.bits.opcode, UInt<3>(0h0)
connect _WIRE_80.valid, UInt<1>(0h0)
connect _WIRE_80.ready, UInt<1>(0h0)
wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_81.bits, _WIRE_80.bits
connect _WIRE_81.valid, _WIRE_80.valid
connect _WIRE_81.ready, _WIRE_80.ready
invalidate _WIRE_81.bits.corrupt
invalidate _WIRE_81.bits.data
invalidate _WIRE_81.bits.mask
invalidate _WIRE_81.bits.address
invalidate _WIRE_81.bits.source
invalidate _WIRE_81.bits.size
invalidate _WIRE_81.bits.param
invalidate _WIRE_81.bits.opcode
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, in[0].d.ready)
node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsDIO_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(in[0].d.ready, allowed[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3
node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_4
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10)
wire _in_0_d_bits_WIRE_6 : UInt<1>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13)
wire _in_0_d_bits_WIRE_7 : UInt<7>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
wire _in_0_d_bits_WIRE_8 : UInt<3>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) | module TLXbar_prcibus_i1_o2_a21d64s7k1z3u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _portsAOI_in_0_a_ready_T_2 = ~(auto_anon_in_a_bits_address[16]) & auto_anon_out_0_a_ready | auto_anon_in_a_bits_address[16] & auto_anon_out_1_a_ready; // @[Mux.scala:30:73]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid = {auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_out_1_d_valid} | _readys_filter_T_1)); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_101
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_102
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_103 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_104 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_50( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [8:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLPLIC :
input clock : Clock
input reset : Reset
output auto : { flip int_in : UInt<1>[1], int_out : UInt<1>[1], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_31
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire intnodeIn : UInt<1>[1]
invalidate intnodeIn[0]
wire intnodeOut : UInt<1>[1]
invalidate intnodeOut[0]
connect nodeIn, auto.in
connect auto.int_out, intnodeOut
connect intnodeIn, auto.int_in
inst gateways_gateway of LevelGateway
connect gateways_gateway.clock, clock
connect gateways_gateway.reset, reset
connect gateways_gateway.io.interrupt, intnodeIn[0]
reg priority : UInt<1>[1], clock
reg threshold : UInt<1>[1], clock
wire _pending_WIRE : UInt<1>[1]
connect _pending_WIRE[0], UInt<1>(0h0)
regreset pending : UInt<1>[1], clock, reset, _pending_WIRE
reg enables_0_0 : UInt<1>, clock
wire enableVec : UInt<1>[1]
connect enableVec[0], enables_0_0
node _enableVec0_T = cat(enableVec[0], UInt<1>(0h0))
wire enableVec0 : UInt<2>[1]
connect enableVec0[0], _enableVec0_T
reg maxDevs : UInt<1>[1], clock
inst fanin of PLICFanIn
connect fanin.clock, clock
connect fanin.reset, reset
connect fanin.io.prio[0], priority[0]
node _fanin_io_ip_T = and(enableVec[0], pending[0])
connect fanin.io.ip, _fanin_io_ip_T
connect maxDevs[0], fanin.io.dev
reg intnodeOut_0_REG : UInt, clock
connect intnodeOut_0_REG, fanin.io.max
node _intnodeOut_0_T = gt(intnodeOut_0_REG, threshold[0])
connect intnodeOut[0], _intnodeOut_0_T
wire claimer : UInt<1>[1]
node _T = sub(claimer[0], UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = and(claimer[0], _T_1)
node _T_3 = eq(_T_2, UInt<1>(0h0))
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:251 assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node claiming = mux(claimer[0], maxDevs[0], UInt<1>(0h0))
node claimedDevs_shiftAmount = bits(claiming, 0, 0)
node _claimedDevs_T = dshl(UInt<1>(0h1), claimedDevs_shiftAmount)
node _claimedDevs_T_1 = bits(_claimedDevs_T, 1, 0)
node _claimedDevs_T_2 = bits(_claimedDevs_T_1, 0, 0)
node _claimedDevs_T_3 = bits(_claimedDevs_T_1, 1, 1)
wire claimedDevs : UInt<1>[2]
connect claimedDevs[0], _claimedDevs_T_2
connect claimedDevs[1], _claimedDevs_T_3
node _gateway_io_plic_ready_T = eq(pending[0], UInt<1>(0h0))
connect gateways_gateway.io.plic.ready, _gateway_io_plic_ready_T
node _T_7 = or(claimedDevs[1], gateways_gateway.io.plic.valid)
when _T_7 :
node _pending_0_T = eq(claimedDevs[1], UInt<1>(0h0))
connect pending[0], _pending_0_T
wire completer : UInt<1>[1]
node _T_8 = sub(completer[0], UInt<1>(0h1))
node _T_9 = tail(_T_8, 1)
node _T_10 = and(completer[0], _T_9)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:268 assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
wire completerDev : UInt<1>
node completedDevs_shiftAmount = bits(completerDev, 0, 0)
node _completedDevs_T = dshl(UInt<1>(0h1), completedDevs_shiftAmount)
node _completedDevs_T_1 = bits(_completedDevs_T, 1, 0)
node completedDevs = mux(completer[0], _completedDevs_T_1, UInt<1>(0h0))
node _T_15 = bits(completedDevs, 0, 0)
node _T_16 = bits(completedDevs, 1, 1)
connect gateways_gateway.io.plic.complete, _T_16
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(nodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, nodeIn.a.bits.data
connect in.bits.mask, nodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
inst out_back_front_q of Queue1_RegMapperInput_i23_m8
connect out_back_front_q.clock, clock
connect out_back_front_q.reset, reset
connect out_back_front_q.io.enq, out_front
node out_maskMatch = not(UInt<23>(0h40600))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<23>(0h0))
node _out_T_1 = eq(out_bindex, UInt<23>(0h0))
node _out_T_2 = eq(out_findex, UInt<23>(0h0))
node _out_T_3 = eq(out_bindex, UInt<23>(0h0))
node _out_T_4 = eq(out_findex, UInt<23>(0h0))
node _out_T_5 = eq(out_bindex, UInt<23>(0h0))
node _out_T_6 = eq(out_findex, UInt<23>(0h0))
node _out_T_7 = eq(out_bindex, UInt<23>(0h0))
wire out_rivalid : UInt<1>[8]
wire out_wivalid : UInt<1>[8]
wire out_roready : UInt<1>[8]
wire out_woready : UInt<1>[8]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 0, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 0, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 0, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 0, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_8 = bits(out_back_front_q.io.deq.bits.data, 0, 0)
node _out_T_9 = and(out_f_rivalid, UInt<1>(0h1))
node _out_T_10 = and(UInt<1>(0h1), out_f_roready)
node _out_T_11 = eq(out_rimask, UInt<1>(0h0))
node _out_T_12 = eq(out_wimask, UInt<1>(0h0))
node _out_T_13 = eq(out_romask, UInt<1>(0h0))
node _out_T_14 = eq(out_womask, UInt<1>(0h0))
node _out_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _out_T_16 = bits(_out_T_15, 0, 0)
node _out_rimask_T_1 = bits(out_frontMask, 1, 1)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 1, 1)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 1, 1)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 1, 1)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_17 = bits(out_back_front_q.io.deq.bits.data, 1, 1)
node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1))
node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1)
node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_22 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_23 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_16, UInt<1>(0h0))
node out_prepend = cat(pending[0], _out_prepend_T)
node _out_T_24 = or(out_prepend, UInt<2>(0h0))
node _out_T_25 = bits(_out_T_24, 1, 0)
node _out_rimask_T_2 = bits(out_frontMask, 0, 0)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 0, 0)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 0, 0)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 0, 0)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_26 = bits(out_back_front_q.io.deq.bits.data, 0, 0)
when out_f_woready_2 :
connect threshold[0], _out_T_26
node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1))
node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2)
node _out_T_29 = and(out_f_wivalid_2, UInt<1>(0h1))
node _out_T_30 = and(UInt<1>(0h1), out_f_woready_2)
node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_33 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_34 = eq(out_womask_2, UInt<1>(0h0))
node _out_T_35 = or(threshold[0], UInt<1>(0h0))
node _out_T_36 = bits(_out_T_35, 0, 0)
node _out_rimask_T_3 = bits(out_frontMask, 31, 1)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 31, 1)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 31, 1)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 31, 1)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
node _out_T_37 = bits(out_back_front_q.io.deq.bits.data, 31, 1)
node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1))
node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3)
node _out_T_40 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_41 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_42 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_43 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_36, UInt<1>(0h0))
node out_prepend_1 = cat(UInt<1>(0h0), _out_prepend_T_1)
node _out_T_44 = or(out_prepend_1, UInt<32>(0h0))
node _out_T_45 = bits(_out_T_44, 31, 0)
node _out_rimask_T_4 = bits(out_frontMask, 63, 32)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 63, 32)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 63, 32)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 63, 32)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
connect claimer[0], out_f_roready_4
node _out_T_46 = bits(out_back_front_q.io.deq.bits.data, 63, 32)
node _out_T_47 = bits(_out_T_46, 0, 0)
node _out_T_48 = eq(completerDev, _out_T_47)
node _out_T_49 = asUInt(reset)
node _out_T_50 = eq(_out_T_49, UInt<1>(0h0))
when _out_T_50 :
node _out_T_51 = eq(_out_T_48, UInt<1>(0h0))
when _out_T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf
assert(clock, _out_T_48, UInt<1>(0h1), "") : out_assert
node _out_completerDev_T = bits(_out_T_46, 0, 0)
connect completerDev, _out_completerDev_T
node _out_completer_0_T = dshr(enableVec0[0], completerDev)
node _out_completer_0_T_1 = bits(_out_completer_0_T, 0, 0)
node _out_completer_0_T_2 = and(out_f_woready_4, _out_completer_0_T_1)
connect completer[0], _out_completer_0_T_2
node _out_T_52 = and(out_f_rivalid_4, UInt<1>(0h1))
node _out_T_53 = and(UInt<1>(0h1), out_f_roready_4)
node _out_T_54 = and(out_f_wivalid_4, UInt<1>(0h1))
node _out_T_55 = and(UInt<1>(0h1), out_f_woready_4)
node _out_T_56 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_57 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_58 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_59 = eq(out_womask_4, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_45, UInt<32>(0h0))
node out_prepend_2 = cat(maxDevs[0], _out_prepend_T_2)
node _out_T_60 = or(out_prepend_2, UInt<64>(0h0))
node _out_T_61 = bits(_out_T_60, 63, 0)
node _out_rimask_T_5 = bits(out_frontMask, 0, 0)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 0, 0)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 0, 0)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 0, 0)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_62 = bits(out_back_front_q.io.deq.bits.data, 0, 0)
node _out_T_63 = and(out_f_rivalid_5, UInt<1>(0h1))
node _out_T_64 = and(UInt<1>(0h1), out_f_roready_5)
node _out_T_65 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_66 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_67 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_68 = eq(out_womask_5, UInt<1>(0h0))
node _out_T_69 = or(UInt<1>(0h0), UInt<1>(0h0))
node _out_T_70 = bits(_out_T_69, 0, 0)
node _out_rimask_T_6 = bits(out_frontMask, 1, 1)
node out_rimask_6 = orr(_out_rimask_T_6)
node _out_wimask_T_6 = bits(out_frontMask, 1, 1)
node out_wimask_6 = andr(_out_wimask_T_6)
node _out_romask_T_6 = bits(out_backMask, 1, 1)
node out_romask_6 = orr(_out_romask_T_6)
node _out_womask_T_6 = bits(out_backMask, 1, 1)
node out_womask_6 = andr(_out_womask_T_6)
node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6)
node out_f_roready_6 = and(out_roready[6], out_romask_6)
node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6)
node out_f_woready_6 = and(out_woready[6], out_womask_6)
node _out_T_71 = bits(out_back_front_q.io.deq.bits.data, 1, 1)
when out_f_woready_6 :
connect enables_0_0, _out_T_71
node _out_T_72 = and(out_f_rivalid_6, UInt<1>(0h1))
node _out_T_73 = and(UInt<1>(0h1), out_f_roready_6)
node _out_T_74 = and(out_f_wivalid_6, UInt<1>(0h1))
node _out_T_75 = and(UInt<1>(0h1), out_f_woready_6)
node _out_T_76 = eq(out_rimask_6, UInt<1>(0h0))
node _out_T_77 = eq(out_wimask_6, UInt<1>(0h0))
node _out_T_78 = eq(out_romask_6, UInt<1>(0h0))
node _out_T_79 = eq(out_womask_6, UInt<1>(0h0))
node _out_prepend_T_3 = or(_out_T_70, UInt<1>(0h0))
node out_prepend_3 = cat(enables_0_0, _out_prepend_T_3)
node _out_T_80 = or(out_prepend_3, UInt<2>(0h0))
node _out_T_81 = bits(_out_T_80, 1, 0)
node _out_rimask_T_7 = bits(out_frontMask, 32, 32)
node out_rimask_7 = orr(_out_rimask_T_7)
node _out_wimask_T_7 = bits(out_frontMask, 32, 32)
node out_wimask_7 = andr(_out_wimask_T_7)
node _out_romask_T_7 = bits(out_backMask, 32, 32)
node out_romask_7 = orr(_out_romask_T_7)
node _out_womask_T_7 = bits(out_backMask, 32, 32)
node out_womask_7 = andr(_out_womask_T_7)
node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7)
node out_f_roready_7 = and(out_roready[7], out_romask_7)
node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7)
node out_f_woready_7 = and(out_woready[7], out_womask_7)
node _out_T_82 = bits(out_back_front_q.io.deq.bits.data, 32, 32)
when out_f_woready_7 :
connect priority[0], _out_T_82
node _out_T_83 = and(out_f_rivalid_7, UInt<1>(0h1))
node _out_T_84 = and(UInt<1>(0h1), out_f_roready_7)
node _out_T_85 = and(out_f_wivalid_7, UInt<1>(0h1))
node _out_T_86 = and(UInt<1>(0h1), out_f_woready_7)
node _out_T_87 = eq(out_rimask_7, UInt<1>(0h0))
node _out_T_88 = eq(out_wimask_7, UInt<1>(0h0))
node _out_T_89 = eq(out_romask_7, UInt<1>(0h0))
node _out_T_90 = eq(out_womask_7, UInt<1>(0h0))
node _out_prepend_T_4 = or(UInt<1>(0h0), UInt<32>(0h0))
node out_prepend_4 = cat(priority[0], _out_prepend_T_4)
node _out_T_91 = or(out_prepend_4, UInt<33>(0h0))
node _out_T_92 = bits(_out_T_91, 32, 0)
node _out_iindex_T = bits(out_front.bits.index, 0, 0)
node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8)
node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9)
node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10)
node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11)
node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12)
node _out_iindex_T_13 = bits(out_front.bits.index, 13, 13)
node _out_iindex_T_14 = bits(out_front.bits.index, 14, 14)
node _out_iindex_T_15 = bits(out_front.bits.index, 15, 15)
node _out_iindex_T_16 = bits(out_front.bits.index, 16, 16)
node _out_iindex_T_17 = bits(out_front.bits.index, 17, 17)
node _out_iindex_T_18 = bits(out_front.bits.index, 18, 18)
node _out_iindex_T_19 = bits(out_front.bits.index, 19, 19)
node _out_iindex_T_20 = bits(out_front.bits.index, 20, 20)
node _out_iindex_T_21 = bits(out_front.bits.index, 21, 21)
node _out_iindex_T_22 = bits(out_front.bits.index, 22, 22)
node out_iindex_hi = cat(_out_iindex_T_18, _out_iindex_T_10)
node out_iindex = cat(out_iindex_hi, _out_iindex_T_9)
node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0)
node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1)
node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2)
node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3)
node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4)
node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5)
node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6)
node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7)
node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8)
node _out_oindex_T_9 = bits(out_back_front_q.io.deq.bits.index, 9, 9)
node _out_oindex_T_10 = bits(out_back_front_q.io.deq.bits.index, 10, 10)
node _out_oindex_T_11 = bits(out_back_front_q.io.deq.bits.index, 11, 11)
node _out_oindex_T_12 = bits(out_back_front_q.io.deq.bits.index, 12, 12)
node _out_oindex_T_13 = bits(out_back_front_q.io.deq.bits.index, 13, 13)
node _out_oindex_T_14 = bits(out_back_front_q.io.deq.bits.index, 14, 14)
node _out_oindex_T_15 = bits(out_back_front_q.io.deq.bits.index, 15, 15)
node _out_oindex_T_16 = bits(out_back_front_q.io.deq.bits.index, 16, 16)
node _out_oindex_T_17 = bits(out_back_front_q.io.deq.bits.index, 17, 17)
node _out_oindex_T_18 = bits(out_back_front_q.io.deq.bits.index, 18, 18)
node _out_oindex_T_19 = bits(out_back_front_q.io.deq.bits.index, 19, 19)
node _out_oindex_T_20 = bits(out_back_front_q.io.deq.bits.index, 20, 20)
node _out_oindex_T_21 = bits(out_back_front_q.io.deq.bits.index, 21, 21)
node _out_oindex_T_22 = bits(out_back_front_q.io.deq.bits.index, 22, 22)
node out_oindex_hi = cat(_out_oindex_T_18, _out_oindex_T_10)
node out_oindex = cat(out_oindex_hi, _out_oindex_T_9)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node out_frontSel_2 = bits(_out_frontSel_T, 2, 2)
node out_frontSel_3 = bits(_out_frontSel_T, 3, 3)
node out_frontSel_4 = bits(_out_frontSel_T, 4, 4)
node out_frontSel_5 = bits(_out_frontSel_T, 5, 5)
node out_frontSel_6 = bits(_out_frontSel_T, 6, 6)
node out_frontSel_7 = bits(_out_frontSel_T, 7, 7)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node out_backSel_2 = bits(_out_backSel_T, 2, 2)
node out_backSel_3 = bits(_out_backSel_T, 3, 3)
node out_backSel_4 = bits(_out_backSel_T, 4, 4)
node out_backSel_5 = bits(_out_backSel_T, 5, 5)
node out_backSel_6 = bits(_out_backSel_T, 6, 6)
node out_backSel_7 = bits(_out_backSel_T, 7, 7)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T_6)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[7], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T_6, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T)
connect out_rifireMux_out_1, UInt<1>(0h1)
connect out_rivalid[1], _out_rifireMux_T_7
connect out_rivalid[0], _out_rifireMux_T_7
node _out_rifireMux_T_8 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
wire out_rifireMux_out_2 : UInt<1>
node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2)
node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4)
connect out_rifireMux_out_2, UInt<1>(0h1)
connect out_rivalid[6], _out_rifireMux_T_11
connect out_rivalid[5], _out_rifireMux_T_11
node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0))
node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12)
wire out_rifireMux_out_3 : UInt<1>
node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3)
node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1))
connect out_rifireMux_out_3, UInt<1>(0h1)
node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16)
wire out_rifireMux_out_4 : UInt<1>
node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4)
node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_2)
connect out_rifireMux_out_4, UInt<1>(0h1)
connect out_rivalid[4], _out_rifireMux_T_19
connect out_rivalid[3], _out_rifireMux_T_19
connect out_rivalid[2], _out_rifireMux_T_19
node _out_rifireMux_T_20 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20)
wire out_rifireMux_out_5 : UInt<1>
node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5)
node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, UInt<1>(0h1))
connect out_rifireMux_out_5, UInt<1>(0h1)
node _out_rifireMux_T_24 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24)
wire out_rifireMux_out_6 : UInt<1>
node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6)
node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, UInt<1>(0h1))
connect out_rifireMux_out_6, UInt<1>(0h1)
node _out_rifireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28)
wire out_rifireMux_out_7 : UInt<1>
node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7)
node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1))
connect out_rifireMux_out_7, UInt<1>(0h1)
node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32)
node _out_rifireMux_T_34 = geq(out_iindex, UInt<4>(0h8))
wire _out_rifireMux_WIRE : UInt<1>[8]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13
connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17
connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21
connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25
connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29
connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33
node out_rifireMux = mux(_out_rifireMux_T_34, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T_6)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[7], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T_6, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T)
connect out_wifireMux_out_1, UInt<1>(0h1)
connect out_wivalid[1], _out_wifireMux_T_8
connect out_wivalid[0], _out_wifireMux_T_8
node _out_wifireMux_T_9 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
wire out_wifireMux_out_2 : UInt<1>
node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2)
node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4)
connect out_wifireMux_out_2, UInt<1>(0h1)
connect out_wivalid[6], _out_wifireMux_T_12
connect out_wivalid[5], _out_wifireMux_T_12
node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0))
node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13)
wire out_wifireMux_out_3 : UInt<1>
node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3)
node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1))
connect out_wifireMux_out_3, UInt<1>(0h1)
node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17)
wire out_wifireMux_out_4 : UInt<1>
node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4)
node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_2)
connect out_wifireMux_out_4, UInt<1>(0h1)
connect out_wivalid[4], _out_wifireMux_T_20
connect out_wivalid[3], _out_wifireMux_T_20
connect out_wivalid[2], _out_wifireMux_T_20
node _out_wifireMux_T_21 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21)
wire out_wifireMux_out_5 : UInt<1>
node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5)
node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, UInt<1>(0h1))
connect out_wifireMux_out_5, UInt<1>(0h1)
node _out_wifireMux_T_25 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25)
wire out_wifireMux_out_6 : UInt<1>
node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6)
node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, UInt<1>(0h1))
connect out_wifireMux_out_6, UInt<1>(0h1)
node _out_wifireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29)
wire out_wifireMux_out_7 : UInt<1>
node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7)
node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1))
connect out_wifireMux_out_7, UInt<1>(0h1)
node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33)
node _out_wifireMux_T_35 = geq(out_iindex, UInt<4>(0h8))
wire _out_wifireMux_WIRE : UInt<1>[8]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14
connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18
connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22
connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26
connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30
connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34
node out_wifireMux = mux(_out_wifireMux_T_35, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_7)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[7], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_7, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_1)
connect out_rofireMux_out_1, UInt<1>(0h1)
connect out_roready[1], _out_rofireMux_T_7
connect out_roready[0], _out_rofireMux_T_7
node _out_rofireMux_T_8 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
wire out_rofireMux_out_2 : UInt<1>
node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2)
node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5)
connect out_rofireMux_out_2, UInt<1>(0h1)
connect out_roready[6], _out_rofireMux_T_11
connect out_roready[5], _out_rofireMux_T_11
node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0))
node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12)
wire out_rofireMux_out_3 : UInt<1>
node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3)
node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1))
connect out_rofireMux_out_3, UInt<1>(0h1)
node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16)
wire out_rofireMux_out_4 : UInt<1>
node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4)
node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, _out_T_3)
connect out_rofireMux_out_4, UInt<1>(0h1)
connect out_roready[4], _out_rofireMux_T_19
connect out_roready[3], _out_rofireMux_T_19
connect out_roready[2], _out_rofireMux_T_19
node _out_rofireMux_T_20 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20)
wire out_rofireMux_out_5 : UInt<1>
node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5)
node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, UInt<1>(0h1))
connect out_rofireMux_out_5, UInt<1>(0h1)
node _out_rofireMux_T_24 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24)
wire out_rofireMux_out_6 : UInt<1>
node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6)
node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, UInt<1>(0h1))
connect out_rofireMux_out_6, UInt<1>(0h1)
node _out_rofireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28)
wire out_rofireMux_out_7 : UInt<1>
node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7)
node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, UInt<1>(0h1))
connect out_rofireMux_out_7, UInt<1>(0h1)
node _out_rofireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32)
node _out_rofireMux_T_34 = geq(out_oindex, UInt<4>(0h8))
wire _out_rofireMux_WIRE : UInt<1>[8]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13
connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17
connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21
connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25
connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29
connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33
node out_rofireMux = mux(_out_rofireMux_T_34, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_7)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[7], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_7, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_1)
connect out_wofireMux_out_1, UInt<1>(0h1)
connect out_woready[1], _out_wofireMux_T_8
connect out_woready[0], _out_wofireMux_T_8
node _out_wofireMux_T_9 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
wire out_wofireMux_out_2 : UInt<1>
node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2)
node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5)
connect out_wofireMux_out_2, UInt<1>(0h1)
connect out_woready[6], _out_wofireMux_T_12
connect out_woready[5], _out_wofireMux_T_12
node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0))
node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13)
wire out_wofireMux_out_3 : UInt<1>
node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3)
node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1))
connect out_wofireMux_out_3, UInt<1>(0h1)
node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17)
wire out_wofireMux_out_4 : UInt<1>
node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4)
node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_3)
connect out_wofireMux_out_4, UInt<1>(0h1)
connect out_woready[4], _out_wofireMux_T_20
connect out_woready[3], _out_wofireMux_T_20
connect out_woready[2], _out_wofireMux_T_20
node _out_wofireMux_T_21 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21)
wire out_wofireMux_out_5 : UInt<1>
node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5)
node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, UInt<1>(0h1))
connect out_wofireMux_out_5, UInt<1>(0h1)
node _out_wofireMux_T_25 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25)
wire out_wofireMux_out_6 : UInt<1>
node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6)
node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, UInt<1>(0h1))
connect out_wofireMux_out_6, UInt<1>(0h1)
node _out_wofireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29)
wire out_wofireMux_out_7 : UInt<1>
node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7)
node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1))
connect out_wofireMux_out_7, UInt<1>(0h1)
node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33)
node _out_wofireMux_T_35 = geq(out_oindex, UInt<4>(0h8))
wire _out_wofireMux_WIRE : UInt<1>[8]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14
connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18
connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22
connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26
connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30
connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34
node out_wofireMux = mux(_out_wofireMux_T_35, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_q_io_deq_ready_T = and(out.ready, out_oready)
connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T
node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_back_front_q.io.deq.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<4>(0h8))
wire _out_out_bits_data_WIRE : UInt<1>[8]
connect _out_out_bits_data_WIRE[0], _out_T_7
connect _out_out_bits_data_WIRE[1], _out_T_1
connect _out_out_bits_data_WIRE[2], _out_T_5
connect _out_out_bits_data_WIRE[3], UInt<1>(0h1)
connect _out_out_bits_data_WIRE[4], _out_T_3
connect _out_out_bits_data_WIRE[5], UInt<1>(0h1)
connect _out_out_bits_data_WIRE[6], UInt<1>(0h1)
connect _out_out_bits_data_WIRE[7], UInt<1>(0h1)
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<4>(0h8))
wire _out_out_bits_data_WIRE_1 : UInt<64>[8]
connect _out_out_bits_data_WIRE_1[0], _out_T_92
connect _out_out_bits_data_WIRE_1[1], _out_T_25
connect _out_out_bits_data_WIRE_1[2], _out_T_81
connect _out_out_bits_data_WIRE_1[3], UInt<1>(0h0)
connect _out_out_bits_data_WIRE_1[4], _out_T_61
connect _out_out_bits_data_WIRE_1[5], UInt<1>(0h0)
connect _out_out_bits_data_WIRE_1[6], UInt<1>(0h0)
connect _out_out_bits_data_WIRE_1[7], UInt<1>(0h0)
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_back_front_q.io.deq.bits.extra
connect in.valid, nodeIn.a.valid
connect nodeIn.a.ready, in.ready
connect nodeIn.d.valid, out.valid
connect out.ready, nodeIn.d.ready
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate nodeIn_d_bits_d.data
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
connect nodeIn.d.bits.data, out.bits.data
node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLPLIC( // @[Plic.scala:132:9]
input clock, // @[Plic.scala:132:9]
input reset, // @[Plic.scala:132:9]
input auto_int_in_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_0, // @[LazyModuleImp.scala:107:25]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24]
wire _fanin_io_dev; // @[Plic.scala:189:27]
wire _fanin_io_max; // @[Plic.scala:189:27]
wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27]
wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9]
wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9]
wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9]
wire _out_T_49 = reset; // @[Plic.scala:298:19]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9]
wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55]
wire _out_T_15 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_3 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_5 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_6 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_7 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [31:0] _out_prepend_T_4 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [22:0] out_maskMatch = 23'h7BF9FF; // @[RegisterRouter.scala:87:24]
wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9]
wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9]
wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_int_out_0_0; // @[Plic.scala:132:9]
wire auto_in_a_ready_0; // @[Plic.scala:132:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9]
wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9]
wire [10:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9]
wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9]
wire auto_in_d_valid_0; // @[Plic.scala:132:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9]
wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9]
wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9]
wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9]
wire _intnodeOut_0_T; // @[Plic.scala:193:60]
assign auto_int_out_0_0 = intnodeOut_0; // @[Plic.scala:132:9]
reg priority_0; // @[Plic.scala:167:31]
reg threshold_0; // @[Plic.scala:170:31]
wire _out_T_35 = threshold_0; // @[RegisterRouter.scala:87:24]
reg pending_0; // @[Plic.scala:172:26]
reg enables_0_0; // @[Plic.scala:178:26]
wire enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28]
wire [1:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52]
wire [1:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}]
reg maxDevs_0; // @[Plic.scala:185:22]
wire _fanin_io_ip_T = enableVec_0 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40]
reg intnodeOut_0_REG; // @[Plic.scala:193:45]
assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}]
assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60]
wire out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire claimer_0; // @[Plic.scala:250:23]
wire claiming = claimer_0 & maxDevs_0; // @[Plic.scala:185:22, :250:23, :252:49]
wire claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49]
wire [1:0] _claimedDevs_T = 2'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}]
wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27]
wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}]
wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27]
wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}]
wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18]
wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34]
wire _out_completer_0_T_2; // @[Plic.scala:301:35]
wire completer_0; // @[Plic.scala:267:25]
wire _out_completerDev_T; // @[package.scala:163:13]
wire completerDev; // @[Plic.scala:269:28]
wire completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49]
wire [1:0] _completedDevs_T = 2'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _completedDevs_T_1 = _completedDevs_T; // @[OneHot.scala:65:{12,27}]
wire [1:0] completedDevs = completer_0 ? _completedDevs_T_1 : 2'h0; // @[OneHot.scala:65:27]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire [22:0] out_findex = out_front_bits_index & 23'h7BF9FF; // @[RegisterRouter.scala:87:24]
wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF9FF; // @[RegisterRouter.scala:87:24]
wire _GEN = out_findex == 23'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_1 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_4 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_6 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_6 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = _out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = _out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_6 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_6 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = _out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = _out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_17 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_71 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_24 = out_prepend; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_rimask_T_3 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_wimask_T_3 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_romask_T_3 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_womask_T_3 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_37 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_42 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_1 = {1'h0, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_44 = {30'h0, out_prepend_1}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_45 = _out_T_44; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_2 = _out_T_45; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_4 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_4 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_4 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_4 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
assign claimer_0 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_46 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = _out_T_46[0]; // @[package.scala:163:13]
assign _out_completerDev_T = _out_T_46[0]; // @[package.scala:163:13]
wire _out_T_48 = completerDev == _out_T_47; // @[package.scala:163:13]
wire _out_T_50 = ~_out_T_49; // @[Plic.scala:298:19]
wire _out_T_51 = ~_out_T_48; // @[Plic.scala:298:{19,33}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_25 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_241
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_243
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_244
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_25( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_241 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_243 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_244 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_26 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
inst mulFullRaw of MulFullRawFN_26
connect mulFullRaw.io.a.sig, io.a.sig
connect mulFullRaw.io.a.sExp, io.a.sExp
connect mulFullRaw.io.a.sign, io.a.sign
connect mulFullRaw.io.a.isZero, io.a.isZero
connect mulFullRaw.io.a.isInf, io.a.isInf
connect mulFullRaw.io.a.isNaN, io.a.isNaN
connect mulFullRaw.io.b.sig, io.b.sig
connect mulFullRaw.io.b.sExp, io.b.sExp
connect mulFullRaw.io.b.sign, io.b.sign
connect mulFullRaw.io.b.isZero, io.b.isZero
connect mulFullRaw.io.b.isInf, io.b.isInf
connect mulFullRaw.io.b.isNaN, io.b.isNaN
connect io.invalidExc, mulFullRaw.io.invalidExc
connect io.rawOut, mulFullRaw.io.rawOut
node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22)
node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0)
node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1)
node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2)
connect io.rawOut.sig, _io_rawOut_sig_T_3 | module MulRawFN_26( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_26 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_890 = orr(a_set_wo_ready)
node _T_891 = eq(_T_890, UInt<1>(0h0))
node _T_892 = or(_T_889, _T_891)
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_892, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_101
node _T_896 = orr(inflight)
node _T_897 = eq(_T_896, UInt<1>(0h0))
node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_899 = or(_T_897, _T_898)
node _T_900 = lt(watchdog, plusarg_reader.out)
node _T_901 = or(_T_899, _T_900)
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_901, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_905 = and(io.in.a.ready, io.in.a.valid)
node _T_906 = and(io.in.d.ready, io.in.d.valid)
node _T_907 = or(_T_905, _T_906)
when _T_907 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_908 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_911 = and(_T_909, _T_910)
node _T_912 = and(_T_908, _T_911)
when _T_912 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_914 = and(_T_913, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_917 = and(_T_915, _T_916)
node _T_918 = and(_T_914, _T_917)
when _T_918 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_919 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_920 = bits(_T_919, 0, 0)
node _T_921 = eq(_T_920, UInt<1>(0h0))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_921, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_928 = and(io.in.d.ready, io.in.d.valid)
node _T_929 = and(_T_928, d_first_2)
node _T_930 = and(_T_929, UInt<1>(0h1))
node _T_931 = and(_T_930, d_release_ack_1)
when _T_931 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_932 = and(io.in.d.valid, d_first_2)
node _T_933 = and(_T_932, UInt<1>(0h1))
node _T_934 = and(_T_933, d_release_ack_1)
when _T_934 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_935 = dshr(inflight_1, io.in.d.bits.source)
node _T_936 = bits(_T_935, 0, 0)
node _T_937 = or(_T_936, same_cycle_resp_1)
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_937, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_941, UInt<1>(0h1), "") : assert_109
else :
node _T_945 = eq(io.in.d.bits.size, c_size_lookup)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_945, UInt<1>(0h1), "") : assert_110
node _T_949 = and(io.in.d.valid, d_first_2)
node _T_950 = and(_T_949, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_951 = and(_T_950, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_953 = and(_T_951, _T_952)
node _T_954 = and(_T_953, d_release_ack_1)
node _T_955 = eq(c_probe_ack, UInt<1>(0h0))
node _T_956 = and(_T_954, _T_955)
when _T_956 :
node _T_957 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_958 = or(_T_957, _WIRE_23.ready)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_958, UInt<1>(0h1), "") : assert_111
node _T_962 = orr(c_set_wo_ready)
when _T_962 :
node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_963, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_102
node _T_967 = orr(inflight_1)
node _T_968 = eq(_T_967, UInt<1>(0h0))
node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_970 = or(_T_968, _T_969)
node _T_971 = lt(watchdog_1, plusarg_reader_1.out)
node _T_972 = or(_T_970, _T_971)
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_972, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_977 = and(io.in.d.ready, io.in.d.valid)
node _T_978 = or(_T_976, _T_977)
when _T_978 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_50( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_905 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_905; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_905; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_978 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_978; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_978; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_978; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_905 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_978 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_949 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_949 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_931 = _T_978 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_931 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_931 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_931 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_48 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_48( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BTBBranchPredictorBank_1 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 4)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 4)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
wire s1_meta : { write_way : UInt<1>}
reg f3_meta_REG : { write_way : UInt<1>}, clock
connect f3_meta_REG, s1_meta
reg f3_meta : { write_way : UInt<1>}, clock
connect f3_meta, f3_meta_REG
connect io.f3_meta, f3_meta.write_way
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<7>(0h7f))
when _T :
connect doing_reset, UInt<1>(0h0)
smem meta_0 : UInt<30>[4] [128]
smem meta_1 : UInt<30>[4] [128]
smem btb_0 : UInt<14>[4] [128]
smem btb_1 : UInt<14>[4] [128]
smem ebtb : UInt<40> [128]
wire _s1_req_rbtb_WIRE : UInt<36>
invalidate _s1_req_rbtb_WIRE
when io.f0_valid :
connect _s1_req_rbtb_WIRE, s0_idx
node _s1_req_rbtb_T = bits(_s1_req_rbtb_WIRE, 6, 0)
read mport s1_req_rbtb_MPORT = btb_0[_s1_req_rbtb_T], clock
wire _s1_req_rbtb_WIRE_1 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_2 : UInt<14>
connect _s1_req_rbtb_WIRE_2, s1_req_rbtb_MPORT[0]
node _s1_req_rbtb_T_1 = bits(_s1_req_rbtb_WIRE_2, 0, 0)
connect _s1_req_rbtb_WIRE_1.extended, _s1_req_rbtb_T_1
node _s1_req_rbtb_T_2 = bits(_s1_req_rbtb_WIRE_2, 13, 1)
node _s1_req_rbtb_T_3 = asSInt(_s1_req_rbtb_T_2)
connect _s1_req_rbtb_WIRE_1.offset, _s1_req_rbtb_T_3
wire _s1_req_rbtb_WIRE_3 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_4 : UInt<14>
connect _s1_req_rbtb_WIRE_4, s1_req_rbtb_MPORT[1]
node _s1_req_rbtb_T_4 = bits(_s1_req_rbtb_WIRE_4, 0, 0)
connect _s1_req_rbtb_WIRE_3.extended, _s1_req_rbtb_T_4
node _s1_req_rbtb_T_5 = bits(_s1_req_rbtb_WIRE_4, 13, 1)
node _s1_req_rbtb_T_6 = asSInt(_s1_req_rbtb_T_5)
connect _s1_req_rbtb_WIRE_3.offset, _s1_req_rbtb_T_6
wire _s1_req_rbtb_WIRE_5 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_6 : UInt<14>
connect _s1_req_rbtb_WIRE_6, s1_req_rbtb_MPORT[2]
node _s1_req_rbtb_T_7 = bits(_s1_req_rbtb_WIRE_6, 0, 0)
connect _s1_req_rbtb_WIRE_5.extended, _s1_req_rbtb_T_7
node _s1_req_rbtb_T_8 = bits(_s1_req_rbtb_WIRE_6, 13, 1)
node _s1_req_rbtb_T_9 = asSInt(_s1_req_rbtb_T_8)
connect _s1_req_rbtb_WIRE_5.offset, _s1_req_rbtb_T_9
wire _s1_req_rbtb_WIRE_7 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_8 : UInt<14>
connect _s1_req_rbtb_WIRE_8, s1_req_rbtb_MPORT[3]
node _s1_req_rbtb_T_10 = bits(_s1_req_rbtb_WIRE_8, 0, 0)
connect _s1_req_rbtb_WIRE_7.extended, _s1_req_rbtb_T_10
node _s1_req_rbtb_T_11 = bits(_s1_req_rbtb_WIRE_8, 13, 1)
node _s1_req_rbtb_T_12 = asSInt(_s1_req_rbtb_T_11)
connect _s1_req_rbtb_WIRE_7.offset, _s1_req_rbtb_T_12
wire _s1_req_rbtb_WIRE_9 : { offset : SInt<13>, extended : UInt<1>}[4]
connect _s1_req_rbtb_WIRE_9[0].extended, _s1_req_rbtb_WIRE_1.extended
connect _s1_req_rbtb_WIRE_9[0].offset, _s1_req_rbtb_WIRE_1.offset
connect _s1_req_rbtb_WIRE_9[1].extended, _s1_req_rbtb_WIRE_3.extended
connect _s1_req_rbtb_WIRE_9[1].offset, _s1_req_rbtb_WIRE_3.offset
connect _s1_req_rbtb_WIRE_9[2].extended, _s1_req_rbtb_WIRE_5.extended
connect _s1_req_rbtb_WIRE_9[2].offset, _s1_req_rbtb_WIRE_5.offset
connect _s1_req_rbtb_WIRE_9[3].extended, _s1_req_rbtb_WIRE_7.extended
connect _s1_req_rbtb_WIRE_9[3].offset, _s1_req_rbtb_WIRE_7.offset
wire _s1_req_rbtb_WIRE_10 : UInt<36>
invalidate _s1_req_rbtb_WIRE_10
when io.f0_valid :
connect _s1_req_rbtb_WIRE_10, s0_idx
node _s1_req_rbtb_T_13 = bits(_s1_req_rbtb_WIRE_10, 6, 0)
read mport s1_req_rbtb_MPORT_1 = btb_1[_s1_req_rbtb_T_13], clock
wire _s1_req_rbtb_WIRE_11 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_12 : UInt<14>
connect _s1_req_rbtb_WIRE_12, s1_req_rbtb_MPORT_1[0]
node _s1_req_rbtb_T_14 = bits(_s1_req_rbtb_WIRE_12, 0, 0)
connect _s1_req_rbtb_WIRE_11.extended, _s1_req_rbtb_T_14
node _s1_req_rbtb_T_15 = bits(_s1_req_rbtb_WIRE_12, 13, 1)
node _s1_req_rbtb_T_16 = asSInt(_s1_req_rbtb_T_15)
connect _s1_req_rbtb_WIRE_11.offset, _s1_req_rbtb_T_16
wire _s1_req_rbtb_WIRE_13 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_14 : UInt<14>
connect _s1_req_rbtb_WIRE_14, s1_req_rbtb_MPORT_1[1]
node _s1_req_rbtb_T_17 = bits(_s1_req_rbtb_WIRE_14, 0, 0)
connect _s1_req_rbtb_WIRE_13.extended, _s1_req_rbtb_T_17
node _s1_req_rbtb_T_18 = bits(_s1_req_rbtb_WIRE_14, 13, 1)
node _s1_req_rbtb_T_19 = asSInt(_s1_req_rbtb_T_18)
connect _s1_req_rbtb_WIRE_13.offset, _s1_req_rbtb_T_19
wire _s1_req_rbtb_WIRE_15 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_16 : UInt<14>
connect _s1_req_rbtb_WIRE_16, s1_req_rbtb_MPORT_1[2]
node _s1_req_rbtb_T_20 = bits(_s1_req_rbtb_WIRE_16, 0, 0)
connect _s1_req_rbtb_WIRE_15.extended, _s1_req_rbtb_T_20
node _s1_req_rbtb_T_21 = bits(_s1_req_rbtb_WIRE_16, 13, 1)
node _s1_req_rbtb_T_22 = asSInt(_s1_req_rbtb_T_21)
connect _s1_req_rbtb_WIRE_15.offset, _s1_req_rbtb_T_22
wire _s1_req_rbtb_WIRE_17 : { offset : SInt<13>, extended : UInt<1>}
wire _s1_req_rbtb_WIRE_18 : UInt<14>
connect _s1_req_rbtb_WIRE_18, s1_req_rbtb_MPORT_1[3]
node _s1_req_rbtb_T_23 = bits(_s1_req_rbtb_WIRE_18, 0, 0)
connect _s1_req_rbtb_WIRE_17.extended, _s1_req_rbtb_T_23
node _s1_req_rbtb_T_24 = bits(_s1_req_rbtb_WIRE_18, 13, 1)
node _s1_req_rbtb_T_25 = asSInt(_s1_req_rbtb_T_24)
connect _s1_req_rbtb_WIRE_17.offset, _s1_req_rbtb_T_25
wire _s1_req_rbtb_WIRE_19 : { offset : SInt<13>, extended : UInt<1>}[4]
connect _s1_req_rbtb_WIRE_19[0].extended, _s1_req_rbtb_WIRE_11.extended
connect _s1_req_rbtb_WIRE_19[0].offset, _s1_req_rbtb_WIRE_11.offset
connect _s1_req_rbtb_WIRE_19[1].extended, _s1_req_rbtb_WIRE_13.extended
connect _s1_req_rbtb_WIRE_19[1].offset, _s1_req_rbtb_WIRE_13.offset
connect _s1_req_rbtb_WIRE_19[2].extended, _s1_req_rbtb_WIRE_15.extended
connect _s1_req_rbtb_WIRE_19[2].offset, _s1_req_rbtb_WIRE_15.offset
connect _s1_req_rbtb_WIRE_19[3].extended, _s1_req_rbtb_WIRE_17.extended
connect _s1_req_rbtb_WIRE_19[3].offset, _s1_req_rbtb_WIRE_17.offset
wire s1_req_rbtb : { offset : SInt<13>, extended : UInt<1>}[4][2]
connect s1_req_rbtb[0], _s1_req_rbtb_WIRE_9
connect s1_req_rbtb[1], _s1_req_rbtb_WIRE_19
wire _s1_req_rmeta_WIRE : UInt<36>
invalidate _s1_req_rmeta_WIRE
when io.f0_valid :
connect _s1_req_rmeta_WIRE, s0_idx
node _s1_req_rmeta_T = bits(_s1_req_rmeta_WIRE, 6, 0)
read mport s1_req_rmeta_MPORT = meta_0[_s1_req_rmeta_T], clock
wire _s1_req_rmeta_WIRE_1 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_2 : UInt<30>
connect _s1_req_rmeta_WIRE_2, s1_req_rmeta_MPORT[0]
node _s1_req_rmeta_T_1 = bits(_s1_req_rmeta_WIRE_2, 28, 0)
connect _s1_req_rmeta_WIRE_1.tag, _s1_req_rmeta_T_1
node _s1_req_rmeta_T_2 = bits(_s1_req_rmeta_WIRE_2, 29, 29)
connect _s1_req_rmeta_WIRE_1.is_br, _s1_req_rmeta_T_2
wire _s1_req_rmeta_WIRE_3 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_4 : UInt<30>
connect _s1_req_rmeta_WIRE_4, s1_req_rmeta_MPORT[1]
node _s1_req_rmeta_T_3 = bits(_s1_req_rmeta_WIRE_4, 28, 0)
connect _s1_req_rmeta_WIRE_3.tag, _s1_req_rmeta_T_3
node _s1_req_rmeta_T_4 = bits(_s1_req_rmeta_WIRE_4, 29, 29)
connect _s1_req_rmeta_WIRE_3.is_br, _s1_req_rmeta_T_4
wire _s1_req_rmeta_WIRE_5 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_6 : UInt<30>
connect _s1_req_rmeta_WIRE_6, s1_req_rmeta_MPORT[2]
node _s1_req_rmeta_T_5 = bits(_s1_req_rmeta_WIRE_6, 28, 0)
connect _s1_req_rmeta_WIRE_5.tag, _s1_req_rmeta_T_5
node _s1_req_rmeta_T_6 = bits(_s1_req_rmeta_WIRE_6, 29, 29)
connect _s1_req_rmeta_WIRE_5.is_br, _s1_req_rmeta_T_6
wire _s1_req_rmeta_WIRE_7 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_8 : UInt<30>
connect _s1_req_rmeta_WIRE_8, s1_req_rmeta_MPORT[3]
node _s1_req_rmeta_T_7 = bits(_s1_req_rmeta_WIRE_8, 28, 0)
connect _s1_req_rmeta_WIRE_7.tag, _s1_req_rmeta_T_7
node _s1_req_rmeta_T_8 = bits(_s1_req_rmeta_WIRE_8, 29, 29)
connect _s1_req_rmeta_WIRE_7.is_br, _s1_req_rmeta_T_8
wire _s1_req_rmeta_WIRE_9 : { is_br : UInt<1>, tag : UInt<29>}[4]
connect _s1_req_rmeta_WIRE_9[0].tag, _s1_req_rmeta_WIRE_1.tag
connect _s1_req_rmeta_WIRE_9[0].is_br, _s1_req_rmeta_WIRE_1.is_br
connect _s1_req_rmeta_WIRE_9[1].tag, _s1_req_rmeta_WIRE_3.tag
connect _s1_req_rmeta_WIRE_9[1].is_br, _s1_req_rmeta_WIRE_3.is_br
connect _s1_req_rmeta_WIRE_9[2].tag, _s1_req_rmeta_WIRE_5.tag
connect _s1_req_rmeta_WIRE_9[2].is_br, _s1_req_rmeta_WIRE_5.is_br
connect _s1_req_rmeta_WIRE_9[3].tag, _s1_req_rmeta_WIRE_7.tag
connect _s1_req_rmeta_WIRE_9[3].is_br, _s1_req_rmeta_WIRE_7.is_br
wire _s1_req_rmeta_WIRE_10 : UInt<36>
invalidate _s1_req_rmeta_WIRE_10
when io.f0_valid :
connect _s1_req_rmeta_WIRE_10, s0_idx
node _s1_req_rmeta_T_9 = bits(_s1_req_rmeta_WIRE_10, 6, 0)
read mport s1_req_rmeta_MPORT_1 = meta_1[_s1_req_rmeta_T_9], clock
wire _s1_req_rmeta_WIRE_11 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_12 : UInt<30>
connect _s1_req_rmeta_WIRE_12, s1_req_rmeta_MPORT_1[0]
node _s1_req_rmeta_T_10 = bits(_s1_req_rmeta_WIRE_12, 28, 0)
connect _s1_req_rmeta_WIRE_11.tag, _s1_req_rmeta_T_10
node _s1_req_rmeta_T_11 = bits(_s1_req_rmeta_WIRE_12, 29, 29)
connect _s1_req_rmeta_WIRE_11.is_br, _s1_req_rmeta_T_11
wire _s1_req_rmeta_WIRE_13 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_14 : UInt<30>
connect _s1_req_rmeta_WIRE_14, s1_req_rmeta_MPORT_1[1]
node _s1_req_rmeta_T_12 = bits(_s1_req_rmeta_WIRE_14, 28, 0)
connect _s1_req_rmeta_WIRE_13.tag, _s1_req_rmeta_T_12
node _s1_req_rmeta_T_13 = bits(_s1_req_rmeta_WIRE_14, 29, 29)
connect _s1_req_rmeta_WIRE_13.is_br, _s1_req_rmeta_T_13
wire _s1_req_rmeta_WIRE_15 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_16 : UInt<30>
connect _s1_req_rmeta_WIRE_16, s1_req_rmeta_MPORT_1[2]
node _s1_req_rmeta_T_14 = bits(_s1_req_rmeta_WIRE_16, 28, 0)
connect _s1_req_rmeta_WIRE_15.tag, _s1_req_rmeta_T_14
node _s1_req_rmeta_T_15 = bits(_s1_req_rmeta_WIRE_16, 29, 29)
connect _s1_req_rmeta_WIRE_15.is_br, _s1_req_rmeta_T_15
wire _s1_req_rmeta_WIRE_17 : { is_br : UInt<1>, tag : UInt<29>}
wire _s1_req_rmeta_WIRE_18 : UInt<30>
connect _s1_req_rmeta_WIRE_18, s1_req_rmeta_MPORT_1[3]
node _s1_req_rmeta_T_16 = bits(_s1_req_rmeta_WIRE_18, 28, 0)
connect _s1_req_rmeta_WIRE_17.tag, _s1_req_rmeta_T_16
node _s1_req_rmeta_T_17 = bits(_s1_req_rmeta_WIRE_18, 29, 29)
connect _s1_req_rmeta_WIRE_17.is_br, _s1_req_rmeta_T_17
wire _s1_req_rmeta_WIRE_19 : { is_br : UInt<1>, tag : UInt<29>}[4]
connect _s1_req_rmeta_WIRE_19[0].tag, _s1_req_rmeta_WIRE_11.tag
connect _s1_req_rmeta_WIRE_19[0].is_br, _s1_req_rmeta_WIRE_11.is_br
connect _s1_req_rmeta_WIRE_19[1].tag, _s1_req_rmeta_WIRE_13.tag
connect _s1_req_rmeta_WIRE_19[1].is_br, _s1_req_rmeta_WIRE_13.is_br
connect _s1_req_rmeta_WIRE_19[2].tag, _s1_req_rmeta_WIRE_15.tag
connect _s1_req_rmeta_WIRE_19[2].is_br, _s1_req_rmeta_WIRE_15.is_br
connect _s1_req_rmeta_WIRE_19[3].tag, _s1_req_rmeta_WIRE_17.tag
connect _s1_req_rmeta_WIRE_19[3].is_br, _s1_req_rmeta_WIRE_17.is_br
wire s1_req_rmeta : { is_br : UInt<1>, tag : UInt<29>}[4][2]
connect s1_req_rmeta[0], _s1_req_rmeta_WIRE_9
connect s1_req_rmeta[1], _s1_req_rmeta_WIRE_19
wire _s1_req_rebtb_WIRE : UInt<36>
invalidate _s1_req_rebtb_WIRE
when io.f0_valid :
connect _s1_req_rebtb_WIRE, s0_idx
node _s1_req_rebtb_T = bits(_s1_req_rebtb_WIRE, 6, 0)
read mport s1_req_rebtb = ebtb[_s1_req_rebtb_T], clock
node s1_req_tag = shr(s1_idx, 7)
wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4]
wire s1_is_br : UInt<1>[4]
wire s1_is_jal : UInt<1>[4]
node _s1_hit_ohs_T = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_1 = eq(s1_req_rmeta[0][0].tag, _s1_hit_ohs_T)
node _s1_hit_ohs_T_2 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_3 = eq(s1_req_rmeta[1][0].tag, _s1_hit_ohs_T_2)
wire _s1_hit_ohs_WIRE : UInt<1>[2]
connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1
connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3
node _s1_hit_ohs_T_4 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_5 = eq(s1_req_rmeta[0][1].tag, _s1_hit_ohs_T_4)
node _s1_hit_ohs_T_6 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_7 = eq(s1_req_rmeta[1][1].tag, _s1_hit_ohs_T_6)
wire _s1_hit_ohs_WIRE_1 : UInt<1>[2]
connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_5
connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_7
node _s1_hit_ohs_T_8 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_9 = eq(s1_req_rmeta[0][2].tag, _s1_hit_ohs_T_8)
node _s1_hit_ohs_T_10 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_11 = eq(s1_req_rmeta[1][2].tag, _s1_hit_ohs_T_10)
wire _s1_hit_ohs_WIRE_2 : UInt<1>[2]
connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_9
connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_11
node _s1_hit_ohs_T_12 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_13 = eq(s1_req_rmeta[0][3].tag, _s1_hit_ohs_T_12)
node _s1_hit_ohs_T_14 = bits(s1_req_tag, 28, 0)
node _s1_hit_ohs_T_15 = eq(s1_req_rmeta[1][3].tag, _s1_hit_ohs_T_14)
wire _s1_hit_ohs_WIRE_3 : UInt<1>[2]
connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_13
connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_15
wire s1_hit_ohs : UInt<1>[2][4]
connect s1_hit_ohs[0], _s1_hit_ohs_WIRE
connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1
connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2
connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3
node s1_hits_0 = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1])
node s1_hits_1 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1])
node s1_hits_2 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1])
node s1_hits_3 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1])
node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), UInt<1>(0h1))
node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), UInt<1>(0h1))
node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), UInt<1>(0h1))
node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), UInt<1>(0h1))
node _s1_resp_0_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_0_valid_T_1 = and(_s1_resp_0_valid_T, s1_valid)
node _s1_resp_0_valid_T_2 = and(_s1_resp_0_valid_T_1, s1_hits_0)
connect s1_resp[0].valid, _s1_resp_0_valid_T_2
node _s1_resp_0_bits_T = asSInt(s1_pc)
node _s1_resp_0_bits_T_1 = add(_s1_resp_0_bits_T, asSInt(UInt<1>(0h0)))
node _s1_resp_0_bits_T_2 = tail(_s1_resp_0_bits_T_1, 1)
node _s1_resp_0_bits_T_3 = asSInt(_s1_resp_0_bits_T_2)
node _s1_resp_0_bits_T_4 = add(_s1_resp_0_bits_T_3, s1_req_rbtb[s1_hit_ways_0][0].offset)
node _s1_resp_0_bits_T_5 = tail(_s1_resp_0_bits_T_4, 1)
node _s1_resp_0_bits_T_6 = asSInt(_s1_resp_0_bits_T_5)
node _s1_resp_0_bits_T_7 = asUInt(_s1_resp_0_bits_T_6)
node _s1_resp_0_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_0][0].extended, s1_req_rebtb, _s1_resp_0_bits_T_7)
connect s1_resp[0].bits, _s1_resp_0_bits_T_8
node _s1_is_br_0_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_0_T_1 = and(_s1_is_br_0_T, s1_resp[0].valid)
node _s1_is_br_0_T_2 = and(_s1_is_br_0_T_1, s1_req_rmeta[s1_hit_ways_0][0].is_br)
connect s1_is_br[0], _s1_is_br_0_T_2
node _s1_is_jal_0_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_0_T_1 = and(_s1_is_jal_0_T, s1_resp[0].valid)
node _s1_is_jal_0_T_2 = eq(s1_req_rmeta[s1_hit_ways_0][0].is_br, UInt<1>(0h0))
node _s1_is_jal_0_T_3 = and(_s1_is_jal_0_T_1, _s1_is_jal_0_T_2)
connect s1_is_jal[0], _s1_is_jal_0_T_3
connect io.resp.f2[0], io.resp_in[0].f2[0]
connect io.resp.f3[0], io.resp_in[0].f3[0]
reg REG : UInt<1>, clock
connect REG, s1_hits_0
when REG :
reg io_resp_f2_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_0_predicted_pc_REG, s1_resp[0]
connect io.resp.f2[0].predicted_pc, io_resp_f2_0_predicted_pc_REG
reg io_resp_f2_0_is_br_REG : UInt<1>, clock
connect io_resp_f2_0_is_br_REG, s1_is_br[0]
connect io.resp.f2[0].is_br, io_resp_f2_0_is_br_REG
reg io_resp_f2_0_is_jal_REG : UInt<1>, clock
connect io_resp_f2_0_is_jal_REG, s1_is_jal[0]
connect io.resp.f2[0].is_jal, io_resp_f2_0_is_jal_REG
reg REG_1 : UInt<1>, clock
connect REG_1, s1_is_jal[0]
when REG_1 :
connect io.resp.f2[0].taken, UInt<1>(0h1)
reg REG_2 : UInt<1>, clock
connect REG_2, s1_hits_0
reg REG_3 : UInt<1>, clock
connect REG_3, REG_2
when REG_3 :
reg io_resp_f3_0_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_0_predicted_pc_REG.bits, io.resp.f2[0].predicted_pc.bits
connect io_resp_f3_0_predicted_pc_REG.valid, io.resp.f2[0].predicted_pc.valid
connect io.resp.f3[0].predicted_pc, io_resp_f3_0_predicted_pc_REG
reg io_resp_f3_0_is_br_REG : UInt<1>, clock
connect io_resp_f3_0_is_br_REG, io.resp.f2[0].is_br
connect io.resp.f3[0].is_br, io_resp_f3_0_is_br_REG
reg io_resp_f3_0_is_jal_REG : UInt<1>, clock
connect io_resp_f3_0_is_jal_REG, io.resp.f2[0].is_jal
connect io.resp.f3[0].is_jal, io_resp_f3_0_is_jal_REG
reg REG_4 : UInt<1>, clock
connect REG_4, s1_is_jal[0]
reg REG_5 : UInt<1>, clock
connect REG_5, REG_4
when REG_5 :
connect io.resp.f3[0].taken, UInt<1>(0h1)
node _s1_resp_1_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_1_valid_T_1 = and(_s1_resp_1_valid_T, s1_valid)
node _s1_resp_1_valid_T_2 = and(_s1_resp_1_valid_T_1, s1_hits_1)
connect s1_resp[1].valid, _s1_resp_1_valid_T_2
node _s1_resp_1_bits_T = asSInt(s1_pc)
node _s1_resp_1_bits_T_1 = add(_s1_resp_1_bits_T, asSInt(UInt<3>(0h2)))
node _s1_resp_1_bits_T_2 = tail(_s1_resp_1_bits_T_1, 1)
node _s1_resp_1_bits_T_3 = asSInt(_s1_resp_1_bits_T_2)
node _s1_resp_1_bits_T_4 = add(_s1_resp_1_bits_T_3, s1_req_rbtb[s1_hit_ways_1][1].offset)
node _s1_resp_1_bits_T_5 = tail(_s1_resp_1_bits_T_4, 1)
node _s1_resp_1_bits_T_6 = asSInt(_s1_resp_1_bits_T_5)
node _s1_resp_1_bits_T_7 = asUInt(_s1_resp_1_bits_T_6)
node _s1_resp_1_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_1][1].extended, s1_req_rebtb, _s1_resp_1_bits_T_7)
connect s1_resp[1].bits, _s1_resp_1_bits_T_8
node _s1_is_br_1_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_1_T_1 = and(_s1_is_br_1_T, s1_resp[1].valid)
node _s1_is_br_1_T_2 = and(_s1_is_br_1_T_1, s1_req_rmeta[s1_hit_ways_1][1].is_br)
connect s1_is_br[1], _s1_is_br_1_T_2
node _s1_is_jal_1_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_1_T_1 = and(_s1_is_jal_1_T, s1_resp[1].valid)
node _s1_is_jal_1_T_2 = eq(s1_req_rmeta[s1_hit_ways_1][1].is_br, UInt<1>(0h0))
node _s1_is_jal_1_T_3 = and(_s1_is_jal_1_T_1, _s1_is_jal_1_T_2)
connect s1_is_jal[1], _s1_is_jal_1_T_3
connect io.resp.f2[1], io.resp_in[0].f2[1]
connect io.resp.f3[1], io.resp_in[0].f3[1]
reg REG_6 : UInt<1>, clock
connect REG_6, s1_hits_1
when REG_6 :
reg io_resp_f2_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_1_predicted_pc_REG, s1_resp[1]
connect io.resp.f2[1].predicted_pc, io_resp_f2_1_predicted_pc_REG
reg io_resp_f2_1_is_br_REG : UInt<1>, clock
connect io_resp_f2_1_is_br_REG, s1_is_br[1]
connect io.resp.f2[1].is_br, io_resp_f2_1_is_br_REG
reg io_resp_f2_1_is_jal_REG : UInt<1>, clock
connect io_resp_f2_1_is_jal_REG, s1_is_jal[1]
connect io.resp.f2[1].is_jal, io_resp_f2_1_is_jal_REG
reg REG_7 : UInt<1>, clock
connect REG_7, s1_is_jal[1]
when REG_7 :
connect io.resp.f2[1].taken, UInt<1>(0h1)
reg REG_8 : UInt<1>, clock
connect REG_8, s1_hits_1
reg REG_9 : UInt<1>, clock
connect REG_9, REG_8
when REG_9 :
reg io_resp_f3_1_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_1_predicted_pc_REG.bits, io.resp.f2[1].predicted_pc.bits
connect io_resp_f3_1_predicted_pc_REG.valid, io.resp.f2[1].predicted_pc.valid
connect io.resp.f3[1].predicted_pc, io_resp_f3_1_predicted_pc_REG
reg io_resp_f3_1_is_br_REG : UInt<1>, clock
connect io_resp_f3_1_is_br_REG, io.resp.f2[1].is_br
connect io.resp.f3[1].is_br, io_resp_f3_1_is_br_REG
reg io_resp_f3_1_is_jal_REG : UInt<1>, clock
connect io_resp_f3_1_is_jal_REG, io.resp.f2[1].is_jal
connect io.resp.f3[1].is_jal, io_resp_f3_1_is_jal_REG
reg REG_10 : UInt<1>, clock
connect REG_10, s1_is_jal[1]
reg REG_11 : UInt<1>, clock
connect REG_11, REG_10
when REG_11 :
connect io.resp.f3[1].taken, UInt<1>(0h1)
node _s1_resp_2_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_2_valid_T_1 = and(_s1_resp_2_valid_T, s1_valid)
node _s1_resp_2_valid_T_2 = and(_s1_resp_2_valid_T_1, s1_hits_2)
connect s1_resp[2].valid, _s1_resp_2_valid_T_2
node _s1_resp_2_bits_T = asSInt(s1_pc)
node _s1_resp_2_bits_T_1 = add(_s1_resp_2_bits_T, asSInt(UInt<4>(0h4)))
node _s1_resp_2_bits_T_2 = tail(_s1_resp_2_bits_T_1, 1)
node _s1_resp_2_bits_T_3 = asSInt(_s1_resp_2_bits_T_2)
node _s1_resp_2_bits_T_4 = add(_s1_resp_2_bits_T_3, s1_req_rbtb[s1_hit_ways_2][2].offset)
node _s1_resp_2_bits_T_5 = tail(_s1_resp_2_bits_T_4, 1)
node _s1_resp_2_bits_T_6 = asSInt(_s1_resp_2_bits_T_5)
node _s1_resp_2_bits_T_7 = asUInt(_s1_resp_2_bits_T_6)
node _s1_resp_2_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_2][2].extended, s1_req_rebtb, _s1_resp_2_bits_T_7)
connect s1_resp[2].bits, _s1_resp_2_bits_T_8
node _s1_is_br_2_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_2_T_1 = and(_s1_is_br_2_T, s1_resp[2].valid)
node _s1_is_br_2_T_2 = and(_s1_is_br_2_T_1, s1_req_rmeta[s1_hit_ways_2][2].is_br)
connect s1_is_br[2], _s1_is_br_2_T_2
node _s1_is_jal_2_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_2_T_1 = and(_s1_is_jal_2_T, s1_resp[2].valid)
node _s1_is_jal_2_T_2 = eq(s1_req_rmeta[s1_hit_ways_2][2].is_br, UInt<1>(0h0))
node _s1_is_jal_2_T_3 = and(_s1_is_jal_2_T_1, _s1_is_jal_2_T_2)
connect s1_is_jal[2], _s1_is_jal_2_T_3
connect io.resp.f2[2], io.resp_in[0].f2[2]
connect io.resp.f3[2], io.resp_in[0].f3[2]
reg REG_12 : UInt<1>, clock
connect REG_12, s1_hits_2
when REG_12 :
reg io_resp_f2_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_2_predicted_pc_REG, s1_resp[2]
connect io.resp.f2[2].predicted_pc, io_resp_f2_2_predicted_pc_REG
reg io_resp_f2_2_is_br_REG : UInt<1>, clock
connect io_resp_f2_2_is_br_REG, s1_is_br[2]
connect io.resp.f2[2].is_br, io_resp_f2_2_is_br_REG
reg io_resp_f2_2_is_jal_REG : UInt<1>, clock
connect io_resp_f2_2_is_jal_REG, s1_is_jal[2]
connect io.resp.f2[2].is_jal, io_resp_f2_2_is_jal_REG
reg REG_13 : UInt<1>, clock
connect REG_13, s1_is_jal[2]
when REG_13 :
connect io.resp.f2[2].taken, UInt<1>(0h1)
reg REG_14 : UInt<1>, clock
connect REG_14, s1_hits_2
reg REG_15 : UInt<1>, clock
connect REG_15, REG_14
when REG_15 :
reg io_resp_f3_2_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_2_predicted_pc_REG.bits, io.resp.f2[2].predicted_pc.bits
connect io_resp_f3_2_predicted_pc_REG.valid, io.resp.f2[2].predicted_pc.valid
connect io.resp.f3[2].predicted_pc, io_resp_f3_2_predicted_pc_REG
reg io_resp_f3_2_is_br_REG : UInt<1>, clock
connect io_resp_f3_2_is_br_REG, io.resp.f2[2].is_br
connect io.resp.f3[2].is_br, io_resp_f3_2_is_br_REG
reg io_resp_f3_2_is_jal_REG : UInt<1>, clock
connect io_resp_f3_2_is_jal_REG, io.resp.f2[2].is_jal
connect io.resp.f3[2].is_jal, io_resp_f3_2_is_jal_REG
reg REG_16 : UInt<1>, clock
connect REG_16, s1_is_jal[2]
reg REG_17 : UInt<1>, clock
connect REG_17, REG_16
when REG_17 :
connect io.resp.f3[2].taken, UInt<1>(0h1)
node _s1_resp_3_valid_T = eq(doing_reset, UInt<1>(0h0))
node _s1_resp_3_valid_T_1 = and(_s1_resp_3_valid_T, s1_valid)
node _s1_resp_3_valid_T_2 = and(_s1_resp_3_valid_T_1, s1_hits_3)
connect s1_resp[3].valid, _s1_resp_3_valid_T_2
node _s1_resp_3_bits_T = asSInt(s1_pc)
node _s1_resp_3_bits_T_1 = add(_s1_resp_3_bits_T, asSInt(UInt<4>(0h6)))
node _s1_resp_3_bits_T_2 = tail(_s1_resp_3_bits_T_1, 1)
node _s1_resp_3_bits_T_3 = asSInt(_s1_resp_3_bits_T_2)
node _s1_resp_3_bits_T_4 = add(_s1_resp_3_bits_T_3, s1_req_rbtb[s1_hit_ways_3][3].offset)
node _s1_resp_3_bits_T_5 = tail(_s1_resp_3_bits_T_4, 1)
node _s1_resp_3_bits_T_6 = asSInt(_s1_resp_3_bits_T_5)
node _s1_resp_3_bits_T_7 = asUInt(_s1_resp_3_bits_T_6)
node _s1_resp_3_bits_T_8 = mux(s1_req_rbtb[s1_hit_ways_3][3].extended, s1_req_rebtb, _s1_resp_3_bits_T_7)
connect s1_resp[3].bits, _s1_resp_3_bits_T_8
node _s1_is_br_3_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_br_3_T_1 = and(_s1_is_br_3_T, s1_resp[3].valid)
node _s1_is_br_3_T_2 = and(_s1_is_br_3_T_1, s1_req_rmeta[s1_hit_ways_3][3].is_br)
connect s1_is_br[3], _s1_is_br_3_T_2
node _s1_is_jal_3_T = eq(doing_reset, UInt<1>(0h0))
node _s1_is_jal_3_T_1 = and(_s1_is_jal_3_T, s1_resp[3].valid)
node _s1_is_jal_3_T_2 = eq(s1_req_rmeta[s1_hit_ways_3][3].is_br, UInt<1>(0h0))
node _s1_is_jal_3_T_3 = and(_s1_is_jal_3_T_1, _s1_is_jal_3_T_2)
connect s1_is_jal[3], _s1_is_jal_3_T_3
connect io.resp.f2[3], io.resp_in[0].f2[3]
connect io.resp.f3[3], io.resp_in[0].f3[3]
reg REG_18 : UInt<1>, clock
connect REG_18, s1_hits_3
when REG_18 :
reg io_resp_f2_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f2_3_predicted_pc_REG, s1_resp[3]
connect io.resp.f2[3].predicted_pc, io_resp_f2_3_predicted_pc_REG
reg io_resp_f2_3_is_br_REG : UInt<1>, clock
connect io_resp_f2_3_is_br_REG, s1_is_br[3]
connect io.resp.f2[3].is_br, io_resp_f2_3_is_br_REG
reg io_resp_f2_3_is_jal_REG : UInt<1>, clock
connect io_resp_f2_3_is_jal_REG, s1_is_jal[3]
connect io.resp.f2[3].is_jal, io_resp_f2_3_is_jal_REG
reg REG_19 : UInt<1>, clock
connect REG_19, s1_is_jal[3]
when REG_19 :
connect io.resp.f2[3].taken, UInt<1>(0h1)
reg REG_20 : UInt<1>, clock
connect REG_20, s1_hits_3
reg REG_21 : UInt<1>, clock
connect REG_21, REG_20
when REG_21 :
reg io_resp_f3_3_predicted_pc_REG : { valid : UInt<1>, bits : UInt<40>}, clock
connect io_resp_f3_3_predicted_pc_REG.bits, io.resp.f2[3].predicted_pc.bits
connect io_resp_f3_3_predicted_pc_REG.valid, io.resp.f2[3].predicted_pc.valid
connect io.resp.f3[3].predicted_pc, io_resp_f3_3_predicted_pc_REG
reg io_resp_f3_3_is_br_REG : UInt<1>, clock
connect io_resp_f3_3_is_br_REG, io.resp.f2[3].is_br
connect io.resp.f3[3].is_br, io_resp_f3_3_is_br_REG
reg io_resp_f3_3_is_jal_REG : UInt<1>, clock
connect io_resp_f3_3_is_jal_REG, io.resp.f2[3].is_jal
connect io.resp.f3[3].is_jal, io_resp_f3_3_is_jal_REG
reg REG_22 : UInt<1>, clock
connect REG_22, s1_is_jal[3]
reg REG_23 : UInt<1>, clock
connect REG_23, REG_22
when REG_23 :
connect io.resp.f3[3].taken, UInt<1>(0h1)
wire _alloc_way_r_metas_WIRE : UInt<29>[4]
connect _alloc_way_r_metas_WIRE[0], s1_req_rmeta[0][0].tag
connect _alloc_way_r_metas_WIRE[1], s1_req_rmeta[0][1].tag
connect _alloc_way_r_metas_WIRE[2], s1_req_rmeta[0][2].tag
connect _alloc_way_r_metas_WIRE[3], s1_req_rmeta[0][3].tag
wire _alloc_way_r_metas_WIRE_1 : UInt<29>[4]
connect _alloc_way_r_metas_WIRE_1[0], s1_req_rmeta[1][0].tag
connect _alloc_way_r_metas_WIRE_1[1], s1_req_rmeta[1][1].tag
connect _alloc_way_r_metas_WIRE_1[2], s1_req_rmeta[1][2].tag
connect _alloc_way_r_metas_WIRE_1[3], s1_req_rmeta[1][3].tag
wire _alloc_way_r_metas_WIRE_2 : UInt<29>[4][2]
connect _alloc_way_r_metas_WIRE_2[0], _alloc_way_r_metas_WIRE
connect _alloc_way_r_metas_WIRE_2[1], _alloc_way_r_metas_WIRE_1
node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_2[0][1], _alloc_way_r_metas_WIRE_2[0][0])
node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_2[0][3], _alloc_way_r_metas_WIRE_2[0][2])
node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo)
node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_2[1][1], _alloc_way_r_metas_WIRE_2[1][0])
node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_2[1][3], _alloc_way_r_metas_WIRE_2[1][2])
node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1)
node _alloc_way_r_metas_T_2 = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T)
node _alloc_way_r_metas_T_3 = bits(s1_req_tag, 28, 0)
node alloc_way_r_metas = cat(_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3)
node alloc_way_chunks_0 = bits(alloc_way_r_metas, 0, 0)
node alloc_way_chunks_1 = bits(alloc_way_r_metas, 1, 1)
node alloc_way_chunks_2 = bits(alloc_way_r_metas, 2, 2)
node alloc_way_chunks_3 = bits(alloc_way_r_metas, 3, 3)
node alloc_way_chunks_4 = bits(alloc_way_r_metas, 4, 4)
node alloc_way_chunks_5 = bits(alloc_way_r_metas, 5, 5)
node alloc_way_chunks_6 = bits(alloc_way_r_metas, 6, 6)
node alloc_way_chunks_7 = bits(alloc_way_r_metas, 7, 7)
node alloc_way_chunks_8 = bits(alloc_way_r_metas, 8, 8)
node alloc_way_chunks_9 = bits(alloc_way_r_metas, 9, 9)
node alloc_way_chunks_10 = bits(alloc_way_r_metas, 10, 10)
node alloc_way_chunks_11 = bits(alloc_way_r_metas, 11, 11)
node alloc_way_chunks_12 = bits(alloc_way_r_metas, 12, 12)
node alloc_way_chunks_13 = bits(alloc_way_r_metas, 13, 13)
node alloc_way_chunks_14 = bits(alloc_way_r_metas, 14, 14)
node alloc_way_chunks_15 = bits(alloc_way_r_metas, 15, 15)
node alloc_way_chunks_16 = bits(alloc_way_r_metas, 16, 16)
node alloc_way_chunks_17 = bits(alloc_way_r_metas, 17, 17)
node alloc_way_chunks_18 = bits(alloc_way_r_metas, 18, 18)
node alloc_way_chunks_19 = bits(alloc_way_r_metas, 19, 19)
node alloc_way_chunks_20 = bits(alloc_way_r_metas, 20, 20)
node alloc_way_chunks_21 = bits(alloc_way_r_metas, 21, 21)
node alloc_way_chunks_22 = bits(alloc_way_r_metas, 22, 22)
node alloc_way_chunks_23 = bits(alloc_way_r_metas, 23, 23)
node alloc_way_chunks_24 = bits(alloc_way_r_metas, 24, 24)
node alloc_way_chunks_25 = bits(alloc_way_r_metas, 25, 25)
node alloc_way_chunks_26 = bits(alloc_way_r_metas, 26, 26)
node alloc_way_chunks_27 = bits(alloc_way_r_metas, 27, 27)
node alloc_way_chunks_28 = bits(alloc_way_r_metas, 28, 28)
node alloc_way_chunks_29 = bits(alloc_way_r_metas, 29, 29)
node alloc_way_chunks_30 = bits(alloc_way_r_metas, 30, 30)
node alloc_way_chunks_31 = bits(alloc_way_r_metas, 31, 31)
node alloc_way_chunks_32 = bits(alloc_way_r_metas, 32, 32)
node alloc_way_chunks_33 = bits(alloc_way_r_metas, 33, 33)
node alloc_way_chunks_34 = bits(alloc_way_r_metas, 34, 34)
node alloc_way_chunks_35 = bits(alloc_way_r_metas, 35, 35)
node alloc_way_chunks_36 = bits(alloc_way_r_metas, 36, 36)
node alloc_way_chunks_37 = bits(alloc_way_r_metas, 37, 37)
node alloc_way_chunks_38 = bits(alloc_way_r_metas, 38, 38)
node alloc_way_chunks_39 = bits(alloc_way_r_metas, 39, 39)
node alloc_way_chunks_40 = bits(alloc_way_r_metas, 40, 40)
node alloc_way_chunks_41 = bits(alloc_way_r_metas, 41, 41)
node alloc_way_chunks_42 = bits(alloc_way_r_metas, 42, 42)
node alloc_way_chunks_43 = bits(alloc_way_r_metas, 43, 43)
node alloc_way_chunks_44 = bits(alloc_way_r_metas, 44, 44)
node alloc_way_chunks_45 = bits(alloc_way_r_metas, 45, 45)
node alloc_way_chunks_46 = bits(alloc_way_r_metas, 46, 46)
node alloc_way_chunks_47 = bits(alloc_way_r_metas, 47, 47)
node alloc_way_chunks_48 = bits(alloc_way_r_metas, 48, 48)
node alloc_way_chunks_49 = bits(alloc_way_r_metas, 49, 49)
node alloc_way_chunks_50 = bits(alloc_way_r_metas, 50, 50)
node alloc_way_chunks_51 = bits(alloc_way_r_metas, 51, 51)
node alloc_way_chunks_52 = bits(alloc_way_r_metas, 52, 52)
node alloc_way_chunks_53 = bits(alloc_way_r_metas, 53, 53)
node alloc_way_chunks_54 = bits(alloc_way_r_metas, 54, 54)
node alloc_way_chunks_55 = bits(alloc_way_r_metas, 55, 55)
node alloc_way_chunks_56 = bits(alloc_way_r_metas, 56, 56)
node alloc_way_chunks_57 = bits(alloc_way_r_metas, 57, 57)
node alloc_way_chunks_58 = bits(alloc_way_r_metas, 58, 58)
node alloc_way_chunks_59 = bits(alloc_way_r_metas, 59, 59)
node alloc_way_chunks_60 = bits(alloc_way_r_metas, 60, 60)
node alloc_way_chunks_61 = bits(alloc_way_r_metas, 61, 61)
node alloc_way_chunks_62 = bits(alloc_way_r_metas, 62, 62)
node alloc_way_chunks_63 = bits(alloc_way_r_metas, 63, 63)
node alloc_way_chunks_64 = bits(alloc_way_r_metas, 64, 64)
node alloc_way_chunks_65 = bits(alloc_way_r_metas, 65, 65)
node alloc_way_chunks_66 = bits(alloc_way_r_metas, 66, 66)
node alloc_way_chunks_67 = bits(alloc_way_r_metas, 67, 67)
node alloc_way_chunks_68 = bits(alloc_way_r_metas, 68, 68)
node alloc_way_chunks_69 = bits(alloc_way_r_metas, 69, 69)
node alloc_way_chunks_70 = bits(alloc_way_r_metas, 70, 70)
node alloc_way_chunks_71 = bits(alloc_way_r_metas, 71, 71)
node alloc_way_chunks_72 = bits(alloc_way_r_metas, 72, 72)
node alloc_way_chunks_73 = bits(alloc_way_r_metas, 73, 73)
node alloc_way_chunks_74 = bits(alloc_way_r_metas, 74, 74)
node alloc_way_chunks_75 = bits(alloc_way_r_metas, 75, 75)
node alloc_way_chunks_76 = bits(alloc_way_r_metas, 76, 76)
node alloc_way_chunks_77 = bits(alloc_way_r_metas, 77, 77)
node alloc_way_chunks_78 = bits(alloc_way_r_metas, 78, 78)
node alloc_way_chunks_79 = bits(alloc_way_r_metas, 79, 79)
node alloc_way_chunks_80 = bits(alloc_way_r_metas, 80, 80)
node alloc_way_chunks_81 = bits(alloc_way_r_metas, 81, 81)
node alloc_way_chunks_82 = bits(alloc_way_r_metas, 82, 82)
node alloc_way_chunks_83 = bits(alloc_way_r_metas, 83, 83)
node alloc_way_chunks_84 = bits(alloc_way_r_metas, 84, 84)
node alloc_way_chunks_85 = bits(alloc_way_r_metas, 85, 85)
node alloc_way_chunks_86 = bits(alloc_way_r_metas, 86, 86)
node alloc_way_chunks_87 = bits(alloc_way_r_metas, 87, 87)
node alloc_way_chunks_88 = bits(alloc_way_r_metas, 88, 88)
node alloc_way_chunks_89 = bits(alloc_way_r_metas, 89, 89)
node alloc_way_chunks_90 = bits(alloc_way_r_metas, 90, 90)
node alloc_way_chunks_91 = bits(alloc_way_r_metas, 91, 91)
node alloc_way_chunks_92 = bits(alloc_way_r_metas, 92, 92)
node alloc_way_chunks_93 = bits(alloc_way_r_metas, 93, 93)
node alloc_way_chunks_94 = bits(alloc_way_r_metas, 94, 94)
node alloc_way_chunks_95 = bits(alloc_way_r_metas, 95, 95)
node alloc_way_chunks_96 = bits(alloc_way_r_metas, 96, 96)
node alloc_way_chunks_97 = bits(alloc_way_r_metas, 97, 97)
node alloc_way_chunks_98 = bits(alloc_way_r_metas, 98, 98)
node alloc_way_chunks_99 = bits(alloc_way_r_metas, 99, 99)
node alloc_way_chunks_100 = bits(alloc_way_r_metas, 100, 100)
node alloc_way_chunks_101 = bits(alloc_way_r_metas, 101, 101)
node alloc_way_chunks_102 = bits(alloc_way_r_metas, 102, 102)
node alloc_way_chunks_103 = bits(alloc_way_r_metas, 103, 103)
node alloc_way_chunks_104 = bits(alloc_way_r_metas, 104, 104)
node alloc_way_chunks_105 = bits(alloc_way_r_metas, 105, 105)
node alloc_way_chunks_106 = bits(alloc_way_r_metas, 106, 106)
node alloc_way_chunks_107 = bits(alloc_way_r_metas, 107, 107)
node alloc_way_chunks_108 = bits(alloc_way_r_metas, 108, 108)
node alloc_way_chunks_109 = bits(alloc_way_r_metas, 109, 109)
node alloc_way_chunks_110 = bits(alloc_way_r_metas, 110, 110)
node alloc_way_chunks_111 = bits(alloc_way_r_metas, 111, 111)
node alloc_way_chunks_112 = bits(alloc_way_r_metas, 112, 112)
node alloc_way_chunks_113 = bits(alloc_way_r_metas, 113, 113)
node alloc_way_chunks_114 = bits(alloc_way_r_metas, 114, 114)
node alloc_way_chunks_115 = bits(alloc_way_r_metas, 115, 115)
node alloc_way_chunks_116 = bits(alloc_way_r_metas, 116, 116)
node alloc_way_chunks_117 = bits(alloc_way_r_metas, 117, 117)
node alloc_way_chunks_118 = bits(alloc_way_r_metas, 118, 118)
node alloc_way_chunks_119 = bits(alloc_way_r_metas, 119, 119)
node alloc_way_chunks_120 = bits(alloc_way_r_metas, 120, 120)
node alloc_way_chunks_121 = bits(alloc_way_r_metas, 121, 121)
node alloc_way_chunks_122 = bits(alloc_way_r_metas, 122, 122)
node alloc_way_chunks_123 = bits(alloc_way_r_metas, 123, 123)
node alloc_way_chunks_124 = bits(alloc_way_r_metas, 124, 124)
node alloc_way_chunks_125 = bits(alloc_way_r_metas, 125, 125)
node alloc_way_chunks_126 = bits(alloc_way_r_metas, 126, 126)
node alloc_way_chunks_127 = bits(alloc_way_r_metas, 127, 127)
node alloc_way_chunks_128 = bits(alloc_way_r_metas, 128, 128)
node alloc_way_chunks_129 = bits(alloc_way_r_metas, 129, 129)
node alloc_way_chunks_130 = bits(alloc_way_r_metas, 130, 130)
node alloc_way_chunks_131 = bits(alloc_way_r_metas, 131, 131)
node alloc_way_chunks_132 = bits(alloc_way_r_metas, 132, 132)
node alloc_way_chunks_133 = bits(alloc_way_r_metas, 133, 133)
node alloc_way_chunks_134 = bits(alloc_way_r_metas, 134, 134)
node alloc_way_chunks_135 = bits(alloc_way_r_metas, 135, 135)
node alloc_way_chunks_136 = bits(alloc_way_r_metas, 136, 136)
node alloc_way_chunks_137 = bits(alloc_way_r_metas, 137, 137)
node alloc_way_chunks_138 = bits(alloc_way_r_metas, 138, 138)
node alloc_way_chunks_139 = bits(alloc_way_r_metas, 139, 139)
node alloc_way_chunks_140 = bits(alloc_way_r_metas, 140, 140)
node alloc_way_chunks_141 = bits(alloc_way_r_metas, 141, 141)
node alloc_way_chunks_142 = bits(alloc_way_r_metas, 142, 142)
node alloc_way_chunks_143 = bits(alloc_way_r_metas, 143, 143)
node alloc_way_chunks_144 = bits(alloc_way_r_metas, 144, 144)
node alloc_way_chunks_145 = bits(alloc_way_r_metas, 145, 145)
node alloc_way_chunks_146 = bits(alloc_way_r_metas, 146, 146)
node alloc_way_chunks_147 = bits(alloc_way_r_metas, 147, 147)
node alloc_way_chunks_148 = bits(alloc_way_r_metas, 148, 148)
node alloc_way_chunks_149 = bits(alloc_way_r_metas, 149, 149)
node alloc_way_chunks_150 = bits(alloc_way_r_metas, 150, 150)
node alloc_way_chunks_151 = bits(alloc_way_r_metas, 151, 151)
node alloc_way_chunks_152 = bits(alloc_way_r_metas, 152, 152)
node alloc_way_chunks_153 = bits(alloc_way_r_metas, 153, 153)
node alloc_way_chunks_154 = bits(alloc_way_r_metas, 154, 154)
node alloc_way_chunks_155 = bits(alloc_way_r_metas, 155, 155)
node alloc_way_chunks_156 = bits(alloc_way_r_metas, 156, 156)
node alloc_way_chunks_157 = bits(alloc_way_r_metas, 157, 157)
node alloc_way_chunks_158 = bits(alloc_way_r_metas, 158, 158)
node alloc_way_chunks_159 = bits(alloc_way_r_metas, 159, 159)
node alloc_way_chunks_160 = bits(alloc_way_r_metas, 160, 160)
node alloc_way_chunks_161 = bits(alloc_way_r_metas, 161, 161)
node alloc_way_chunks_162 = bits(alloc_way_r_metas, 162, 162)
node alloc_way_chunks_163 = bits(alloc_way_r_metas, 163, 163)
node alloc_way_chunks_164 = bits(alloc_way_r_metas, 164, 164)
node alloc_way_chunks_165 = bits(alloc_way_r_metas, 165, 165)
node alloc_way_chunks_166 = bits(alloc_way_r_metas, 166, 166)
node alloc_way_chunks_167 = bits(alloc_way_r_metas, 167, 167)
node alloc_way_chunks_168 = bits(alloc_way_r_metas, 168, 168)
node alloc_way_chunks_169 = bits(alloc_way_r_metas, 169, 169)
node alloc_way_chunks_170 = bits(alloc_way_r_metas, 170, 170)
node alloc_way_chunks_171 = bits(alloc_way_r_metas, 171, 171)
node alloc_way_chunks_172 = bits(alloc_way_r_metas, 172, 172)
node alloc_way_chunks_173 = bits(alloc_way_r_metas, 173, 173)
node alloc_way_chunks_174 = bits(alloc_way_r_metas, 174, 174)
node alloc_way_chunks_175 = bits(alloc_way_r_metas, 175, 175)
node alloc_way_chunks_176 = bits(alloc_way_r_metas, 176, 176)
node alloc_way_chunks_177 = bits(alloc_way_r_metas, 177, 177)
node alloc_way_chunks_178 = bits(alloc_way_r_metas, 178, 178)
node alloc_way_chunks_179 = bits(alloc_way_r_metas, 179, 179)
node alloc_way_chunks_180 = bits(alloc_way_r_metas, 180, 180)
node alloc_way_chunks_181 = bits(alloc_way_r_metas, 181, 181)
node alloc_way_chunks_182 = bits(alloc_way_r_metas, 182, 182)
node alloc_way_chunks_183 = bits(alloc_way_r_metas, 183, 183)
node alloc_way_chunks_184 = bits(alloc_way_r_metas, 184, 184)
node alloc_way_chunks_185 = bits(alloc_way_r_metas, 185, 185)
node alloc_way_chunks_186 = bits(alloc_way_r_metas, 186, 186)
node alloc_way_chunks_187 = bits(alloc_way_r_metas, 187, 187)
node alloc_way_chunks_188 = bits(alloc_way_r_metas, 188, 188)
node alloc_way_chunks_189 = bits(alloc_way_r_metas, 189, 189)
node alloc_way_chunks_190 = bits(alloc_way_r_metas, 190, 190)
node alloc_way_chunks_191 = bits(alloc_way_r_metas, 191, 191)
node alloc_way_chunks_192 = bits(alloc_way_r_metas, 192, 192)
node alloc_way_chunks_193 = bits(alloc_way_r_metas, 193, 193)
node alloc_way_chunks_194 = bits(alloc_way_r_metas, 194, 194)
node alloc_way_chunks_195 = bits(alloc_way_r_metas, 195, 195)
node alloc_way_chunks_196 = bits(alloc_way_r_metas, 196, 196)
node alloc_way_chunks_197 = bits(alloc_way_r_metas, 197, 197)
node alloc_way_chunks_198 = bits(alloc_way_r_metas, 198, 198)
node alloc_way_chunks_199 = bits(alloc_way_r_metas, 199, 199)
node alloc_way_chunks_200 = bits(alloc_way_r_metas, 200, 200)
node alloc_way_chunks_201 = bits(alloc_way_r_metas, 201, 201)
node alloc_way_chunks_202 = bits(alloc_way_r_metas, 202, 202)
node alloc_way_chunks_203 = bits(alloc_way_r_metas, 203, 203)
node alloc_way_chunks_204 = bits(alloc_way_r_metas, 204, 204)
node alloc_way_chunks_205 = bits(alloc_way_r_metas, 205, 205)
node alloc_way_chunks_206 = bits(alloc_way_r_metas, 206, 206)
node alloc_way_chunks_207 = bits(alloc_way_r_metas, 207, 207)
node alloc_way_chunks_208 = bits(alloc_way_r_metas, 208, 208)
node alloc_way_chunks_209 = bits(alloc_way_r_metas, 209, 209)
node alloc_way_chunks_210 = bits(alloc_way_r_metas, 210, 210)
node alloc_way_chunks_211 = bits(alloc_way_r_metas, 211, 211)
node alloc_way_chunks_212 = bits(alloc_way_r_metas, 212, 212)
node alloc_way_chunks_213 = bits(alloc_way_r_metas, 213, 213)
node alloc_way_chunks_214 = bits(alloc_way_r_metas, 214, 214)
node alloc_way_chunks_215 = bits(alloc_way_r_metas, 215, 215)
node alloc_way_chunks_216 = bits(alloc_way_r_metas, 216, 216)
node alloc_way_chunks_217 = bits(alloc_way_r_metas, 217, 217)
node alloc_way_chunks_218 = bits(alloc_way_r_metas, 218, 218)
node alloc_way_chunks_219 = bits(alloc_way_r_metas, 219, 219)
node alloc_way_chunks_220 = bits(alloc_way_r_metas, 220, 220)
node alloc_way_chunks_221 = bits(alloc_way_r_metas, 221, 221)
node alloc_way_chunks_222 = bits(alloc_way_r_metas, 222, 222)
node alloc_way_chunks_223 = bits(alloc_way_r_metas, 223, 223)
node alloc_way_chunks_224 = bits(alloc_way_r_metas, 224, 224)
node alloc_way_chunks_225 = bits(alloc_way_r_metas, 225, 225)
node alloc_way_chunks_226 = bits(alloc_way_r_metas, 226, 226)
node alloc_way_chunks_227 = bits(alloc_way_r_metas, 227, 227)
node alloc_way_chunks_228 = bits(alloc_way_r_metas, 228, 228)
node alloc_way_chunks_229 = bits(alloc_way_r_metas, 229, 229)
node alloc_way_chunks_230 = bits(alloc_way_r_metas, 230, 230)
node alloc_way_chunks_231 = bits(alloc_way_r_metas, 231, 231)
node alloc_way_chunks_232 = bits(alloc_way_r_metas, 232, 232)
node alloc_way_chunks_233 = bits(alloc_way_r_metas, 233, 233)
node alloc_way_chunks_234 = bits(alloc_way_r_metas, 234, 234)
node alloc_way_chunks_235 = bits(alloc_way_r_metas, 235, 235)
node alloc_way_chunks_236 = bits(alloc_way_r_metas, 236, 236)
node alloc_way_chunks_237 = bits(alloc_way_r_metas, 237, 237)
node alloc_way_chunks_238 = bits(alloc_way_r_metas, 238, 238)
node alloc_way_chunks_239 = bits(alloc_way_r_metas, 239, 239)
node alloc_way_chunks_240 = bits(alloc_way_r_metas, 240, 240)
node alloc_way_chunks_241 = bits(alloc_way_r_metas, 241, 241)
node alloc_way_chunks_242 = bits(alloc_way_r_metas, 242, 242)
node alloc_way_chunks_243 = bits(alloc_way_r_metas, 243, 243)
node alloc_way_chunks_244 = bits(alloc_way_r_metas, 244, 244)
node alloc_way_chunks_245 = bits(alloc_way_r_metas, 245, 245)
node alloc_way_chunks_246 = bits(alloc_way_r_metas, 246, 246)
node alloc_way_chunks_247 = bits(alloc_way_r_metas, 247, 247)
node alloc_way_chunks_248 = bits(alloc_way_r_metas, 248, 248)
node alloc_way_chunks_249 = bits(alloc_way_r_metas, 249, 249)
node alloc_way_chunks_250 = bits(alloc_way_r_metas, 250, 250)
node alloc_way_chunks_251 = bits(alloc_way_r_metas, 251, 251)
node alloc_way_chunks_252 = bits(alloc_way_r_metas, 252, 252)
node alloc_way_chunks_253 = bits(alloc_way_r_metas, 253, 253)
node alloc_way_chunks_254 = bits(alloc_way_r_metas, 254, 254)
node alloc_way_chunks_255 = bits(alloc_way_r_metas, 255, 255)
node alloc_way_chunks_256 = bits(alloc_way_r_metas, 256, 256)
node alloc_way_chunks_257 = bits(alloc_way_r_metas, 257, 257)
node alloc_way_chunks_258 = bits(alloc_way_r_metas, 258, 258)
node alloc_way_chunks_259 = bits(alloc_way_r_metas, 259, 259)
node alloc_way_chunks_260 = bits(alloc_way_r_metas, 260, 260)
node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1)
node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2)
node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3)
node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4)
node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5)
node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6)
node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7)
node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8)
node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9)
node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10)
node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11)
node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12)
node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13)
node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14)
node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15)
node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16)
node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17)
node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18)
node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19)
node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20)
node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21)
node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22)
node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23)
node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24)
node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25)
node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26)
node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27)
node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28)
node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29)
node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30)
node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31)
node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32)
node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33)
node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34)
node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35)
node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36)
node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37)
node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38)
node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39)
node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40)
node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41)
node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42)
node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43)
node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44)
node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45)
node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46)
node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47)
node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48)
node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49)
node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50)
node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51)
node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52)
node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53)
node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54)
node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55)
node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56)
node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57)
node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58)
node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59)
node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60)
node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61)
node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62)
node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63)
node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64)
node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65)
node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66)
node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67)
node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68)
node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69)
node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70)
node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71)
node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72)
node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73)
node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74)
node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75)
node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76)
node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77)
node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78)
node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79)
node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80)
node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81)
node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82)
node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83)
node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84)
node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85)
node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86)
node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87)
node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88)
node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89)
node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90)
node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91)
node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92)
node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93)
node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94)
node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95)
node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96)
node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97)
node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98)
node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99)
node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100)
node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101)
node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102)
node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103)
node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104)
node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105)
node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106)
node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107)
node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108)
node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109)
node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110)
node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111)
node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112)
node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113)
node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114)
node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115)
node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116)
node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117)
node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118)
node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119)
node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120)
node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121)
node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122)
node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123)
node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124)
node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125)
node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126)
node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127)
node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128)
node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129)
node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130)
node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131)
node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132)
node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133)
node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134)
node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135)
node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136)
node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137)
node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138)
node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139)
node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140)
node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141)
node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142)
node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143)
node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144)
node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145)
node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146)
node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147)
node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148)
node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149)
node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150)
node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151)
node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152)
node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153)
node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154)
node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155)
node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156)
node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157)
node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158)
node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159)
node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160)
node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161)
node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162)
node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163)
node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164)
node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165)
node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166)
node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167)
node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168)
node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169)
node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170)
node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171)
node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172)
node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173)
node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174)
node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175)
node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176)
node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177)
node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178)
node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179)
node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180)
node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181)
node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182)
node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183)
node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184)
node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185)
node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186)
node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187)
node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188)
node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189)
node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190)
node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191)
node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192)
node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193)
node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194)
node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195)
node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196)
node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197)
node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198)
node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199)
node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200)
node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201)
node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202)
node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203)
node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204)
node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205)
node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206)
node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207)
node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208)
node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209)
node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210)
node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211)
node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212)
node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213)
node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214)
node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215)
node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216)
node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217)
node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218)
node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219)
node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220)
node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221)
node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222)
node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223)
node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224)
node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225)
node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226)
node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227)
node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228)
node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229)
node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230)
node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231)
node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232)
node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233)
node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234)
node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235)
node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236)
node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237)
node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238)
node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239)
node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240)
node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241)
node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242)
node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243)
node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244)
node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245)
node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246)
node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247)
node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248)
node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249)
node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250)
node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251)
node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252)
node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253)
node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254)
node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255)
node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256)
node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257)
node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258)
node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259)
node alloc_way = xor(_alloc_way_T_258, alloc_way_chunks_260)
node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1)
node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2)
node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3)
node _s1_meta_write_way_T_3 = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0])
node _s1_meta_write_way_T_4 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0])
node _s1_meta_write_way_T_5 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0])
node _s1_meta_write_way_T_6 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0])
node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4)
node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5)
node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6)
node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0)
node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1)
node _s1_meta_write_way_T_12 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), UInt<1>(0h1))
node _s1_meta_write_way_T_13 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_12, alloc_way)
connect s1_meta.write_way, _s1_meta_write_way_T_13
wire s1_update_meta : { write_way : UInt<1>}
wire _s1_update_meta_WIRE : UInt<1>
connect _s1_update_meta_WIRE, s1_update.bits.meta
node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 0, 0)
connect s1_update_meta.write_way, _s1_update_meta_T
node _max_offset_value_T = not(UInt<12>(0h0))
node _max_offset_value_T_1 = cat(UInt<1>(0h0), _max_offset_value_T)
node max_offset_value = asSInt(_max_offset_value_T_1)
node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0))
node min_offset_value = asSInt(_min_offset_value_T)
node _new_offset_value_T = asSInt(s1_update.bits.target)
node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1)
node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1)
node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1)
node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3)
node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4)
node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1)
node new_offset_value = asSInt(_new_offset_value_T_6)
node _offset_is_extended_T = gt(new_offset_value, max_offset_value)
node _offset_is_extended_T_1 = lt(new_offset_value, min_offset_value)
node offset_is_extended = or(_offset_is_extended_T, _offset_is_extended_T_1)
wire s1_update_wbtb_data : { offset : SInt<13>, extended : UInt<1>}
connect s1_update_wbtb_data.extended, offset_is_extended
connect s1_update_wbtb_data.offset, new_offset_value
node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits)
node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid)
node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken)
node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4)
node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0))
node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6)
node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0))
node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8)
node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask)
node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2)
node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0))
node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4)
node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0))
node _s1_update_wmeta_mask_T_7 = mux(s1_update.valid, UInt<4>(0hf), UInt<4>(0h0))
node _s1_update_wmeta_mask_T_8 = and(_s1_update_wmeta_mask_T_7, s1_update.bits.btb_mispredicts)
node _s1_update_wmeta_mask_T_9 = or(_s1_update_wmeta_mask_T_6, _s1_update_wmeta_mask_T_8)
node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_9)
wire s1_update_wmeta_data : { is_br : UInt<1>, tag : UInt<29>}[4]
node _s1_update_wmeta_data_0_tag_T = bits(s1_update.bits.btb_mispredicts, 0, 0)
node _s1_update_wmeta_data_0_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_0_tag_T_2 = mux(_s1_update_wmeta_data_0_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_0_tag_T_1)
connect s1_update_wmeta_data[0].tag, _s1_update_wmeta_data_0_tag_T_2
node _s1_update_wmeta_data_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0)
connect s1_update_wmeta_data[0].is_br, _s1_update_wmeta_data_0_is_br_T
node _s1_update_wmeta_data_1_tag_T = bits(s1_update.bits.btb_mispredicts, 1, 1)
node _s1_update_wmeta_data_1_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_1_tag_T_2 = mux(_s1_update_wmeta_data_1_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_1_tag_T_1)
connect s1_update_wmeta_data[1].tag, _s1_update_wmeta_data_1_tag_T_2
node _s1_update_wmeta_data_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1)
connect s1_update_wmeta_data[1].is_br, _s1_update_wmeta_data_1_is_br_T
node _s1_update_wmeta_data_2_tag_T = bits(s1_update.bits.btb_mispredicts, 2, 2)
node _s1_update_wmeta_data_2_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_2_tag_T_2 = mux(_s1_update_wmeta_data_2_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_2_tag_T_1)
connect s1_update_wmeta_data[2].tag, _s1_update_wmeta_data_2_tag_T_2
node _s1_update_wmeta_data_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2)
connect s1_update_wmeta_data[2].is_br, _s1_update_wmeta_data_2_is_br_T
node _s1_update_wmeta_data_3_tag_T = bits(s1_update.bits.btb_mispredicts, 3, 3)
node _s1_update_wmeta_data_3_tag_T_1 = shr(s1_update_idx, 7)
node _s1_update_wmeta_data_3_tag_T_2 = mux(_s1_update_wmeta_data_3_tag_T, UInt<1>(0h0), _s1_update_wmeta_data_3_tag_T_1)
connect s1_update_wmeta_data[3].tag, _s1_update_wmeta_data_3_tag_T_2
node _s1_update_wmeta_data_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3)
connect s1_update_wmeta_data[3].is_br, _s1_update_wmeta_data_3_is_br_T
node _T_1 = eq(s1_update_meta.write_way, UInt<1>(0h0))
node _T_2 = or(doing_reset, _T_1)
node _T_3 = or(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE : UInt<14>[4]
connect _WIRE[0], UInt<14>(0h0)
connect _WIRE[1], UInt<14>(0h0)
connect _WIRE[2], UInt<14>(0h0)
connect _WIRE[3], UInt<14>(0h0)
node _T_5 = asUInt(s1_update_wbtb_data.offset)
node _T_6 = cat(_T_5, s1_update_wbtb_data.extended)
node _T_7 = asUInt(s1_update_wbtb_data.offset)
node _T_8 = cat(_T_7, s1_update_wbtb_data.extended)
node _T_9 = asUInt(s1_update_wbtb_data.offset)
node _T_10 = cat(_T_9, s1_update_wbtb_data.extended)
node _T_11 = asUInt(s1_update_wbtb_data.offset)
node _T_12 = cat(_T_11, s1_update_wbtb_data.extended)
wire _WIRE_1 : UInt<14>[4]
connect _WIRE_1[0], _T_6
connect _WIRE_1[1], _T_8
connect _WIRE_1[2], _T_10
connect _WIRE_1[3], _T_12
node _T_13 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_14 = not(UInt<4>(0h0))
node _T_15 = mux(doing_reset, _T_14, s1_update_wbtb_mask)
node _T_16 = bits(_T_15, 0, 0)
node _T_17 = bits(_T_15, 1, 1)
node _T_18 = bits(_T_15, 2, 2)
node _T_19 = bits(_T_15, 3, 3)
node _T_20 = or(_T_4, UInt<7>(0h0))
node _T_21 = bits(_T_20, 6, 0)
write mport MPORT = btb_0[_T_21], clock
when _T_16 :
connect MPORT[0], _T_13[0]
when _T_17 :
connect MPORT[1], _T_13[1]
when _T_18 :
connect MPORT[2], _T_13[2]
when _T_19 :
connect MPORT[3], _T_13[3]
node _T_22 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE_2 : UInt<30>[4]
connect _WIRE_2[0], UInt<30>(0h0)
connect _WIRE_2[1], UInt<30>(0h0)
connect _WIRE_2[2], UInt<30>(0h0)
connect _WIRE_2[3], UInt<30>(0h0)
node _T_23 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag)
node _T_24 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag)
node _T_25 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag)
node _T_26 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag)
wire _WIRE_3 : UInt<30>[4]
connect _WIRE_3[0], _T_23
connect _WIRE_3[1], _T_24
connect _WIRE_3[2], _T_25
connect _WIRE_3[3], _T_26
node _T_27 = mux(doing_reset, _WIRE_2, _WIRE_3)
node _T_28 = not(UInt<4>(0h0))
node _T_29 = mux(doing_reset, _T_28, s1_update_wmeta_mask)
node _T_30 = bits(_T_29, 0, 0)
node _T_31 = bits(_T_29, 1, 1)
node _T_32 = bits(_T_29, 2, 2)
node _T_33 = bits(_T_29, 3, 3)
node _T_34 = or(_T_22, UInt<7>(0h0))
node _T_35 = bits(_T_34, 6, 0)
write mport MPORT_1 = meta_0[_T_35], clock
when _T_30 :
connect MPORT_1[0], _T_27[0]
when _T_31 :
connect MPORT_1[1], _T_27[1]
when _T_32 :
connect MPORT_1[2], _T_27[2]
when _T_33 :
connect MPORT_1[3], _T_27[3]
node _T_36 = eq(s1_update_meta.write_way, UInt<1>(0h1))
node _T_37 = or(doing_reset, _T_36)
node _T_38 = or(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE_4 : UInt<14>[4]
connect _WIRE_4[0], UInt<14>(0h0)
connect _WIRE_4[1], UInt<14>(0h0)
connect _WIRE_4[2], UInt<14>(0h0)
connect _WIRE_4[3], UInt<14>(0h0)
node _T_40 = asUInt(s1_update_wbtb_data.offset)
node _T_41 = cat(_T_40, s1_update_wbtb_data.extended)
node _T_42 = asUInt(s1_update_wbtb_data.offset)
node _T_43 = cat(_T_42, s1_update_wbtb_data.extended)
node _T_44 = asUInt(s1_update_wbtb_data.offset)
node _T_45 = cat(_T_44, s1_update_wbtb_data.extended)
node _T_46 = asUInt(s1_update_wbtb_data.offset)
node _T_47 = cat(_T_46, s1_update_wbtb_data.extended)
wire _WIRE_5 : UInt<14>[4]
connect _WIRE_5[0], _T_41
connect _WIRE_5[1], _T_43
connect _WIRE_5[2], _T_45
connect _WIRE_5[3], _T_47
node _T_48 = mux(doing_reset, _WIRE_4, _WIRE_5)
node _T_49 = not(UInt<4>(0h0))
node _T_50 = mux(doing_reset, _T_49, s1_update_wbtb_mask)
node _T_51 = bits(_T_50, 0, 0)
node _T_52 = bits(_T_50, 1, 1)
node _T_53 = bits(_T_50, 2, 2)
node _T_54 = bits(_T_50, 3, 3)
node _T_55 = or(_T_39, UInt<7>(0h0))
node _T_56 = bits(_T_55, 6, 0)
write mport MPORT_2 = btb_1[_T_56], clock
when _T_51 :
connect MPORT_2[0], _T_48[0]
when _T_52 :
connect MPORT_2[1], _T_48[1]
when _T_53 :
connect MPORT_2[2], _T_48[2]
when _T_54 :
connect MPORT_2[3], _T_48[3]
node _T_57 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE_6 : UInt<30>[4]
connect _WIRE_6[0], UInt<30>(0h0)
connect _WIRE_6[1], UInt<30>(0h0)
connect _WIRE_6[2], UInt<30>(0h0)
connect _WIRE_6[3], UInt<30>(0h0)
node _T_58 = cat(s1_update_wmeta_data[0].is_br, s1_update_wmeta_data[0].tag)
node _T_59 = cat(s1_update_wmeta_data[1].is_br, s1_update_wmeta_data[1].tag)
node _T_60 = cat(s1_update_wmeta_data[2].is_br, s1_update_wmeta_data[2].tag)
node _T_61 = cat(s1_update_wmeta_data[3].is_br, s1_update_wmeta_data[3].tag)
wire _WIRE_7 : UInt<30>[4]
connect _WIRE_7[0], _T_58
connect _WIRE_7[1], _T_59
connect _WIRE_7[2], _T_60
connect _WIRE_7[3], _T_61
node _T_62 = mux(doing_reset, _WIRE_6, _WIRE_7)
node _T_63 = not(UInt<4>(0h0))
node _T_64 = mux(doing_reset, _T_63, s1_update_wmeta_mask)
node _T_65 = bits(_T_64, 0, 0)
node _T_66 = bits(_T_64, 1, 1)
node _T_67 = bits(_T_64, 2, 2)
node _T_68 = bits(_T_64, 3, 3)
node _T_69 = or(_T_57, UInt<7>(0h0))
node _T_70 = bits(_T_69, 6, 0)
write mport MPORT_3 = meta_1[_T_70], clock
when _T_65 :
connect MPORT_3[0], _T_62[0]
when _T_66 :
connect MPORT_3[1], _T_62[1]
when _T_67 :
connect MPORT_3[2], _T_62[2]
when _T_68 :
connect MPORT_3[3], _T_62[3]
node _T_71 = neq(s1_update_wbtb_mask, UInt<1>(0h0))
node _T_72 = and(_T_71, offset_is_extended)
when _T_72 :
node _T_73 = or(s1_update_idx, UInt<7>(0h0))
node _T_74 = bits(_T_73, 6, 0)
write mport MPORT_4 = ebtb[_T_74], clock
connect MPORT_4, s1_update.bits.target | module BTBBranchPredictorBank_1( // @[btb.scala:23:7]
input clock, // @[btb.scala:23:7]
input reset, // @[btb.scala:23:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire [29:0] meta_1_MPORT_3_data_3; // @[btb.scala:183:12]
wire [29:0] meta_1_MPORT_3_data_2; // @[btb.scala:183:12]
wire [29:0] meta_1_MPORT_3_data_1; // @[btb.scala:183:12]
wire [29:0] meta_1_MPORT_3_data_0; // @[btb.scala:183:12]
wire [13:0] btb_1_MPORT_2_data_3; // @[btb.scala:172:12]
wire [13:0] btb_1_MPORT_2_data_2; // @[btb.scala:172:12]
wire [13:0] btb_1_MPORT_2_data_1; // @[btb.scala:172:12]
wire [13:0] btb_1_MPORT_2_data_0; // @[btb.scala:172:12]
wire [29:0] meta_0_MPORT_1_data_3; // @[btb.scala:183:12]
wire [29:0] meta_0_MPORT_1_data_2; // @[btb.scala:183:12]
wire [29:0] meta_0_MPORT_1_data_1; // @[btb.scala:183:12]
wire [29:0] meta_0_MPORT_1_data_0; // @[btb.scala:183:12]
wire [13:0] btb_0_MPORT_data_3; // @[btb.scala:172:12]
wire [13:0] btb_0_MPORT_data_2; // @[btb.scala:172:12]
wire [13:0] btb_0_MPORT_data_1; // @[btb.scala:172:12]
wire [13:0] btb_0_MPORT_data_0; // @[btb.scala:172:12]
wire _s1_update_meta_WIRE; // @[btb.scala:138:55]
wire _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:93]
wire [12:0] _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:93]
wire _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:93]
wire [39:0] _ebtb_R0_data; // @[btb.scala:67:29]
wire [55:0] _btb_1_R0_data; // @[btb.scala:66:47]
wire [55:0] _btb_0_R0_data; // @[btb.scala:66:47]
wire [119:0] _meta_1_R0_data; // @[btb.scala:65:47]
wire [119:0] _meta_0_R0_data; // @[btb.scala:65:47]
wire io_f0_valid_0 = io_f0_valid; // @[btb.scala:23:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[btb.scala:23:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[btb.scala:23:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[btb.scala:23:7]
wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[btb.scala:23:7]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[btb.scala:23:7]
wire io_f3_fire_0 = io_f3_fire; // @[btb.scala:23:7]
wire io_update_valid_0 = io_update_valid; // @[btb.scala:23:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[btb.scala:23:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[btb.scala:23:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[btb.scala:23:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[btb.scala:23:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[btb.scala:23:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[btb.scala:23:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[btb.scala:23:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[btb.scala:23:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[btb.scala:23:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[btb.scala:23:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[btb.scala:23:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[btb.scala:23:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[btb.scala:23:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[btb.scala:23:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[btb.scala:23:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[btb.scala:23:7]
wire [11:0] _max_offset_value_T = 12'hFFF; // @[btb.scala:140:35]
wire [12:0] _max_offset_value_T_1 = 13'hFFF; // @[btb.scala:140:{29,59}]
wire [12:0] max_offset_value = 13'hFFF; // @[btb.scala:140:59]
wire [12:0] _min_offset_value_T = 13'h1000; // @[btb.scala:141:{29,59}]
wire [12:0] min_offset_value = 13'h1000; // @[btb.scala:141:59]
wire io_f1_lhist = 1'h0; // @[btb.scala:23:7]
wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[btb.scala:23:7]
wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[btb.scala:23:7]
wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_0_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_0_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_0_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_1_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_1_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_1_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_2_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_2_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_2_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f2_3_taken_0; // @[btb.scala:23:7]
wire io_resp_f2_3_is_br_0; // @[btb.scala:23:7]
wire io_resp_f2_3_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_0_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_0_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_0_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_1_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_1_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_1_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_2_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_2_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_2_is_jal_0; // @[btb.scala:23:7]
wire io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7]
wire io_resp_f3_3_taken_0; // @[btb.scala:23:7]
wire io_resp_f3_3_is_br_0; // @[btb.scala:23:7]
wire io_resp_f3_3_is_jal_0; // @[btb.scala:23:7]
wire [119:0] io_f3_meta_0; // @[btb.scala:23:7]
wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rbtb_WIRE = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rbtb_WIRE_10 = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rmeta_WIRE = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rmeta_WIRE_10 = s0_idx; // @[frontend.scala:162:35]
wire [35:0] _s1_req_rebtb_WIRE = s0_idx; // @[frontend.scala:162:35]
reg [35:0] s1_idx; // @[predictor.scala:163:29]
reg [35:0] s2_idx; // @[predictor.scala:164:29]
reg [35:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_0_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_1_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_2_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_3_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [35:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
wire _s1_meta_write_way_T_13; // @[btb.scala:133:27]
wire s1_meta_write_way; // @[btb.scala:52:21]
reg f3_meta_REG_write_way; // @[btb.scala:53:32]
reg f3_meta_write_way; // @[btb.scala:53:24]
assign io_f3_meta_0 = {119'h0, f3_meta_write_way}; // @[btb.scala:23:7, :53:24, :56:14]
reg doing_reset; // @[btb.scala:60:28]
reg [6:0] reset_idx; // @[btb.scala:61:28]
wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[btb.scala:60:28, :61:28, :62:26]
wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[btb.scala:62:26]
wire [29:0] _s1_req_rmeta_WIRE_2 = _meta_0_R0_data[29:0]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_4 = _meta_0_R0_data[59:30]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_6 = _meta_0_R0_data[89:60]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_8 = _meta_0_R0_data[119:90]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_12 = _meta_1_R0_data[29:0]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_14 = _meta_1_R0_data[59:30]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_16 = _meta_1_R0_data[89:60]; // @[btb.scala:65:47, :74:93]
wire [29:0] _s1_req_rmeta_WIRE_18 = _meta_1_R0_data[119:90]; // @[btb.scala:65:47, :74:93]
wire [13:0] _s1_req_rbtb_WIRE_2 = _btb_0_R0_data[13:0]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_4 = _btb_0_R0_data[27:14]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_6 = _btb_0_R0_data[41:28]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_8 = _btb_0_R0_data[55:42]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_12 = _btb_1_R0_data[13:0]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_14 = _btb_1_R0_data[27:14]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_16 = _btb_1_R0_data[41:28]; // @[btb.scala:66:47, :73:93]
wire [13:0] _s1_req_rbtb_WIRE_18 = _btb_1_R0_data[55:42]; // @[btb.scala:66:47, :73:93]
wire [6:0] _s1_req_rbtb_T = _s1_req_rbtb_WIRE[6:0]; // @[btb.scala:73:59]
wire [12:0] _s1_req_rbtb_T_3; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_1; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_0_offset = _s1_req_rbtb_WIRE_1_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_0_extended = _s1_req_rbtb_WIRE_1_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_1 = _s1_req_rbtb_WIRE_2[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_1_extended = _s1_req_rbtb_T_1; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_2 = _s1_req_rbtb_WIRE_2[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_3 = _s1_req_rbtb_T_2; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_1_offset = _s1_req_rbtb_T_3; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_6; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_4; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_1_offset = _s1_req_rbtb_WIRE_3_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_1_extended = _s1_req_rbtb_WIRE_3_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_4 = _s1_req_rbtb_WIRE_4[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_3_extended = _s1_req_rbtb_T_4; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_5 = _s1_req_rbtb_WIRE_4[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_6 = _s1_req_rbtb_T_5; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_3_offset = _s1_req_rbtb_T_6; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_9; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_7; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_2_offset = _s1_req_rbtb_WIRE_5_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_2_extended = _s1_req_rbtb_WIRE_5_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_7 = _s1_req_rbtb_WIRE_6[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_5_extended = _s1_req_rbtb_T_7; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_8 = _s1_req_rbtb_WIRE_6[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_9 = _s1_req_rbtb_T_8; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_5_offset = _s1_req_rbtb_T_9; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_12; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_10; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_9_3_offset = _s1_req_rbtb_WIRE_7_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_9_3_extended = _s1_req_rbtb_WIRE_7_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_10 = _s1_req_rbtb_WIRE_8[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_7_extended = _s1_req_rbtb_T_10; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_11 = _s1_req_rbtb_WIRE_8[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_12 = _s1_req_rbtb_T_11; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_7_offset = _s1_req_rbtb_T_12; // @[btb.scala:73:93]
wire [12:0] s1_req_rbtb_0_0_offset = _s1_req_rbtb_WIRE_9_0_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_0_extended = _s1_req_rbtb_WIRE_9_0_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_0_1_offset = _s1_req_rbtb_WIRE_9_1_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_1_extended = _s1_req_rbtb_WIRE_9_1_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_0_2_offset = _s1_req_rbtb_WIRE_9_2_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_2_extended = _s1_req_rbtb_WIRE_9_2_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_0_3_offset = _s1_req_rbtb_WIRE_9_3_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_0_3_extended = _s1_req_rbtb_WIRE_9_3_extended; // @[btb.scala:73:{29,52}]
wire [6:0] _s1_req_rbtb_T_13 = _s1_req_rbtb_WIRE_10[6:0]; // @[btb.scala:73:59]
wire [12:0] _s1_req_rbtb_T_16; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_14; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_0_offset = _s1_req_rbtb_WIRE_11_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_0_extended = _s1_req_rbtb_WIRE_11_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_14 = _s1_req_rbtb_WIRE_12[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_11_extended = _s1_req_rbtb_T_14; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_15 = _s1_req_rbtb_WIRE_12[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_16 = _s1_req_rbtb_T_15; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_11_offset = _s1_req_rbtb_T_16; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_19; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_17; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_1_offset = _s1_req_rbtb_WIRE_13_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_1_extended = _s1_req_rbtb_WIRE_13_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_17 = _s1_req_rbtb_WIRE_14[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_13_extended = _s1_req_rbtb_T_17; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_18 = _s1_req_rbtb_WIRE_14[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_19 = _s1_req_rbtb_T_18; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_13_offset = _s1_req_rbtb_T_19; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_22; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_20; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_2_offset = _s1_req_rbtb_WIRE_15_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_2_extended = _s1_req_rbtb_WIRE_15_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_20 = _s1_req_rbtb_WIRE_16[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_15_extended = _s1_req_rbtb_T_20; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_21 = _s1_req_rbtb_WIRE_16[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_22 = _s1_req_rbtb_T_21; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_15_offset = _s1_req_rbtb_T_22; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_25; // @[btb.scala:73:93]
wire _s1_req_rbtb_T_23; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_WIRE_19_3_offset = _s1_req_rbtb_WIRE_17_offset; // @[btb.scala:73:{52,93}]
wire _s1_req_rbtb_WIRE_19_3_extended = _s1_req_rbtb_WIRE_17_extended; // @[btb.scala:73:{52,93}]
assign _s1_req_rbtb_T_23 = _s1_req_rbtb_WIRE_18[0]; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_17_extended = _s1_req_rbtb_T_23; // @[btb.scala:73:93]
wire [12:0] _s1_req_rbtb_T_24 = _s1_req_rbtb_WIRE_18[13:1]; // @[btb.scala:73:93]
assign _s1_req_rbtb_T_25 = _s1_req_rbtb_T_24; // @[btb.scala:73:93]
assign _s1_req_rbtb_WIRE_17_offset = _s1_req_rbtb_T_25; // @[btb.scala:73:93]
wire [12:0] s1_req_rbtb_1_0_offset = _s1_req_rbtb_WIRE_19_0_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_0_extended = _s1_req_rbtb_WIRE_19_0_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_1_1_offset = _s1_req_rbtb_WIRE_19_1_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_1_extended = _s1_req_rbtb_WIRE_19_1_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_1_2_offset = _s1_req_rbtb_WIRE_19_2_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_2_extended = _s1_req_rbtb_WIRE_19_2_extended; // @[btb.scala:73:{29,52}]
wire [12:0] s1_req_rbtb_1_3_offset = _s1_req_rbtb_WIRE_19_3_offset; // @[btb.scala:73:{29,52}]
wire s1_req_rbtb_1_3_extended = _s1_req_rbtb_WIRE_19_3_extended; // @[btb.scala:73:{29,52}]
wire [6:0] _s1_req_rmeta_T = _s1_req_rmeta_WIRE[6:0]; // @[btb.scala:74:60]
wire _s1_req_rmeta_T_2; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_1; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_0_is_br = _s1_req_rmeta_WIRE_1_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_0_tag = _s1_req_rmeta_WIRE_1_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_1 = _s1_req_rmeta_WIRE_2[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_1_tag = _s1_req_rmeta_T_1; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_2 = _s1_req_rmeta_WIRE_2[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_1_is_br = _s1_req_rmeta_T_2; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_4; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_3; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_1_is_br = _s1_req_rmeta_WIRE_3_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_1_tag = _s1_req_rmeta_WIRE_3_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_3 = _s1_req_rmeta_WIRE_4[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_3_tag = _s1_req_rmeta_T_3; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_4 = _s1_req_rmeta_WIRE_4[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_3_is_br = _s1_req_rmeta_T_4; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_6; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_5; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_2_is_br = _s1_req_rmeta_WIRE_5_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_2_tag = _s1_req_rmeta_WIRE_5_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_5 = _s1_req_rmeta_WIRE_6[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_5_tag = _s1_req_rmeta_T_5; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_6 = _s1_req_rmeta_WIRE_6[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_5_is_br = _s1_req_rmeta_T_6; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_8; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_7; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_9_3_is_br = _s1_req_rmeta_WIRE_7_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_9_3_tag = _s1_req_rmeta_WIRE_7_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_7 = _s1_req_rmeta_WIRE_8[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_7_tag = _s1_req_rmeta_T_7; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_8 = _s1_req_rmeta_WIRE_8[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_7_is_br = _s1_req_rmeta_T_8; // @[btb.scala:74:93]
wire s1_req_rmeta_0_0_is_br = _s1_req_rmeta_WIRE_9_0_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_0_tag = _s1_req_rmeta_WIRE_9_0_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_0_1_is_br = _s1_req_rmeta_WIRE_9_1_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_1_tag = _s1_req_rmeta_WIRE_9_1_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_0_2_is_br = _s1_req_rmeta_WIRE_9_2_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_2_tag = _s1_req_rmeta_WIRE_9_2_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_0_3_is_br = _s1_req_rmeta_WIRE_9_3_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_0_3_tag = _s1_req_rmeta_WIRE_9_3_tag; // @[btb.scala:74:{29,53}]
wire [6:0] _s1_req_rmeta_T_9 = _s1_req_rmeta_WIRE_10[6:0]; // @[btb.scala:74:60]
wire _s1_req_rmeta_T_11; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_10; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_0_is_br = _s1_req_rmeta_WIRE_11_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_0_tag = _s1_req_rmeta_WIRE_11_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_10 = _s1_req_rmeta_WIRE_12[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_11_tag = _s1_req_rmeta_T_10; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_11 = _s1_req_rmeta_WIRE_12[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_11_is_br = _s1_req_rmeta_T_11; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_13; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_12; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_1_is_br = _s1_req_rmeta_WIRE_13_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_1_tag = _s1_req_rmeta_WIRE_13_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_12 = _s1_req_rmeta_WIRE_14[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_13_tag = _s1_req_rmeta_T_12; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_13 = _s1_req_rmeta_WIRE_14[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_13_is_br = _s1_req_rmeta_T_13; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_15; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_14; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_2_is_br = _s1_req_rmeta_WIRE_15_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_2_tag = _s1_req_rmeta_WIRE_15_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_14 = _s1_req_rmeta_WIRE_16[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_15_tag = _s1_req_rmeta_T_14; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_15 = _s1_req_rmeta_WIRE_16[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_15_is_br = _s1_req_rmeta_T_15; // @[btb.scala:74:93]
wire _s1_req_rmeta_T_17; // @[btb.scala:74:93]
wire [28:0] _s1_req_rmeta_T_16; // @[btb.scala:74:93]
wire _s1_req_rmeta_WIRE_19_3_is_br = _s1_req_rmeta_WIRE_17_is_br; // @[btb.scala:74:{53,93}]
wire [28:0] _s1_req_rmeta_WIRE_19_3_tag = _s1_req_rmeta_WIRE_17_tag; // @[btb.scala:74:{53,93}]
assign _s1_req_rmeta_T_16 = _s1_req_rmeta_WIRE_18[28:0]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_17_tag = _s1_req_rmeta_T_16; // @[btb.scala:74:93]
assign _s1_req_rmeta_T_17 = _s1_req_rmeta_WIRE_18[29]; // @[btb.scala:74:93]
assign _s1_req_rmeta_WIRE_17_is_br = _s1_req_rmeta_T_17; // @[btb.scala:74:93]
wire s1_req_rmeta_1_0_is_br = _s1_req_rmeta_WIRE_19_0_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_0_tag = _s1_req_rmeta_WIRE_19_0_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_1_1_is_br = _s1_req_rmeta_WIRE_19_1_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_1_tag = _s1_req_rmeta_WIRE_19_1_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_1_2_is_br = _s1_req_rmeta_WIRE_19_2_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_2_tag = _s1_req_rmeta_WIRE_19_2_tag; // @[btb.scala:74:{29,53}]
wire s1_req_rmeta_1_3_is_br = _s1_req_rmeta_WIRE_19_3_is_br; // @[btb.scala:74:{29,53}]
wire [28:0] s1_req_rmeta_1_3_tag = _s1_req_rmeta_WIRE_19_3_tag; // @[btb.scala:74:{29,53}]
wire [28:0] _alloc_way_r_metas_WIRE_0 = s1_req_rmeta_0_0_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1 = s1_req_rmeta_0_1_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_2 = s1_req_rmeta_0_2_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_3 = s1_req_rmeta_0_3_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_0 = s1_req_rmeta_1_0_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_1 = s1_req_rmeta_1_1_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_2 = s1_req_rmeta_1_2_tag; // @[btb.scala:74:29, :123:62]
wire [28:0] _alloc_way_r_metas_WIRE_1_3 = s1_req_rmeta_1_3_tag; // @[btb.scala:74:29, :123:62]
wire [6:0] _s1_req_rebtb_T = _s1_req_rebtb_WIRE[6:0]; // @[btb.scala:75:31]
wire [28:0] s1_req_tag = s1_idx[35:7]; // @[predictor.scala:163:29]
wire [28:0] _s1_hit_ohs_T = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_2 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_4 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_6 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_8 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_10 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_12 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _s1_hit_ohs_T_14 = s1_req_tag; // @[btb.scala:76:29, :84:44]
wire [28:0] _alloc_way_r_metas_T_3 = s1_req_tag; // @[btb.scala:76:29, :123:98]
wire _s1_resp_0_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_0_bits_T_8; // @[btb.scala:94:28]
wire _s1_resp_1_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_1_bits_T_8; // @[btb.scala:94:28]
wire _s1_resp_2_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_2_bits_T_8; // @[btb.scala:94:28]
wire _s1_resp_3_valid_T_2; // @[btb.scala:93:50]
wire [39:0] _s1_resp_3_bits_T_8; // @[btb.scala:94:28]
wire s1_resp_0_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_0_bits; // @[btb.scala:78:23]
wire s1_resp_1_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_1_bits; // @[btb.scala:78:23]
wire s1_resp_2_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_2_bits; // @[btb.scala:78:23]
wire s1_resp_3_valid; // @[btb.scala:78:23]
wire [39:0] s1_resp_3_bits; // @[btb.scala:78:23]
wire _s1_is_br_0_T_2; // @[btb.scala:98:54]
wire _s1_is_br_1_T_2; // @[btb.scala:98:54]
wire _s1_is_br_2_T_2; // @[btb.scala:98:54]
wire _s1_is_br_3_T_2; // @[btb.scala:98:54]
wire s1_is_br_0; // @[btb.scala:79:23]
wire s1_is_br_1; // @[btb.scala:79:23]
wire s1_is_br_2; // @[btb.scala:79:23]
wire s1_is_br_3; // @[btb.scala:79:23]
wire _s1_is_jal_0_T_3; // @[btb.scala:99:54]
wire _s1_is_jal_1_T_3; // @[btb.scala:99:54]
wire _s1_is_jal_2_T_3; // @[btb.scala:99:54]
wire _s1_is_jal_3_T_3; // @[btb.scala:99:54]
wire s1_is_jal_0; // @[btb.scala:80:23]
wire s1_is_jal_1; // @[btb.scala:80:23]
wire s1_is_jal_2; // @[btb.scala:80:23]
wire s1_is_jal_3; // @[btb.scala:80:23]
wire _s1_hit_ohs_T_1 = s1_req_rmeta_0_0_tag == _s1_hit_ohs_T; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_3 = s1_req_rmeta_1_0_tag == _s1_hit_ohs_T_2; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[btb.scala:82:27, :83:12]
wire _s1_hit_ohs_T_5 = s1_req_rmeta_0_1_tag == _s1_hit_ohs_T_4; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_5; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_7 = s1_req_rmeta_1_1_tag == _s1_hit_ohs_T_6; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_7; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[btb.scala:82:27, :83:12]
wire _s1_hit_ohs_T_9 = s1_req_rmeta_0_2_tag == _s1_hit_ohs_T_8; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_9; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_11 = s1_req_rmeta_1_2_tag == _s1_hit_ohs_T_10; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_11; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[btb.scala:82:27, :83:12]
wire _s1_hit_ohs_T_13 = s1_req_rmeta_0_3_tag == _s1_hit_ohs_T_12; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_13; // @[btb.scala:83:12, :84:30]
wire _s1_hit_ohs_T_15 = s1_req_rmeta_1_3_tag == _s1_hit_ohs_T_14; // @[btb.scala:74:29, :84:{30,44}]
wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_15; // @[btb.scala:83:12, :84:30]
wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[btb.scala:82:27, :83:12]
wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[btb.scala:82:27, :83:12]
wire s1_hits_0 = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[btb.scala:82:27, :87:55]
wire s1_hits_1 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[btb.scala:82:27, :87:55]
wire s1_hits_2 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[btb.scala:82:27, :87:55]
wire s1_hits_3 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[btb.scala:82:27, :87:55]
wire s1_hit_ways_0 = ~s1_hit_ohs_0_0; // @[Mux.scala:50:70]
wire s1_hit_ways_1 = ~s1_hit_ohs_1_0; // @[Mux.scala:50:70]
wire s1_hit_ways_2 = ~s1_hit_ohs_2_0; // @[Mux.scala:50:70]
wire s1_hit_ways_3 = ~s1_hit_ohs_3_0; // @[Mux.scala:50:70]
wire _s1_resp_0_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_0_valid_T_1 = _s1_resp_0_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_0_valid_T_2 = _s1_resp_0_valid_T_1 & s1_hits_0; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_0_valid = _s1_resp_0_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_0_bits_T_1 = {_s1_resp_0_bits_T[39], _s1_resp_0_bits_T}; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_0_bits_T_2 = _s1_resp_0_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_0_bits_T_3 = _s1_resp_0_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN = s1_hit_ways_0 ? s1_req_rbtb_1_0_offset : s1_req_rbtb_0_0_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_0_bits_T_4 = {_s1_resp_0_bits_T_3[39], _s1_resp_0_bits_T_3} + {{28{_GEN[12]}}, _GEN}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_0_bits_T_5 = _s1_resp_0_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_0_bits_T_6 = _s1_resp_0_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_0_bits_T_7 = _s1_resp_0_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_0_bits_T_8 = (s1_hit_ways_0 ? s1_req_rbtb_1_0_extended : s1_req_rbtb_0_0_extended) ? _ebtb_R0_data : _s1_resp_0_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_0_bits = _s1_resp_0_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_0_T_1 = _s1_is_br_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_0 = s1_hit_ways_0 ? s1_req_rmeta_1_0_is_br : s1_req_rmeta_0_0_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_0_T_2 = _s1_is_br_0_T_1 & _GEN_0; // @[btb.scala:98:{34,54}]
assign s1_is_br_0 = _s1_is_br_0_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_0_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_0_T_1 = _s1_is_jal_0_T & s1_resp_0_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_0_T_2 = ~_GEN_0; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_0_T_3 = _s1_is_jal_0_T_1 & _s1_is_jal_0_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_0 = _s1_is_jal_0_T_3; // @[btb.scala:80:23, :99:54]
reg REG; // @[btb.scala:104:18]
reg io_resp_f2_0_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_0_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_0_predicted_pc_valid_0 = REG ? io_resp_f2_0_predicted_pc_REG_valid : io_resp_in_0_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_0_predicted_pc_bits_0 = REG ? io_resp_f2_0_predicted_pc_REG_bits : io_resp_in_0_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_0_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_0_is_br_0 = REG ? io_resp_f2_0_is_br_REG : io_resp_in_0_f2_0_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_0_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_0_is_jal_0 = REG ? io_resp_f2_0_is_jal_REG : io_resp_in_0_f2_0_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_1; // @[btb.scala:108:20]
assign io_resp_f2_0_taken_0 = REG & REG_1 | io_resp_in_0_f2_0_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_2; // @[btb.scala:112:26]
reg REG_3; // @[btb.scala:112:18]
reg io_resp_f3_0_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_0_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_0_predicted_pc_valid_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_valid : io_resp_in_0_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_0_predicted_pc_bits_0 = REG_3 ? io_resp_f3_0_predicted_pc_REG_bits : io_resp_in_0_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_0_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_0_is_br_0 = REG_3 ? io_resp_f3_0_is_br_REG : io_resp_in_0_f3_0_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_0_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_0_is_jal_0 = REG_3 ? io_resp_f3_0_is_jal_REG : io_resp_in_0_f3_0_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_4; // @[btb.scala:116:28]
reg REG_5; // @[btb.scala:116:20]
assign io_resp_f3_0_taken_0 = REG_3 & REG_5 | io_resp_in_0_f3_0_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire _s1_resp_1_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_1_valid_T_1 = _s1_resp_1_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_1_valid_T_2 = _s1_resp_1_valid_T_1 & s1_hits_1; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_1_valid = _s1_resp_1_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_1_bits_T_1 = {_s1_resp_1_bits_T[39], _s1_resp_1_bits_T} + 41'h2; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_1_bits_T_2 = _s1_resp_1_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_1_bits_T_3 = _s1_resp_1_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN_1 = s1_hit_ways_1 ? s1_req_rbtb_1_1_offset : s1_req_rbtb_0_1_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_1_bits_T_4 = {_s1_resp_1_bits_T_3[39], _s1_resp_1_bits_T_3} + {{28{_GEN_1[12]}}, _GEN_1}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_1_bits_T_5 = _s1_resp_1_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_1_bits_T_6 = _s1_resp_1_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_1_bits_T_7 = _s1_resp_1_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_1_bits_T_8 = (s1_hit_ways_1 ? s1_req_rbtb_1_1_extended : s1_req_rbtb_0_1_extended) ? _ebtb_R0_data : _s1_resp_1_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_1_bits = _s1_resp_1_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_1_T_1 = _s1_is_br_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_2 = s1_hit_ways_1 ? s1_req_rmeta_1_1_is_br : s1_req_rmeta_0_1_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_1_T_2 = _s1_is_br_1_T_1 & _GEN_2; // @[btb.scala:98:{34,54}]
assign s1_is_br_1 = _s1_is_br_1_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_1_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_1_T_1 = _s1_is_jal_1_T & s1_resp_1_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_1_T_2 = ~_GEN_2; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_1_T_3 = _s1_is_jal_1_T_1 & _s1_is_jal_1_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_1 = _s1_is_jal_1_T_3; // @[btb.scala:80:23, :99:54]
reg REG_6; // @[btb.scala:104:18]
reg io_resp_f2_1_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_1_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_1_predicted_pc_valid_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_valid : io_resp_in_0_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_1_predicted_pc_bits_0 = REG_6 ? io_resp_f2_1_predicted_pc_REG_bits : io_resp_in_0_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_1_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_1_is_br_0 = REG_6 ? io_resp_f2_1_is_br_REG : io_resp_in_0_f2_1_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_1_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_1_is_jal_0 = REG_6 ? io_resp_f2_1_is_jal_REG : io_resp_in_0_f2_1_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_7; // @[btb.scala:108:20]
assign io_resp_f2_1_taken_0 = REG_6 & REG_7 | io_resp_in_0_f2_1_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_8; // @[btb.scala:112:26]
reg REG_9; // @[btb.scala:112:18]
reg io_resp_f3_1_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_1_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_1_predicted_pc_valid_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_valid : io_resp_in_0_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_1_predicted_pc_bits_0 = REG_9 ? io_resp_f3_1_predicted_pc_REG_bits : io_resp_in_0_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_1_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_1_is_br_0 = REG_9 ? io_resp_f3_1_is_br_REG : io_resp_in_0_f3_1_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_1_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_1_is_jal_0 = REG_9 ? io_resp_f3_1_is_jal_REG : io_resp_in_0_f3_1_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_10; // @[btb.scala:116:28]
reg REG_11; // @[btb.scala:116:20]
assign io_resp_f3_1_taken_0 = REG_9 & REG_11 | io_resp_in_0_f3_1_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire _s1_resp_2_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_2_valid_T_1 = _s1_resp_2_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_2_valid_T_2 = _s1_resp_2_valid_T_1 & s1_hits_2; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_2_valid = _s1_resp_2_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_2_bits_T_1 = {_s1_resp_2_bits_T[39], _s1_resp_2_bits_T} + 41'h4; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_2_bits_T_2 = _s1_resp_2_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_2_bits_T_3 = _s1_resp_2_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN_3 = s1_hit_ways_2 ? s1_req_rbtb_1_2_offset : s1_req_rbtb_0_2_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_2_bits_T_4 = {_s1_resp_2_bits_T_3[39], _s1_resp_2_bits_T_3} + {{28{_GEN_3[12]}}, _GEN_3}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_2_bits_T_5 = _s1_resp_2_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_2_bits_T_6 = _s1_resp_2_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_2_bits_T_7 = _s1_resp_2_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_2_bits_T_8 = (s1_hit_ways_2 ? s1_req_rbtb_1_2_extended : s1_req_rbtb_0_2_extended) ? _ebtb_R0_data : _s1_resp_2_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_2_bits = _s1_resp_2_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_2_T_1 = _s1_is_br_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_4 = s1_hit_ways_2 ? s1_req_rmeta_1_2_is_br : s1_req_rmeta_0_2_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_2_T_2 = _s1_is_br_2_T_1 & _GEN_4; // @[btb.scala:98:{34,54}]
assign s1_is_br_2 = _s1_is_br_2_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_2_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_2_T_1 = _s1_is_jal_2_T & s1_resp_2_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_2_T_2 = ~_GEN_4; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_2_T_3 = _s1_is_jal_2_T_1 & _s1_is_jal_2_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_2 = _s1_is_jal_2_T_3; // @[btb.scala:80:23, :99:54]
reg REG_12; // @[btb.scala:104:18]
reg io_resp_f2_2_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_2_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_2_predicted_pc_valid_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_valid : io_resp_in_0_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_2_predicted_pc_bits_0 = REG_12 ? io_resp_f2_2_predicted_pc_REG_bits : io_resp_in_0_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_2_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_2_is_br_0 = REG_12 ? io_resp_f2_2_is_br_REG : io_resp_in_0_f2_2_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_2_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_2_is_jal_0 = REG_12 ? io_resp_f2_2_is_jal_REG : io_resp_in_0_f2_2_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_13; // @[btb.scala:108:20]
assign io_resp_f2_2_taken_0 = REG_12 & REG_13 | io_resp_in_0_f2_2_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_14; // @[btb.scala:112:26]
reg REG_15; // @[btb.scala:112:18]
reg io_resp_f3_2_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_2_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_2_predicted_pc_valid_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_valid : io_resp_in_0_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_2_predicted_pc_bits_0 = REG_15 ? io_resp_f3_2_predicted_pc_REG_bits : io_resp_in_0_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_2_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_2_is_br_0 = REG_15 ? io_resp_f3_2_is_br_REG : io_resp_in_0_f3_2_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_2_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_2_is_jal_0 = REG_15 ? io_resp_f3_2_is_jal_REG : io_resp_in_0_f3_2_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_16; // @[btb.scala:116:28]
reg REG_17; // @[btb.scala:116:20]
assign io_resp_f3_2_taken_0 = REG_15 & REG_17 | io_resp_in_0_f3_2_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire _s1_resp_3_valid_T = ~doing_reset; // @[btb.scala:60:28, :93:25]
wire _s1_resp_3_valid_T_1 = _s1_resp_3_valid_T & s1_valid; // @[predictor.scala:168:25]
assign _s1_resp_3_valid_T_2 = _s1_resp_3_valid_T_1 & s1_hits_3; // @[btb.scala:87:55, :93:{38,50}]
assign s1_resp_3_valid = _s1_resp_3_valid_T_2; // @[btb.scala:78:23, :93:50]
wire [40:0] _s1_resp_3_bits_T_1 = {_s1_resp_3_bits_T[39], _s1_resp_3_bits_T} + 41'h6; // @[btb.scala:97:{14,21}]
wire [39:0] _s1_resp_3_bits_T_2 = _s1_resp_3_bits_T_1[39:0]; // @[btb.scala:97:21]
wire [39:0] _s1_resp_3_bits_T_3 = _s1_resp_3_bits_T_2; // @[btb.scala:97:21]
wire [12:0] _GEN_5 = s1_hit_ways_3 ? s1_req_rbtb_1_3_offset : s1_req_rbtb_0_3_offset; // @[Mux.scala:50:70]
wire [40:0] _s1_resp_3_bits_T_4 = {_s1_resp_3_bits_T_3[39], _s1_resp_3_bits_T_3} + {{28{_GEN_5[12]}}, _GEN_5}; // @[btb.scala:97:{21,34}]
wire [39:0] _s1_resp_3_bits_T_5 = _s1_resp_3_bits_T_4[39:0]; // @[btb.scala:97:34]
wire [39:0] _s1_resp_3_bits_T_6 = _s1_resp_3_bits_T_5; // @[btb.scala:97:34]
wire [39:0] _s1_resp_3_bits_T_7 = _s1_resp_3_bits_T_6; // @[btb.scala:97:{34,54}]
assign _s1_resp_3_bits_T_8 = (s1_hit_ways_3 ? s1_req_rbtb_1_3_extended : s1_req_rbtb_0_3_extended) ? _ebtb_R0_data : _s1_resp_3_bits_T_7; // @[Mux.scala:50:70]
assign s1_resp_3_bits = _s1_resp_3_bits_T_8; // @[btb.scala:78:23, :94:28]
wire _s1_is_br_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :98:21]
wire _s1_is_br_3_T_1 = _s1_is_br_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :98:{21,34}]
wire _GEN_6 = s1_hit_ways_3 ? s1_req_rmeta_1_3_is_br : s1_req_rmeta_0_3_is_br; // @[Mux.scala:50:70]
assign _s1_is_br_3_T_2 = _s1_is_br_3_T_1 & _GEN_6; // @[btb.scala:98:{34,54}]
assign s1_is_br_3 = _s1_is_br_3_T_2; // @[btb.scala:79:23, :98:54]
wire _s1_is_jal_3_T = ~doing_reset; // @[btb.scala:60:28, :93:25, :99:21]
wire _s1_is_jal_3_T_1 = _s1_is_jal_3_T & s1_resp_3_valid; // @[btb.scala:78:23, :99:{21,34}]
wire _s1_is_jal_3_T_2 = ~_GEN_6; // @[btb.scala:98:54, :99:57]
assign _s1_is_jal_3_T_3 = _s1_is_jal_3_T_1 & _s1_is_jal_3_T_2; // @[btb.scala:99:{34,54,57}]
assign s1_is_jal_3 = _s1_is_jal_3_T_3; // @[btb.scala:80:23, :99:54]
reg REG_18; // @[btb.scala:104:18]
reg io_resp_f2_3_predicted_pc_REG_valid; // @[btb.scala:105:44]
reg [39:0] io_resp_f2_3_predicted_pc_REG_bits; // @[btb.scala:105:44]
assign io_resp_f2_3_predicted_pc_valid_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_valid : io_resp_in_0_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
assign io_resp_f2_3_predicted_pc_bits_0 = REG_18 ? io_resp_f2_3_predicted_pc_REG_bits : io_resp_in_0_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :105:{34,44}]
reg io_resp_f2_3_is_br_REG; // @[btb.scala:106:44]
assign io_resp_f2_3_is_br_0 = REG_18 ? io_resp_f2_3_is_br_REG : io_resp_in_0_f2_3_is_br_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :106:{34,44}]
reg io_resp_f2_3_is_jal_REG; // @[btb.scala:107:44]
assign io_resp_f2_3_is_jal_0 = REG_18 ? io_resp_f2_3_is_jal_REG : io_resp_in_0_f2_3_is_jal_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :107:{34,44}]
reg REG_19; // @[btb.scala:108:20]
assign io_resp_f2_3_taken_0 = REG_18 & REG_19 | io_resp_in_0_f2_3_taken_0; // @[btb.scala:23:7, :102:19, :104:{18,32}, :108:{20,36}, :109:34]
reg REG_20; // @[btb.scala:112:26]
reg REG_21; // @[btb.scala:112:18]
reg io_resp_f3_3_predicted_pc_REG_valid; // @[btb.scala:113:44]
reg [39:0] io_resp_f3_3_predicted_pc_REG_bits; // @[btb.scala:113:44]
assign io_resp_f3_3_predicted_pc_valid_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_valid : io_resp_in_0_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
assign io_resp_f3_3_predicted_pc_bits_0 = REG_21 ? io_resp_f3_3_predicted_pc_REG_bits : io_resp_in_0_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :113:{34,44}]
reg io_resp_f3_3_is_br_REG; // @[btb.scala:114:44]
assign io_resp_f3_3_is_br_0 = REG_21 ? io_resp_f3_3_is_br_REG : io_resp_in_0_f3_3_is_br_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :114:{34,44}]
reg io_resp_f3_3_is_jal_REG; // @[btb.scala:115:44]
assign io_resp_f3_3_is_jal_0 = REG_21 ? io_resp_f3_3_is_jal_REG : io_resp_in_0_f3_3_is_jal_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :115:{34,44}]
reg REG_22; // @[btb.scala:116:28]
reg REG_23; // @[btb.scala:116:20]
assign io_resp_f3_3_taken_0 = REG_21 & REG_23 | io_resp_in_0_f3_3_taken_0; // @[btb.scala:23:7, :103:19, :112:{18,41}, :116:{20,45}, :117:34]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_0 = _alloc_way_r_metas_WIRE_0; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_1 = _alloc_way_r_metas_WIRE_1; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_2 = _alloc_way_r_metas_WIRE_2; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_0_3 = _alloc_way_r_metas_WIRE_3; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[btb.scala:123:{30,62}]
wire [28:0] _alloc_way_r_metas_WIRE_2_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[btb.scala:123:{30,62}]
wire [57:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_2_0_1, _alloc_way_r_metas_WIRE_2_0_0}; // @[btb.scala:123:{30,80}]
wire [57:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_2_0_3, _alloc_way_r_metas_WIRE_2_0_2}; // @[btb.scala:123:{30,80}]
wire [115:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[btb.scala:123:80]
wire [57:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_2_1_1, _alloc_way_r_metas_WIRE_2_1_0}; // @[btb.scala:123:{30,80}]
wire [57:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_2_1_3, _alloc_way_r_metas_WIRE_2_1_2}; // @[btb.scala:123:{30,80}]
wire [115:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[btb.scala:123:80]
wire [231:0] _alloc_way_r_metas_T_2 = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[btb.scala:123:80]
wire [260:0] alloc_way_r_metas = {_alloc_way_r_metas_T_2, _alloc_way_r_metas_T_3}; // @[btb.scala:123:{22,80,98}]
wire alloc_way_chunks_0 = alloc_way_r_metas[0]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_1 = alloc_way_r_metas[1]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_2 = alloc_way_r_metas[2]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_3 = alloc_way_r_metas[3]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_4 = alloc_way_r_metas[4]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_5 = alloc_way_r_metas[5]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_6 = alloc_way_r_metas[6]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_7 = alloc_way_r_metas[7]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_8 = alloc_way_r_metas[8]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_9 = alloc_way_r_metas[9]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_10 = alloc_way_r_metas[10]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_11 = alloc_way_r_metas[11]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_12 = alloc_way_r_metas[12]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_13 = alloc_way_r_metas[13]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_14 = alloc_way_r_metas[14]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_15 = alloc_way_r_metas[15]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_16 = alloc_way_r_metas[16]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_17 = alloc_way_r_metas[17]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_18 = alloc_way_r_metas[18]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_19 = alloc_way_r_metas[19]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_20 = alloc_way_r_metas[20]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_21 = alloc_way_r_metas[21]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_22 = alloc_way_r_metas[22]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_23 = alloc_way_r_metas[23]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_24 = alloc_way_r_metas[24]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_25 = alloc_way_r_metas[25]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_26 = alloc_way_r_metas[26]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_27 = alloc_way_r_metas[27]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_28 = alloc_way_r_metas[28]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_29 = alloc_way_r_metas[29]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_30 = alloc_way_r_metas[30]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_31 = alloc_way_r_metas[31]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_32 = alloc_way_r_metas[32]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_33 = alloc_way_r_metas[33]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_34 = alloc_way_r_metas[34]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_35 = alloc_way_r_metas[35]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_36 = alloc_way_r_metas[36]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_37 = alloc_way_r_metas[37]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_38 = alloc_way_r_metas[38]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_39 = alloc_way_r_metas[39]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_40 = alloc_way_r_metas[40]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_41 = alloc_way_r_metas[41]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_42 = alloc_way_r_metas[42]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_43 = alloc_way_r_metas[43]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_44 = alloc_way_r_metas[44]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_45 = alloc_way_r_metas[45]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_46 = alloc_way_r_metas[46]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_47 = alloc_way_r_metas[47]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_48 = alloc_way_r_metas[48]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_49 = alloc_way_r_metas[49]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_50 = alloc_way_r_metas[50]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_51 = alloc_way_r_metas[51]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_52 = alloc_way_r_metas[52]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_53 = alloc_way_r_metas[53]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_54 = alloc_way_r_metas[54]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_55 = alloc_way_r_metas[55]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_56 = alloc_way_r_metas[56]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_57 = alloc_way_r_metas[57]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_58 = alloc_way_r_metas[58]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_59 = alloc_way_r_metas[59]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_60 = alloc_way_r_metas[60]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_61 = alloc_way_r_metas[61]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_62 = alloc_way_r_metas[62]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_63 = alloc_way_r_metas[63]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_64 = alloc_way_r_metas[64]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_65 = alloc_way_r_metas[65]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_66 = alloc_way_r_metas[66]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_67 = alloc_way_r_metas[67]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_68 = alloc_way_r_metas[68]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_69 = alloc_way_r_metas[69]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_70 = alloc_way_r_metas[70]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_71 = alloc_way_r_metas[71]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_72 = alloc_way_r_metas[72]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_73 = alloc_way_r_metas[73]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_74 = alloc_way_r_metas[74]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_75 = alloc_way_r_metas[75]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_76 = alloc_way_r_metas[76]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_77 = alloc_way_r_metas[77]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_78 = alloc_way_r_metas[78]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_79 = alloc_way_r_metas[79]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_80 = alloc_way_r_metas[80]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_81 = alloc_way_r_metas[81]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_82 = alloc_way_r_metas[82]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_83 = alloc_way_r_metas[83]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_84 = alloc_way_r_metas[84]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_85 = alloc_way_r_metas[85]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_86 = alloc_way_r_metas[86]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_87 = alloc_way_r_metas[87]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_88 = alloc_way_r_metas[88]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_89 = alloc_way_r_metas[89]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_90 = alloc_way_r_metas[90]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_91 = alloc_way_r_metas[91]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_92 = alloc_way_r_metas[92]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_93 = alloc_way_r_metas[93]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_94 = alloc_way_r_metas[94]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_95 = alloc_way_r_metas[95]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_96 = alloc_way_r_metas[96]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_97 = alloc_way_r_metas[97]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_98 = alloc_way_r_metas[98]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_99 = alloc_way_r_metas[99]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_100 = alloc_way_r_metas[100]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_101 = alloc_way_r_metas[101]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_102 = alloc_way_r_metas[102]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_103 = alloc_way_r_metas[103]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_104 = alloc_way_r_metas[104]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_105 = alloc_way_r_metas[105]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_106 = alloc_way_r_metas[106]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_107 = alloc_way_r_metas[107]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_108 = alloc_way_r_metas[108]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_109 = alloc_way_r_metas[109]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_110 = alloc_way_r_metas[110]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_111 = alloc_way_r_metas[111]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_112 = alloc_way_r_metas[112]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_113 = alloc_way_r_metas[113]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_114 = alloc_way_r_metas[114]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_115 = alloc_way_r_metas[115]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_116 = alloc_way_r_metas[116]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_117 = alloc_way_r_metas[117]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_118 = alloc_way_r_metas[118]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_119 = alloc_way_r_metas[119]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_120 = alloc_way_r_metas[120]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_121 = alloc_way_r_metas[121]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_122 = alloc_way_r_metas[122]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_123 = alloc_way_r_metas[123]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_124 = alloc_way_r_metas[124]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_125 = alloc_way_r_metas[125]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_126 = alloc_way_r_metas[126]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_127 = alloc_way_r_metas[127]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_128 = alloc_way_r_metas[128]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_129 = alloc_way_r_metas[129]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_130 = alloc_way_r_metas[130]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_131 = alloc_way_r_metas[131]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_132 = alloc_way_r_metas[132]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_133 = alloc_way_r_metas[133]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_134 = alloc_way_r_metas[134]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_135 = alloc_way_r_metas[135]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_136 = alloc_way_r_metas[136]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_137 = alloc_way_r_metas[137]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_138 = alloc_way_r_metas[138]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_139 = alloc_way_r_metas[139]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_140 = alloc_way_r_metas[140]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_141 = alloc_way_r_metas[141]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_142 = alloc_way_r_metas[142]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_143 = alloc_way_r_metas[143]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_144 = alloc_way_r_metas[144]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_145 = alloc_way_r_metas[145]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_146 = alloc_way_r_metas[146]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_147 = alloc_way_r_metas[147]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_148 = alloc_way_r_metas[148]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_149 = alloc_way_r_metas[149]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_150 = alloc_way_r_metas[150]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_151 = alloc_way_r_metas[151]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_152 = alloc_way_r_metas[152]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_153 = alloc_way_r_metas[153]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_154 = alloc_way_r_metas[154]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_155 = alloc_way_r_metas[155]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_156 = alloc_way_r_metas[156]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_157 = alloc_way_r_metas[157]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_158 = alloc_way_r_metas[158]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_159 = alloc_way_r_metas[159]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_160 = alloc_way_r_metas[160]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_161 = alloc_way_r_metas[161]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_162 = alloc_way_r_metas[162]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_163 = alloc_way_r_metas[163]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_164 = alloc_way_r_metas[164]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_165 = alloc_way_r_metas[165]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_166 = alloc_way_r_metas[166]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_167 = alloc_way_r_metas[167]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_168 = alloc_way_r_metas[168]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_169 = alloc_way_r_metas[169]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_170 = alloc_way_r_metas[170]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_171 = alloc_way_r_metas[171]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_172 = alloc_way_r_metas[172]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_173 = alloc_way_r_metas[173]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_174 = alloc_way_r_metas[174]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_175 = alloc_way_r_metas[175]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_176 = alloc_way_r_metas[176]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_177 = alloc_way_r_metas[177]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_178 = alloc_way_r_metas[178]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_179 = alloc_way_r_metas[179]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_180 = alloc_way_r_metas[180]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_181 = alloc_way_r_metas[181]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_182 = alloc_way_r_metas[182]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_183 = alloc_way_r_metas[183]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_184 = alloc_way_r_metas[184]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_185 = alloc_way_r_metas[185]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_186 = alloc_way_r_metas[186]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_187 = alloc_way_r_metas[187]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_188 = alloc_way_r_metas[188]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_189 = alloc_way_r_metas[189]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_190 = alloc_way_r_metas[190]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_191 = alloc_way_r_metas[191]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_192 = alloc_way_r_metas[192]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_193 = alloc_way_r_metas[193]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_194 = alloc_way_r_metas[194]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_195 = alloc_way_r_metas[195]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_196 = alloc_way_r_metas[196]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_197 = alloc_way_r_metas[197]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_198 = alloc_way_r_metas[198]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_199 = alloc_way_r_metas[199]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_200 = alloc_way_r_metas[200]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_201 = alloc_way_r_metas[201]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_202 = alloc_way_r_metas[202]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_203 = alloc_way_r_metas[203]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_204 = alloc_way_r_metas[204]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_205 = alloc_way_r_metas[205]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_206 = alloc_way_r_metas[206]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_207 = alloc_way_r_metas[207]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_208 = alloc_way_r_metas[208]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_209 = alloc_way_r_metas[209]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_210 = alloc_way_r_metas[210]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_211 = alloc_way_r_metas[211]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_212 = alloc_way_r_metas[212]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_213 = alloc_way_r_metas[213]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_214 = alloc_way_r_metas[214]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_215 = alloc_way_r_metas[215]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_216 = alloc_way_r_metas[216]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_217 = alloc_way_r_metas[217]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_218 = alloc_way_r_metas[218]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_219 = alloc_way_r_metas[219]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_220 = alloc_way_r_metas[220]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_221 = alloc_way_r_metas[221]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_222 = alloc_way_r_metas[222]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_223 = alloc_way_r_metas[223]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_224 = alloc_way_r_metas[224]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_225 = alloc_way_r_metas[225]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_226 = alloc_way_r_metas[226]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_227 = alloc_way_r_metas[227]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_228 = alloc_way_r_metas[228]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_229 = alloc_way_r_metas[229]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_230 = alloc_way_r_metas[230]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_231 = alloc_way_r_metas[231]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_232 = alloc_way_r_metas[232]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_233 = alloc_way_r_metas[233]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_234 = alloc_way_r_metas[234]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_235 = alloc_way_r_metas[235]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_236 = alloc_way_r_metas[236]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_237 = alloc_way_r_metas[237]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_238 = alloc_way_r_metas[238]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_239 = alloc_way_r_metas[239]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_240 = alloc_way_r_metas[240]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_241 = alloc_way_r_metas[241]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_242 = alloc_way_r_metas[242]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_243 = alloc_way_r_metas[243]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_244 = alloc_way_r_metas[244]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_245 = alloc_way_r_metas[245]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_246 = alloc_way_r_metas[246]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_247 = alloc_way_r_metas[247]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_248 = alloc_way_r_metas[248]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_249 = alloc_way_r_metas[249]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_250 = alloc_way_r_metas[250]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_251 = alloc_way_r_metas[251]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_252 = alloc_way_r_metas[252]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_253 = alloc_way_r_metas[253]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_254 = alloc_way_r_metas[254]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_255 = alloc_way_r_metas[255]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_256 = alloc_way_r_metas[256]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_257 = alloc_way_r_metas[257]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_258 = alloc_way_r_metas[258]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_259 = alloc_way_r_metas[259]; // @[btb.scala:123:22, :127:14]
wire alloc_way_chunks_260 = alloc_way_r_metas[260]; // @[btb.scala:123:22, :127:14]
wire _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[btb.scala:127:14, :129:20]
wire _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[btb.scala:127:14, :129:20]
wire alloc_way = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[btb.scala:127:14, :129:20]
wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[btb.scala:87:55, :133:44]
wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[btb.scala:87:55, :133:44]
wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[btb.scala:87:55, :133:44]
wire [1:0] _s1_meta_write_way_T_3 = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_4 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_5 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_6 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[btb.scala:82:27, :134:38]
wire [1:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[btb.scala:134:{38,54}]
wire [1:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[btb.scala:134:{38,54}]
wire [1:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[btb.scala:134:{38,54}]
wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_12 = ~_s1_meta_write_way_T_10; // @[OneHot.scala:48:45]
assign _s1_meta_write_way_T_13 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_12 : alloc_way; // @[Mux.scala:50:70]
assign s1_meta_write_way = _s1_meta_write_way_T_13; // @[btb.scala:52:21, :133:27]
wire _s1_update_meta_T; // @[btb.scala:138:55]
wire s1_update_meta_write_way; // @[btb.scala:138:55]
assign _s1_update_meta_T = _s1_update_meta_WIRE; // @[btb.scala:138:55]
assign _s1_update_meta_WIRE = s1_update_bits_meta[0]; // @[predictor.scala:184:30]
assign s1_update_meta_write_way = _s1_update_meta_T; // @[btb.scala:138:55]
wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:184:30]
wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:184:30]
wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[btb.scala:143:24]
wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[btb.scala:143:{24,62}]
wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[btb.scala:142:{49,56}, :143:62]
wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[btb.scala:142:56]
wire [39:0] new_offset_value = _new_offset_value_T_6; // @[btb.scala:142:56]
wire _offset_is_extended_T = $signed(new_offset_value) > 40'shFFF; // @[btb.scala:142:56, :144:46]
wire _offset_is_extended_T_1 = $signed(new_offset_value) < -40'sh1000; // @[btb.scala:142:56, :145:46]
wire offset_is_extended = _offset_is_extended_T | _offset_is_extended_T_1; // @[btb.scala:144:{46,65}, :145:46]
wire s1_update_wbtb_data_extended = offset_is_extended; // @[btb.scala:144:65, :148:34]
wire [12:0] s1_update_wbtb_data_offset; // @[btb.scala:148:34]
assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[btb.scala:142:56, :148:34, :150:32]
wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35]
wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:184:30]
wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
wire _GEN_7 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :184:30]
wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49]
assign _s1_update_wbtb_mask_T_3 = _GEN_7; // @[predictor.scala:96:49]
wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49]
assign _s1_update_wmeta_mask_T_1 = _GEN_7; // @[predictor.scala:96:49]
wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30]
wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}]
wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}]
wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26]
wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[btb.scala:152:{9,97}]
wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35]
wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:184:30]
wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30]
wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}]
wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}]
wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :184:30]
wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[btb.scala:155:{10,38}]
wire [3:0] _s1_update_wmeta_mask_T_7 = {4{s1_update_valid}}; // @[predictor.scala:184:30]
wire [3:0] _s1_update_wmeta_mask_T_8 = _s1_update_wmeta_mask_T_7 & s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
wire [3:0] _s1_update_wmeta_mask_T_9 = _s1_update_wmeta_mask_T_6 | _s1_update_wmeta_mask_T_8; // @[btb.scala:155:{10,74}, :156:40]
wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_9; // @[btb.scala:154:{52,78}, :155:74]
wire _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:162:43]
wire _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:162:43]
wire _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:162:43]
wire _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:163:62]
wire [28:0] _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:162:43]
wire s1_update_wmeta_data_0_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_0_tag; // @[btb.scala:159:34]
wire s1_update_wmeta_data_1_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_1_tag; // @[btb.scala:159:34]
wire s1_update_wmeta_data_2_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_2_tag; // @[btb.scala:159:34]
wire s1_update_wmeta_data_3_is_br; // @[btb.scala:159:34]
wire [28:0] s1_update_wmeta_data_3_tag; // @[btb.scala:159:34]
wire _s1_update_wmeta_data_0_tag_T = s1_update_bits_btb_mispredicts[0]; // @[predictor.scala:184:30]
wire [28:0] _s1_update_wmeta_data_0_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
wire [28:0] _s1_update_wmeta_data_1_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
wire [28:0] _s1_update_wmeta_data_2_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
wire [28:0] _s1_update_wmeta_data_3_tag_T_1 = s1_update_idx[35:7]; // @[predictor.scala:185:30]
assign _s1_update_wmeta_data_0_tag_T_2 = _s1_update_wmeta_data_0_tag_T ? 29'h0 : _s1_update_wmeta_data_0_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_0_tag = _s1_update_wmeta_data_0_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_0_is_br = _s1_update_wmeta_data_0_is_br_T; // @[btb.scala:159:34, :163:62]
wire _s1_update_wmeta_data_1_tag_T = s1_update_bits_btb_mispredicts[1]; // @[predictor.scala:184:30]
assign _s1_update_wmeta_data_1_tag_T_2 = _s1_update_wmeta_data_1_tag_T ? 29'h0 : _s1_update_wmeta_data_1_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_1_tag = _s1_update_wmeta_data_1_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_1_is_br = _s1_update_wmeta_data_1_is_br_T; // @[btb.scala:159:34, :163:62]
wire _s1_update_wmeta_data_2_tag_T = s1_update_bits_btb_mispredicts[2]; // @[predictor.scala:184:30]
assign _s1_update_wmeta_data_2_tag_T_2 = _s1_update_wmeta_data_2_tag_T ? 29'h0 : _s1_update_wmeta_data_2_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_2_tag = _s1_update_wmeta_data_2_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_2_is_br = _s1_update_wmeta_data_2_is_br_T; // @[btb.scala:159:34, :163:62]
wire _s1_update_wmeta_data_3_tag_T = s1_update_bits_btb_mispredicts[3]; // @[predictor.scala:184:30]
assign _s1_update_wmeta_data_3_tag_T_2 = _s1_update_wmeta_data_3_tag_T ? 29'h0 : _s1_update_wmeta_data_3_tag_T_1; // @[btb.scala:162:{43,74,98}]
assign s1_update_wmeta_data_3_tag = _s1_update_wmeta_data_3_tag_T_2; // @[btb.scala:159:34, :162:43]
assign _s1_update_wmeta_data_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30]
assign s1_update_wmeta_data_3_is_br = _s1_update_wmeta_data_3_is_br_T; // @[btb.scala:159:34, :163:62]
wire btb_0_MPORT_en = doing_reset | ~s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:{23,51}]
wire [6:0] _T_34 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30]
assign btb_0_MPORT_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_0_MPORT_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_0_MPORT_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_0_MPORT_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign meta_0_MPORT_1_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_0_MPORT_1_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_0_MPORT_1_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_0_MPORT_1_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
wire btb_1_MPORT_2_en = doing_reset | s1_update_meta_write_way; // @[btb.scala:60:28, :138:55, :167:23]
wire [6:0] _T_69 = doing_reset ? reset_idx : s1_update_idx[6:0]; // @[predictor.scala:185:30]
assign btb_1_MPORT_2_data_0 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_1_MPORT_2_data_1 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_1_MPORT_2_data_2 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign btb_1_MPORT_2_data_3 = doing_reset ? 14'h0 : {s1_update_wbtb_data_offset, s1_update_wbtb_data_extended}; // @[btb.scala:60:28, :148:34, :172:12, :174:61]
assign meta_1_MPORT_3_data_0 = doing_reset ? 30'h0 : {s1_update_wmeta_data_0_is_br, s1_update_wmeta_data_0_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_1_MPORT_3_data_1 = doing_reset ? 30'h0 : {s1_update_wmeta_data_1_is_br, s1_update_wmeta_data_1_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_1_MPORT_3_data_2 = doing_reset ? 30'h0 : {s1_update_wmeta_data_2_is_br, s1_update_wmeta_data_2_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
assign meta_1_MPORT_3_data_3 = doing_reset ? 30'h0 : {s1_update_wmeta_data_3_is_br, s1_update_wmeta_data_3_tag}; // @[btb.scala:60:28, :159:34, :183:12, :185:46]
always @(posedge clock) begin // @[btb.scala:23:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
f3_meta_REG_write_way <= s1_meta_write_way; // @[btb.scala:52:21, :53:32]
f3_meta_write_way <= f3_meta_REG_write_way; // @[btb.scala:53:{24,32}]
REG <= s1_hits_0; // @[btb.scala:87:55, :104:18]
io_resp_f2_0_predicted_pc_REG_valid <= s1_resp_0_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_0_predicted_pc_REG_bits <= s1_resp_0_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_0_is_br_REG <= s1_is_br_0; // @[btb.scala:79:23, :106:44]
io_resp_f2_0_is_jal_REG <= s1_is_jal_0; // @[btb.scala:80:23, :107:44]
REG_1 <= s1_is_jal_0; // @[btb.scala:80:23, :108:20]
REG_2 <= s1_hits_0; // @[btb.scala:87:55, :112:26]
REG_3 <= REG_2; // @[btb.scala:112:{18,26}]
io_resp_f3_0_predicted_pc_REG_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_0_predicted_pc_REG_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_0_is_br_REG <= io_resp_f2_0_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_0_is_jal_REG <= io_resp_f2_0_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_4 <= s1_is_jal_0; // @[btb.scala:80:23, :116:28]
REG_5 <= REG_4; // @[btb.scala:116:{20,28}]
REG_6 <= s1_hits_1; // @[btb.scala:87:55, :104:18]
io_resp_f2_1_predicted_pc_REG_valid <= s1_resp_1_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_1_predicted_pc_REG_bits <= s1_resp_1_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_1_is_br_REG <= s1_is_br_1; // @[btb.scala:79:23, :106:44]
io_resp_f2_1_is_jal_REG <= s1_is_jal_1; // @[btb.scala:80:23, :107:44]
REG_7 <= s1_is_jal_1; // @[btb.scala:80:23, :108:20]
REG_8 <= s1_hits_1; // @[btb.scala:87:55, :112:26]
REG_9 <= REG_8; // @[btb.scala:112:{18,26}]
io_resp_f3_1_predicted_pc_REG_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_1_predicted_pc_REG_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_1_is_br_REG <= io_resp_f2_1_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_1_is_jal_REG <= io_resp_f2_1_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_10 <= s1_is_jal_1; // @[btb.scala:80:23, :116:28]
REG_11 <= REG_10; // @[btb.scala:116:{20,28}]
REG_12 <= s1_hits_2; // @[btb.scala:87:55, :104:18]
io_resp_f2_2_predicted_pc_REG_valid <= s1_resp_2_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_2_predicted_pc_REG_bits <= s1_resp_2_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_2_is_br_REG <= s1_is_br_2; // @[btb.scala:79:23, :106:44]
io_resp_f2_2_is_jal_REG <= s1_is_jal_2; // @[btb.scala:80:23, :107:44]
REG_13 <= s1_is_jal_2; // @[btb.scala:80:23, :108:20]
REG_14 <= s1_hits_2; // @[btb.scala:87:55, :112:26]
REG_15 <= REG_14; // @[btb.scala:112:{18,26}]
io_resp_f3_2_predicted_pc_REG_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_2_predicted_pc_REG_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_2_is_br_REG <= io_resp_f2_2_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_2_is_jal_REG <= io_resp_f2_2_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_16 <= s1_is_jal_2; // @[btb.scala:80:23, :116:28]
REG_17 <= REG_16; // @[btb.scala:116:{20,28}]
REG_18 <= s1_hits_3; // @[btb.scala:87:55, :104:18]
io_resp_f2_3_predicted_pc_REG_valid <= s1_resp_3_valid; // @[btb.scala:78:23, :105:44]
io_resp_f2_3_predicted_pc_REG_bits <= s1_resp_3_bits; // @[btb.scala:78:23, :105:44]
io_resp_f2_3_is_br_REG <= s1_is_br_3; // @[btb.scala:79:23, :106:44]
io_resp_f2_3_is_jal_REG <= s1_is_jal_3; // @[btb.scala:80:23, :107:44]
REG_19 <= s1_is_jal_3; // @[btb.scala:80:23, :108:20]
REG_20 <= s1_hits_3; // @[btb.scala:87:55, :112:26]
REG_21 <= REG_20; // @[btb.scala:112:{18,26}]
io_resp_f3_3_predicted_pc_REG_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_3_predicted_pc_REG_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7, :113:44]
io_resp_f3_3_is_br_REG <= io_resp_f2_3_is_br_0; // @[btb.scala:23:7, :114:44]
io_resp_f3_3_is_jal_REG <= io_resp_f2_3_is_jal_0; // @[btb.scala:23:7, :115:44]
REG_22 <= s1_is_jal_3; // @[btb.scala:80:23, :116:28]
REG_23 <= REG_22; // @[btb.scala:116:{20,28}]
if (reset) begin // @[btb.scala:23:7]
doing_reset <= 1'h1; // @[btb.scala:60:28]
reset_idx <= 7'h0; // @[btb.scala:61:28]
end
else begin // @[btb.scala:23:7]
doing_reset <= reset_idx != 7'h7F & doing_reset; // @[btb.scala:60:28, :61:28, :63:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[btb.scala:61:28, :62:26]
end
always @(posedge)
meta_0_0 meta_0 ( // @[btb.scala:65:47]
.R0_addr (_s1_req_rmeta_T), // @[btb.scala:74:60]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_meta_0_R0_data),
.W0_addr (_T_34), // @[btb.scala:169:12]
.W0_en (btb_0_MPORT_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({meta_0_MPORT_1_data_3, meta_0_MPORT_1_data_2, meta_0_MPORT_1_data_1, meta_0_MPORT_1_data_0}), // @[btb.scala:65:47, :183:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12]
); // @[btb.scala:65:47]
meta_1_0 meta_1 ( // @[btb.scala:65:47]
.R0_addr (_s1_req_rmeta_T_9), // @[btb.scala:74:60]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_meta_1_R0_data),
.W0_addr (_T_69), // @[btb.scala:169:12]
.W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({meta_1_MPORT_3_data_3, meta_1_MPORT_3_data_2, meta_1_MPORT_3_data_1, meta_1_MPORT_3_data_0}), // @[btb.scala:65:47, :183:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wmeta_mask) // @[btb.scala:60:28, :154:78, :186:12]
); // @[btb.scala:65:47]
btb_0_0 btb_0 ( // @[btb.scala:66:47]
.R0_addr (_s1_req_rbtb_T), // @[btb.scala:73:59]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_btb_0_R0_data),
.W0_addr (_T_34), // @[btb.scala:169:12]
.W0_en (btb_0_MPORT_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({btb_0_MPORT_data_3, btb_0_MPORT_data_2, btb_0_MPORT_data_1, btb_0_MPORT_data_0}), // @[btb.scala:66:47, :172:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12]
); // @[btb.scala:66:47]
btb_1_0 btb_1 ( // @[btb.scala:66:47]
.R0_addr (_s1_req_rbtb_T_13), // @[btb.scala:73:59]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_btb_1_R0_data),
.W0_addr (_T_69), // @[btb.scala:169:12]
.W0_en (btb_1_MPORT_2_en), // @[btb.scala:167:23]
.W0_clk (clock),
.W0_data ({btb_1_MPORT_2_data_3, btb_1_MPORT_2_data_2, btb_1_MPORT_2_data_1, btb_1_MPORT_2_data_0}), // @[btb.scala:66:47, :172:12]
.W0_mask (doing_reset ? 4'hF : s1_update_wbtb_mask) // @[btb.scala:60:28, :151:58, :175:12]
); // @[btb.scala:66:47]
ebtb_0 ebtb ( // @[btb.scala:67:29]
.R0_addr (_s1_req_rebtb_T), // @[btb.scala:75:31]
.R0_en (io_f0_valid_0), // @[btb.scala:23:7]
.R0_clk (clock),
.R0_data (_ebtb_R0_data),
.W0_addr (s1_update_idx[6:0]), // @[predictor.scala:185:30]
.W0_en ((|s1_update_wbtb_mask) & offset_is_extended), // @[btb.scala:144:65, :151:58, :194:{29,37}]
.W0_clk (clock),
.W0_data (s1_update_bits_target) // @[predictor.scala:184:30]
); // @[btb.scala:67:29]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[btb.scala:23:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[btb.scala:23:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[btb.scala:23:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[btb.scala:23:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[btb.scala:23:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[btb.scala:23:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[btb.scala:23:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[btb.scala:23:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[btb.scala:23:7]
assign io_f3_meta = io_f3_meta_0; // @[btb.scala:23:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}}
wire _in_flight_WIRE : UInt<1>[10]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
connect _in_flight_WIRE[8], UInt<1>(0h0)
connect _in_flight_WIRE[9], UInt<1>(0h0)
regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_38 = and(_T_36, _T_37)
node _T_39 = or(_T_17, _T_24)
node _T_40 = or(_T_39, _T_31)
node _T_41 = or(_T_40, _T_38)
node _T_42 = or(_T_10, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_42, UInt<1>(0h1), "") : assert_2
node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_49 = and(_T_47, _T_48)
node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_63 = and(_T_61, _T_62)
node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_65 = and(_T_63, _T_64)
node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_70 = and(_T_68, _T_69)
node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_76 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_79 = and(_T_77, _T_78)
node _T_80 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_83 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_84 = and(_T_82, _T_83)
node _T_85 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_86 = and(_T_84, _T_85)
node _T_87 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_90 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_91 = and(_T_89, _T_90)
node _T_92 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_97 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_98 = and(_T_96, _T_97)
node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_100 = and(_T_98, _T_99)
node _T_101 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_102 = and(_T_100, _T_101)
node _T_103 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_104 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_105 = and(_T_103, _T_104)
node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_107 = and(_T_105, _T_106)
node _T_108 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_109 = and(_T_107, _T_108)
node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_111 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_112 = and(_T_110, _T_111)
node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_114 = and(_T_112, _T_113)
node _T_115 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_116 = and(_T_114, _T_115)
node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_118 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_121 = and(_T_119, _T_120)
node _T_122 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_123 = and(_T_121, _T_122)
node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_125 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_132 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_139 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_142 = and(_T_140, _T_141)
node _T_143 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_146 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4))
node _T_149 = and(_T_147, _T_148)
node _T_150 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_151 = and(_T_149, _T_150)
node _T_152 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_153 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_156 = and(_T_154, _T_155)
node _T_157 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_160 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_163 = and(_T_161, _T_162)
node _T_164 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_165 = and(_T_163, _T_164)
node _T_166 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_167 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_170 = and(_T_168, _T_169)
node _T_171 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_172 = and(_T_170, _T_171)
node _T_173 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_174 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_179 = and(_T_177, _T_178)
node _T_180 = or(_T_53, _T_60)
node _T_181 = or(_T_180, _T_67)
node _T_182 = or(_T_181, _T_74)
node _T_183 = or(_T_182, _T_81)
node _T_184 = or(_T_183, _T_88)
node _T_185 = or(_T_184, _T_95)
node _T_186 = or(_T_185, _T_102)
node _T_187 = or(_T_186, _T_109)
node _T_188 = or(_T_187, _T_116)
node _T_189 = or(_T_188, _T_123)
node _T_190 = or(_T_189, _T_130)
node _T_191 = or(_T_190, _T_137)
node _T_192 = or(_T_191, _T_144)
node _T_193 = or(_T_192, _T_151)
node _T_194 = or(_T_193, _T_158)
node _T_195 = or(_T_194, _T_165)
node _T_196 = or(_T_195, _T_172)
node _T_197 = or(_T_196, _T_179)
node _T_198 = or(_T_46, _T_197)
node _T_199 = asUInt(reset)
node _T_200 = eq(_T_199, UInt<1>(0h0))
when _T_200 :
node _T_201 = eq(_T_198, UInt<1>(0h0))
when _T_201 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_198, UInt<1>(0h1), "") : assert_3
node _T_202 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_204 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_230 = and(_T_228, _T_229)
node _T_231 = or(_T_209, _T_216)
node _T_232 = or(_T_231, _T_223)
node _T_233 = or(_T_232, _T_230)
node _T_234 = or(_T_202, _T_233)
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_234, UInt<1>(0h1), "") : assert_4
node _T_238 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_239 = or(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_239, UInt<1>(0h1), "") : assert_5
node _T_243 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_245 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_271 = and(_T_269, _T_270)
node _T_272 = or(_T_250, _T_257)
node _T_273 = or(_T_272, _T_264)
node _T_274 = or(_T_273, _T_271)
node _T_275 = or(_T_243, _T_274)
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_275, UInt<1>(0h1), "") : assert_6
node _T_279 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_280 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_281 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_282 = and(_T_280, _T_281)
node _T_283 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_284 = and(_T_282, _T_283)
node _T_285 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_286 = and(_T_284, _T_285)
node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_288 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_289 = and(_T_287, _T_288)
node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_291 = and(_T_289, _T_290)
node _T_292 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_295 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_296 = and(_T_294, _T_295)
node _T_297 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_298 = and(_T_296, _T_297)
node _T_299 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_302 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_303 = and(_T_301, _T_302)
node _T_304 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_305 = and(_T_303, _T_304)
node _T_306 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_309 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_310 = and(_T_308, _T_309)
node _T_311 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_312 = and(_T_310, _T_311)
node _T_313 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_316 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_317 = and(_T_315, _T_316)
node _T_318 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_323 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_328 = and(_T_326, _T_327)
node _T_329 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_330 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_331 = and(_T_329, _T_330)
node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_335 = and(_T_333, _T_334)
node _T_336 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_337 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_338 = and(_T_336, _T_337)
node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_344 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_349 = and(_T_347, _T_348)
node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_351 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_358 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_363 = and(_T_361, _T_362)
node _T_364 = or(_T_286, _T_293)
node _T_365 = or(_T_364, _T_300)
node _T_366 = or(_T_365, _T_307)
node _T_367 = or(_T_366, _T_314)
node _T_368 = or(_T_367, _T_321)
node _T_369 = or(_T_368, _T_328)
node _T_370 = or(_T_369, _T_335)
node _T_371 = or(_T_370, _T_342)
node _T_372 = or(_T_371, _T_349)
node _T_373 = or(_T_372, _T_356)
node _T_374 = or(_T_373, _T_363)
node _T_375 = or(_T_279, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_375, UInt<1>(0h1), "") : assert_7
node _T_379 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_380 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_381 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
node _T_385 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_388 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_389 = and(_T_387, _T_388)
node _T_390 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_391 = and(_T_389, _T_390)
node _T_392 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_395 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_400 = and(_T_398, _T_399)
node _T_401 = or(_T_386, _T_393)
node _T_402 = or(_T_401, _T_400)
node _T_403 = or(_T_379, _T_402)
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_403, UInt<1>(0h1), "") : assert_8
node _T_407 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_408 = or(_T_407, UInt<1>(0h0))
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9
assert(clock, _T_408, UInt<1>(0h1), "") : assert_9
node _T_412 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9))
node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_414 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_415 = and(_T_413, _T_414)
node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_421 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_428 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_435 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_442 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_447 = and(_T_445, _T_446)
node _T_448 = or(_T_419, _T_426)
node _T_449 = or(_T_448, _T_433)
node _T_450 = or(_T_449, _T_440)
node _T_451 = or(_T_450, _T_447)
node _T_452 = or(_T_412, _T_451)
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10
assert(clock, _T_452, UInt<1>(0h1), "") : assert_10 | module NoCMonitor_1( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h4; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h8; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module CoherenceManagerWrapper :
output auto : { coupler_to_bus_named_mbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coherent_jbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip l2_ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coh_clock_groups_in : { member : { coh_0 : { clock : Clock, reset : Reset}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst coh_clock_groups of ClockGroupAggregator_coh
inst clockGroup of ClockGroup_5
inst fixedClockNode of FixedClockBroadcast_1
inst broadcast of BundleBridgeNexus_NoOutput_5
inst l2 of InclusiveCache
connect l2.clock, childClock
connect l2.reset, childReset
inst filter of TLFilter
connect filter.clock, childClock
connect filter.reset, childReset
inst InclusiveCache_inner_TLBuffer of TLBuffer_a32d64s9k3z3c
connect InclusiveCache_inner_TLBuffer.clock, childClock
connect InclusiveCache_inner_TLBuffer.reset, childReset
inst InclusiveCache_outer_TLBuffer of TLBuffer_a32d64s3k3z3c
connect InclusiveCache_outer_TLBuffer.clock, childClock
connect InclusiveCache_outer_TLBuffer.reset, childReset
inst cork of TLCacheCork
connect cork.clock, childClock
connect cork.reset, childReset
inst coherent_jbar of TLJbar
connect coherent_jbar.clock, childClock
connect coherent_jbar.reset, childReset
inst binder of BankBinder
connect binder.clock, childClock
connect binder.reset, childReset
inst coupler_to_bus_named_mbus of TLInterconnectCoupler_coh_to_bus_named_mbus
connect coupler_to_bus_named_mbus.clock, childClock
connect coupler_to_bus_named_mbus.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
connect clockGroup.auto.in, coh_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out
connect InclusiveCache_outer_TLBuffer.auto.in, l2.auto.out
connect InclusiveCache_inner_TLBuffer.auto.in, filter.auto.anon_out
connect l2.auto.in, InclusiveCache_inner_TLBuffer.auto.out
connect cork.auto.in, InclusiveCache_outer_TLBuffer.auto.out
connect binder.auto.in, cork.auto.out
connect filter.auto.anon_in, coherent_jbar.auto.anon_out
connect coupler_to_bus_named_mbus.auto.widget_anon_in, binder.auto.out
connect coh_clock_groups.auto.in, auto.coh_clock_groups_in
connect l2.auto.ctrls_ctrl_in, auto.l2_ctrls_ctrl_in
connect coherent_jbar.auto.anon_in, auto.coherent_jbar_anon_in
connect coupler_to_bus_named_mbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_mbus_bus_xing_out.d
connect auto.coupler_to_bus_named_mbus_bus_xing_out.a.bits, coupler_to_bus_named_mbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_mbus_bus_xing_out.a.valid, coupler_to_bus_named_mbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_mbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_mbus_bus_xing_out.a.ready
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset
extmodule plusarg_reader_112 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_113 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9]
input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [8:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18]
wire [8:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire [8:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9]
wire [8:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [8:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [8:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28]
wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28]
wire [3:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28]
wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28]
wire _cork_auto_out_a_valid; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26]
wire [3:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26]
wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26]
wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26]
wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26]
wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26]
wire _cork_auto_out_d_ready; // @[Configs.scala:120:26]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69]
wire [8:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69]
wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69]
wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69]
wire [8:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69]
wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69]
wire _l2_auto_in_a_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_b_valid; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24]
wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24]
wire _l2_auto_in_c_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_d_valid; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24]
wire [8:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24]
wire [63:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [8:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9]
wire [8:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [13:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24]
wire [8:0] auto_coherent_jbar_anon_in_b_bits_source = 9'h1E0; // @[ClockDomain.scala:14:9]
wire [8:0] filter_auto_anon_in_b_bits_source = 9'h1E0; // @[Filter.scala:60:9]
wire [8:0] filter_auto_anon_out_b_bits_source = 9'h1E0; // @[Filter.scala:60:9]
wire [8:0] filter_anonOut_b_bits_source = 9'h1E0; // @[MixedNode.scala:542:17]
wire [8:0] filter_anonIn_b_bits_source = 9'h1E0; // @[MixedNode.scala:551:17]
wire [8:0] coherent_jbar_auto_anon_in_b_bits_source = 9'h1E0; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_auto_anon_out_b_bits_source = 9'h1E0; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_anonOut_b_bits_source = 9'h1E0; // @[MixedNode.scala:542:17]
wire [8:0] coherent_jbar_anonIn_b_bits_source = 9'h1E0; // @[MixedNode.scala:551:17]
wire [8:0] coherent_jbar_in_0_b_bits_source = 9'h1E0; // @[Xbar.scala:159:18]
wire [8:0] coherent_jbar__anonIn_b_bits_source_T = 9'h1E0; // @[Xbar.scala:156:69]
wire [8:0] coherent_jbar_out_0_b_bits_source = 9'h1E0; // @[Xbar.scala:216:19]
wire [8:0] coherent_jbar__requestBOI_uncommonBits_T = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] coherent_jbar_requestBOI_uncommonBits = 9'h1E0; // @[Parameters.scala:52:56]
wire [8:0] coherent_jbar_portsBIO_filtered_0_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [7:0] auto_coherent_jbar_anon_in_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9]
wire [7:0] filter_auto_anon_in_b_bits_mask = 8'hFF; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_b_bits_mask = 8'hFF; // @[Filter.scala:60:9]
wire [7:0] filter_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_auto_anon_in_b_bits_mask = 8'hFF; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_out_b_bits_mask = 8'hFF; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] coherent_jbar_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_in_0_b_bits_mask = 8'hFF; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_out_0_b_bits_mask = 8'hFF; // @[Xbar.scala:216:19]
wire [7:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [63:0] auto_coherent_jbar_anon_in_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] filter_auto_anon_in_b_bits_data = 64'h0; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_b_bits_data = 64'h0; // @[Filter.scala:60:9]
wire [63:0] filter_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_auto_anon_in_b_bits_data = 64'h0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_out_b_bits_data = 64'h0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] coherent_jbar_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_in_0_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_out_0_b_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] coherent_jbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28]
wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24]
wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] coherent_jbar_beatsBO_decode = 3'h7; // @[Edges.scala:220:59]
wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9]
wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [8:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [13:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9]
wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [8:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [8:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [7:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [7:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [63:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [8:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [8:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [63:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [8:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [8:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [8:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [63:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9]
wire [8:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9]
wire [8:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9]
assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9]
assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9]
assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9]
assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9]
assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9]
assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [8:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [8:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire [8:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9]
wire [8:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [8:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire [8:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [2:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata ? coherent_jbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata ? coherent_jbar_beatsCI_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata ? coherent_jbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
InclusiveCache l2 ( // @[Configs.scala:93:24]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0),
.auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0),
.auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0),
.auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0),
.auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0),
.auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0),
.auto_in_a_ready (_l2_auto_in_a_ready),
.auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69]
.auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69]
.auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69]
.auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69]
.auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69]
.auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69]
.auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69]
.auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69]
.auto_in_b_valid (_l2_auto_in_b_valid),
.auto_in_b_bits_param (_l2_auto_in_b_bits_param),
.auto_in_b_bits_address (_l2_auto_in_b_bits_address),
.auto_in_c_ready (_l2_auto_in_c_ready),
.auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69]
.auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69]
.auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69]
.auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69]
.auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69]
.auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69]
.auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69]
.auto_in_d_valid (_l2_auto_in_d_valid),
.auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_l2_auto_in_d_bits_param),
.auto_in_d_bits_size (_l2_auto_in_d_bits_size),
.auto_in_d_bits_source (_l2_auto_in_d_bits_source),
.auto_in_d_bits_sink (_l2_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_l2_auto_in_d_bits_denied),
.auto_in_d_bits_data (_l2_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt),
.auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69]
.auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69]
.auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9]
.auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid),
.auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode),
.auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param),
.auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size),
.auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source),
.auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address),
.auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask),
.auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data),
.auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt),
.auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9]
.auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid),
.auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode),
.auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param),
.auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size),
.auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source),
.auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address),
.auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data),
.auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt),
.auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready),
.auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9]
.auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9]
.auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9]
.auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9]
.auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9]
.auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9]
.auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9]
.auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9]
.auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9]
.auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid),
.auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink)
); // @[Configs.scala:93:24]
TLBuffer_a32d64s9k3z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (filter_auto_anon_out_a_ready),
.auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9]
.auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9]
.auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9]
.auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9]
.auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9]
.auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9]
.auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9]
.auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9]
.auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9]
.auto_in_b_valid (filter_auto_anon_out_b_valid),
.auto_in_b_bits_param (filter_auto_anon_out_b_bits_param),
.auto_in_b_bits_address (filter_auto_anon_out_b_bits_address),
.auto_in_c_ready (filter_auto_anon_out_c_ready),
.auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9]
.auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9]
.auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9]
.auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9]
.auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9]
.auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9]
.auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9]
.auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9]
.auto_in_d_valid (filter_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (filter_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (filter_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (filter_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (filter_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt),
.auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9]
.auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9]
.auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24]
.auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt),
.auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready),
.auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24]
.auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24]
.auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24]
.auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24]
.auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid),
.auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode),
.auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param),
.auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size),
.auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source),
.auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address),
.auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data),
.auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt),
.auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready),
.auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24]
.auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24]
.auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24]
.auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24]
.auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24]
.auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24]
.auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24]
.auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24]
.auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24]
.auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid),
.auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink)
); // @[Parameters.scala:56:69]
TLCacheCork cork ( // @[Configs.scala:120:26]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready),
.auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9]
.auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9]
.auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9]
.auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9]
.auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9]
.auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9]
.auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9]
.auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready),
.auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9]
.auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9]
.auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9]
.auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9]
.auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9]
.auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9]
.auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9]
.auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid),
.auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode),
.auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param),
.auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size),
.auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source),
.auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink),
.auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied),
.auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data),
.auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt),
.auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9]
.auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9]
.auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28]
.auto_out_a_valid (_cork_auto_out_a_valid),
.auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_cork_auto_out_a_bits_param),
.auto_out_a_bits_size (_cork_auto_out_a_bits_size),
.auto_out_a_bits_source (_cork_auto_out_a_bits_source),
.auto_out_a_bits_address (_cork_auto_out_a_bits_address),
.auto_out_a_bits_mask (_cork_auto_out_a_bits_mask),
.auto_out_a_bits_data (_cork_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt),
.auto_out_d_ready (_cork_auto_out_d_ready),
.auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28]
.auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28]
.auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28]
.auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28]
.auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28]
.auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28]
.auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28]
.auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28]
.auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28]
); // @[Configs.scala:120:26]
BankBinder binder ( // @[BankBinder.scala:71:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_binder_auto_in_a_ready),
.auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26]
.auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26]
.auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26]
.auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26]
.auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26]
.auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26]
.auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26]
.auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26]
.auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26]
.auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26]
.auto_in_d_valid (_binder_auto_in_d_valid),
.auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_binder_auto_in_d_bits_param),
.auto_in_d_bits_size (_binder_auto_in_d_bits_size),
.auto_in_d_bits_source (_binder_auto_in_d_bits_source),
.auto_in_d_bits_sink (_binder_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_binder_auto_in_d_bits_denied),
.auto_in_d_bits_data (_binder_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt),
.auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid),
.auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode),
.auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param),
.auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size),
.auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source),
.auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address),
.auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask),
.auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt),
.auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready),
.auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7]
); // @[BankBinder.scala:71:28]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_33 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_303
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_304
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_305
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_306
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_33( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_303 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_304 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_305 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_306 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_310 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_310( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_PLIC :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_25
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0)
reg dOrig : UInt, clock
regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0)
node dFragnum = bits(anonOut.d.bits.source, 2, 0)
node dFirst = eq(acknum, UInt<1>(0h0))
node dLast = eq(dFragnum, UInt<1>(0h0))
node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0)
node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount)
node dsizeOH = bits(_dsizeOH_T, 3, 0)
node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size)
node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0)
node dsizeOH1 = not(_dsizeOH1_T_1)
node dHasData = bits(anonOut.d.bits.opcode, 0, 0)
node acknum_fragment = shl(dFragnum, 0)
node acknum_size = shr(dsizeOH1, 3)
node _T = eq(anonOut.d.valid, UInt<1>(0h0))
node _T_1 = and(acknum_fragment, acknum_size)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = or(_T, _T_2)
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0))
node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T)
node _ack_decrement_T = shr(dsizeOH, 3)
node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T)
node _dFirst_size_T = shl(dFragnum, 3)
node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1)
node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1)
node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1))
node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1)
node _dFirst_size_T_5 = not(_dFirst_size_T_4)
node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5)
node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4)
node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0)
node _dFirst_size_T_7 = orr(dFirst_size_hi)
node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo)
node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2)
node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0)
node _dFirst_size_T_9 = orr(dFirst_size_hi_1)
node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1)
node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1)
node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11)
node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12)
node _T_7 = and(anonOut.d.ready, anonOut.d.valid)
when _T_7 :
node _acknum_T = sub(acknum, ack_decrement)
node _acknum_T_1 = tail(_acknum_T, 1)
node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1)
connect acknum, _acknum_T_2
when dFirst :
connect dOrig, dFirst_size
node _dToggle_T = bits(anonOut.d.bits.source, 3, 3)
connect dToggle, _dToggle_T
node _drop_T = eq(dHasData, UInt<1>(0h0))
node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast)
node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0))
node drop = and(_drop_T, _drop_T_2)
node _anonOut_d_ready_T = or(anonIn.d.ready, drop)
connect anonOut.d.ready, _anonOut_d_ready_T
node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0))
node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T)
connect anonIn.d.valid, _anonIn_d_valid_T_1
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig)
connect anonIn.d.bits.size, _anonIn_d_bits_size_T
inst repeater of Repeater_TLBundleA_a28d64s7k1z3u
connect repeater.clock, clock
connect repeater.reset, reset
connect repeater.io.enq, anonIn.a
node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0))
node _find_T_1 = cvt(_find_T)
node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0)))
node _find_T_3 = asSInt(_find_T_2)
node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0)))
wire find : UInt<1>[1]
connect find[0], _find_T_4
node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode)
node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3))
node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode)
node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1)
node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode)
node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3)
node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode)
node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5)
node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode)
node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7)
node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode)
node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9)
node _aFrag_T = gt(repeater.io.deq.bits.size, limit)
node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size)
node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size)
node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0)
node aOrigOH1 = not(_aOrigOH1_T_1)
node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag)
node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0)
node aFragOH1 = not(_aFragOH1_T_1)
node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2)
node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0))
node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1)
regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0)
node aFirst = eq(gennum, UInt<1>(0h0))
node _old_gennum1_T = shr(aOrigOH1, 3)
node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1))
node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1)
node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2)
node _new_gennum_T = not(old_gennum1)
node _new_gennum_T_1 = shr(aMask, 3)
node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1)
node new_gennum = not(_new_gennum_T_2)
node _aFragnum_T = shr(old_gennum1, 0)
node _aFragnum_T_1 = not(_aFragnum_T)
node _aFragnum_T_2 = shr(aFragOH1, 3)
node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2)
node aFragnum = not(_aFragnum_T_3)
node aLast = eq(aFragnum, UInt<1>(0h0))
reg aToggle_r : UInt<1>, clock
when aFirst :
connect aToggle_r, dToggle
node _aToggle_T = mux(aFirst, dToggle, aToggle_r)
node aToggle = eq(_aToggle_T, UInt<1>(0h0))
node _T_8 = and(anonOut.a.ready, anonOut.a.valid)
when _T_8 :
connect gennum, new_gennum
node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0))
node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0))
node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1)
connect repeater.io.repeat, _repeater_io_repeat_T_2
connect anonOut.a.bits, repeater.io.deq.bits
connect anonOut.a.valid, repeater.io.deq.valid
connect repeater.io.deq.ready, anonOut.a.ready
node _anonOut_a_bits_address_T = shl(old_gennum1, 3)
node _anonOut_a_bits_address_T_1 = not(aOrigOH1)
node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1)
node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1)
node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7))
node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4)
node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5)
connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6
node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle)
node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum)
connect anonOut.a.bits.source, _anonOut_a_bits_source_T
connect anonOut.a.bits.size, aFrag
node _T_9 = eq(repeater.io.full, UInt<1>(0h0))
node _T_10 = eq(aHasData, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
connect anonOut.a.bits.data, anonIn.a.bits.data
node _T_15 = eq(repeater.io.full, UInt<1>(0h0))
node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff))
node _T_17 = or(_T_15, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T
wire anonOut_a_bits_user_out : { }
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLFragmenter_PLIC( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30]
wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [27:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49]
wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18]
wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}]
wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}]
wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}]
reg aToggle_r; // @[Fragmenter.scala:309:54] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_25 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0)
node _source_ok_T_28 = shr(io.in.a.bits.source, 5)
node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0))
node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f))
node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0)
node _source_ok_T_34 = shr(io.in.a.bits.source, 5)
node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1))
node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f))
node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0)
node _source_ok_T_40 = shr(io.in.a.bits.source, 5)
node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2))
node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f))
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0)
node _source_ok_T_46 = shr(io.in.a.bits.source, 5)
node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3))
node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f))
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0)
node _source_ok_T_52 = shr(io.in.a.bits.source, 5)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0)
node _source_ok_T_58 = shr(io.in.a.bits.source, 5)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0)
node _source_ok_T_64 = shr(io.in.a.bits.source, 5)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0)
node _source_ok_T_70 = shr(io.in.a.bits.source, 5)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE : UInt<1>[17]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_33
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_45
connect _source_ok_WIRE[11], _source_ok_T_51
connect _source_ok_WIRE[12], _source_ok_T_57
connect _source_ok_WIRE[13], _source_ok_T_63
connect _source_ok_WIRE[14], _source_ok_T_69
connect _source_ok_WIRE[15], _source_ok_T_75
connect _source_ok_WIRE[16], _source_ok_T_76
node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7])
node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8])
node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15])
node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<7>(0h40))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<7>(0h41))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<7>(0h42))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<7>(0h43))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_88 = shr(io.in.a.bits.source, 5)
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_91 = and(_T_89, _T_90)
node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_101 = shr(io.in.a.bits.source, 5)
node _T_102 = eq(_T_101, UInt<1>(0h1))
node _T_103 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_104 = and(_T_102, _T_103)
node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_114 = shr(io.in.a.bits.source, 5)
node _T_115 = eq(_T_114, UInt<2>(0h2))
node _T_116 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_117 = and(_T_115, _T_116)
node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(_T_119, UInt<1>(0h0))
node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = or(_T_120, _T_125)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_127 = shr(io.in.a.bits.source, 5)
node _T_128 = eq(_T_127, UInt<2>(0h3))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(_T_132, UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = or(_T_133, _T_138)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_140 = shr(io.in.a.bits.source, 5)
node _T_141 = eq(_T_140, UInt<3>(0h4))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = or(_T_146, _T_151)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0)
node _T_153 = shr(io.in.a.bits.source, 5)
node _T_154 = eq(_T_153, UInt<3>(0h5))
node _T_155 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_156 = and(_T_154, _T_155)
node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(_T_158, UInt<1>(0h0))
node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_161 = cvt(_T_160)
node _T_162 = and(_T_161, asSInt(UInt<1>(0h0)))
node _T_163 = asSInt(_T_162)
node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = or(_T_159, _T_164)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0)
node _T_166 = shr(io.in.a.bits.source, 5)
node _T_167 = eq(_T_166, UInt<3>(0h6))
node _T_168 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_169 = and(_T_167, _T_168)
node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = or(_T_172, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0)
node _T_179 = shr(io.in.a.bits.source, 5)
node _T_180 = eq(_T_179, UInt<3>(0h7))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = and(_T_11, _T_24)
node _T_201 = and(_T_200, _T_37)
node _T_202 = and(_T_201, _T_50)
node _T_203 = and(_T_202, _T_63)
node _T_204 = and(_T_203, _T_71)
node _T_205 = and(_T_204, _T_79)
node _T_206 = and(_T_205, _T_87)
node _T_207 = and(_T_206, _T_100)
node _T_208 = and(_T_207, _T_113)
node _T_209 = and(_T_208, _T_126)
node _T_210 = and(_T_209, _T_139)
node _T_211 = and(_T_210, _T_152)
node _T_212 = and(_T_211, _T_165)
node _T_213 = and(_T_212, _T_178)
node _T_214 = and(_T_213, _T_191)
node _T_215 = and(_T_214, _T_199)
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_215, UInt<1>(0h1), "") : assert_1
node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_219 :
node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_224 = shr(io.in.a.bits.source, 2)
node _T_225 = eq(_T_224, UInt<7>(0h40))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_229 = and(_T_227, _T_228)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_230 = shr(io.in.a.bits.source, 2)
node _T_231 = eq(_T_230, UInt<7>(0h41))
node _T_232 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_233 = and(_T_231, _T_232)
node _T_234 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_235 = and(_T_233, _T_234)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_236 = shr(io.in.a.bits.source, 2)
node _T_237 = eq(_T_236, UInt<7>(0h42))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_241 = and(_T_239, _T_240)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_242 = shr(io.in.a.bits.source, 2)
node _T_243 = eq(_T_242, UInt<7>(0h43))
node _T_244 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_245 = and(_T_243, _T_244)
node _T_246 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0)
node _T_251 = shr(io.in.a.bits.source, 5)
node _T_252 = eq(_T_251, UInt<1>(0h0))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0)
node _T_257 = shr(io.in.a.bits.source, 5)
node _T_258 = eq(_T_257, UInt<1>(0h1))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0)
node _T_263 = shr(io.in.a.bits.source, 5)
node _T_264 = eq(_T_263, UInt<2>(0h2))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f))
node _T_268 = and(_T_266, _T_267)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0)
node _T_269 = shr(io.in.a.bits.source, 5)
node _T_270 = eq(_T_269, UInt<2>(0h3))
node _T_271 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_272 = and(_T_270, _T_271)
node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f))
node _T_274 = and(_T_272, _T_273)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0)
node _T_275 = shr(io.in.a.bits.source, 5)
node _T_276 = eq(_T_275, UInt<3>(0h4))
node _T_277 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_278 = and(_T_276, _T_277)
node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f))
node _T_280 = and(_T_278, _T_279)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0)
node _T_281 = shr(io.in.a.bits.source, 5)
node _T_282 = eq(_T_281, UInt<3>(0h5))
node _T_283 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_284 = and(_T_282, _T_283)
node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f))
node _T_286 = and(_T_284, _T_285)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0)
node _T_287 = shr(io.in.a.bits.source, 5)
node _T_288 = eq(_T_287, UInt<3>(0h6))
node _T_289 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_290 = and(_T_288, _T_289)
node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f))
node _T_292 = and(_T_290, _T_291)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0)
node _T_293 = shr(io.in.a.bits.source, 5)
node _T_294 = eq(_T_293, UInt<3>(0h7))
node _T_295 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_296 = and(_T_294, _T_295)
node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f))
node _T_298 = and(_T_296, _T_297)
node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_300 = or(_T_223, _T_229)
node _T_301 = or(_T_300, _T_235)
node _T_302 = or(_T_301, _T_241)
node _T_303 = or(_T_302, _T_247)
node _T_304 = or(_T_303, _T_248)
node _T_305 = or(_T_304, _T_249)
node _T_306 = or(_T_305, _T_250)
node _T_307 = or(_T_306, _T_256)
node _T_308 = or(_T_307, _T_262)
node _T_309 = or(_T_308, _T_268)
node _T_310 = or(_T_309, _T_274)
node _T_311 = or(_T_310, _T_280)
node _T_312 = or(_T_311, _T_286)
node _T_313 = or(_T_312, _T_292)
node _T_314 = or(_T_313, _T_298)
node _T_315 = or(_T_314, _T_299)
node _T_316 = and(_T_222, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<14>(0h2000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_330 = cvt(_T_329)
node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000)))
node _T_332 = asSInt(_T_331)
node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0)))
node _T_334 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<18>(0h2f000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_345 = cvt(_T_344)
node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000)))
node _T_347 = asSInt(_T_346)
node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0)))
node _T_349 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_350 = cvt(_T_349)
node _T_351 = and(_T_350, asSInt(UInt<27>(0h4000000)))
node _T_352 = asSInt(_T_351)
node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0)))
node _T_354 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_355 = cvt(_T_354)
node _T_356 = and(_T_355, asSInt(UInt<13>(0h1000)))
node _T_357 = asSInt(_T_356)
node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0)))
node _T_359 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<19>(0h40000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = or(_T_323, _T_328)
node _T_365 = or(_T_364, _T_333)
node _T_366 = or(_T_365, _T_338)
node _T_367 = or(_T_366, _T_343)
node _T_368 = or(_T_367, _T_348)
node _T_369 = or(_T_368, _T_353)
node _T_370 = or(_T_369, _T_358)
node _T_371 = or(_T_370, _T_363)
node _T_372 = and(_T_318, _T_371)
node _T_373 = or(UInt<1>(0h0), _T_372)
node _T_374 = and(_T_317, _T_373)
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_374, UInt<1>(0h1), "") : assert_2
node _T_378 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_379 = shr(io.in.a.bits.source, 2)
node _T_380 = eq(_T_379, UInt<7>(0h40))
node _T_381 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_382 = and(_T_380, _T_381)
node _T_383 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_384 = and(_T_382, _T_383)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_385 = shr(io.in.a.bits.source, 2)
node _T_386 = eq(_T_385, UInt<7>(0h41))
node _T_387 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_388 = and(_T_386, _T_387)
node _T_389 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_390 = and(_T_388, _T_389)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_391 = shr(io.in.a.bits.source, 2)
node _T_392 = eq(_T_391, UInt<7>(0h42))
node _T_393 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_394 = and(_T_392, _T_393)
node _T_395 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_396 = and(_T_394, _T_395)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_397 = shr(io.in.a.bits.source, 2)
node _T_398 = eq(_T_397, UInt<7>(0h43))
node _T_399 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_400 = and(_T_398, _T_399)
node _T_401 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_402 = and(_T_400, _T_401)
node _T_403 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_404 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_405 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0)
node _T_406 = shr(io.in.a.bits.source, 5)
node _T_407 = eq(_T_406, UInt<1>(0h0))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_28, UInt<5>(0h1f))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0)
node _T_412 = shr(io.in.a.bits.source, 5)
node _T_413 = eq(_T_412, UInt<1>(0h1))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_29, UInt<5>(0h1f))
node _T_417 = and(_T_415, _T_416)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0)
node _T_418 = shr(io.in.a.bits.source, 5)
node _T_419 = eq(_T_418, UInt<2>(0h2))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_30, UInt<5>(0h1f))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0)
node _T_424 = shr(io.in.a.bits.source, 5)
node _T_425 = eq(_T_424, UInt<2>(0h3))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_31, UInt<5>(0h1f))
node _T_429 = and(_T_427, _T_428)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0)
node _T_430 = shr(io.in.a.bits.source, 5)
node _T_431 = eq(_T_430, UInt<3>(0h4))
node _T_432 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_433 = and(_T_431, _T_432)
node _T_434 = leq(uncommonBits_32, UInt<5>(0h1f))
node _T_435 = and(_T_433, _T_434)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0)
node _T_436 = shr(io.in.a.bits.source, 5)
node _T_437 = eq(_T_436, UInt<3>(0h5))
node _T_438 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_439 = and(_T_437, _T_438)
node _T_440 = leq(uncommonBits_33, UInt<5>(0h1f))
node _T_441 = and(_T_439, _T_440)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0)
node _T_442 = shr(io.in.a.bits.source, 5)
node _T_443 = eq(_T_442, UInt<3>(0h6))
node _T_444 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_445 = and(_T_443, _T_444)
node _T_446 = leq(uncommonBits_34, UInt<5>(0h1f))
node _T_447 = and(_T_445, _T_446)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0)
node _T_448 = shr(io.in.a.bits.source, 5)
node _T_449 = eq(_T_448, UInt<3>(0h7))
node _T_450 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_451 = and(_T_449, _T_450)
node _T_452 = leq(uncommonBits_35, UInt<5>(0h1f))
node _T_453 = and(_T_451, _T_452)
node _T_454 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE : UInt<1>[17]
connect _WIRE[0], _T_378
connect _WIRE[1], _T_384
connect _WIRE[2], _T_390
connect _WIRE[3], _T_396
connect _WIRE[4], _T_402
connect _WIRE[5], _T_403
connect _WIRE[6], _T_404
connect _WIRE[7], _T_405
connect _WIRE[8], _T_411
connect _WIRE[9], _T_417
connect _WIRE[10], _T_423
connect _WIRE[11], _T_429
connect _WIRE[12], _T_435
connect _WIRE[13], _T_441
connect _WIRE[14], _T_447
connect _WIRE[15], _T_453
connect _WIRE[16], _T_454
node _T_455 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_456 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_457 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_458 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_459 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_460 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_461 = mux(_WIRE[5], _T_455, UInt<1>(0h0))
node _T_462 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_463 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_464 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_465 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_466 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_467 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_468 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_469 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_470 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_471 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_472 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_473 = or(_T_456, _T_457)
node _T_474 = or(_T_473, _T_458)
node _T_475 = or(_T_474, _T_459)
node _T_476 = or(_T_475, _T_460)
node _T_477 = or(_T_476, _T_461)
node _T_478 = or(_T_477, _T_462)
node _T_479 = or(_T_478, _T_463)
node _T_480 = or(_T_479, _T_464)
node _T_481 = or(_T_480, _T_465)
node _T_482 = or(_T_481, _T_466)
node _T_483 = or(_T_482, _T_467)
node _T_484 = or(_T_483, _T_468)
node _T_485 = or(_T_484, _T_469)
node _T_486 = or(_T_485, _T_470)
node _T_487 = or(_T_486, _T_471)
node _T_488 = or(_T_487, _T_472)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_488
node _T_489 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_490 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_491 = and(_T_489, _T_490)
node _T_492 = or(UInt<1>(0h0), _T_491)
node _T_493 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_494 = cvt(_T_493)
node _T_495 = and(_T_494, asSInt(UInt<14>(0h2000)))
node _T_496 = asSInt(_T_495)
node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0)))
node _T_498 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_499 = cvt(_T_498)
node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000)))
node _T_501 = asSInt(_T_500)
node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0)))
node _T_503 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_504 = cvt(_T_503)
node _T_505 = and(_T_504, asSInt(UInt<17>(0h10000)))
node _T_506 = asSInt(_T_505)
node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0)))
node _T_508 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_509 = cvt(_T_508)
node _T_510 = and(_T_509, asSInt(UInt<18>(0h2f000)))
node _T_511 = asSInt(_T_510)
node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0)))
node _T_513 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_514 = cvt(_T_513)
node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000)))
node _T_516 = asSInt(_T_515)
node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0)))
node _T_518 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_519 = cvt(_T_518)
node _T_520 = and(_T_519, asSInt(UInt<13>(0h1000)))
node _T_521 = asSInt(_T_520)
node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0)))
node _T_523 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_524 = cvt(_T_523)
node _T_525 = and(_T_524, asSInt(UInt<27>(0h4000000)))
node _T_526 = asSInt(_T_525)
node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0)))
node _T_528 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_529 = cvt(_T_528)
node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000)))
node _T_531 = asSInt(_T_530)
node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0)))
node _T_533 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_534 = cvt(_T_533)
node _T_535 = and(_T_534, asSInt(UInt<19>(0h40000)))
node _T_536 = asSInt(_T_535)
node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0)))
node _T_538 = or(_T_497, _T_502)
node _T_539 = or(_T_538, _T_507)
node _T_540 = or(_T_539, _T_512)
node _T_541 = or(_T_540, _T_517)
node _T_542 = or(_T_541, _T_522)
node _T_543 = or(_T_542, _T_527)
node _T_544 = or(_T_543, _T_532)
node _T_545 = or(_T_544, _T_537)
node _T_546 = and(_T_492, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_WIRE_1, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_548, UInt<1>(0h1), "") : assert_3
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(source_ok, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_555 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_T_555, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_555, UInt<1>(0h1), "") : assert_5
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(is_aligned, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_562 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_562, UInt<1>(0h1), "") : assert_7
node _T_566 = not(io.in.a.bits.mask)
node _T_567 = eq(_T_566, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_567, UInt<1>(0h1), "") : assert_8
node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(_T_571, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_571, UInt<1>(0h1), "") : assert_9
node _T_575 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_575 :
node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_578 = and(_T_576, _T_577)
node _T_579 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_580 = shr(io.in.a.bits.source, 2)
node _T_581 = eq(_T_580, UInt<7>(0h40))
node _T_582 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_583 = and(_T_581, _T_582)
node _T_584 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_585 = and(_T_583, _T_584)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_586 = shr(io.in.a.bits.source, 2)
node _T_587 = eq(_T_586, UInt<7>(0h41))
node _T_588 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_589 = and(_T_587, _T_588)
node _T_590 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_591 = and(_T_589, _T_590)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_592 = shr(io.in.a.bits.source, 2)
node _T_593 = eq(_T_592, UInt<7>(0h42))
node _T_594 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_595 = and(_T_593, _T_594)
node _T_596 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_597 = and(_T_595, _T_596)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_598 = shr(io.in.a.bits.source, 2)
node _T_599 = eq(_T_598, UInt<7>(0h43))
node _T_600 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_601 = and(_T_599, _T_600)
node _T_602 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_603 = and(_T_601, _T_602)
node _T_604 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_605 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_606 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0)
node _T_607 = shr(io.in.a.bits.source, 5)
node _T_608 = eq(_T_607, UInt<1>(0h0))
node _T_609 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_610 = and(_T_608, _T_609)
node _T_611 = leq(uncommonBits_40, UInt<5>(0h1f))
node _T_612 = and(_T_610, _T_611)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0)
node _T_613 = shr(io.in.a.bits.source, 5)
node _T_614 = eq(_T_613, UInt<1>(0h1))
node _T_615 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_616 = and(_T_614, _T_615)
node _T_617 = leq(uncommonBits_41, UInt<5>(0h1f))
node _T_618 = and(_T_616, _T_617)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0)
node _T_619 = shr(io.in.a.bits.source, 5)
node _T_620 = eq(_T_619, UInt<2>(0h2))
node _T_621 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_622 = and(_T_620, _T_621)
node _T_623 = leq(uncommonBits_42, UInt<5>(0h1f))
node _T_624 = and(_T_622, _T_623)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0)
node _T_625 = shr(io.in.a.bits.source, 5)
node _T_626 = eq(_T_625, UInt<2>(0h3))
node _T_627 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_628 = and(_T_626, _T_627)
node _T_629 = leq(uncommonBits_43, UInt<5>(0h1f))
node _T_630 = and(_T_628, _T_629)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0)
node _T_631 = shr(io.in.a.bits.source, 5)
node _T_632 = eq(_T_631, UInt<3>(0h4))
node _T_633 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_634 = and(_T_632, _T_633)
node _T_635 = leq(uncommonBits_44, UInt<5>(0h1f))
node _T_636 = and(_T_634, _T_635)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0)
node _T_637 = shr(io.in.a.bits.source, 5)
node _T_638 = eq(_T_637, UInt<3>(0h5))
node _T_639 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_640 = and(_T_638, _T_639)
node _T_641 = leq(uncommonBits_45, UInt<5>(0h1f))
node _T_642 = and(_T_640, _T_641)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0)
node _T_643 = shr(io.in.a.bits.source, 5)
node _T_644 = eq(_T_643, UInt<3>(0h6))
node _T_645 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_646 = and(_T_644, _T_645)
node _T_647 = leq(uncommonBits_46, UInt<5>(0h1f))
node _T_648 = and(_T_646, _T_647)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0)
node _T_649 = shr(io.in.a.bits.source, 5)
node _T_650 = eq(_T_649, UInt<3>(0h7))
node _T_651 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_652 = and(_T_650, _T_651)
node _T_653 = leq(uncommonBits_47, UInt<5>(0h1f))
node _T_654 = and(_T_652, _T_653)
node _T_655 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_656 = or(_T_579, _T_585)
node _T_657 = or(_T_656, _T_591)
node _T_658 = or(_T_657, _T_597)
node _T_659 = or(_T_658, _T_603)
node _T_660 = or(_T_659, _T_604)
node _T_661 = or(_T_660, _T_605)
node _T_662 = or(_T_661, _T_606)
node _T_663 = or(_T_662, _T_612)
node _T_664 = or(_T_663, _T_618)
node _T_665 = or(_T_664, _T_624)
node _T_666 = or(_T_665, _T_630)
node _T_667 = or(_T_666, _T_636)
node _T_668 = or(_T_667, _T_642)
node _T_669 = or(_T_668, _T_648)
node _T_670 = or(_T_669, _T_654)
node _T_671 = or(_T_670, _T_655)
node _T_672 = and(_T_578, _T_671)
node _T_673 = or(UInt<1>(0h0), _T_672)
node _T_674 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_675 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_676 = cvt(_T_675)
node _T_677 = and(_T_676, asSInt(UInt<14>(0h2000)))
node _T_678 = asSInt(_T_677)
node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0)))
node _T_680 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_681 = cvt(_T_680)
node _T_682 = and(_T_681, asSInt(UInt<13>(0h1000)))
node _T_683 = asSInt(_T_682)
node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0)))
node _T_685 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_686 = cvt(_T_685)
node _T_687 = and(_T_686, asSInt(UInt<17>(0h10000)))
node _T_688 = asSInt(_T_687)
node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0)))
node _T_690 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_691 = cvt(_T_690)
node _T_692 = and(_T_691, asSInt(UInt<18>(0h2f000)))
node _T_693 = asSInt(_T_692)
node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0)))
node _T_695 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_696 = cvt(_T_695)
node _T_697 = and(_T_696, asSInt(UInt<17>(0h10000)))
node _T_698 = asSInt(_T_697)
node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0)))
node _T_700 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_701 = cvt(_T_700)
node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000)))
node _T_703 = asSInt(_T_702)
node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0)))
node _T_705 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<27>(0h4000000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<19>(0h40000)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = or(_T_679, _T_684)
node _T_721 = or(_T_720, _T_689)
node _T_722 = or(_T_721, _T_694)
node _T_723 = or(_T_722, _T_699)
node _T_724 = or(_T_723, _T_704)
node _T_725 = or(_T_724, _T_709)
node _T_726 = or(_T_725, _T_714)
node _T_727 = or(_T_726, _T_719)
node _T_728 = and(_T_674, _T_727)
node _T_729 = or(UInt<1>(0h0), _T_728)
node _T_730 = and(_T_673, _T_729)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_730, UInt<1>(0h1), "") : assert_10
node _T_734 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_735 = shr(io.in.a.bits.source, 2)
node _T_736 = eq(_T_735, UInt<7>(0h40))
node _T_737 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_738 = and(_T_736, _T_737)
node _T_739 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_740 = and(_T_738, _T_739)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_741 = shr(io.in.a.bits.source, 2)
node _T_742 = eq(_T_741, UInt<7>(0h41))
node _T_743 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_744 = and(_T_742, _T_743)
node _T_745 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_746 = and(_T_744, _T_745)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_747 = shr(io.in.a.bits.source, 2)
node _T_748 = eq(_T_747, UInt<7>(0h42))
node _T_749 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_750 = and(_T_748, _T_749)
node _T_751 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_752 = and(_T_750, _T_751)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_753 = shr(io.in.a.bits.source, 2)
node _T_754 = eq(_T_753, UInt<7>(0h43))
node _T_755 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_756 = and(_T_754, _T_755)
node _T_757 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_758 = and(_T_756, _T_757)
node _T_759 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_760 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_761 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0)
node _T_762 = shr(io.in.a.bits.source, 5)
node _T_763 = eq(_T_762, UInt<1>(0h0))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_52, UInt<5>(0h1f))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0)
node _T_768 = shr(io.in.a.bits.source, 5)
node _T_769 = eq(_T_768, UInt<1>(0h1))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_53, UInt<5>(0h1f))
node _T_773 = and(_T_771, _T_772)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0)
node _T_774 = shr(io.in.a.bits.source, 5)
node _T_775 = eq(_T_774, UInt<2>(0h2))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_54, UInt<5>(0h1f))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0)
node _T_780 = shr(io.in.a.bits.source, 5)
node _T_781 = eq(_T_780, UInt<2>(0h3))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_55, UInt<5>(0h1f))
node _T_785 = and(_T_783, _T_784)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0)
node _T_786 = shr(io.in.a.bits.source, 5)
node _T_787 = eq(_T_786, UInt<3>(0h4))
node _T_788 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_789 = and(_T_787, _T_788)
node _T_790 = leq(uncommonBits_56, UInt<5>(0h1f))
node _T_791 = and(_T_789, _T_790)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0)
node _T_792 = shr(io.in.a.bits.source, 5)
node _T_793 = eq(_T_792, UInt<3>(0h5))
node _T_794 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_795 = and(_T_793, _T_794)
node _T_796 = leq(uncommonBits_57, UInt<5>(0h1f))
node _T_797 = and(_T_795, _T_796)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0)
node _T_798 = shr(io.in.a.bits.source, 5)
node _T_799 = eq(_T_798, UInt<3>(0h6))
node _T_800 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_801 = and(_T_799, _T_800)
node _T_802 = leq(uncommonBits_58, UInt<5>(0h1f))
node _T_803 = and(_T_801, _T_802)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0)
node _T_804 = shr(io.in.a.bits.source, 5)
node _T_805 = eq(_T_804, UInt<3>(0h7))
node _T_806 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_807 = and(_T_805, _T_806)
node _T_808 = leq(uncommonBits_59, UInt<5>(0h1f))
node _T_809 = and(_T_807, _T_808)
node _T_810 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE_2 : UInt<1>[17]
connect _WIRE_2[0], _T_734
connect _WIRE_2[1], _T_740
connect _WIRE_2[2], _T_746
connect _WIRE_2[3], _T_752
connect _WIRE_2[4], _T_758
connect _WIRE_2[5], _T_759
connect _WIRE_2[6], _T_760
connect _WIRE_2[7], _T_761
connect _WIRE_2[8], _T_767
connect _WIRE_2[9], _T_773
connect _WIRE_2[10], _T_779
connect _WIRE_2[11], _T_785
connect _WIRE_2[12], _T_791
connect _WIRE_2[13], _T_797
connect _WIRE_2[14], _T_803
connect _WIRE_2[15], _T_809
connect _WIRE_2[16], _T_810
node _T_811 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_812 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_813 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_814 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_815 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_816 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_817 = mux(_WIRE_2[5], _T_811, UInt<1>(0h0))
node _T_818 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_819 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_820 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_821 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_822 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_823 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_824 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_825 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_826 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_827 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_828 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_829 = or(_T_812, _T_813)
node _T_830 = or(_T_829, _T_814)
node _T_831 = or(_T_830, _T_815)
node _T_832 = or(_T_831, _T_816)
node _T_833 = or(_T_832, _T_817)
node _T_834 = or(_T_833, _T_818)
node _T_835 = or(_T_834, _T_819)
node _T_836 = or(_T_835, _T_820)
node _T_837 = or(_T_836, _T_821)
node _T_838 = or(_T_837, _T_822)
node _T_839 = or(_T_838, _T_823)
node _T_840 = or(_T_839, _T_824)
node _T_841 = or(_T_840, _T_825)
node _T_842 = or(_T_841, _T_826)
node _T_843 = or(_T_842, _T_827)
node _T_844 = or(_T_843, _T_828)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_844
node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_846 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_847 = and(_T_845, _T_846)
node _T_848 = or(UInt<1>(0h0), _T_847)
node _T_849 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<14>(0h2000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<19>(0h40000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = or(_T_853, _T_858)
node _T_895 = or(_T_894, _T_863)
node _T_896 = or(_T_895, _T_868)
node _T_897 = or(_T_896, _T_873)
node _T_898 = or(_T_897, _T_878)
node _T_899 = or(_T_898, _T_883)
node _T_900 = or(_T_899, _T_888)
node _T_901 = or(_T_900, _T_893)
node _T_902 = and(_T_848, _T_901)
node _T_903 = or(UInt<1>(0h0), _T_902)
node _T_904 = and(_WIRE_3, _T_903)
node _T_905 = asUInt(reset)
node _T_906 = eq(_T_905, UInt<1>(0h0))
when _T_906 :
node _T_907 = eq(_T_904, UInt<1>(0h0))
when _T_907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_904, UInt<1>(0h1), "") : assert_11
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(source_ok, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_911 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(_T_911, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_911, UInt<1>(0h1), "") : assert_13
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(is_aligned, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_918 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_918, UInt<1>(0h1), "") : assert_15
node _T_922 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(_T_922, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_922, UInt<1>(0h1), "") : assert_16
node _T_926 = not(io.in.a.bits.mask)
node _T_927 = eq(_T_926, UInt<1>(0h0))
node _T_928 = asUInt(reset)
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(_T_927, UInt<1>(0h0))
when _T_930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_927, UInt<1>(0h1), "") : assert_17
node _T_931 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(_T_931, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_931, UInt<1>(0h1), "") : assert_18
node _T_935 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_935 :
node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_937 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_938 = and(_T_936, _T_937)
node _T_939 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_940 = shr(io.in.a.bits.source, 2)
node _T_941 = eq(_T_940, UInt<7>(0h40))
node _T_942 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_943 = and(_T_941, _T_942)
node _T_944 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_945 = and(_T_943, _T_944)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_946 = shr(io.in.a.bits.source, 2)
node _T_947 = eq(_T_946, UInt<7>(0h41))
node _T_948 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_949 = and(_T_947, _T_948)
node _T_950 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_951 = and(_T_949, _T_950)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_952 = shr(io.in.a.bits.source, 2)
node _T_953 = eq(_T_952, UInt<7>(0h42))
node _T_954 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_955 = and(_T_953, _T_954)
node _T_956 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_957 = and(_T_955, _T_956)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_958 = shr(io.in.a.bits.source, 2)
node _T_959 = eq(_T_958, UInt<7>(0h43))
node _T_960 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_961 = and(_T_959, _T_960)
node _T_962 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_963 = and(_T_961, _T_962)
node _T_964 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_965 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_966 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0)
node _T_967 = shr(io.in.a.bits.source, 5)
node _T_968 = eq(_T_967, UInt<1>(0h0))
node _T_969 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_970 = and(_T_968, _T_969)
node _T_971 = leq(uncommonBits_64, UInt<5>(0h1f))
node _T_972 = and(_T_970, _T_971)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0)
node _T_973 = shr(io.in.a.bits.source, 5)
node _T_974 = eq(_T_973, UInt<1>(0h1))
node _T_975 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_976 = and(_T_974, _T_975)
node _T_977 = leq(uncommonBits_65, UInt<5>(0h1f))
node _T_978 = and(_T_976, _T_977)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0)
node _T_979 = shr(io.in.a.bits.source, 5)
node _T_980 = eq(_T_979, UInt<2>(0h2))
node _T_981 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_982 = and(_T_980, _T_981)
node _T_983 = leq(uncommonBits_66, UInt<5>(0h1f))
node _T_984 = and(_T_982, _T_983)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0)
node _T_985 = shr(io.in.a.bits.source, 5)
node _T_986 = eq(_T_985, UInt<2>(0h3))
node _T_987 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_988 = and(_T_986, _T_987)
node _T_989 = leq(uncommonBits_67, UInt<5>(0h1f))
node _T_990 = and(_T_988, _T_989)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0)
node _T_991 = shr(io.in.a.bits.source, 5)
node _T_992 = eq(_T_991, UInt<3>(0h4))
node _T_993 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_994 = and(_T_992, _T_993)
node _T_995 = leq(uncommonBits_68, UInt<5>(0h1f))
node _T_996 = and(_T_994, _T_995)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0)
node _T_997 = shr(io.in.a.bits.source, 5)
node _T_998 = eq(_T_997, UInt<3>(0h5))
node _T_999 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_1000 = and(_T_998, _T_999)
node _T_1001 = leq(uncommonBits_69, UInt<5>(0h1f))
node _T_1002 = and(_T_1000, _T_1001)
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0)
node _T_1003 = shr(io.in.a.bits.source, 5)
node _T_1004 = eq(_T_1003, UInt<3>(0h6))
node _T_1005 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_1006 = and(_T_1004, _T_1005)
node _T_1007 = leq(uncommonBits_70, UInt<5>(0h1f))
node _T_1008 = and(_T_1006, _T_1007)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0)
node _T_1009 = shr(io.in.a.bits.source, 5)
node _T_1010 = eq(_T_1009, UInt<3>(0h7))
node _T_1011 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_1012 = and(_T_1010, _T_1011)
node _T_1013 = leq(uncommonBits_71, UInt<5>(0h1f))
node _T_1014 = and(_T_1012, _T_1013)
node _T_1015 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1016 = or(_T_939, _T_945)
node _T_1017 = or(_T_1016, _T_951)
node _T_1018 = or(_T_1017, _T_957)
node _T_1019 = or(_T_1018, _T_963)
node _T_1020 = or(_T_1019, _T_964)
node _T_1021 = or(_T_1020, _T_965)
node _T_1022 = or(_T_1021, _T_966)
node _T_1023 = or(_T_1022, _T_972)
node _T_1024 = or(_T_1023, _T_978)
node _T_1025 = or(_T_1024, _T_984)
node _T_1026 = or(_T_1025, _T_990)
node _T_1027 = or(_T_1026, _T_996)
node _T_1028 = or(_T_1027, _T_1002)
node _T_1029 = or(_T_1028, _T_1008)
node _T_1030 = or(_T_1029, _T_1014)
node _T_1031 = or(_T_1030, _T_1015)
node _T_1032 = and(_T_938, _T_1031)
node _T_1033 = or(UInt<1>(0h0), _T_1032)
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_19
node _T_1037 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1038 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1039 = and(_T_1037, _T_1038)
node _T_1040 = or(UInt<1>(0h0), _T_1039)
node _T_1041 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1042 = cvt(_T_1041)
node _T_1043 = and(_T_1042, asSInt(UInt<13>(0h1000)))
node _T_1044 = asSInt(_T_1043)
node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0)))
node _T_1046 = and(_T_1040, _T_1045)
node _T_1047 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1048 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = or(UInt<1>(0h0), _T_1049)
node _T_1051 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1052 = cvt(_T_1051)
node _T_1053 = and(_T_1052, asSInt(UInt<14>(0h2000)))
node _T_1054 = asSInt(_T_1053)
node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0)))
node _T_1056 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1057 = cvt(_T_1056)
node _T_1058 = and(_T_1057, asSInt(UInt<17>(0h10000)))
node _T_1059 = asSInt(_T_1058)
node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0)))
node _T_1061 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1062 = cvt(_T_1061)
node _T_1063 = and(_T_1062, asSInt(UInt<18>(0h2f000)))
node _T_1064 = asSInt(_T_1063)
node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0)))
node _T_1066 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1067 = cvt(_T_1066)
node _T_1068 = and(_T_1067, asSInt(UInt<17>(0h10000)))
node _T_1069 = asSInt(_T_1068)
node _T_1070 = eq(_T_1069, asSInt(UInt<1>(0h0)))
node _T_1071 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1072 = cvt(_T_1071)
node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000)))
node _T_1074 = asSInt(_T_1073)
node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0)))
node _T_1076 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1077 = cvt(_T_1076)
node _T_1078 = and(_T_1077, asSInt(UInt<27>(0h4000000)))
node _T_1079 = asSInt(_T_1078)
node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0)))
node _T_1081 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1082 = cvt(_T_1081)
node _T_1083 = and(_T_1082, asSInt(UInt<13>(0h1000)))
node _T_1084 = asSInt(_T_1083)
node _T_1085 = eq(_T_1084, asSInt(UInt<1>(0h0)))
node _T_1086 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1087 = cvt(_T_1086)
node _T_1088 = and(_T_1087, asSInt(UInt<19>(0h40000)))
node _T_1089 = asSInt(_T_1088)
node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0)))
node _T_1091 = or(_T_1055, _T_1060)
node _T_1092 = or(_T_1091, _T_1065)
node _T_1093 = or(_T_1092, _T_1070)
node _T_1094 = or(_T_1093, _T_1075)
node _T_1095 = or(_T_1094, _T_1080)
node _T_1096 = or(_T_1095, _T_1085)
node _T_1097 = or(_T_1096, _T_1090)
node _T_1098 = and(_T_1050, _T_1097)
node _T_1099 = or(UInt<1>(0h0), _T_1046)
node _T_1100 = or(_T_1099, _T_1098)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_20
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(source_ok, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(is_aligned, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_1110 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_23
node _T_1114 = eq(io.in.a.bits.mask, mask)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_24
node _T_1118 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_25
node _T_1122 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1125 = and(_T_1123, _T_1124)
node _T_1126 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_1127 = shr(io.in.a.bits.source, 2)
node _T_1128 = eq(_T_1127, UInt<7>(0h40))
node _T_1129 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_1130 = and(_T_1128, _T_1129)
node _T_1131 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_1132 = and(_T_1130, _T_1131)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_1133 = shr(io.in.a.bits.source, 2)
node _T_1134 = eq(_T_1133, UInt<7>(0h41))
node _T_1135 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_1136 = and(_T_1134, _T_1135)
node _T_1137 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_1138 = and(_T_1136, _T_1137)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0)
node _T_1139 = shr(io.in.a.bits.source, 2)
node _T_1140 = eq(_T_1139, UInt<7>(0h42))
node _T_1141 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_1142 = and(_T_1140, _T_1141)
node _T_1143 = leq(uncommonBits_74, UInt<2>(0h3))
node _T_1144 = and(_T_1142, _T_1143)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_1145 = shr(io.in.a.bits.source, 2)
node _T_1146 = eq(_T_1145, UInt<7>(0h43))
node _T_1147 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1148 = and(_T_1146, _T_1147)
node _T_1149 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_1150 = and(_T_1148, _T_1149)
node _T_1151 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1152 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1153 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0)
node _T_1154 = shr(io.in.a.bits.source, 5)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
node _T_1156 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = leq(uncommonBits_76, UInt<5>(0h1f))
node _T_1159 = and(_T_1157, _T_1158)
node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0)
node _T_1160 = shr(io.in.a.bits.source, 5)
node _T_1161 = eq(_T_1160, UInt<1>(0h1))
node _T_1162 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_1163 = and(_T_1161, _T_1162)
node _T_1164 = leq(uncommonBits_77, UInt<5>(0h1f))
node _T_1165 = and(_T_1163, _T_1164)
node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0)
node _T_1166 = shr(io.in.a.bits.source, 5)
node _T_1167 = eq(_T_1166, UInt<2>(0h2))
node _T_1168 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_1169 = and(_T_1167, _T_1168)
node _T_1170 = leq(uncommonBits_78, UInt<5>(0h1f))
node _T_1171 = and(_T_1169, _T_1170)
node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0)
node _T_1172 = shr(io.in.a.bits.source, 5)
node _T_1173 = eq(_T_1172, UInt<2>(0h3))
node _T_1174 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_1175 = and(_T_1173, _T_1174)
node _T_1176 = leq(uncommonBits_79, UInt<5>(0h1f))
node _T_1177 = and(_T_1175, _T_1176)
node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0)
node _T_1178 = shr(io.in.a.bits.source, 5)
node _T_1179 = eq(_T_1178, UInt<3>(0h4))
node _T_1180 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_1181 = and(_T_1179, _T_1180)
node _T_1182 = leq(uncommonBits_80, UInt<5>(0h1f))
node _T_1183 = and(_T_1181, _T_1182)
node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0)
node _T_1184 = shr(io.in.a.bits.source, 5)
node _T_1185 = eq(_T_1184, UInt<3>(0h5))
node _T_1186 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_1187 = and(_T_1185, _T_1186)
node _T_1188 = leq(uncommonBits_81, UInt<5>(0h1f))
node _T_1189 = and(_T_1187, _T_1188)
node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0)
node _T_1190 = shr(io.in.a.bits.source, 5)
node _T_1191 = eq(_T_1190, UInt<3>(0h6))
node _T_1192 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_1193 = and(_T_1191, _T_1192)
node _T_1194 = leq(uncommonBits_82, UInt<5>(0h1f))
node _T_1195 = and(_T_1193, _T_1194)
node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0)
node _T_1196 = shr(io.in.a.bits.source, 5)
node _T_1197 = eq(_T_1196, UInt<3>(0h7))
node _T_1198 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_1199 = and(_T_1197, _T_1198)
node _T_1200 = leq(uncommonBits_83, UInt<5>(0h1f))
node _T_1201 = and(_T_1199, _T_1200)
node _T_1202 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1203 = or(_T_1126, _T_1132)
node _T_1204 = or(_T_1203, _T_1138)
node _T_1205 = or(_T_1204, _T_1144)
node _T_1206 = or(_T_1205, _T_1150)
node _T_1207 = or(_T_1206, _T_1151)
node _T_1208 = or(_T_1207, _T_1152)
node _T_1209 = or(_T_1208, _T_1153)
node _T_1210 = or(_T_1209, _T_1159)
node _T_1211 = or(_T_1210, _T_1165)
node _T_1212 = or(_T_1211, _T_1171)
node _T_1213 = or(_T_1212, _T_1177)
node _T_1214 = or(_T_1213, _T_1183)
node _T_1215 = or(_T_1214, _T_1189)
node _T_1216 = or(_T_1215, _T_1195)
node _T_1217 = or(_T_1216, _T_1201)
node _T_1218 = or(_T_1217, _T_1202)
node _T_1219 = and(_T_1125, _T_1218)
node _T_1220 = or(UInt<1>(0h0), _T_1219)
node _T_1221 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1222 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1223 = and(_T_1221, _T_1222)
node _T_1224 = or(UInt<1>(0h0), _T_1223)
node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1226 = cvt(_T_1225)
node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000)))
node _T_1228 = asSInt(_T_1227)
node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0)))
node _T_1230 = and(_T_1224, _T_1229)
node _T_1231 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1232 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1233 = and(_T_1231, _T_1232)
node _T_1234 = or(UInt<1>(0h0), _T_1233)
node _T_1235 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1236 = cvt(_T_1235)
node _T_1237 = and(_T_1236, asSInt(UInt<14>(0h2000)))
node _T_1238 = asSInt(_T_1237)
node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0)))
node _T_1240 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<18>(0h2f000)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1246 = cvt(_T_1245)
node _T_1247 = and(_T_1246, asSInt(UInt<17>(0h10000)))
node _T_1248 = asSInt(_T_1247)
node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0)))
node _T_1250 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1251 = cvt(_T_1250)
node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000)))
node _T_1253 = asSInt(_T_1252)
node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0)))
node _T_1255 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1256 = cvt(_T_1255)
node _T_1257 = and(_T_1256, asSInt(UInt<27>(0h4000000)))
node _T_1258 = asSInt(_T_1257)
node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0)))
node _T_1260 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1261 = cvt(_T_1260)
node _T_1262 = and(_T_1261, asSInt(UInt<13>(0h1000)))
node _T_1263 = asSInt(_T_1262)
node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0)))
node _T_1265 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1266 = cvt(_T_1265)
node _T_1267 = and(_T_1266, asSInt(UInt<19>(0h40000)))
node _T_1268 = asSInt(_T_1267)
node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0)))
node _T_1270 = or(_T_1239, _T_1244)
node _T_1271 = or(_T_1270, _T_1249)
node _T_1272 = or(_T_1271, _T_1254)
node _T_1273 = or(_T_1272, _T_1259)
node _T_1274 = or(_T_1273, _T_1264)
node _T_1275 = or(_T_1274, _T_1269)
node _T_1276 = and(_T_1234, _T_1275)
node _T_1277 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1278 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1279 = cvt(_T_1278)
node _T_1280 = and(_T_1279, asSInt(UInt<17>(0h10000)))
node _T_1281 = asSInt(_T_1280)
node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0)))
node _T_1283 = and(_T_1277, _T_1282)
node _T_1284 = or(UInt<1>(0h0), _T_1230)
node _T_1285 = or(_T_1284, _T_1276)
node _T_1286 = or(_T_1285, _T_1283)
node _T_1287 = and(_T_1220, _T_1286)
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_26
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(source_ok, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(is_aligned, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1297 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_29
node _T_1301 = eq(io.in.a.bits.mask, mask)
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(_T_1301, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1301, UInt<1>(0h1), "") : assert_30
node _T_1305 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1305 :
node _T_1306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1308 = and(_T_1306, _T_1307)
node _T_1309 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0)
node _T_1310 = shr(io.in.a.bits.source, 2)
node _T_1311 = eq(_T_1310, UInt<7>(0h40))
node _T_1312 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = leq(uncommonBits_84, UInt<2>(0h3))
node _T_1315 = and(_T_1313, _T_1314)
node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1316 = shr(io.in.a.bits.source, 2)
node _T_1317 = eq(_T_1316, UInt<7>(0h41))
node _T_1318 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1319 = and(_T_1317, _T_1318)
node _T_1320 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1321 = and(_T_1319, _T_1320)
node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1322 = shr(io.in.a.bits.source, 2)
node _T_1323 = eq(_T_1322, UInt<7>(0h42))
node _T_1324 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1325 = and(_T_1323, _T_1324)
node _T_1326 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1327 = and(_T_1325, _T_1326)
node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1328 = shr(io.in.a.bits.source, 2)
node _T_1329 = eq(_T_1328, UInt<7>(0h43))
node _T_1330 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1331 = and(_T_1329, _T_1330)
node _T_1332 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1333 = and(_T_1331, _T_1332)
node _T_1334 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1335 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1336 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0)
node _T_1337 = shr(io.in.a.bits.source, 5)
node _T_1338 = eq(_T_1337, UInt<1>(0h0))
node _T_1339 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1340 = and(_T_1338, _T_1339)
node _T_1341 = leq(uncommonBits_88, UInt<5>(0h1f))
node _T_1342 = and(_T_1340, _T_1341)
node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0)
node _T_1343 = shr(io.in.a.bits.source, 5)
node _T_1344 = eq(_T_1343, UInt<1>(0h1))
node _T_1345 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1346 = and(_T_1344, _T_1345)
node _T_1347 = leq(uncommonBits_89, UInt<5>(0h1f))
node _T_1348 = and(_T_1346, _T_1347)
node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0)
node _T_1349 = shr(io.in.a.bits.source, 5)
node _T_1350 = eq(_T_1349, UInt<2>(0h2))
node _T_1351 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_1352 = and(_T_1350, _T_1351)
node _T_1353 = leq(uncommonBits_90, UInt<5>(0h1f))
node _T_1354 = and(_T_1352, _T_1353)
node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0)
node _T_1355 = shr(io.in.a.bits.source, 5)
node _T_1356 = eq(_T_1355, UInt<2>(0h3))
node _T_1357 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_1358 = and(_T_1356, _T_1357)
node _T_1359 = leq(uncommonBits_91, UInt<5>(0h1f))
node _T_1360 = and(_T_1358, _T_1359)
node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0)
node _T_1361 = shr(io.in.a.bits.source, 5)
node _T_1362 = eq(_T_1361, UInt<3>(0h4))
node _T_1363 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_1364 = and(_T_1362, _T_1363)
node _T_1365 = leq(uncommonBits_92, UInt<5>(0h1f))
node _T_1366 = and(_T_1364, _T_1365)
node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0)
node _T_1367 = shr(io.in.a.bits.source, 5)
node _T_1368 = eq(_T_1367, UInt<3>(0h5))
node _T_1369 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_1370 = and(_T_1368, _T_1369)
node _T_1371 = leq(uncommonBits_93, UInt<5>(0h1f))
node _T_1372 = and(_T_1370, _T_1371)
node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0)
node _T_1373 = shr(io.in.a.bits.source, 5)
node _T_1374 = eq(_T_1373, UInt<3>(0h6))
node _T_1375 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_1376 = and(_T_1374, _T_1375)
node _T_1377 = leq(uncommonBits_94, UInt<5>(0h1f))
node _T_1378 = and(_T_1376, _T_1377)
node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0)
node _T_1379 = shr(io.in.a.bits.source, 5)
node _T_1380 = eq(_T_1379, UInt<3>(0h7))
node _T_1381 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_1382 = and(_T_1380, _T_1381)
node _T_1383 = leq(uncommonBits_95, UInt<5>(0h1f))
node _T_1384 = and(_T_1382, _T_1383)
node _T_1385 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1386 = or(_T_1309, _T_1315)
node _T_1387 = or(_T_1386, _T_1321)
node _T_1388 = or(_T_1387, _T_1327)
node _T_1389 = or(_T_1388, _T_1333)
node _T_1390 = or(_T_1389, _T_1334)
node _T_1391 = or(_T_1390, _T_1335)
node _T_1392 = or(_T_1391, _T_1336)
node _T_1393 = or(_T_1392, _T_1342)
node _T_1394 = or(_T_1393, _T_1348)
node _T_1395 = or(_T_1394, _T_1354)
node _T_1396 = or(_T_1395, _T_1360)
node _T_1397 = or(_T_1396, _T_1366)
node _T_1398 = or(_T_1397, _T_1372)
node _T_1399 = or(_T_1398, _T_1378)
node _T_1400 = or(_T_1399, _T_1384)
node _T_1401 = or(_T_1400, _T_1385)
node _T_1402 = and(_T_1308, _T_1401)
node _T_1403 = or(UInt<1>(0h0), _T_1402)
node _T_1404 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1405 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1406 = and(_T_1404, _T_1405)
node _T_1407 = or(UInt<1>(0h0), _T_1406)
node _T_1408 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1409 = cvt(_T_1408)
node _T_1410 = and(_T_1409, asSInt(UInt<13>(0h1000)))
node _T_1411 = asSInt(_T_1410)
node _T_1412 = eq(_T_1411, asSInt(UInt<1>(0h0)))
node _T_1413 = and(_T_1407, _T_1412)
node _T_1414 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1415 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1416 = and(_T_1414, _T_1415)
node _T_1417 = or(UInt<1>(0h0), _T_1416)
node _T_1418 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1419 = cvt(_T_1418)
node _T_1420 = and(_T_1419, asSInt(UInt<14>(0h2000)))
node _T_1421 = asSInt(_T_1420)
node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0)))
node _T_1423 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1424 = cvt(_T_1423)
node _T_1425 = and(_T_1424, asSInt(UInt<18>(0h2f000)))
node _T_1426 = asSInt(_T_1425)
node _T_1427 = eq(_T_1426, asSInt(UInt<1>(0h0)))
node _T_1428 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1429 = cvt(_T_1428)
node _T_1430 = and(_T_1429, asSInt(UInt<17>(0h10000)))
node _T_1431 = asSInt(_T_1430)
node _T_1432 = eq(_T_1431, asSInt(UInt<1>(0h0)))
node _T_1433 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1434 = cvt(_T_1433)
node _T_1435 = and(_T_1434, asSInt(UInt<13>(0h1000)))
node _T_1436 = asSInt(_T_1435)
node _T_1437 = eq(_T_1436, asSInt(UInt<1>(0h0)))
node _T_1438 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1439 = cvt(_T_1438)
node _T_1440 = and(_T_1439, asSInt(UInt<27>(0h4000000)))
node _T_1441 = asSInt(_T_1440)
node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0)))
node _T_1443 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1444 = cvt(_T_1443)
node _T_1445 = and(_T_1444, asSInt(UInt<13>(0h1000)))
node _T_1446 = asSInt(_T_1445)
node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0)))
node _T_1448 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1449 = cvt(_T_1448)
node _T_1450 = and(_T_1449, asSInt(UInt<19>(0h40000)))
node _T_1451 = asSInt(_T_1450)
node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0)))
node _T_1453 = or(_T_1422, _T_1427)
node _T_1454 = or(_T_1453, _T_1432)
node _T_1455 = or(_T_1454, _T_1437)
node _T_1456 = or(_T_1455, _T_1442)
node _T_1457 = or(_T_1456, _T_1447)
node _T_1458 = or(_T_1457, _T_1452)
node _T_1459 = and(_T_1417, _T_1458)
node _T_1460 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1461 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1462 = cvt(_T_1461)
node _T_1463 = and(_T_1462, asSInt(UInt<17>(0h10000)))
node _T_1464 = asSInt(_T_1463)
node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0)))
node _T_1466 = and(_T_1460, _T_1465)
node _T_1467 = or(UInt<1>(0h0), _T_1413)
node _T_1468 = or(_T_1467, _T_1459)
node _T_1469 = or(_T_1468, _T_1466)
node _T_1470 = and(_T_1403, _T_1469)
node _T_1471 = asUInt(reset)
node _T_1472 = eq(_T_1471, UInt<1>(0h0))
when _T_1472 :
node _T_1473 = eq(_T_1470, UInt<1>(0h0))
when _T_1473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1470, UInt<1>(0h1), "") : assert_31
node _T_1474 = asUInt(reset)
node _T_1475 = eq(_T_1474, UInt<1>(0h0))
when _T_1475 :
node _T_1476 = eq(source_ok, UInt<1>(0h0))
when _T_1476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(is_aligned, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1480 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1481 = asUInt(reset)
node _T_1482 = eq(_T_1481, UInt<1>(0h0))
when _T_1482 :
node _T_1483 = eq(_T_1480, UInt<1>(0h0))
when _T_1483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1480, UInt<1>(0h1), "") : assert_34
node _T_1484 = not(mask)
node _T_1485 = and(io.in.a.bits.mask, _T_1484)
node _T_1486 = eq(_T_1485, UInt<1>(0h0))
node _T_1487 = asUInt(reset)
node _T_1488 = eq(_T_1487, UInt<1>(0h0))
when _T_1488 :
node _T_1489 = eq(_T_1486, UInt<1>(0h0))
when _T_1489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1486, UInt<1>(0h1), "") : assert_35
node _T_1490 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1490 :
node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1492 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1493 = and(_T_1491, _T_1492)
node _T_1494 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0)
node _T_1495 = shr(io.in.a.bits.source, 2)
node _T_1496 = eq(_T_1495, UInt<7>(0h40))
node _T_1497 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1498 = and(_T_1496, _T_1497)
node _T_1499 = leq(uncommonBits_96, UInt<2>(0h3))
node _T_1500 = and(_T_1498, _T_1499)
node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0)
node _T_1501 = shr(io.in.a.bits.source, 2)
node _T_1502 = eq(_T_1501, UInt<7>(0h41))
node _T_1503 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1504 = and(_T_1502, _T_1503)
node _T_1505 = leq(uncommonBits_97, UInt<2>(0h3))
node _T_1506 = and(_T_1504, _T_1505)
node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0)
node _T_1507 = shr(io.in.a.bits.source, 2)
node _T_1508 = eq(_T_1507, UInt<7>(0h42))
node _T_1509 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1510 = and(_T_1508, _T_1509)
node _T_1511 = leq(uncommonBits_98, UInt<2>(0h3))
node _T_1512 = and(_T_1510, _T_1511)
node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0)
node _T_1513 = shr(io.in.a.bits.source, 2)
node _T_1514 = eq(_T_1513, UInt<7>(0h43))
node _T_1515 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1516 = and(_T_1514, _T_1515)
node _T_1517 = leq(uncommonBits_99, UInt<2>(0h3))
node _T_1518 = and(_T_1516, _T_1517)
node _T_1519 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1520 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1521 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0)
node _T_1522 = shr(io.in.a.bits.source, 5)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
node _T_1524 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1525 = and(_T_1523, _T_1524)
node _T_1526 = leq(uncommonBits_100, UInt<5>(0h1f))
node _T_1527 = and(_T_1525, _T_1526)
node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0)
node _T_1528 = shr(io.in.a.bits.source, 5)
node _T_1529 = eq(_T_1528, UInt<1>(0h1))
node _T_1530 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1531 = and(_T_1529, _T_1530)
node _T_1532 = leq(uncommonBits_101, UInt<5>(0h1f))
node _T_1533 = and(_T_1531, _T_1532)
node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0)
node _T_1534 = shr(io.in.a.bits.source, 5)
node _T_1535 = eq(_T_1534, UInt<2>(0h2))
node _T_1536 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1537 = and(_T_1535, _T_1536)
node _T_1538 = leq(uncommonBits_102, UInt<5>(0h1f))
node _T_1539 = and(_T_1537, _T_1538)
node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0)
node _T_1540 = shr(io.in.a.bits.source, 5)
node _T_1541 = eq(_T_1540, UInt<2>(0h3))
node _T_1542 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_1543 = and(_T_1541, _T_1542)
node _T_1544 = leq(uncommonBits_103, UInt<5>(0h1f))
node _T_1545 = and(_T_1543, _T_1544)
node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0)
node _T_1546 = shr(io.in.a.bits.source, 5)
node _T_1547 = eq(_T_1546, UInt<3>(0h4))
node _T_1548 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_1549 = and(_T_1547, _T_1548)
node _T_1550 = leq(uncommonBits_104, UInt<5>(0h1f))
node _T_1551 = and(_T_1549, _T_1550)
node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0)
node _T_1552 = shr(io.in.a.bits.source, 5)
node _T_1553 = eq(_T_1552, UInt<3>(0h5))
node _T_1554 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_1555 = and(_T_1553, _T_1554)
node _T_1556 = leq(uncommonBits_105, UInt<5>(0h1f))
node _T_1557 = and(_T_1555, _T_1556)
node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0)
node _T_1558 = shr(io.in.a.bits.source, 5)
node _T_1559 = eq(_T_1558, UInt<3>(0h6))
node _T_1560 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_1561 = and(_T_1559, _T_1560)
node _T_1562 = leq(uncommonBits_106, UInt<5>(0h1f))
node _T_1563 = and(_T_1561, _T_1562)
node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0)
node _T_1564 = shr(io.in.a.bits.source, 5)
node _T_1565 = eq(_T_1564, UInt<3>(0h7))
node _T_1566 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_1567 = and(_T_1565, _T_1566)
node _T_1568 = leq(uncommonBits_107, UInt<5>(0h1f))
node _T_1569 = and(_T_1567, _T_1568)
node _T_1570 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1571 = or(_T_1494, _T_1500)
node _T_1572 = or(_T_1571, _T_1506)
node _T_1573 = or(_T_1572, _T_1512)
node _T_1574 = or(_T_1573, _T_1518)
node _T_1575 = or(_T_1574, _T_1519)
node _T_1576 = or(_T_1575, _T_1520)
node _T_1577 = or(_T_1576, _T_1521)
node _T_1578 = or(_T_1577, _T_1527)
node _T_1579 = or(_T_1578, _T_1533)
node _T_1580 = or(_T_1579, _T_1539)
node _T_1581 = or(_T_1580, _T_1545)
node _T_1582 = or(_T_1581, _T_1551)
node _T_1583 = or(_T_1582, _T_1557)
node _T_1584 = or(_T_1583, _T_1563)
node _T_1585 = or(_T_1584, _T_1569)
node _T_1586 = or(_T_1585, _T_1570)
node _T_1587 = and(_T_1493, _T_1586)
node _T_1588 = or(UInt<1>(0h0), _T_1587)
node _T_1589 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1590 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1591 = and(_T_1589, _T_1590)
node _T_1592 = or(UInt<1>(0h0), _T_1591)
node _T_1593 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1594 = cvt(_T_1593)
node _T_1595 = and(_T_1594, asSInt(UInt<15>(0h5000)))
node _T_1596 = asSInt(_T_1595)
node _T_1597 = eq(_T_1596, asSInt(UInt<1>(0h0)))
node _T_1598 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1599 = cvt(_T_1598)
node _T_1600 = and(_T_1599, asSInt(UInt<13>(0h1000)))
node _T_1601 = asSInt(_T_1600)
node _T_1602 = eq(_T_1601, asSInt(UInt<1>(0h0)))
node _T_1603 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1604 = cvt(_T_1603)
node _T_1605 = and(_T_1604, asSInt(UInt<19>(0h40000)))
node _T_1606 = asSInt(_T_1605)
node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0)))
node _T_1608 = or(_T_1597, _T_1602)
node _T_1609 = or(_T_1608, _T_1607)
node _T_1610 = and(_T_1592, _T_1609)
node _T_1611 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1612 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1613 = cvt(_T_1612)
node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000)))
node _T_1615 = asSInt(_T_1614)
node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0)))
node _T_1617 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1618 = cvt(_T_1617)
node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000)))
node _T_1620 = asSInt(_T_1619)
node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0)))
node _T_1622 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1623 = cvt(_T_1622)
node _T_1624 = and(_T_1623, asSInt(UInt<18>(0h2f000)))
node _T_1625 = asSInt(_T_1624)
node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0)))
node _T_1627 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1628 = cvt(_T_1627)
node _T_1629 = and(_T_1628, asSInt(UInt<17>(0h10000)))
node _T_1630 = asSInt(_T_1629)
node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0)))
node _T_1632 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1633 = cvt(_T_1632)
node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000)))
node _T_1635 = asSInt(_T_1634)
node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0)))
node _T_1637 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1638 = cvt(_T_1637)
node _T_1639 = and(_T_1638, asSInt(UInt<27>(0h4000000)))
node _T_1640 = asSInt(_T_1639)
node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0)))
node _T_1642 = or(_T_1616, _T_1621)
node _T_1643 = or(_T_1642, _T_1626)
node _T_1644 = or(_T_1643, _T_1631)
node _T_1645 = or(_T_1644, _T_1636)
node _T_1646 = or(_T_1645, _T_1641)
node _T_1647 = and(_T_1611, _T_1646)
node _T_1648 = or(UInt<1>(0h0), _T_1610)
node _T_1649 = or(_T_1648, _T_1647)
node _T_1650 = and(_T_1588, _T_1649)
node _T_1651 = asUInt(reset)
node _T_1652 = eq(_T_1651, UInt<1>(0h0))
when _T_1652 :
node _T_1653 = eq(_T_1650, UInt<1>(0h0))
when _T_1653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1650, UInt<1>(0h1), "") : assert_36
node _T_1654 = asUInt(reset)
node _T_1655 = eq(_T_1654, UInt<1>(0h0))
when _T_1655 :
node _T_1656 = eq(source_ok, UInt<1>(0h0))
when _T_1656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1657 = asUInt(reset)
node _T_1658 = eq(_T_1657, UInt<1>(0h0))
when _T_1658 :
node _T_1659 = eq(is_aligned, UInt<1>(0h0))
when _T_1659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1660 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1661 = asUInt(reset)
node _T_1662 = eq(_T_1661, UInt<1>(0h0))
when _T_1662 :
node _T_1663 = eq(_T_1660, UInt<1>(0h0))
when _T_1663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1660, UInt<1>(0h1), "") : assert_39
node _T_1664 = eq(io.in.a.bits.mask, mask)
node _T_1665 = asUInt(reset)
node _T_1666 = eq(_T_1665, UInt<1>(0h0))
when _T_1666 :
node _T_1667 = eq(_T_1664, UInt<1>(0h0))
when _T_1667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1664, UInt<1>(0h1), "") : assert_40
node _T_1668 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1668 :
node _T_1669 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1670 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1671 = and(_T_1669, _T_1670)
node _T_1672 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0)
node _T_1673 = shr(io.in.a.bits.source, 2)
node _T_1674 = eq(_T_1673, UInt<7>(0h40))
node _T_1675 = leq(UInt<1>(0h0), uncommonBits_108)
node _T_1676 = and(_T_1674, _T_1675)
node _T_1677 = leq(uncommonBits_108, UInt<2>(0h3))
node _T_1678 = and(_T_1676, _T_1677)
node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0)
node _T_1679 = shr(io.in.a.bits.source, 2)
node _T_1680 = eq(_T_1679, UInt<7>(0h41))
node _T_1681 = leq(UInt<1>(0h0), uncommonBits_109)
node _T_1682 = and(_T_1680, _T_1681)
node _T_1683 = leq(uncommonBits_109, UInt<2>(0h3))
node _T_1684 = and(_T_1682, _T_1683)
node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0)
node _T_1685 = shr(io.in.a.bits.source, 2)
node _T_1686 = eq(_T_1685, UInt<7>(0h42))
node _T_1687 = leq(UInt<1>(0h0), uncommonBits_110)
node _T_1688 = and(_T_1686, _T_1687)
node _T_1689 = leq(uncommonBits_110, UInt<2>(0h3))
node _T_1690 = and(_T_1688, _T_1689)
node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0)
node _T_1691 = shr(io.in.a.bits.source, 2)
node _T_1692 = eq(_T_1691, UInt<7>(0h43))
node _T_1693 = leq(UInt<1>(0h0), uncommonBits_111)
node _T_1694 = and(_T_1692, _T_1693)
node _T_1695 = leq(uncommonBits_111, UInt<2>(0h3))
node _T_1696 = and(_T_1694, _T_1695)
node _T_1697 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1698 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1699 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0)
node _T_1700 = shr(io.in.a.bits.source, 5)
node _T_1701 = eq(_T_1700, UInt<1>(0h0))
node _T_1702 = leq(UInt<1>(0h0), uncommonBits_112)
node _T_1703 = and(_T_1701, _T_1702)
node _T_1704 = leq(uncommonBits_112, UInt<5>(0h1f))
node _T_1705 = and(_T_1703, _T_1704)
node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0)
node _T_1706 = shr(io.in.a.bits.source, 5)
node _T_1707 = eq(_T_1706, UInt<1>(0h1))
node _T_1708 = leq(UInt<1>(0h0), uncommonBits_113)
node _T_1709 = and(_T_1707, _T_1708)
node _T_1710 = leq(uncommonBits_113, UInt<5>(0h1f))
node _T_1711 = and(_T_1709, _T_1710)
node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0)
node _T_1712 = shr(io.in.a.bits.source, 5)
node _T_1713 = eq(_T_1712, UInt<2>(0h2))
node _T_1714 = leq(UInt<1>(0h0), uncommonBits_114)
node _T_1715 = and(_T_1713, _T_1714)
node _T_1716 = leq(uncommonBits_114, UInt<5>(0h1f))
node _T_1717 = and(_T_1715, _T_1716)
node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0)
node _T_1718 = shr(io.in.a.bits.source, 5)
node _T_1719 = eq(_T_1718, UInt<2>(0h3))
node _T_1720 = leq(UInt<1>(0h0), uncommonBits_115)
node _T_1721 = and(_T_1719, _T_1720)
node _T_1722 = leq(uncommonBits_115, UInt<5>(0h1f))
node _T_1723 = and(_T_1721, _T_1722)
node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0)
node _T_1724 = shr(io.in.a.bits.source, 5)
node _T_1725 = eq(_T_1724, UInt<3>(0h4))
node _T_1726 = leq(UInt<1>(0h0), uncommonBits_116)
node _T_1727 = and(_T_1725, _T_1726)
node _T_1728 = leq(uncommonBits_116, UInt<5>(0h1f))
node _T_1729 = and(_T_1727, _T_1728)
node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0)
node _T_1730 = shr(io.in.a.bits.source, 5)
node _T_1731 = eq(_T_1730, UInt<3>(0h5))
node _T_1732 = leq(UInt<1>(0h0), uncommonBits_117)
node _T_1733 = and(_T_1731, _T_1732)
node _T_1734 = leq(uncommonBits_117, UInt<5>(0h1f))
node _T_1735 = and(_T_1733, _T_1734)
node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0)
node _T_1736 = shr(io.in.a.bits.source, 5)
node _T_1737 = eq(_T_1736, UInt<3>(0h6))
node _T_1738 = leq(UInt<1>(0h0), uncommonBits_118)
node _T_1739 = and(_T_1737, _T_1738)
node _T_1740 = leq(uncommonBits_118, UInt<5>(0h1f))
node _T_1741 = and(_T_1739, _T_1740)
node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0)
node _T_1742 = shr(io.in.a.bits.source, 5)
node _T_1743 = eq(_T_1742, UInt<3>(0h7))
node _T_1744 = leq(UInt<1>(0h0), uncommonBits_119)
node _T_1745 = and(_T_1743, _T_1744)
node _T_1746 = leq(uncommonBits_119, UInt<5>(0h1f))
node _T_1747 = and(_T_1745, _T_1746)
node _T_1748 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1749 = or(_T_1672, _T_1678)
node _T_1750 = or(_T_1749, _T_1684)
node _T_1751 = or(_T_1750, _T_1690)
node _T_1752 = or(_T_1751, _T_1696)
node _T_1753 = or(_T_1752, _T_1697)
node _T_1754 = or(_T_1753, _T_1698)
node _T_1755 = or(_T_1754, _T_1699)
node _T_1756 = or(_T_1755, _T_1705)
node _T_1757 = or(_T_1756, _T_1711)
node _T_1758 = or(_T_1757, _T_1717)
node _T_1759 = or(_T_1758, _T_1723)
node _T_1760 = or(_T_1759, _T_1729)
node _T_1761 = or(_T_1760, _T_1735)
node _T_1762 = or(_T_1761, _T_1741)
node _T_1763 = or(_T_1762, _T_1747)
node _T_1764 = or(_T_1763, _T_1748)
node _T_1765 = and(_T_1671, _T_1764)
node _T_1766 = or(UInt<1>(0h0), _T_1765)
node _T_1767 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1768 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1769 = and(_T_1767, _T_1768)
node _T_1770 = or(UInt<1>(0h0), _T_1769)
node _T_1771 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1772 = cvt(_T_1771)
node _T_1773 = and(_T_1772, asSInt(UInt<15>(0h5000)))
node _T_1774 = asSInt(_T_1773)
node _T_1775 = eq(_T_1774, asSInt(UInt<1>(0h0)))
node _T_1776 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1777 = cvt(_T_1776)
node _T_1778 = and(_T_1777, asSInt(UInt<13>(0h1000)))
node _T_1779 = asSInt(_T_1778)
node _T_1780 = eq(_T_1779, asSInt(UInt<1>(0h0)))
node _T_1781 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1782 = cvt(_T_1781)
node _T_1783 = and(_T_1782, asSInt(UInt<19>(0h40000)))
node _T_1784 = asSInt(_T_1783)
node _T_1785 = eq(_T_1784, asSInt(UInt<1>(0h0)))
node _T_1786 = or(_T_1775, _T_1780)
node _T_1787 = or(_T_1786, _T_1785)
node _T_1788 = and(_T_1770, _T_1787)
node _T_1789 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1790 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1791 = cvt(_T_1790)
node _T_1792 = and(_T_1791, asSInt(UInt<13>(0h1000)))
node _T_1793 = asSInt(_T_1792)
node _T_1794 = eq(_T_1793, asSInt(UInt<1>(0h0)))
node _T_1795 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1796 = cvt(_T_1795)
node _T_1797 = and(_T_1796, asSInt(UInt<17>(0h10000)))
node _T_1798 = asSInt(_T_1797)
node _T_1799 = eq(_T_1798, asSInt(UInt<1>(0h0)))
node _T_1800 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1801 = cvt(_T_1800)
node _T_1802 = and(_T_1801, asSInt(UInt<18>(0h2f000)))
node _T_1803 = asSInt(_T_1802)
node _T_1804 = eq(_T_1803, asSInt(UInt<1>(0h0)))
node _T_1805 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1806 = cvt(_T_1805)
node _T_1807 = and(_T_1806, asSInt(UInt<17>(0h10000)))
node _T_1808 = asSInt(_T_1807)
node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0)))
node _T_1810 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1811 = cvt(_T_1810)
node _T_1812 = and(_T_1811, asSInt(UInt<13>(0h1000)))
node _T_1813 = asSInt(_T_1812)
node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0)))
node _T_1815 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1816 = cvt(_T_1815)
node _T_1817 = and(_T_1816, asSInt(UInt<27>(0h4000000)))
node _T_1818 = asSInt(_T_1817)
node _T_1819 = eq(_T_1818, asSInt(UInt<1>(0h0)))
node _T_1820 = or(_T_1794, _T_1799)
node _T_1821 = or(_T_1820, _T_1804)
node _T_1822 = or(_T_1821, _T_1809)
node _T_1823 = or(_T_1822, _T_1814)
node _T_1824 = or(_T_1823, _T_1819)
node _T_1825 = and(_T_1789, _T_1824)
node _T_1826 = or(UInt<1>(0h0), _T_1788)
node _T_1827 = or(_T_1826, _T_1825)
node _T_1828 = and(_T_1766, _T_1827)
node _T_1829 = asUInt(reset)
node _T_1830 = eq(_T_1829, UInt<1>(0h0))
when _T_1830 :
node _T_1831 = eq(_T_1828, UInt<1>(0h0))
when _T_1831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1828, UInt<1>(0h1), "") : assert_41
node _T_1832 = asUInt(reset)
node _T_1833 = eq(_T_1832, UInt<1>(0h0))
when _T_1833 :
node _T_1834 = eq(source_ok, UInt<1>(0h0))
when _T_1834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1835 = asUInt(reset)
node _T_1836 = eq(_T_1835, UInt<1>(0h0))
when _T_1836 :
node _T_1837 = eq(is_aligned, UInt<1>(0h0))
when _T_1837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1838 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1839 = asUInt(reset)
node _T_1840 = eq(_T_1839, UInt<1>(0h0))
when _T_1840 :
node _T_1841 = eq(_T_1838, UInt<1>(0h0))
when _T_1841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1838, UInt<1>(0h1), "") : assert_44
node _T_1842 = eq(io.in.a.bits.mask, mask)
node _T_1843 = asUInt(reset)
node _T_1844 = eq(_T_1843, UInt<1>(0h0))
when _T_1844 :
node _T_1845 = eq(_T_1842, UInt<1>(0h0))
when _T_1845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1842, UInt<1>(0h1), "") : assert_45
node _T_1846 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1846 :
node _T_1847 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1848 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1849 = and(_T_1847, _T_1848)
node _T_1850 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0)
node _T_1851 = shr(io.in.a.bits.source, 2)
node _T_1852 = eq(_T_1851, UInt<7>(0h40))
node _T_1853 = leq(UInt<1>(0h0), uncommonBits_120)
node _T_1854 = and(_T_1852, _T_1853)
node _T_1855 = leq(uncommonBits_120, UInt<2>(0h3))
node _T_1856 = and(_T_1854, _T_1855)
node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0)
node _T_1857 = shr(io.in.a.bits.source, 2)
node _T_1858 = eq(_T_1857, UInt<7>(0h41))
node _T_1859 = leq(UInt<1>(0h0), uncommonBits_121)
node _T_1860 = and(_T_1858, _T_1859)
node _T_1861 = leq(uncommonBits_121, UInt<2>(0h3))
node _T_1862 = and(_T_1860, _T_1861)
node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0)
node _T_1863 = shr(io.in.a.bits.source, 2)
node _T_1864 = eq(_T_1863, UInt<7>(0h42))
node _T_1865 = leq(UInt<1>(0h0), uncommonBits_122)
node _T_1866 = and(_T_1864, _T_1865)
node _T_1867 = leq(uncommonBits_122, UInt<2>(0h3))
node _T_1868 = and(_T_1866, _T_1867)
node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0)
node _T_1869 = shr(io.in.a.bits.source, 2)
node _T_1870 = eq(_T_1869, UInt<7>(0h43))
node _T_1871 = leq(UInt<1>(0h0), uncommonBits_123)
node _T_1872 = and(_T_1870, _T_1871)
node _T_1873 = leq(uncommonBits_123, UInt<2>(0h3))
node _T_1874 = and(_T_1872, _T_1873)
node _T_1875 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1876 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1877 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0)
node _T_1878 = shr(io.in.a.bits.source, 5)
node _T_1879 = eq(_T_1878, UInt<1>(0h0))
node _T_1880 = leq(UInt<1>(0h0), uncommonBits_124)
node _T_1881 = and(_T_1879, _T_1880)
node _T_1882 = leq(uncommonBits_124, UInt<5>(0h1f))
node _T_1883 = and(_T_1881, _T_1882)
node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0)
node _T_1884 = shr(io.in.a.bits.source, 5)
node _T_1885 = eq(_T_1884, UInt<1>(0h1))
node _T_1886 = leq(UInt<1>(0h0), uncommonBits_125)
node _T_1887 = and(_T_1885, _T_1886)
node _T_1888 = leq(uncommonBits_125, UInt<5>(0h1f))
node _T_1889 = and(_T_1887, _T_1888)
node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0)
node _T_1890 = shr(io.in.a.bits.source, 5)
node _T_1891 = eq(_T_1890, UInt<2>(0h2))
node _T_1892 = leq(UInt<1>(0h0), uncommonBits_126)
node _T_1893 = and(_T_1891, _T_1892)
node _T_1894 = leq(uncommonBits_126, UInt<5>(0h1f))
node _T_1895 = and(_T_1893, _T_1894)
node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0)
node _T_1896 = shr(io.in.a.bits.source, 5)
node _T_1897 = eq(_T_1896, UInt<2>(0h3))
node _T_1898 = leq(UInt<1>(0h0), uncommonBits_127)
node _T_1899 = and(_T_1897, _T_1898)
node _T_1900 = leq(uncommonBits_127, UInt<5>(0h1f))
node _T_1901 = and(_T_1899, _T_1900)
node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0)
node _T_1902 = shr(io.in.a.bits.source, 5)
node _T_1903 = eq(_T_1902, UInt<3>(0h4))
node _T_1904 = leq(UInt<1>(0h0), uncommonBits_128)
node _T_1905 = and(_T_1903, _T_1904)
node _T_1906 = leq(uncommonBits_128, UInt<5>(0h1f))
node _T_1907 = and(_T_1905, _T_1906)
node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0)
node _T_1908 = shr(io.in.a.bits.source, 5)
node _T_1909 = eq(_T_1908, UInt<3>(0h5))
node _T_1910 = leq(UInt<1>(0h0), uncommonBits_129)
node _T_1911 = and(_T_1909, _T_1910)
node _T_1912 = leq(uncommonBits_129, UInt<5>(0h1f))
node _T_1913 = and(_T_1911, _T_1912)
node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0)
node _T_1914 = shr(io.in.a.bits.source, 5)
node _T_1915 = eq(_T_1914, UInt<3>(0h6))
node _T_1916 = leq(UInt<1>(0h0), uncommonBits_130)
node _T_1917 = and(_T_1915, _T_1916)
node _T_1918 = leq(uncommonBits_130, UInt<5>(0h1f))
node _T_1919 = and(_T_1917, _T_1918)
node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0)
node _T_1920 = shr(io.in.a.bits.source, 5)
node _T_1921 = eq(_T_1920, UInt<3>(0h7))
node _T_1922 = leq(UInt<1>(0h0), uncommonBits_131)
node _T_1923 = and(_T_1921, _T_1922)
node _T_1924 = leq(uncommonBits_131, UInt<5>(0h1f))
node _T_1925 = and(_T_1923, _T_1924)
node _T_1926 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1927 = or(_T_1850, _T_1856)
node _T_1928 = or(_T_1927, _T_1862)
node _T_1929 = or(_T_1928, _T_1868)
node _T_1930 = or(_T_1929, _T_1874)
node _T_1931 = or(_T_1930, _T_1875)
node _T_1932 = or(_T_1931, _T_1876)
node _T_1933 = or(_T_1932, _T_1877)
node _T_1934 = or(_T_1933, _T_1883)
node _T_1935 = or(_T_1934, _T_1889)
node _T_1936 = or(_T_1935, _T_1895)
node _T_1937 = or(_T_1936, _T_1901)
node _T_1938 = or(_T_1937, _T_1907)
node _T_1939 = or(_T_1938, _T_1913)
node _T_1940 = or(_T_1939, _T_1919)
node _T_1941 = or(_T_1940, _T_1925)
node _T_1942 = or(_T_1941, _T_1926)
node _T_1943 = and(_T_1849, _T_1942)
node _T_1944 = or(UInt<1>(0h0), _T_1943)
node _T_1945 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1946 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1947 = and(_T_1945, _T_1946)
node _T_1948 = or(UInt<1>(0h0), _T_1947)
node _T_1949 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1950 = cvt(_T_1949)
node _T_1951 = and(_T_1950, asSInt(UInt<13>(0h1000)))
node _T_1952 = asSInt(_T_1951)
node _T_1953 = eq(_T_1952, asSInt(UInt<1>(0h0)))
node _T_1954 = and(_T_1948, _T_1953)
node _T_1955 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1956 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1957 = cvt(_T_1956)
node _T_1958 = and(_T_1957, asSInt(UInt<14>(0h2000)))
node _T_1959 = asSInt(_T_1958)
node _T_1960 = eq(_T_1959, asSInt(UInt<1>(0h0)))
node _T_1961 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1962 = cvt(_T_1961)
node _T_1963 = and(_T_1962, asSInt(UInt<17>(0h10000)))
node _T_1964 = asSInt(_T_1963)
node _T_1965 = eq(_T_1964, asSInt(UInt<1>(0h0)))
node _T_1966 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1967 = cvt(_T_1966)
node _T_1968 = and(_T_1967, asSInt(UInt<18>(0h2f000)))
node _T_1969 = asSInt(_T_1968)
node _T_1970 = eq(_T_1969, asSInt(UInt<1>(0h0)))
node _T_1971 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1972 = cvt(_T_1971)
node _T_1973 = and(_T_1972, asSInt(UInt<17>(0h10000)))
node _T_1974 = asSInt(_T_1973)
node _T_1975 = eq(_T_1974, asSInt(UInt<1>(0h0)))
node _T_1976 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1977 = cvt(_T_1976)
node _T_1978 = and(_T_1977, asSInt(UInt<13>(0h1000)))
node _T_1979 = asSInt(_T_1978)
node _T_1980 = eq(_T_1979, asSInt(UInt<1>(0h0)))
node _T_1981 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1982 = cvt(_T_1981)
node _T_1983 = and(_T_1982, asSInt(UInt<27>(0h4000000)))
node _T_1984 = asSInt(_T_1983)
node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0)))
node _T_1986 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1987 = cvt(_T_1986)
node _T_1988 = and(_T_1987, asSInt(UInt<13>(0h1000)))
node _T_1989 = asSInt(_T_1988)
node _T_1990 = eq(_T_1989, asSInt(UInt<1>(0h0)))
node _T_1991 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1992 = cvt(_T_1991)
node _T_1993 = and(_T_1992, asSInt(UInt<19>(0h40000)))
node _T_1994 = asSInt(_T_1993)
node _T_1995 = eq(_T_1994, asSInt(UInt<1>(0h0)))
node _T_1996 = or(_T_1960, _T_1965)
node _T_1997 = or(_T_1996, _T_1970)
node _T_1998 = or(_T_1997, _T_1975)
node _T_1999 = or(_T_1998, _T_1980)
node _T_2000 = or(_T_1999, _T_1985)
node _T_2001 = or(_T_2000, _T_1990)
node _T_2002 = or(_T_2001, _T_1995)
node _T_2003 = and(_T_1955, _T_2002)
node _T_2004 = or(UInt<1>(0h0), _T_1954)
node _T_2005 = or(_T_2004, _T_2003)
node _T_2006 = and(_T_1944, _T_2005)
node _T_2007 = asUInt(reset)
node _T_2008 = eq(_T_2007, UInt<1>(0h0))
when _T_2008 :
node _T_2009 = eq(_T_2006, UInt<1>(0h0))
when _T_2009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_2006, UInt<1>(0h1), "") : assert_46
node _T_2010 = asUInt(reset)
node _T_2011 = eq(_T_2010, UInt<1>(0h0))
when _T_2011 :
node _T_2012 = eq(source_ok, UInt<1>(0h0))
when _T_2012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_2013 = asUInt(reset)
node _T_2014 = eq(_T_2013, UInt<1>(0h0))
when _T_2014 :
node _T_2015 = eq(is_aligned, UInt<1>(0h0))
when _T_2015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_2016 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_2017 = asUInt(reset)
node _T_2018 = eq(_T_2017, UInt<1>(0h0))
when _T_2018 :
node _T_2019 = eq(_T_2016, UInt<1>(0h0))
when _T_2019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_2016, UInt<1>(0h1), "") : assert_49
node _T_2020 = eq(io.in.a.bits.mask, mask)
node _T_2021 = asUInt(reset)
node _T_2022 = eq(_T_2021, UInt<1>(0h0))
when _T_2022 :
node _T_2023 = eq(_T_2020, UInt<1>(0h0))
when _T_2023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_2020, UInt<1>(0h1), "") : assert_50
node _T_2024 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_2025 = asUInt(reset)
node _T_2026 = eq(_T_2025, UInt<1>(0h0))
when _T_2026 :
node _T_2027 = eq(_T_2024, UInt<1>(0h0))
when _T_2027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_2024, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_2028 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2029 = asUInt(reset)
node _T_2030 = eq(_T_2029, UInt<1>(0h0))
when _T_2030 :
node _T_2031 = eq(_T_2028, UInt<1>(0h0))
when _T_2031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_2028, UInt<1>(0h1), "") : assert_52
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_93 = shr(io.in.d.bits.source, 2)
node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40))
node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_99 = shr(io.in.d.bits.source, 2)
node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41))
node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103)
node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0)
node _source_ok_T_105 = shr(io.in.d.bits.source, 2)
node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42))
node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3))
node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109)
node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0)
node _source_ok_T_111 = shr(io.in.d.bits.source, 2)
node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43))
node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3))
node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115)
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0)
node _source_ok_T_120 = shr(io.in.d.bits.source, 5)
node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0))
node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122)
node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f))
node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124)
node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0)
node _source_ok_T_126 = shr(io.in.d.bits.source, 5)
node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1))
node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128)
node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f))
node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130)
node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0)
node _source_ok_T_132 = shr(io.in.d.bits.source, 5)
node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2))
node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18)
node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134)
node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f))
node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136)
node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0)
node _source_ok_T_138 = shr(io.in.d.bits.source, 5)
node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3))
node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19)
node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140)
node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f))
node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142)
node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0)
node _source_ok_T_144 = shr(io.in.d.bits.source, 5)
node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4))
node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20)
node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146)
node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f))
node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148)
node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0)
node _source_ok_T_150 = shr(io.in.d.bits.source, 5)
node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5))
node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21)
node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152)
node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f))
node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154)
node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0)
node _source_ok_T_156 = shr(io.in.d.bits.source, 5)
node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6))
node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22)
node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158)
node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f))
node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160)
node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0)
node _source_ok_T_162 = shr(io.in.d.bits.source, 5)
node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7))
node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23)
node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164)
node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f))
node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166)
node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE_1 : UInt<1>[17]
connect _source_ok_WIRE_1[0], _source_ok_T_92
connect _source_ok_WIRE_1[1], _source_ok_T_98
connect _source_ok_WIRE_1[2], _source_ok_T_104
connect _source_ok_WIRE_1[3], _source_ok_T_110
connect _source_ok_WIRE_1[4], _source_ok_T_116
connect _source_ok_WIRE_1[5], _source_ok_T_117
connect _source_ok_WIRE_1[6], _source_ok_T_118
connect _source_ok_WIRE_1[7], _source_ok_T_119
connect _source_ok_WIRE_1[8], _source_ok_T_125
connect _source_ok_WIRE_1[9], _source_ok_T_131
connect _source_ok_WIRE_1[10], _source_ok_T_137
connect _source_ok_WIRE_1[11], _source_ok_T_143
connect _source_ok_WIRE_1[12], _source_ok_T_149
connect _source_ok_WIRE_1[13], _source_ok_T_155
connect _source_ok_WIRE_1[14], _source_ok_T_161
connect _source_ok_WIRE_1[15], _source_ok_T_167
connect _source_ok_WIRE_1[16], _source_ok_T_168
node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2])
node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3])
node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4])
node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5])
node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6])
node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7])
node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8])
node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9])
node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10])
node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11])
node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12])
node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13])
node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14])
node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15])
node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_2032 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_2032 :
node _T_2033 = asUInt(reset)
node _T_2034 = eq(_T_2033, UInt<1>(0h0))
when _T_2034 :
node _T_2035 = eq(source_ok_1, UInt<1>(0h0))
when _T_2035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_2036 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2037 = asUInt(reset)
node _T_2038 = eq(_T_2037, UInt<1>(0h0))
when _T_2038 :
node _T_2039 = eq(_T_2036, UInt<1>(0h0))
when _T_2039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_2036, UInt<1>(0h1), "") : assert_54
node _T_2040 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2041 = asUInt(reset)
node _T_2042 = eq(_T_2041, UInt<1>(0h0))
when _T_2042 :
node _T_2043 = eq(_T_2040, UInt<1>(0h0))
when _T_2043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_2040, UInt<1>(0h1), "") : assert_55
node _T_2044 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2045 = asUInt(reset)
node _T_2046 = eq(_T_2045, UInt<1>(0h0))
when _T_2046 :
node _T_2047 = eq(_T_2044, UInt<1>(0h0))
when _T_2047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_2044, UInt<1>(0h1), "") : assert_56
node _T_2048 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2049 = asUInt(reset)
node _T_2050 = eq(_T_2049, UInt<1>(0h0))
when _T_2050 :
node _T_2051 = eq(_T_2048, UInt<1>(0h0))
when _T_2051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_2048, UInt<1>(0h1), "") : assert_57
node _T_2052 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_2052 :
node _T_2053 = asUInt(reset)
node _T_2054 = eq(_T_2053, UInt<1>(0h0))
when _T_2054 :
node _T_2055 = eq(source_ok_1, UInt<1>(0h0))
when _T_2055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_2056 = asUInt(reset)
node _T_2057 = eq(_T_2056, UInt<1>(0h0))
when _T_2057 :
node _T_2058 = eq(sink_ok, UInt<1>(0h0))
when _T_2058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_2059 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2060 = asUInt(reset)
node _T_2061 = eq(_T_2060, UInt<1>(0h0))
when _T_2061 :
node _T_2062 = eq(_T_2059, UInt<1>(0h0))
when _T_2062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_2059, UInt<1>(0h1), "") : assert_60
node _T_2063 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2064 = asUInt(reset)
node _T_2065 = eq(_T_2064, UInt<1>(0h0))
when _T_2065 :
node _T_2066 = eq(_T_2063, UInt<1>(0h0))
when _T_2066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_2063, UInt<1>(0h1), "") : assert_61
node _T_2067 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2068 = asUInt(reset)
node _T_2069 = eq(_T_2068, UInt<1>(0h0))
when _T_2069 :
node _T_2070 = eq(_T_2067, UInt<1>(0h0))
when _T_2070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_2067, UInt<1>(0h1), "") : assert_62
node _T_2071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2072 = asUInt(reset)
node _T_2073 = eq(_T_2072, UInt<1>(0h0))
when _T_2073 :
node _T_2074 = eq(_T_2071, UInt<1>(0h0))
when _T_2074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_2071, UInt<1>(0h1), "") : assert_63
node _T_2075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2076 = or(UInt<1>(0h1), _T_2075)
node _T_2077 = asUInt(reset)
node _T_2078 = eq(_T_2077, UInt<1>(0h0))
when _T_2078 :
node _T_2079 = eq(_T_2076, UInt<1>(0h0))
when _T_2079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_2076, UInt<1>(0h1), "") : assert_64
node _T_2080 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_2080 :
node _T_2081 = asUInt(reset)
node _T_2082 = eq(_T_2081, UInt<1>(0h0))
when _T_2082 :
node _T_2083 = eq(source_ok_1, UInt<1>(0h0))
when _T_2083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_2084 = asUInt(reset)
node _T_2085 = eq(_T_2084, UInt<1>(0h0))
when _T_2085 :
node _T_2086 = eq(sink_ok, UInt<1>(0h0))
when _T_2086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_2087 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2088 = asUInt(reset)
node _T_2089 = eq(_T_2088, UInt<1>(0h0))
when _T_2089 :
node _T_2090 = eq(_T_2087, UInt<1>(0h0))
when _T_2090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_2087, UInt<1>(0h1), "") : assert_67
node _T_2091 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2092 = asUInt(reset)
node _T_2093 = eq(_T_2092, UInt<1>(0h0))
when _T_2093 :
node _T_2094 = eq(_T_2091, UInt<1>(0h0))
when _T_2094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_2091, UInt<1>(0h1), "") : assert_68
node _T_2095 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2096 = asUInt(reset)
node _T_2097 = eq(_T_2096, UInt<1>(0h0))
when _T_2097 :
node _T_2098 = eq(_T_2095, UInt<1>(0h0))
when _T_2098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_2095, UInt<1>(0h1), "") : assert_69
node _T_2099 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2100 = or(_T_2099, io.in.d.bits.corrupt)
node _T_2101 = asUInt(reset)
node _T_2102 = eq(_T_2101, UInt<1>(0h0))
when _T_2102 :
node _T_2103 = eq(_T_2100, UInt<1>(0h0))
when _T_2103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_2100, UInt<1>(0h1), "") : assert_70
node _T_2104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2105 = or(UInt<1>(0h1), _T_2104)
node _T_2106 = asUInt(reset)
node _T_2107 = eq(_T_2106, UInt<1>(0h0))
when _T_2107 :
node _T_2108 = eq(_T_2105, UInt<1>(0h0))
when _T_2108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_2105, UInt<1>(0h1), "") : assert_71
node _T_2109 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_2109 :
node _T_2110 = asUInt(reset)
node _T_2111 = eq(_T_2110, UInt<1>(0h0))
when _T_2111 :
node _T_2112 = eq(source_ok_1, UInt<1>(0h0))
when _T_2112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_2113 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2114 = asUInt(reset)
node _T_2115 = eq(_T_2114, UInt<1>(0h0))
when _T_2115 :
node _T_2116 = eq(_T_2113, UInt<1>(0h0))
when _T_2116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_2113, UInt<1>(0h1), "") : assert_73
node _T_2117 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2118 = asUInt(reset)
node _T_2119 = eq(_T_2118, UInt<1>(0h0))
when _T_2119 :
node _T_2120 = eq(_T_2117, UInt<1>(0h0))
when _T_2120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_2117, UInt<1>(0h1), "") : assert_74
node _T_2121 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2122 = or(UInt<1>(0h1), _T_2121)
node _T_2123 = asUInt(reset)
node _T_2124 = eq(_T_2123, UInt<1>(0h0))
when _T_2124 :
node _T_2125 = eq(_T_2122, UInt<1>(0h0))
when _T_2125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_2122, UInt<1>(0h1), "") : assert_75
node _T_2126 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_2126 :
node _T_2127 = asUInt(reset)
node _T_2128 = eq(_T_2127, UInt<1>(0h0))
when _T_2128 :
node _T_2129 = eq(source_ok_1, UInt<1>(0h0))
when _T_2129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_2130 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2131 = asUInt(reset)
node _T_2132 = eq(_T_2131, UInt<1>(0h0))
when _T_2132 :
node _T_2133 = eq(_T_2130, UInt<1>(0h0))
when _T_2133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_2130, UInt<1>(0h1), "") : assert_77
node _T_2134 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2135 = or(_T_2134, io.in.d.bits.corrupt)
node _T_2136 = asUInt(reset)
node _T_2137 = eq(_T_2136, UInt<1>(0h0))
when _T_2137 :
node _T_2138 = eq(_T_2135, UInt<1>(0h0))
when _T_2138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_2135, UInt<1>(0h1), "") : assert_78
node _T_2139 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2140 = or(UInt<1>(0h1), _T_2139)
node _T_2141 = asUInt(reset)
node _T_2142 = eq(_T_2141, UInt<1>(0h0))
when _T_2142 :
node _T_2143 = eq(_T_2140, UInt<1>(0h0))
when _T_2143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_2140, UInt<1>(0h1), "") : assert_79
node _T_2144 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_2144 :
node _T_2145 = asUInt(reset)
node _T_2146 = eq(_T_2145, UInt<1>(0h0))
when _T_2146 :
node _T_2147 = eq(source_ok_1, UInt<1>(0h0))
when _T_2147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_2148 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2149 = asUInt(reset)
node _T_2150 = eq(_T_2149, UInt<1>(0h0))
when _T_2150 :
node _T_2151 = eq(_T_2148, UInt<1>(0h0))
when _T_2151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_2148, UInt<1>(0h1), "") : assert_81
node _T_2152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2153 = asUInt(reset)
node _T_2154 = eq(_T_2153, UInt<1>(0h0))
when _T_2154 :
node _T_2155 = eq(_T_2152, UInt<1>(0h0))
when _T_2155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_2152, UInt<1>(0h1), "") : assert_82
node _T_2156 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2157 = or(UInt<1>(0h1), _T_2156)
node _T_2158 = asUInt(reset)
node _T_2159 = eq(_T_2158, UInt<1>(0h0))
when _T_2159 :
node _T_2160 = eq(_T_2157, UInt<1>(0h0))
when _T_2160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_2157, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<10>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_2161 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_2162 = asUInt(reset)
node _T_2163 = eq(_T_2162, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = eq(_T_2161, UInt<1>(0h0))
when _T_2164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_2161, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<10>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_2165 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_2166 = asUInt(reset)
node _T_2167 = eq(_T_2166, UInt<1>(0h0))
when _T_2167 :
node _T_2168 = eq(_T_2165, UInt<1>(0h0))
when _T_2168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_2165, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_2169 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_2170 = asUInt(reset)
node _T_2171 = eq(_T_2170, UInt<1>(0h0))
when _T_2171 :
node _T_2172 = eq(_T_2169, UInt<1>(0h0))
when _T_2172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_2169, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2173 = eq(a_first, UInt<1>(0h0))
node _T_2174 = and(io.in.a.valid, _T_2173)
when _T_2174 :
node _T_2175 = eq(io.in.a.bits.opcode, opcode)
node _T_2176 = asUInt(reset)
node _T_2177 = eq(_T_2176, UInt<1>(0h0))
when _T_2177 :
node _T_2178 = eq(_T_2175, UInt<1>(0h0))
when _T_2178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_2175, UInt<1>(0h1), "") : assert_87
node _T_2179 = eq(io.in.a.bits.param, param)
node _T_2180 = asUInt(reset)
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
when _T_2181 :
node _T_2182 = eq(_T_2179, UInt<1>(0h0))
when _T_2182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_2179, UInt<1>(0h1), "") : assert_88
node _T_2183 = eq(io.in.a.bits.size, size)
node _T_2184 = asUInt(reset)
node _T_2185 = eq(_T_2184, UInt<1>(0h0))
when _T_2185 :
node _T_2186 = eq(_T_2183, UInt<1>(0h0))
when _T_2186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_2183, UInt<1>(0h1), "") : assert_89
node _T_2187 = eq(io.in.a.bits.source, source)
node _T_2188 = asUInt(reset)
node _T_2189 = eq(_T_2188, UInt<1>(0h0))
when _T_2189 :
node _T_2190 = eq(_T_2187, UInt<1>(0h0))
when _T_2190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_2187, UInt<1>(0h1), "") : assert_90
node _T_2191 = eq(io.in.a.bits.address, address)
node _T_2192 = asUInt(reset)
node _T_2193 = eq(_T_2192, UInt<1>(0h0))
when _T_2193 :
node _T_2194 = eq(_T_2191, UInt<1>(0h0))
when _T_2194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_2191, UInt<1>(0h1), "") : assert_91
node _T_2195 = and(io.in.a.ready, io.in.a.valid)
node _T_2196 = and(_T_2195, a_first)
when _T_2196 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2197 = eq(d_first, UInt<1>(0h0))
node _T_2198 = and(io.in.d.valid, _T_2197)
when _T_2198 :
node _T_2199 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2200 = asUInt(reset)
node _T_2201 = eq(_T_2200, UInt<1>(0h0))
when _T_2201 :
node _T_2202 = eq(_T_2199, UInt<1>(0h0))
when _T_2202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_2199, UInt<1>(0h1), "") : assert_92
node _T_2203 = eq(io.in.d.bits.param, param_1)
node _T_2204 = asUInt(reset)
node _T_2205 = eq(_T_2204, UInt<1>(0h0))
when _T_2205 :
node _T_2206 = eq(_T_2203, UInt<1>(0h0))
when _T_2206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_2203, UInt<1>(0h1), "") : assert_93
node _T_2207 = eq(io.in.d.bits.size, size_1)
node _T_2208 = asUInt(reset)
node _T_2209 = eq(_T_2208, UInt<1>(0h0))
when _T_2209 :
node _T_2210 = eq(_T_2207, UInt<1>(0h0))
when _T_2210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_2207, UInt<1>(0h1), "") : assert_94
node _T_2211 = eq(io.in.d.bits.source, source_1)
node _T_2212 = asUInt(reset)
node _T_2213 = eq(_T_2212, UInt<1>(0h0))
when _T_2213 :
node _T_2214 = eq(_T_2211, UInt<1>(0h0))
when _T_2214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_2211, UInt<1>(0h1), "") : assert_95
node _T_2215 = eq(io.in.d.bits.sink, sink)
node _T_2216 = asUInt(reset)
node _T_2217 = eq(_T_2216, UInt<1>(0h0))
when _T_2217 :
node _T_2218 = eq(_T_2215, UInt<1>(0h0))
when _T_2218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_2215, UInt<1>(0h1), "") : assert_96
node _T_2219 = eq(io.in.d.bits.denied, denied)
node _T_2220 = asUInt(reset)
node _T_2221 = eq(_T_2220, UInt<1>(0h0))
when _T_2221 :
node _T_2222 = eq(_T_2219, UInt<1>(0h0))
when _T_2222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_2219, UInt<1>(0h1), "") : assert_97
node _T_2223 = and(io.in.d.ready, io.in.d.valid)
node _T_2224 = and(_T_2223, d_first)
when _T_2224 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes : UInt<4104>, clock, reset, UInt<4104>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<513>
connect a_set, UInt<513>(0h0)
wire a_set_wo_ready : UInt<513>
connect a_set_wo_ready, UInt<513>(0h0)
wire a_opcodes_set : UInt<2052>
connect a_opcodes_set, UInt<2052>(0h0)
wire a_sizes_set : UInt<4104>
connect a_sizes_set, UInt<4104>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2225 = and(io.in.a.valid, a_first_1)
node _T_2226 = and(_T_2225, UInt<1>(0h1))
when _T_2226 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2227 = and(io.in.a.ready, io.in.a.valid)
node _T_2228 = and(_T_2227, a_first_1)
node _T_2229 = and(_T_2228, UInt<1>(0h1))
when _T_2229 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2230 = dshr(inflight, io.in.a.bits.source)
node _T_2231 = bits(_T_2230, 0, 0)
node _T_2232 = eq(_T_2231, UInt<1>(0h0))
node _T_2233 = asUInt(reset)
node _T_2234 = eq(_T_2233, UInt<1>(0h0))
when _T_2234 :
node _T_2235 = eq(_T_2232, UInt<1>(0h0))
when _T_2235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_2232, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<513>
connect d_clr, UInt<513>(0h0)
wire d_clr_wo_ready : UInt<513>
connect d_clr_wo_ready, UInt<513>(0h0)
wire d_opcodes_clr : UInt<2052>
connect d_opcodes_clr, UInt<2052>(0h0)
wire d_sizes_clr : UInt<4104>
connect d_sizes_clr, UInt<4104>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2236 = and(io.in.d.valid, d_first_1)
node _T_2237 = and(_T_2236, UInt<1>(0h1))
node _T_2238 = eq(d_release_ack, UInt<1>(0h0))
node _T_2239 = and(_T_2237, _T_2238)
when _T_2239 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2240 = and(io.in.d.ready, io.in.d.valid)
node _T_2241 = and(_T_2240, d_first_1)
node _T_2242 = and(_T_2241, UInt<1>(0h1))
node _T_2243 = eq(d_release_ack, UInt<1>(0h0))
node _T_2244 = and(_T_2242, _T_2243)
when _T_2244 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2245 = and(io.in.d.valid, d_first_1)
node _T_2246 = and(_T_2245, UInt<1>(0h1))
node _T_2247 = eq(d_release_ack, UInt<1>(0h0))
node _T_2248 = and(_T_2246, _T_2247)
when _T_2248 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2249 = dshr(inflight, io.in.d.bits.source)
node _T_2250 = bits(_T_2249, 0, 0)
node _T_2251 = or(_T_2250, same_cycle_resp)
node _T_2252 = asUInt(reset)
node _T_2253 = eq(_T_2252, UInt<1>(0h0))
when _T_2253 :
node _T_2254 = eq(_T_2251, UInt<1>(0h0))
when _T_2254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_2251, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_2255 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2256 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2257 = or(_T_2255, _T_2256)
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
node _T_2260 = eq(_T_2257, UInt<1>(0h0))
when _T_2260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_2257, UInt<1>(0h1), "") : assert_100
node _T_2261 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2262 = asUInt(reset)
node _T_2263 = eq(_T_2262, UInt<1>(0h0))
when _T_2263 :
node _T_2264 = eq(_T_2261, UInt<1>(0h0))
when _T_2264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_2261, UInt<1>(0h1), "") : assert_101
else :
node _T_2265 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2266 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2267 = or(_T_2265, _T_2266)
node _T_2268 = asUInt(reset)
node _T_2269 = eq(_T_2268, UInt<1>(0h0))
when _T_2269 :
node _T_2270 = eq(_T_2267, UInt<1>(0h0))
when _T_2270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_2267, UInt<1>(0h1), "") : assert_102
node _T_2271 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2272 = asUInt(reset)
node _T_2273 = eq(_T_2272, UInt<1>(0h0))
when _T_2273 :
node _T_2274 = eq(_T_2271, UInt<1>(0h0))
when _T_2274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_2271, UInt<1>(0h1), "") : assert_103
node _T_2275 = and(io.in.d.valid, d_first_1)
node _T_2276 = and(_T_2275, a_first_1)
node _T_2277 = and(_T_2276, io.in.a.valid)
node _T_2278 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2279 = and(_T_2277, _T_2278)
node _T_2280 = eq(d_release_ack, UInt<1>(0h0))
node _T_2281 = and(_T_2279, _T_2280)
when _T_2281 :
node _T_2282 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2283 = or(_T_2282, io.in.a.ready)
node _T_2284 = asUInt(reset)
node _T_2285 = eq(_T_2284, UInt<1>(0h0))
when _T_2285 :
node _T_2286 = eq(_T_2283, UInt<1>(0h0))
when _T_2286 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_2283, UInt<1>(0h1), "") : assert_104
node _T_2287 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2288 = orr(a_set_wo_ready)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
node _T_2290 = or(_T_2287, _T_2289)
node _T_2291 = asUInt(reset)
node _T_2292 = eq(_T_2291, UInt<1>(0h0))
when _T_2292 :
node _T_2293 = eq(_T_2290, UInt<1>(0h0))
when _T_2293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_2290, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_50
node _T_2294 = orr(inflight)
node _T_2295 = eq(_T_2294, UInt<1>(0h0))
node _T_2296 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2297 = or(_T_2295, _T_2296)
node _T_2298 = lt(watchdog, plusarg_reader.out)
node _T_2299 = or(_T_2297, _T_2298)
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2303 = and(io.in.a.ready, io.in.a.valid)
node _T_2304 = and(io.in.d.ready, io.in.d.valid)
node _T_2305 = or(_T_2303, _T_2304)
when _T_2305 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes_1 : UInt<4104>, clock, reset, UInt<4104>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<10>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<513>
connect c_set, UInt<513>(0h0)
wire c_set_wo_ready : UInt<513>
connect c_set_wo_ready, UInt<513>(0h0)
wire c_opcodes_set : UInt<2052>
connect c_opcodes_set, UInt<2052>(0h0)
wire c_sizes_set : UInt<4104>
connect c_sizes_set, UInt<4104>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<10>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_2306 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<10>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_2307 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_2308 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_2309 = and(_T_2307, _T_2308)
node _T_2310 = and(_T_2306, _T_2309)
when _T_2310 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<10>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_2311 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_2312 = and(_T_2311, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<10>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_2313 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_2314 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_2315 = and(_T_2313, _T_2314)
node _T_2316 = and(_T_2312, _T_2315)
when _T_2316 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<10>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_2317 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_2318 = bits(_T_2317, 0, 0)
node _T_2319 = eq(_T_2318, UInt<1>(0h0))
node _T_2320 = asUInt(reset)
node _T_2321 = eq(_T_2320, UInt<1>(0h0))
when _T_2321 :
node _T_2322 = eq(_T_2319, UInt<1>(0h0))
when _T_2322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_2319, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<513>
connect d_clr_1, UInt<513>(0h0)
wire d_clr_wo_ready_1 : UInt<513>
connect d_clr_wo_ready_1, UInt<513>(0h0)
wire d_opcodes_clr_1 : UInt<2052>
connect d_opcodes_clr_1, UInt<2052>(0h0)
wire d_sizes_clr_1 : UInt<4104>
connect d_sizes_clr_1, UInt<4104>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2323 = and(io.in.d.valid, d_first_2)
node _T_2324 = and(_T_2323, UInt<1>(0h1))
node _T_2325 = and(_T_2324, d_release_ack_1)
when _T_2325 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2326 = and(io.in.d.ready, io.in.d.valid)
node _T_2327 = and(_T_2326, d_first_2)
node _T_2328 = and(_T_2327, UInt<1>(0h1))
node _T_2329 = and(_T_2328, d_release_ack_1)
when _T_2329 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2330 = and(io.in.d.valid, d_first_2)
node _T_2331 = and(_T_2330, UInt<1>(0h1))
node _T_2332 = and(_T_2331, d_release_ack_1)
when _T_2332 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2333 = dshr(inflight_1, io.in.d.bits.source)
node _T_2334 = bits(_T_2333, 0, 0)
node _T_2335 = or(_T_2334, same_cycle_resp_1)
node _T_2336 = asUInt(reset)
node _T_2337 = eq(_T_2336, UInt<1>(0h0))
when _T_2337 :
node _T_2338 = eq(_T_2335, UInt<1>(0h0))
when _T_2338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_2335, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<10>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_2339 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_2340 = asUInt(reset)
node _T_2341 = eq(_T_2340, UInt<1>(0h0))
when _T_2341 :
node _T_2342 = eq(_T_2339, UInt<1>(0h0))
when _T_2342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_2339, UInt<1>(0h1), "") : assert_109
else :
node _T_2343 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2344 = asUInt(reset)
node _T_2345 = eq(_T_2344, UInt<1>(0h0))
when _T_2345 :
node _T_2346 = eq(_T_2343, UInt<1>(0h0))
when _T_2346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_2343, UInt<1>(0h1), "") : assert_110
node _T_2347 = and(io.in.d.valid, d_first_2)
node _T_2348 = and(_T_2347, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<10>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_2349 = and(_T_2348, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<10>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_2350 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_2351 = and(_T_2349, _T_2350)
node _T_2352 = and(_T_2351, d_release_ack_1)
node _T_2353 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2354 = and(_T_2352, _T_2353)
when _T_2354 :
node _T_2355 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<10>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_2356 = or(_T_2355, _WIRE_27.ready)
node _T_2357 = asUInt(reset)
node _T_2358 = eq(_T_2357, UInt<1>(0h0))
when _T_2358 :
node _T_2359 = eq(_T_2356, UInt<1>(0h0))
when _T_2359 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_2356, UInt<1>(0h1), "") : assert_111
node _T_2360 = orr(c_set_wo_ready)
when _T_2360 :
node _T_2361 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2362 = asUInt(reset)
node _T_2363 = eq(_T_2362, UInt<1>(0h0))
when _T_2363 :
node _T_2364 = eq(_T_2361, UInt<1>(0h0))
when _T_2364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_2361, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_51
node _T_2365 = orr(inflight_1)
node _T_2366 = eq(_T_2365, UInt<1>(0h0))
node _T_2367 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2368 = or(_T_2366, _T_2367)
node _T_2369 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2370 = or(_T_2368, _T_2369)
node _T_2371 = asUInt(reset)
node _T_2372 = eq(_T_2371, UInt<1>(0h0))
when _T_2372 :
node _T_2373 = eq(_T_2370, UInt<1>(0h0))
when _T_2373 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_2370, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<10>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_2374 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_2375 = and(io.in.d.ready, io.in.d.valid)
node _T_2376 = or(_T_2374, _T_2375)
when _T_2376 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_25( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [9:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [9:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [512:0] inflight; // @[Monitor.scala:614:27]
reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Monitor.scala:36:7]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Monitor.scala:36:7]
wire [1023:0] _GEN_0 = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [1023:0] _GEN_3 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [512:0] inflight_1; // @[Monitor.scala:726:35]
reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Monitor.scala:36:7]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_2 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h0))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, UInt<1>(0h0), UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, UInt<1>(0h0))
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, UInt<1>(0h0), UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(_T_81, UInt<1>(0h0))
node _T_83 = asUInt(reset)
node _T_84 = eq(_T_83, UInt<1>(0h0))
when _T_84 :
node _T_85 = eq(_T_82, UInt<1>(0h0))
when _T_85 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_82, UInt<1>(0h1), "") : assert_12
node _T_86 = eq(before, UInt<3>(0h5))
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_87, UInt<1>(0h1), "") : assert_13
node _T_91 = eq(evict, UInt<3>(0h4))
node _T_92 = eq(_T_91, UInt<1>(0h0))
node _T_93 = asUInt(reset)
node _T_94 = eq(_T_93, UInt<1>(0h0))
when _T_94 :
node _T_95 = eq(_T_92, UInt<1>(0h0))
when _T_95 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_92, UInt<1>(0h1), "") : assert_14
node _T_96 = eq(before, UInt<3>(0h4))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_97, UInt<1>(0h1), "") : assert_15
node _T_101 = eq(evict, UInt<3>(0h6))
node _T_102 = eq(before, UInt<3>(0h6))
node _T_103 = eq(evict, UInt<2>(0h3))
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_104, UInt<1>(0h1), "") : assert_16
node _T_108 = eq(before, UInt<2>(0h3))
node _T_109 = eq(_T_108, UInt<1>(0h0))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_109, UInt<1>(0h1), "") : assert_17
node _T_113 = eq(evict, UInt<2>(0h2))
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to evicted should be impossible (false,false,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_114, UInt<1>(0h1), "") : assert_18
node _T_118 = eq(before, UInt<2>(0h2))
node _T_119 = eq(_T_118, UInt<1>(0h0))
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to flushed should be impossible (false,false,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_119, UInt<1>(0h1), "") : assert_19
node _T_123 = eq(s_writeback, UInt<1>(0h0))
node _T_124 = and(_T_123, no_wait)
node _T_125 = and(_T_124, io.schedule.ready)
when _T_125 :
node _T_126 = eq(before, UInt<4>(0h8))
node _T_127 = eq(after, UInt<1>(0h1))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = asUInt(reset)
node _T_131 = eq(_T_130, UInt<1>(0h0))
when _T_131 :
node _T_132 = eq(_T_129, UInt<1>(0h0))
when _T_132 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_129, UInt<1>(0h1), "") : assert_20
node _T_133 = eq(before, UInt<4>(0h8))
node _T_134 = eq(after, UInt<1>(0h0))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(_T_135, UInt<1>(0h0))
node _T_137 = asUInt(reset)
node _T_138 = eq(_T_137, UInt<1>(0h0))
when _T_138 :
node _T_139 = eq(_T_136, UInt<1>(0h0))
when _T_139 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_136, UInt<1>(0h1), "") : assert_21
node _T_140 = eq(before, UInt<4>(0h8))
node _T_141 = eq(after, UInt<3>(0h7))
node _T_142 = and(_T_140, _T_141)
node _T_143 = eq(before, UInt<4>(0h8))
node _T_144 = eq(after, UInt<3>(0h5))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = asUInt(reset)
node _T_148 = eq(_T_147, UInt<1>(0h0))
when _T_148 :
node _T_149 = eq(_T_146, UInt<1>(0h0))
when _T_149 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_146, UInt<1>(0h1), "") : assert_22
node _T_150 = eq(before, UInt<4>(0h8))
node _T_151 = eq(after, UInt<3>(0h4))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = asUInt(reset)
node _T_155 = eq(_T_154, UInt<1>(0h0))
when _T_155 :
node _T_156 = eq(_T_153, UInt<1>(0h0))
when _T_156 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_153, UInt<1>(0h1), "") : assert_23
node _T_157 = eq(before, UInt<4>(0h8))
node _T_158 = eq(after, UInt<3>(0h6))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(before, UInt<4>(0h8))
node _T_161 = eq(after, UInt<2>(0h3))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(_T_162, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_163, UInt<1>(0h1), "") : assert_24
node _T_167 = eq(before, UInt<4>(0h8))
node _T_168 = eq(after, UInt<2>(0h2))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(_T_169, UInt<1>(0h0))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_170, UInt<1>(0h1), "") : assert_25
node _T_174 = eq(before, UInt<1>(0h1))
node _T_175 = eq(after, UInt<4>(0h8))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = asUInt(reset)
node _T_179 = eq(_T_178, UInt<1>(0h0))
when _T_179 :
node _T_180 = eq(_T_177, UInt<1>(0h0))
when _T_180 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_177, UInt<1>(0h1), "") : assert_26
node _T_181 = eq(before, UInt<1>(0h1))
node _T_182 = eq(after, UInt<1>(0h0))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(_T_183, UInt<1>(0h0))
node _T_185 = asUInt(reset)
node _T_186 = eq(_T_185, UInt<1>(0h0))
when _T_186 :
node _T_187 = eq(_T_184, UInt<1>(0h0))
when _T_187 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_184, UInt<1>(0h1), "") : assert_27
node _T_188 = eq(before, UInt<1>(0h1))
node _T_189 = eq(after, UInt<3>(0h7))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_191, UInt<1>(0h1), "") : assert_28
node _T_195 = eq(before, UInt<1>(0h1))
node _T_196 = eq(after, UInt<3>(0h5))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(_T_197, UInt<1>(0h0))
node _T_199 = asUInt(reset)
node _T_200 = eq(_T_199, UInt<1>(0h0))
when _T_200 :
node _T_201 = eq(_T_198, UInt<1>(0h0))
when _T_201 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_198, UInt<1>(0h1), "") : assert_29
node _T_202 = eq(before, UInt<1>(0h1))
node _T_203 = eq(after, UInt<3>(0h4))
node _T_204 = and(_T_202, _T_203)
node _T_205 = eq(_T_204, UInt<1>(0h0))
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(_T_205, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_205, UInt<1>(0h1), "") : assert_30
node _T_209 = eq(before, UInt<1>(0h1))
node _T_210 = eq(after, UInt<3>(0h6))
node _T_211 = and(_T_209, _T_210)
node _T_212 = eq(_T_211, UInt<1>(0h0))
node _T_213 = asUInt(reset)
node _T_214 = eq(_T_213, UInt<1>(0h0))
when _T_214 :
node _T_215 = eq(_T_212, UInt<1>(0h0))
when _T_215 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_212, UInt<1>(0h1), "") : assert_31
node _T_216 = eq(before, UInt<1>(0h1))
node _T_217 = eq(after, UInt<2>(0h3))
node _T_218 = and(_T_216, _T_217)
node _T_219 = eq(_T_218, UInt<1>(0h0))
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_T_219, UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_219, UInt<1>(0h1), "") : assert_32
node _T_223 = eq(before, UInt<1>(0h1))
node _T_224 = eq(after, UInt<2>(0h2))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(_T_225, UInt<1>(0h0))
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_226, UInt<1>(0h1), "") : assert_33
node _T_230 = eq(before, UInt<1>(0h0))
node _T_231 = eq(after, UInt<4>(0h8))
node _T_232 = and(_T_230, _T_231)
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = asUInt(reset)
node _T_235 = eq(_T_234, UInt<1>(0h0))
when _T_235 :
node _T_236 = eq(_T_233, UInt<1>(0h0))
when _T_236 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_233, UInt<1>(0h1), "") : assert_34
node _T_237 = eq(before, UInt<1>(0h0))
node _T_238 = eq(after, UInt<1>(0h1))
node _T_239 = and(_T_237, _T_238)
node _T_240 = eq(_T_239, UInt<1>(0h0))
node _T_241 = asUInt(reset)
node _T_242 = eq(_T_241, UInt<1>(0h0))
when _T_242 :
node _T_243 = eq(_T_240, UInt<1>(0h0))
when _T_243 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_240, UInt<1>(0h1), "") : assert_35
node _T_244 = eq(before, UInt<1>(0h0))
node _T_245 = eq(after, UInt<3>(0h7))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(_T_246, UInt<1>(0h0))
node _T_248 = asUInt(reset)
node _T_249 = eq(_T_248, UInt<1>(0h0))
when _T_249 :
node _T_250 = eq(_T_247, UInt<1>(0h0))
when _T_250 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_247, UInt<1>(0h1), "") : assert_36
node _T_251 = eq(before, UInt<1>(0h0))
node _T_252 = eq(after, UInt<3>(0h5))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_254, UInt<1>(0h1), "") : assert_37
node _T_258 = eq(before, UInt<1>(0h0))
node _T_259 = eq(after, UInt<3>(0h6))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = asUInt(reset)
node _T_263 = eq(_T_262, UInt<1>(0h0))
when _T_263 :
node _T_264 = eq(_T_261, UInt<1>(0h0))
when _T_264 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_261, UInt<1>(0h1), "") : assert_38
node _T_265 = eq(before, UInt<1>(0h0))
node _T_266 = eq(after, UInt<3>(0h4))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_268, UInt<1>(0h1), "") : assert_39
node _T_272 = eq(before, UInt<1>(0h0))
node _T_273 = eq(after, UInt<2>(0h3))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_275, UInt<1>(0h1), "") : assert_40
node _T_279 = eq(before, UInt<1>(0h0))
node _T_280 = eq(after, UInt<2>(0h2))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(_T_281, UInt<1>(0h0))
node _T_283 = asUInt(reset)
node _T_284 = eq(_T_283, UInt<1>(0h0))
when _T_284 :
node _T_285 = eq(_T_282, UInt<1>(0h0))
when _T_285 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_282, UInt<1>(0h1), "") : assert_41
node _T_286 = eq(before, UInt<3>(0h7))
node _T_287 = eq(after, UInt<4>(0h8))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(_T_288, UInt<1>(0h0))
node _T_290 = asUInt(reset)
node _T_291 = eq(_T_290, UInt<1>(0h0))
when _T_291 :
node _T_292 = eq(_T_289, UInt<1>(0h0))
when _T_292 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_289, UInt<1>(0h1), "") : assert_42
node _T_293 = eq(before, UInt<3>(0h7))
node _T_294 = eq(after, UInt<1>(0h1))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(_T_295, UInt<1>(0h0))
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_296, UInt<1>(0h1), "") : assert_43
node _T_300 = eq(before, UInt<3>(0h7))
node _T_301 = eq(after, UInt<1>(0h0))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(_T_302, UInt<1>(0h0))
node _T_304 = asUInt(reset)
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(_T_303, UInt<1>(0h0))
when _T_306 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_303, UInt<1>(0h1), "") : assert_44
node _T_307 = eq(before, UInt<3>(0h7))
node _T_308 = eq(after, UInt<3>(0h5))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(_T_309, UInt<1>(0h0))
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_310, UInt<1>(0h1), "") : assert_45
node _T_314 = eq(before, UInt<3>(0h7))
node _T_315 = eq(after, UInt<3>(0h6))
node _T_316 = and(_T_314, _T_315)
node _T_317 = eq(before, UInt<3>(0h7))
node _T_318 = eq(after, UInt<3>(0h4))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(_T_319, UInt<1>(0h0))
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_T_320, UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_320, UInt<1>(0h1), "") : assert_46
node _T_324 = eq(before, UInt<3>(0h7))
node _T_325 = eq(after, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(_T_326, UInt<1>(0h0))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_327, UInt<1>(0h1), "") : assert_47
node _T_331 = eq(before, UInt<3>(0h7))
node _T_332 = eq(after, UInt<2>(0h2))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(_T_333, UInt<1>(0h0))
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_T_334, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_334, UInt<1>(0h1), "") : assert_48
node _T_338 = eq(before, UInt<3>(0h5))
node _T_339 = eq(after, UInt<4>(0h8))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(_T_340, UInt<1>(0h0))
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_341, UInt<1>(0h1), "") : assert_49
node _T_345 = eq(before, UInt<3>(0h5))
node _T_346 = eq(after, UInt<1>(0h1))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(_T_347, UInt<1>(0h0))
node _T_349 = asUInt(reset)
node _T_350 = eq(_T_349, UInt<1>(0h0))
when _T_350 :
node _T_351 = eq(_T_348, UInt<1>(0h0))
when _T_351 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_348, UInt<1>(0h1), "") : assert_50
node _T_352 = eq(before, UInt<3>(0h5))
node _T_353 = eq(after, UInt<1>(0h0))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(_T_354, UInt<1>(0h0))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_355, UInt<1>(0h1), "") : assert_51
node _T_359 = eq(before, UInt<3>(0h5))
node _T_360 = eq(after, UInt<3>(0h7))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(_T_361, UInt<1>(0h0))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_362, UInt<1>(0h1), "") : assert_52
node _T_366 = eq(before, UInt<3>(0h5))
node _T_367 = eq(after, UInt<3>(0h6))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(_T_368, UInt<1>(0h0))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_369, UInt<1>(0h1), "") : assert_53
node _T_373 = eq(before, UInt<3>(0h5))
node _T_374 = eq(after, UInt<3>(0h4))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(_T_375, UInt<1>(0h0))
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_376, UInt<1>(0h1), "") : assert_54
node _T_380 = eq(before, UInt<3>(0h5))
node _T_381 = eq(after, UInt<2>(0h3))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(_T_382, UInt<1>(0h0))
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_383, UInt<1>(0h1), "") : assert_55
node _T_387 = eq(before, UInt<3>(0h5))
node _T_388 = eq(after, UInt<2>(0h2))
node _T_389 = and(_T_387, _T_388)
node _T_390 = eq(_T_389, UInt<1>(0h0))
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_390, UInt<1>(0h1), "") : assert_56
node _T_394 = eq(before, UInt<3>(0h6))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_397, UInt<1>(0h1), "") : assert_57
node _T_401 = eq(before, UInt<3>(0h6))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_404, UInt<1>(0h1), "") : assert_58
node _T_408 = eq(before, UInt<3>(0h6))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_411, UInt<1>(0h1), "") : assert_59
node _T_415 = eq(before, UInt<3>(0h6))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_418, UInt<1>(0h1), "") : assert_60
node _T_422 = eq(before, UInt<3>(0h6))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_425, UInt<1>(0h1), "") : assert_61
node _T_429 = eq(before, UInt<3>(0h6))
node _T_430 = eq(after, UInt<3>(0h4))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(_T_431, UInt<1>(0h0))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_432, UInt<1>(0h1), "") : assert_62
node _T_436 = eq(before, UInt<3>(0h6))
node _T_437 = eq(after, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(_T_438, UInt<1>(0h0))
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_439, UInt<1>(0h1), "") : assert_63
node _T_443 = eq(before, UInt<3>(0h6))
node _T_444 = eq(after, UInt<2>(0h2))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(_T_445, UInt<1>(0h0))
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_446, UInt<1>(0h1), "") : assert_64
node _T_450 = eq(before, UInt<3>(0h4))
node _T_451 = eq(after, UInt<4>(0h8))
node _T_452 = and(_T_450, _T_451)
node _T_453 = eq(_T_452, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_453, UInt<1>(0h1), "") : assert_65
node _T_457 = eq(before, UInt<3>(0h4))
node _T_458 = eq(after, UInt<1>(0h1))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(_T_459, UInt<1>(0h0))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_460, UInt<1>(0h1), "") : assert_66
node _T_464 = eq(before, UInt<3>(0h4))
node _T_465 = eq(after, UInt<1>(0h0))
node _T_466 = and(_T_464, _T_465)
node _T_467 = eq(_T_466, UInt<1>(0h0))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_467, UInt<1>(0h1), "") : assert_67
node _T_471 = eq(before, UInt<3>(0h4))
node _T_472 = eq(after, UInt<3>(0h7))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(_T_473, UInt<1>(0h0))
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_68
assert(clock, _T_474, UInt<1>(0h1), "") : assert_68
node _T_478 = eq(before, UInt<3>(0h4))
node _T_479 = eq(after, UInt<3>(0h5))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_69
assert(clock, _T_481, UInt<1>(0h1), "") : assert_69
node _T_485 = eq(before, UInt<3>(0h4))
node _T_486 = eq(after, UInt<3>(0h6))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_70
assert(clock, _T_488, UInt<1>(0h1), "") : assert_70
node _T_492 = eq(before, UInt<3>(0h4))
node _T_493 = eq(after, UInt<2>(0h3))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_71
assert(clock, _T_495, UInt<1>(0h1), "") : assert_71
node _T_499 = eq(before, UInt<3>(0h4))
node _T_500 = eq(after, UInt<2>(0h2))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_72
assert(clock, _T_502, UInt<1>(0h1), "") : assert_72
node _T_506 = eq(before, UInt<2>(0h3))
node _T_507 = eq(after, UInt<4>(0h8))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_73
assert(clock, _T_509, UInt<1>(0h1), "") : assert_73
node _T_513 = eq(before, UInt<2>(0h3))
node _T_514 = eq(after, UInt<1>(0h1))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(_T_515, UInt<1>(0h0))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_74
assert(clock, _T_516, UInt<1>(0h1), "") : assert_74
node _T_520 = eq(before, UInt<2>(0h3))
node _T_521 = eq(after, UInt<1>(0h0))
node _T_522 = and(_T_520, _T_521)
node _T_523 = eq(_T_522, UInt<1>(0h0))
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_75
assert(clock, _T_523, UInt<1>(0h1), "") : assert_75
node _T_527 = eq(before, UInt<2>(0h3))
node _T_528 = eq(after, UInt<3>(0h7))
node _T_529 = and(_T_527, _T_528)
node _T_530 = eq(_T_529, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_76
assert(clock, _T_530, UInt<1>(0h1), "") : assert_76
node _T_534 = eq(before, UInt<2>(0h3))
node _T_535 = eq(after, UInt<3>(0h5))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(_T_536, UInt<1>(0h0))
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_77
assert(clock, _T_537, UInt<1>(0h1), "") : assert_77
node _T_541 = eq(before, UInt<2>(0h3))
node _T_542 = eq(after, UInt<3>(0h6))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(_T_543, UInt<1>(0h0))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_78
assert(clock, _T_544, UInt<1>(0h1), "") : assert_78
node _T_548 = eq(before, UInt<2>(0h3))
node _T_549 = eq(after, UInt<3>(0h4))
node _T_550 = and(_T_548, _T_549)
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_79
assert(clock, _T_551, UInt<1>(0h1), "") : assert_79
node _T_555 = eq(before, UInt<2>(0h3))
node _T_556 = eq(after, UInt<2>(0h2))
node _T_557 = and(_T_555, _T_556)
node _T_558 = eq(_T_557, UInt<1>(0h0))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_80
assert(clock, _T_558, UInt<1>(0h1), "") : assert_80
node _T_562 = eq(before, UInt<2>(0h2))
node _T_563 = eq(after, UInt<4>(0h8))
node _T_564 = and(_T_562, _T_563)
node _T_565 = eq(_T_564, UInt<1>(0h0))
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(_T_565, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_81
assert(clock, _T_565, UInt<1>(0h1), "") : assert_81
node _T_569 = eq(before, UInt<2>(0h2))
node _T_570 = eq(after, UInt<1>(0h1))
node _T_571 = and(_T_569, _T_570)
node _T_572 = eq(_T_571, UInt<1>(0h0))
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_82
assert(clock, _T_572, UInt<1>(0h1), "") : assert_82
node _T_576 = eq(before, UInt<2>(0h2))
node _T_577 = eq(after, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
node _T_579 = eq(_T_578, UInt<1>(0h0))
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_83
assert(clock, _T_579, UInt<1>(0h1), "") : assert_83
node _T_583 = eq(before, UInt<2>(0h2))
node _T_584 = eq(after, UInt<3>(0h7))
node _T_585 = and(_T_583, _T_584)
node _T_586 = eq(_T_585, UInt<1>(0h0))
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_84
assert(clock, _T_586, UInt<1>(0h1), "") : assert_84
node _T_590 = eq(before, UInt<2>(0h2))
node _T_591 = eq(after, UInt<3>(0h5))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(_T_592, UInt<1>(0h0))
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(_T_593, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_85
assert(clock, _T_593, UInt<1>(0h1), "") : assert_85
node _T_597 = eq(before, UInt<2>(0h2))
node _T_598 = eq(after, UInt<3>(0h6))
node _T_599 = and(_T_597, _T_598)
node _T_600 = eq(_T_599, UInt<1>(0h0))
node _T_601 = asUInt(reset)
node _T_602 = eq(_T_601, UInt<1>(0h0))
when _T_602 :
node _T_603 = eq(_T_600, UInt<1>(0h0))
when _T_603 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_D should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_86
assert(clock, _T_600, UInt<1>(0h1), "") : assert_86
node _T_604 = eq(before, UInt<2>(0h2))
node _T_605 = eq(after, UInt<3>(0h4))
node _T_606 = and(_T_604, _T_605)
node _T_607 = eq(_T_606, UInt<1>(0h0))
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(_T_607, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_87
assert(clock, _T_607, UInt<1>(0h1), "") : assert_87
node _T_611 = eq(before, UInt<2>(0h2))
node _T_612 = eq(after, UInt<2>(0h3))
node _T_613 = and(_T_611, _T_612)
node _T_614 = eq(_T_613, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_88
assert(clock, _T_614, UInt<1>(0h1), "") : assert_88
node _last_probe_T = or(probes_done, UInt<1>(0h0))
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkd.valid :
node _T_618 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_619 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_620 = or(_T_618, _T_619)
when _T_620 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_621 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_622 = eq(request.offset, UInt<1>(0h0))
node _T_623 = and(_T_621, _T_622)
node _T_624 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_625 = neq(request.offset, UInt<1>(0h0))
node _T_626 = and(_T_624, _T_625)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_627 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_627 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, UInt<1>(0h0), UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_628 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_628 :
node _T_629 = eq(prior, UInt<4>(0h8))
node _T_630 = eq(prior, UInt<1>(0h1))
node _T_631 = eq(_T_630, UInt<1>(0h0))
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(_T_631, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_89
assert(clock, _T_631, UInt<1>(0h1), "") : assert_89
node _T_635 = eq(prior, UInt<1>(0h0))
node _T_636 = eq(_T_635, UInt<1>(0h0))
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_90
assert(clock, _T_636, UInt<1>(0h1), "") : assert_90
node _T_640 = eq(prior, UInt<3>(0h7))
node _T_641 = eq(prior, UInt<3>(0h5))
node _T_642 = eq(_T_641, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TIP_C should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_91
assert(clock, _T_642, UInt<1>(0h1), "") : assert_91
node _T_646 = eq(prior, UInt<3>(0h4))
node _T_647 = eq(_T_646, UInt<1>(0h0))
node _T_648 = asUInt(reset)
node _T_649 = eq(_T_648, UInt<1>(0h0))
when _T_649 :
node _T_650 = eq(_T_647, UInt<1>(0h0))
when _T_650 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TIP_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_92
assert(clock, _T_647, UInt<1>(0h1), "") : assert_92
node _T_651 = eq(prior, UInt<3>(0h6))
node _T_652 = eq(prior, UInt<2>(0h3))
node _T_653 = eq(_T_652, UInt<1>(0h0))
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TRUNK_C should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_93
assert(clock, _T_653, UInt<1>(0h1), "") : assert_93
node _T_657 = eq(prior, UInt<2>(0h2))
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = asUInt(reset)
node _T_660 = eq(_T_659, UInt<1>(0h0))
when _T_660 :
node _T_661 = eq(_T_658, UInt<1>(0h0))
when _T_661 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_TRUNK_CD should be impossible (false,false,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_94
assert(clock, _T_658, UInt<1>(0h1), "") : assert_94
when io.allocate.valid :
node _T_662 = eq(request_valid, UInt<1>(0h0))
node _T_663 = and(io.schedule.ready, io.schedule.valid)
node _T_664 = and(no_wait, _T_663)
node _T_665 = or(_T_662, _T_664)
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_95
assert(clock, _T_665, UInt<1>(0h1), "") : assert_95
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_669 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_670 = or(io.directory.valid, _T_669)
when _T_670 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_671 = and(new_request.prio[2], UInt<1>(0h0))
when _T_671 :
connect s_execute, UInt<1>(0h0)
node _T_672 = bits(new_request.opcode, 0, 0)
node _T_673 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_674 = and(_T_672, _T_673)
when _T_674 :
connect s_writeback, UInt<1>(0h0)
node _T_675 = eq(new_request.param, UInt<3>(0h0))
node _T_676 = eq(new_request.param, UInt<3>(0h4))
node _T_677 = or(_T_675, _T_676)
node _T_678 = eq(new_meta.state, UInt<2>(0h2))
node _T_679 = and(_T_677, _T_678)
when _T_679 :
connect s_writeback, UInt<1>(0h0)
node _T_680 = eq(new_request.param, UInt<3>(0h1))
node _T_681 = eq(new_request.param, UInt<3>(0h2))
node _T_682 = or(_T_680, _T_681)
node _T_683 = eq(new_request.param, UInt<3>(0h5))
node _T_684 = or(_T_682, _T_683)
node _T_685 = and(new_meta.clients, UInt<1>(0h0))
node _T_686 = neq(_T_685, UInt<1>(0h0))
node _T_687 = and(_T_684, _T_686)
when _T_687 :
connect s_writeback, UInt<1>(0h0)
node _T_688 = asUInt(reset)
node _T_689 = eq(_T_688, UInt<1>(0h0))
when _T_689 :
node _T_690 = eq(new_meta.hit, UInt<1>(0h0))
when _T_690 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_96
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_96
else :
node _T_691 = and(new_request.control, UInt<1>(0h1))
when _T_691 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_692 = neq(new_meta.clients, UInt<1>(0h0))
node _T_693 = and(UInt<1>(0h0), _T_692)
when _T_693 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_694 = eq(new_meta.hit, UInt<1>(0h0))
node _T_695 = neq(new_meta.state, UInt<2>(0h0))
node _T_696 = and(_T_694, _T_695)
when _T_696 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_697 = neq(new_meta.clients, UInt<1>(0h0))
node _T_698 = and(UInt<1>(0h0), _T_697)
when _T_698 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_699 = eq(new_meta.hit, UInt<1>(0h0))
node _T_700 = eq(new_meta.state, UInt<2>(0h1))
node _T_701 = and(_T_700, new_needT)
node _T_702 = or(_T_699, _T_701)
when _T_702 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_703 = eq(new_meta.state, UInt<2>(0h2))
node _T_704 = or(new_needT, _T_703)
node _T_705 = and(new_meta.hit, _T_704)
node _T_706 = not(new_skipProbe)
node _T_707 = and(new_meta.clients, _T_706)
node _T_708 = neq(_T_707, UInt<1>(0h0))
node _T_709 = and(_T_705, _T_708)
node _T_710 = and(UInt<1>(0h0), _T_709)
when _T_710 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_711 = eq(new_request.opcode, UInt<3>(0h6))
node _T_712 = eq(new_request.opcode, UInt<3>(0h7))
node _T_713 = or(_T_711, _T_712)
when _T_713 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_714 = bits(new_request.opcode, 2, 2)
node _T_715 = eq(_T_714, UInt<1>(0h0))
node _T_716 = and(_T_715, new_meta.hit)
node _T_717 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_718 = and(_T_716, _T_717)
when _T_718 :
connect s_writeback, UInt<1>(0h0) | module MSHR_2( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire io_sinkc_valid = 1'h0; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last = 1'h0; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data = 1'h0; // @[MSHR.scala:84:7]
wire io_sinke_valid = 1'h0; // @[MSHR.scala:84:7]
wire _io_status_bits_blockB_T_2 = 1'h0; // @[MSHR.scala:168:62]
wire _io_status_bits_blockB_T_4 = 1'h0; // @[MSHR.scala:168:82]
wire _io_status_bits_nestC_T = 1'h0; // @[MSHR.scala:173:43]
wire _io_status_bits_nestC_T_1 = 1'h0; // @[MSHR.scala:173:64]
wire _io_status_bits_nestC_T_2 = 1'h0; // @[MSHR.scala:173:61]
wire _io_schedule_bits_b_valid_T = 1'h0; // @[MSHR.scala:185:31]
wire _io_schedule_bits_b_valid_T_1 = 1'h0; // @[MSHR.scala:185:44]
wire _io_schedule_bits_b_valid_T_2 = 1'h0; // @[MSHR.scala:185:41]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire _final_meta_writeback_clients_T_5 = 1'h0; // @[MSHR.scala:226:56]
wire _final_meta_writeback_clients_T_13 = 1'h0; // @[MSHR.scala:246:40]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _honour_BtoT_T = 1'h0; // @[MSHR.scala:276:47]
wire _honour_BtoT_T_1 = 1'h0; // @[MSHR.scala:276:64]
wire honour_BtoT = 1'h0; // @[MSHR.scala:276:30]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire excluded_client = 1'h0; // @[MSHR.scala:279:28]
wire _io_schedule_bits_b_bits_param_T = 1'h0; // @[MSHR.scala:286:42]
wire _io_schedule_bits_b_bits_tag_T = 1'h0; // @[MSHR.scala:287:42]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _last_probe_T = 1'h0; // @[MSHR.scala:459:33]
wire _probe_toN_T = 1'h0; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = 1'h0; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = 1'h0; // @[Parameters.scala:282:34]
wire _probe_toN_T_3 = 1'h0; // @[Parameters.scala:282:75]
wire probe_toN = 1'h0; // @[Parameters.scala:282:66]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire new_skipProbe = 1'h0; // @[MSHR.scala:509:26]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _final_meta_writeback_clients_T_6 = 1'h1; // @[MSHR.scala:226:52]
wire _final_meta_writeback_clients_T_8 = 1'h1; // @[MSHR.scala:232:54]
wire _final_meta_writeback_clients_T_10 = 1'h1; // @[MSHR.scala:245:66]
wire _final_meta_writeback_clients_T_15 = 1'h1; // @[MSHR.scala:258:54]
wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53]
wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set = 10'h0; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag = 13'h0; // @[MSHR.scala:84:7]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [5:0] io_sinkc_bits_source = 6'h0; // @[MSHR.scala:84:7]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = 2'h1; // @[MSHR.scala:301:53]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign _io_schedule_bits_b_bits_tag_T_1 = request_tag; // @[MSHR.scala:98:20, :287:41]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire _final_meta_writeback_clients_T_7 = meta_clients; // @[MSHR.scala:100:17, :226:50]
wire _final_meta_writeback_clients_T_9 = meta_clients; // @[MSHR.scala:100:17, :232:52]
wire _final_meta_writeback_clients_T_11 = meta_clients; // @[MSHR.scala:100:17, :245:64]
wire _final_meta_writeback_clients_T_16 = meta_clients; // @[MSHR.scala:100:17, :258:52]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
wire _no_wait_T = w_releaseack; // @[MSHR.scala:125:33, :183:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1; // @[MSHR.scala:168:{45,59}]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3; // @[MSHR.scala:168:{59,79}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T; // @[MSHR.scala:169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1; // @[MSHR.scala:169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1; // @[MSHR.scala:183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1; // @[MSHR.scala:184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T; // @[MSHR.scala:186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T; // @[MSHR.scala:187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T; // @[MSHR.scala:190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12; // @[MSHR.scala:245:{40,84}]
assign final_meta_writeback_tag = request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :228:53, :247:30]
assign final_meta_writeback_hit = bad_grant ? meta_hit : ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? 3'h1 : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire last_probe = ~_last_probe_T_2; // @[MSHR.scala:459:{46,64}]
wire _w_grant_T = request_offset == 6'h0; // @[MSHR.scala:98:20, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_15 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_15; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_15; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_711 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_711; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_711; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_pbus_to_gcd :
input clock : Clock
input reset : Reset
output auto : { axi4buf_out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<15>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<11>}}, last : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst axi4buf of AXI4Buffer
connect axi4buf.clock, clock
connect axi4buf.reset, reset
inst tl2axi4 of TLToAXI4
connect tl2axi4.clock, clock
connect tl2axi4.reset, reset
inst fragmenter of TLFragmenter
connect fragmenter.clock, clock
connect fragmenter.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.user.amba_prot.fetch
invalidate tlOut.a.bits.user.amba_prot.secure
invalidate tlOut.a.bits.user.amba_prot.privileged
invalidate tlOut.a.bits.user.amba_prot.writealloc
invalidate tlOut.a.bits.user.amba_prot.readalloc
invalidate tlOut.a.bits.user.amba_prot.modifiable
invalidate tlOut.a.bits.user.amba_prot.bufferable
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.user.amba_prot.fetch
invalidate tlIn.a.bits.user.amba_prot.secure
invalidate tlIn.a.bits.user.amba_prot.privileged
invalidate tlIn.a.bits.user.amba_prot.writealloc
invalidate tlIn.a.bits.user.amba_prot.readalloc
invalidate tlIn.a.bits.user.amba_prot.modifiable
invalidate tlIn.a.bits.user.amba_prot.bufferable
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect fragmenter.auto.anon_in, tlOut
connect axi4buf.auto.in, tl2axi4.auto.out
connect tl2axi4.auto.in, fragmenter.auto.anon_out
connect tlIn, auto.tl_in
connect axi4buf.auto.out.r, auto.axi4buf_out.r
connect auto.axi4buf_out.ar.bits, axi4buf.auto.out.ar.bits
connect auto.axi4buf_out.ar.valid, axi4buf.auto.out.ar.valid
connect axi4buf.auto.out.ar.ready, auto.axi4buf_out.ar.ready
connect axi4buf.auto.out.b, auto.axi4buf_out.b
connect auto.axi4buf_out.w.bits, axi4buf.auto.out.w.bits
connect auto.axi4buf_out.w.valid, axi4buf.auto.out.w.valid
connect axi4buf.auto.out.w.ready, auto.axi4buf_out.w.ready
connect auto.axi4buf_out.aw.bits, axi4buf.auto.out.aw.bits
connect auto.axi4buf_out.aw.valid, axi4buf.auto.out.aw.valid
connect axi4buf.auto.out.aw.ready, auto.axi4buf_out.aw.ready
extmodule plusarg_reader_20 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_21 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_pbus_to_gcd( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_axi4buf_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4buf_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output auto_axi4buf_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [14:0] auto_axi4buf_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4buf_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_axi4buf_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_axi4buf_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4buf_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_axi4buf_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_axi4buf_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_axi4buf_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_axi4buf_out_b_valid, // @[LazyModuleImp.scala:107:25]
input auto_axi4buf_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_axi4buf_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_axi4buf_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_axi4buf_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4buf_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output auto_axi4buf_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [14:0] auto_axi4buf_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4buf_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4buf_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_axi4buf_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output auto_axi4buf_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_axi4buf_out_r_valid, // @[LazyModuleImp.scala:107:25]
input auto_axi4buf_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_axi4buf_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_axi4buf_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_axi4buf_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [14:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [10:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [14:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_user_amba_prot_bufferable; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_user_amba_prot_modifiable; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_user_amba_prot_readalloc; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_user_amba_prot_writealloc; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_user_amba_prot_privileged; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_user_amba_prot_secure; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_user_amba_prot_fetch; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _tl2axi4_auto_in_a_ready; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_in_d_valid; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_in_d_bits_opcode; // @[ToAXI4.scala:301:29]
wire [1:0] _tl2axi4_auto_in_d_bits_size; // @[ToAXI4.scala:301:29]
wire [10:0] _tl2axi4_auto_in_d_bits_source; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_in_d_bits_denied; // @[ToAXI4.scala:301:29]
wire [63:0] _tl2axi4_auto_in_d_bits_data; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_in_d_bits_corrupt; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala:301:29]
wire [14:0] _tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala:301:29]
wire [1:0] _tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29]
wire [10:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_w_valid; // @[ToAXI4.scala:301:29]
wire [63:0] _tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_b_ready; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala:301:29]
wire [14:0] _tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala:301:29]
wire [1:0] _tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29]
wire [10:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_r_ready; // @[ToAXI4.scala:301:29]
wire _axi4buf_auto_in_aw_ready; // @[Buffer.scala:68:29]
wire _axi4buf_auto_in_w_ready; // @[Buffer.scala:68:29]
wire _axi4buf_auto_in_b_valid; // @[Buffer.scala:68:29]
wire [1:0] _axi4buf_auto_in_b_bits_resp; // @[Buffer.scala:68:29]
wire [3:0] _axi4buf_auto_in_b_bits_echo_tl_state_size; // @[Buffer.scala:68:29]
wire [10:0] _axi4buf_auto_in_b_bits_echo_tl_state_source; // @[Buffer.scala:68:29]
wire _axi4buf_auto_in_ar_ready; // @[Buffer.scala:68:29]
wire _axi4buf_auto_in_r_valid; // @[Buffer.scala:68:29]
wire [63:0] _axi4buf_auto_in_r_bits_data; // @[Buffer.scala:68:29]
wire [1:0] _axi4buf_auto_in_r_bits_resp; // @[Buffer.scala:68:29]
wire [3:0] _axi4buf_auto_in_r_bits_echo_tl_state_size; // @[Buffer.scala:68:29]
wire [10:0] _axi4buf_auto_in_r_bits_echo_tl_state_source; // @[Buffer.scala:68:29]
wire _axi4buf_auto_in_r_bits_last; // @[Buffer.scala:68:29]
AXI4Buffer axi4buf ( // @[Buffer.scala:68:29]
.clock (clock),
.reset (reset),
.auto_in_aw_ready (_axi4buf_auto_in_aw_ready),
.auto_in_aw_valid (_tl2axi4_auto_out_aw_valid), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_id (_tl2axi4_auto_out_aw_bits_id), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_len (_tl2axi4_auto_out_aw_bits_len), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_size (_tl2axi4_auto_out_aw_bits_size), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29]
.auto_in_w_ready (_axi4buf_auto_in_w_ready),
.auto_in_w_valid (_tl2axi4_auto_out_w_valid), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_data (_tl2axi4_auto_out_w_bits_data), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_strb (_tl2axi4_auto_out_w_bits_strb), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_last (_tl2axi4_auto_out_w_bits_last), // @[ToAXI4.scala:301:29]
.auto_in_b_ready (_tl2axi4_auto_out_b_ready), // @[ToAXI4.scala:301:29]
.auto_in_b_valid (_axi4buf_auto_in_b_valid),
.auto_in_b_bits_resp (_axi4buf_auto_in_b_bits_resp),
.auto_in_b_bits_echo_tl_state_size (_axi4buf_auto_in_b_bits_echo_tl_state_size),
.auto_in_b_bits_echo_tl_state_source (_axi4buf_auto_in_b_bits_echo_tl_state_source),
.auto_in_ar_ready (_axi4buf_auto_in_ar_ready),
.auto_in_ar_valid (_tl2axi4_auto_out_ar_valid), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_id (_tl2axi4_auto_out_ar_bits_id), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_len (_tl2axi4_auto_out_ar_bits_len), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_size (_tl2axi4_auto_out_ar_bits_size), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29]
.auto_in_r_ready (_tl2axi4_auto_out_r_ready), // @[ToAXI4.scala:301:29]
.auto_in_r_valid (_axi4buf_auto_in_r_valid),
.auto_in_r_bits_data (_axi4buf_auto_in_r_bits_data),
.auto_in_r_bits_resp (_axi4buf_auto_in_r_bits_resp),
.auto_in_r_bits_echo_tl_state_size (_axi4buf_auto_in_r_bits_echo_tl_state_size),
.auto_in_r_bits_echo_tl_state_source (_axi4buf_auto_in_r_bits_echo_tl_state_source),
.auto_in_r_bits_last (_axi4buf_auto_in_r_bits_last),
.auto_out_aw_ready (auto_axi4buf_out_aw_ready),
.auto_out_aw_valid (auto_axi4buf_out_aw_valid),
.auto_out_aw_bits_id (auto_axi4buf_out_aw_bits_id),
.auto_out_aw_bits_addr (auto_axi4buf_out_aw_bits_addr),
.auto_out_aw_bits_echo_tl_state_size (auto_axi4buf_out_aw_bits_echo_tl_state_size),
.auto_out_aw_bits_echo_tl_state_source (auto_axi4buf_out_aw_bits_echo_tl_state_source),
.auto_out_w_ready (auto_axi4buf_out_w_ready),
.auto_out_w_valid (auto_axi4buf_out_w_valid),
.auto_out_w_bits_data (auto_axi4buf_out_w_bits_data),
.auto_out_w_bits_strb (auto_axi4buf_out_w_bits_strb),
.auto_out_b_ready (auto_axi4buf_out_b_ready),
.auto_out_b_valid (auto_axi4buf_out_b_valid),
.auto_out_b_bits_id (auto_axi4buf_out_b_bits_id),
.auto_out_b_bits_echo_tl_state_size (auto_axi4buf_out_b_bits_echo_tl_state_size),
.auto_out_b_bits_echo_tl_state_source (auto_axi4buf_out_b_bits_echo_tl_state_source),
.auto_out_ar_ready (auto_axi4buf_out_ar_ready),
.auto_out_ar_valid (auto_axi4buf_out_ar_valid),
.auto_out_ar_bits_id (auto_axi4buf_out_ar_bits_id),
.auto_out_ar_bits_addr (auto_axi4buf_out_ar_bits_addr),
.auto_out_ar_bits_size (auto_axi4buf_out_ar_bits_size),
.auto_out_ar_bits_echo_tl_state_size (auto_axi4buf_out_ar_bits_echo_tl_state_size),
.auto_out_ar_bits_echo_tl_state_source (auto_axi4buf_out_ar_bits_echo_tl_state_source),
.auto_out_r_ready (auto_axi4buf_out_r_ready),
.auto_out_r_valid (auto_axi4buf_out_r_valid),
.auto_out_r_bits_id (auto_axi4buf_out_r_bits_id),
.auto_out_r_bits_data (auto_axi4buf_out_r_bits_data),
.auto_out_r_bits_echo_tl_state_size (auto_axi4buf_out_r_bits_echo_tl_state_size),
.auto_out_r_bits_echo_tl_state_source (auto_axi4buf_out_r_bits_echo_tl_state_source)
); // @[Buffer.scala:68:29]
TLToAXI4 tl2axi4 ( // @[ToAXI4.scala:301:29]
.clock (clock),
.reset (reset),
.auto_in_a_ready (_tl2axi4_auto_in_a_ready),
.auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_user_amba_prot_bufferable (_fragmenter_auto_anon_out_a_bits_user_amba_prot_bufferable), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_user_amba_prot_modifiable (_fragmenter_auto_anon_out_a_bits_user_amba_prot_modifiable), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_user_amba_prot_readalloc (_fragmenter_auto_anon_out_a_bits_user_amba_prot_readalloc), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_user_amba_prot_writealloc (_fragmenter_auto_anon_out_a_bits_user_amba_prot_writealloc), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_user_amba_prot_privileged (_fragmenter_auto_anon_out_a_bits_user_amba_prot_privileged), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_user_amba_prot_secure (_fragmenter_auto_anon_out_a_bits_user_amba_prot_secure), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_user_amba_prot_fetch (_fragmenter_auto_anon_out_a_bits_user_amba_prot_fetch), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_in_d_valid (_tl2axi4_auto_in_d_valid),
.auto_in_d_bits_opcode (_tl2axi4_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_tl2axi4_auto_in_d_bits_size),
.auto_in_d_bits_source (_tl2axi4_auto_in_d_bits_source),
.auto_in_d_bits_denied (_tl2axi4_auto_in_d_bits_denied),
.auto_in_d_bits_data (_tl2axi4_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_tl2axi4_auto_in_d_bits_corrupt),
.auto_out_aw_ready (_axi4buf_auto_in_aw_ready), // @[Buffer.scala:68:29]
.auto_out_aw_valid (_tl2axi4_auto_out_aw_valid),
.auto_out_aw_bits_id (_tl2axi4_auto_out_aw_bits_id),
.auto_out_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr),
.auto_out_aw_bits_len (_tl2axi4_auto_out_aw_bits_len),
.auto_out_aw_bits_size (_tl2axi4_auto_out_aw_bits_size),
.auto_out_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos),
.auto_out_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size),
.auto_out_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source),
.auto_out_w_ready (_axi4buf_auto_in_w_ready), // @[Buffer.scala:68:29]
.auto_out_w_valid (_tl2axi4_auto_out_w_valid),
.auto_out_w_bits_data (_tl2axi4_auto_out_w_bits_data),
.auto_out_w_bits_strb (_tl2axi4_auto_out_w_bits_strb),
.auto_out_w_bits_last (_tl2axi4_auto_out_w_bits_last),
.auto_out_b_ready (_tl2axi4_auto_out_b_ready),
.auto_out_b_valid (_axi4buf_auto_in_b_valid), // @[Buffer.scala:68:29]
.auto_out_b_bits_resp (_axi4buf_auto_in_b_bits_resp), // @[Buffer.scala:68:29]
.auto_out_b_bits_echo_tl_state_size (_axi4buf_auto_in_b_bits_echo_tl_state_size), // @[Buffer.scala:68:29]
.auto_out_b_bits_echo_tl_state_source (_axi4buf_auto_in_b_bits_echo_tl_state_source), // @[Buffer.scala:68:29]
.auto_out_ar_ready (_axi4buf_auto_in_ar_ready), // @[Buffer.scala:68:29]
.auto_out_ar_valid (_tl2axi4_auto_out_ar_valid),
.auto_out_ar_bits_id (_tl2axi4_auto_out_ar_bits_id),
.auto_out_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr),
.auto_out_ar_bits_len (_tl2axi4_auto_out_ar_bits_len),
.auto_out_ar_bits_size (_tl2axi4_auto_out_ar_bits_size),
.auto_out_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos),
.auto_out_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size),
.auto_out_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source),
.auto_out_r_ready (_tl2axi4_auto_out_r_ready),
.auto_out_r_valid (_axi4buf_auto_in_r_valid), // @[Buffer.scala:68:29]
.auto_out_r_bits_data (_axi4buf_auto_in_r_bits_data), // @[Buffer.scala:68:29]
.auto_out_r_bits_resp (_axi4buf_auto_in_r_bits_resp), // @[Buffer.scala:68:29]
.auto_out_r_bits_echo_tl_state_size (_axi4buf_auto_in_r_bits_echo_tl_state_size), // @[Buffer.scala:68:29]
.auto_out_r_bits_echo_tl_state_source (_axi4buf_auto_in_r_bits_echo_tl_state_source), // @[Buffer.scala:68:29]
.auto_out_r_bits_last (_axi4buf_auto_in_r_bits_last) // @[Buffer.scala:68:29]
); // @[ToAXI4.scala:301:29]
TLFragmenter fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (auto_tl_in_a_ready),
.auto_anon_in_a_valid (auto_tl_in_a_valid),
.auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode),
.auto_anon_in_a_bits_param (auto_tl_in_a_bits_param),
.auto_anon_in_a_bits_size (auto_tl_in_a_bits_size),
.auto_anon_in_a_bits_source (auto_tl_in_a_bits_source),
.auto_anon_in_a_bits_address (auto_tl_in_a_bits_address),
.auto_anon_in_a_bits_user_amba_prot_bufferable (auto_tl_in_a_bits_user_amba_prot_bufferable),
.auto_anon_in_a_bits_user_amba_prot_modifiable (auto_tl_in_a_bits_user_amba_prot_modifiable),
.auto_anon_in_a_bits_user_amba_prot_readalloc (auto_tl_in_a_bits_user_amba_prot_readalloc),
.auto_anon_in_a_bits_user_amba_prot_writealloc (auto_tl_in_a_bits_user_amba_prot_writealloc),
.auto_anon_in_a_bits_user_amba_prot_privileged (auto_tl_in_a_bits_user_amba_prot_privileged),
.auto_anon_in_a_bits_user_amba_prot_secure (auto_tl_in_a_bits_user_amba_prot_secure),
.auto_anon_in_a_bits_user_amba_prot_fetch (auto_tl_in_a_bits_user_amba_prot_fetch),
.auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask),
.auto_anon_in_a_bits_data (auto_tl_in_a_bits_data),
.auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt),
.auto_anon_in_d_ready (auto_tl_in_d_ready),
.auto_anon_in_d_valid (auto_tl_in_d_valid),
.auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode),
.auto_anon_in_d_bits_size (auto_tl_in_d_bits_size),
.auto_anon_in_d_bits_source (auto_tl_in_d_bits_source),
.auto_anon_in_d_bits_denied (auto_tl_in_d_bits_denied),
.auto_anon_in_d_bits_data (auto_tl_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (auto_tl_in_d_bits_corrupt),
.auto_anon_out_a_ready (_tl2axi4_auto_in_a_ready), // @[ToAXI4.scala:301:29]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_user_amba_prot_bufferable (_fragmenter_auto_anon_out_a_bits_user_amba_prot_bufferable),
.auto_anon_out_a_bits_user_amba_prot_modifiable (_fragmenter_auto_anon_out_a_bits_user_amba_prot_modifiable),
.auto_anon_out_a_bits_user_amba_prot_readalloc (_fragmenter_auto_anon_out_a_bits_user_amba_prot_readalloc),
.auto_anon_out_a_bits_user_amba_prot_writealloc (_fragmenter_auto_anon_out_a_bits_user_amba_prot_writealloc),
.auto_anon_out_a_bits_user_amba_prot_privileged (_fragmenter_auto_anon_out_a_bits_user_amba_prot_privileged),
.auto_anon_out_a_bits_user_amba_prot_secure (_fragmenter_auto_anon_out_a_bits_user_amba_prot_secure),
.auto_anon_out_a_bits_user_amba_prot_fetch (_fragmenter_auto_anon_out_a_bits_user_amba_prot_fetch),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_tl2axi4_auto_in_d_valid), // @[ToAXI4.scala:301:29]
.auto_anon_out_d_bits_opcode (_tl2axi4_auto_in_d_bits_opcode), // @[ToAXI4.scala:301:29]
.auto_anon_out_d_bits_size (_tl2axi4_auto_in_d_bits_size), // @[ToAXI4.scala:301:29]
.auto_anon_out_d_bits_source (_tl2axi4_auto_in_d_bits_source), // @[ToAXI4.scala:301:29]
.auto_anon_out_d_bits_denied (_tl2axi4_auto_in_d_bits_denied), // @[ToAXI4.scala:301:29]
.auto_anon_out_d_bits_data (_tl2axi4_auto_in_d_bits_data), // @[ToAXI4.scala:301:29]
.auto_anon_out_d_bits_corrupt (_tl2axi4_auto_in_d_bits_corrupt) // @[ToAXI4.scala:301:29]
); // @[Fragmenter.scala:345:34]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_2 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_1
node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 22, 22)
node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0))
node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1)
connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig
connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp
connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign
connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RecFNToRecFN_2( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [64:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h0; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19]
wire [64:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_1 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_182 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_196
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_182( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_196 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_10 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_115
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_116
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_10( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_115 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_116 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i2_o2_a32d64s6k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonIn_1.e.bits.sink
invalidate anonIn_1.e.valid
invalidate anonIn_1.e.ready
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.c.bits.corrupt
invalidate anonIn_1.c.bits.data
invalidate anonIn_1.c.bits.address
invalidate anonIn_1.c.bits.source
invalidate anonIn_1.c.bits.size
invalidate anonIn_1.c.bits.param
invalidate anonIn_1.c.bits.opcode
invalidate anonIn_1.c.valid
invalidate anonIn_1.c.ready
invalidate anonIn_1.b.bits.corrupt
invalidate anonIn_1.b.bits.data
invalidate anonIn_1.b.bits.mask
invalidate anonIn_1.b.bits.address
invalidate anonIn_1.b.bits.source
invalidate anonIn_1.b.bits.size
invalidate anonIn_1.b.bits.param
invalidate anonIn_1.b.bits.opcode
invalidate anonIn_1.b.valid
invalidate anonIn_1.b.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_1
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink
connect monitor_1.io.in.e.valid, anonIn_1.e.valid
connect monitor_1.io.in.e.ready, anonIn_1.e.ready
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt
connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data
connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address
connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source
connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size
connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param
connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode
connect monitor_1.io.in.c.valid, anonIn_1.c.valid
connect monitor_1.io.in.c.ready, anonIn_1.c.ready
connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt
connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data
connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask
connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address
connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source
connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size
connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param
connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode
connect monitor_1.io.in.b.valid, anonIn_1.b.valid
connect monitor_1.io.in.b.ready, anonIn_1.b.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_anonOut.e.bits.sink
invalidate x1_anonOut.e.valid
invalidate x1_anonOut.e.ready
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.c.bits.corrupt
invalidate x1_anonOut.c.bits.data
invalidate x1_anonOut.c.bits.address
invalidate x1_anonOut.c.bits.source
invalidate x1_anonOut.c.bits.size
invalidate x1_anonOut.c.bits.param
invalidate x1_anonOut.c.bits.opcode
invalidate x1_anonOut.c.valid
invalidate x1_anonOut.c.ready
invalidate x1_anonOut.b.bits.corrupt
invalidate x1_anonOut.b.bits.data
invalidate x1_anonOut.b.bits.mask
invalidate x1_anonOut.b.bits.address
invalidate x1_anonOut.b.bits.source
invalidate x1_anonOut.b.bits.size
invalidate x1_anonOut.b.bits.param
invalidate x1_anonOut.b.bits.opcode
invalidate x1_anonOut.b.valid
invalidate x1_anonOut.b.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
invalidate in[0].b.valid
invalidate in[0].b.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
connect in[0].b.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
invalidate in[0].c.bits.corrupt
invalidate in[0].c.bits.data
invalidate in[0].c.bits.address
invalidate in[0].c.bits.source
invalidate in[0].c.bits.size
invalidate in[0].c.bits.param
invalidate in[0].c.bits.opcode
invalidate in[0].c.valid
invalidate in[0].c.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
invalidate _WIRE_5.bits.corrupt
invalidate _WIRE_5.bits.data
invalidate _WIRE_5.bits.address
invalidate _WIRE_5.bits.source
invalidate _WIRE_5.bits.size
invalidate _WIRE_5.bits.param
invalidate _WIRE_5.bits.opcode
invalidate _WIRE_5.valid
invalidate _WIRE_5.ready
connect in[0].c.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
invalidate in[0].e.bits.sink
invalidate in[0].e.valid
invalidate in[0].e.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits.sink, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.sink
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
connect in[0].e.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<6>(0h20))
connect in[1].a.bits.source, _in_1_a_bits_source_T
connect anonIn_1.b.bits.corrupt, in[1].b.bits.corrupt
connect anonIn_1.b.bits.data, in[1].b.bits.data
connect anonIn_1.b.bits.mask, in[1].b.bits.mask
connect anonIn_1.b.bits.address, in[1].b.bits.address
connect anonIn_1.b.bits.source, in[1].b.bits.source
connect anonIn_1.b.bits.size, in[1].b.bits.size
connect anonIn_1.b.bits.param, in[1].b.bits.param
connect anonIn_1.b.bits.opcode, in[1].b.bits.opcode
connect anonIn_1.b.valid, in[1].b.valid
connect in[1].b.ready, anonIn_1.b.ready
node _anonIn_b_bits_source_T = bits(in[1].b.bits.source, 1, 0)
connect anonIn_1.b.bits.source, _anonIn_b_bits_source_T
connect in[1].c.bits.corrupt, anonIn_1.c.bits.corrupt
connect in[1].c.bits.data, anonIn_1.c.bits.data
connect in[1].c.bits.address, anonIn_1.c.bits.address
connect in[1].c.bits.source, anonIn_1.c.bits.source
connect in[1].c.bits.size, anonIn_1.c.bits.size
connect in[1].c.bits.param, anonIn_1.c.bits.param
connect in[1].c.bits.opcode, anonIn_1.c.bits.opcode
connect in[1].c.valid, anonIn_1.c.valid
connect anonIn_1.c.ready, in[1].c.ready
node _in_1_c_bits_source_T = or(anonIn_1.c.bits.source, UInt<6>(0h20))
connect in[1].c.bits.source, _in_1_c_bits_source_T
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 1, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1
connect in[1].e.bits.sink, anonIn_1.e.bits.sink
connect in[1].e.valid, anonIn_1.e.valid
connect anonIn_1.e.ready, in[1].e.ready
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
invalidate out[0].b.bits.corrupt
invalidate out[0].b.bits.data
invalidate out[0].b.bits.mask
invalidate out[0].b.bits.address
invalidate out[0].b.bits.source
invalidate out[0].b.bits.size
invalidate out[0].b.bits.param
invalidate out[0].b.bits.opcode
invalidate out[0].b.valid
invalidate out[0].b.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.mask, UInt<8>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<2>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
invalidate _WIRE_13.bits.corrupt
invalidate _WIRE_13.bits.data
invalidate _WIRE_13.bits.mask
invalidate _WIRE_13.bits.address
invalidate _WIRE_13.bits.source
invalidate _WIRE_13.bits.size
invalidate _WIRE_13.bits.param
invalidate _WIRE_13.bits.opcode
invalidate _WIRE_13.valid
invalidate _WIRE_13.ready
connect out[0].b.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.mask, UInt<8>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<2>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].c.valid
invalidate out[0].c.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.corrupt
invalidate _WIRE_17.bits.data
invalidate _WIRE_17.bits.address
invalidate _WIRE_17.bits.source
invalidate _WIRE_17.bits.size
invalidate _WIRE_17.bits.param
invalidate _WIRE_17.bits.opcode
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
connect out[0].c.ready, UInt<1>(0h1)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
invalidate out[0].e.bits.sink
invalidate out[0].e.valid
invalidate out[0].e.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
invalidate _WIRE_21.bits.sink
invalidate _WIRE_21.valid
invalidate _WIRE_21.ready
connect out[0].e.ready, UInt<1>(0h1)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.valid, UInt<1>(0h0)
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
connect out[1].b.bits.corrupt, x1_anonOut.b.bits.corrupt
connect out[1].b.bits.data, x1_anonOut.b.bits.data
connect out[1].b.bits.mask, x1_anonOut.b.bits.mask
connect out[1].b.bits.address, x1_anonOut.b.bits.address
connect out[1].b.bits.source, x1_anonOut.b.bits.source
connect out[1].b.bits.size, x1_anonOut.b.bits.size
connect out[1].b.bits.param, x1_anonOut.b.bits.param
connect out[1].b.bits.opcode, x1_anonOut.b.bits.opcode
connect out[1].b.valid, x1_anonOut.b.valid
connect x1_anonOut.b.ready, out[1].b.ready
connect x1_anonOut.c.bits.corrupt, out[1].c.bits.corrupt
connect x1_anonOut.c.bits.data, out[1].c.bits.data
connect x1_anonOut.c.bits.address, out[1].c.bits.address
connect x1_anonOut.c.bits.source, out[1].c.bits.source
connect x1_anonOut.c.bits.size, out[1].c.bits.size
connect x1_anonOut.c.bits.param, out[1].c.bits.param
connect x1_anonOut.c.bits.opcode, out[1].c.bits.opcode
connect x1_anonOut.c.valid, out[1].c.valid
connect out[1].c.ready, x1_anonOut.c.ready
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
connect x1_anonOut.e.bits.sink, out[1].e.bits.sink
connect x1_anonOut.e.valid, out[1].e.valid
connect out[1].e.ready, x1_anonOut.e.ready
node _anonOut_e_bits_sink_T = bits(out[1].e.bits.sink, 2, 0)
connect x1_anonOut.e.bits.sink, _anonOut_e_bits_sink_T
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9)
node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14)
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16)
node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_18 = cvt(_requestAIO_T_17)
node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_20 = asSInt(_requestAIO_T_19)
node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0)))
node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_23 = cvt(_requestAIO_T_22)
node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_25 = asSInt(_requestAIO_T_24)
node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0)))
node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26)
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27)
node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_29 = cvt(_requestAIO_T_28)
node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_31 = asSInt(_requestAIO_T_30)
node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0)))
node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_34 = cvt(_requestAIO_T_33)
node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_36 = asSInt(_requestAIO_T_35)
node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0)))
node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_39 = cvt(_requestAIO_T_38)
node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_41 = asSInt(_requestAIO_T_40)
node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0)))
node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37)
node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42)
node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44)
node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_46 = cvt(_requestAIO_T_45)
node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_48 = asSInt(_requestAIO_T_47)
node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0)))
node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_51 = cvt(_requestAIO_T_50)
node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_53 = asSInt(_requestAIO_T_52)
node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0)))
node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54)
node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55)
node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14)
node _requestCIO_T_15 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_16 = cvt(_requestCIO_T_15)
node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0)))
node _requestCIO_T_18 = asSInt(_requestCIO_T_17)
node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0)))
node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19)
node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0)
node _requestBOI_T = shr(out[0].b.bits.source, 5)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0)
node _requestBOI_T_5 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<4>(0h8))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3))
node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9)
node _requestBOI_uncommonBits_T_2 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 4, 0)
node _requestBOI_T_10 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<5>(0h1f))
node requestBOI_1_0 = and(_requestBOI_T_13, _requestBOI_T_14)
node _requestBOI_uncommonBits_T_3 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 1, 0)
node _requestBOI_T_15 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<4>(0h8))
node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3)
node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17)
node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<2>(0h3))
node requestBOI_1_1 = and(_requestBOI_T_18, _requestBOI_T_19)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 5)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<4>(0h8))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3))
node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 4, 0)
node _requestDOI_T_10 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<5>(0h1f))
node requestDOI_1_0 = and(_requestDOI_T_13, _requestDOI_T_14)
node _requestDOI_uncommonBits_T_3 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 1, 0)
node _requestDOI_T_15 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<4>(0h8))
node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3)
node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17)
node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<2>(0h3))
node requestDOI_1_1 = and(_requestDOI_T_18, _requestDOI_T_19)
node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0)
node _requestEIO_T = shr(in[0].e.bits.sink, 3)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7))
node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4)
node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0)
node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7))
node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].b.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(out[1].b.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0)
node beatsCI_1 = mux(beatsCI_opdata_1, beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect portsAOI_filtered_1[1].bits, in[1].a.bits
node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2)
connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3
node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1)
wire _portsAOI_in_1_a_ready_WIRE : UInt<1>
connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2
connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[0].bits.data, out[0].b.bits.data
connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[0].bits.address, out[0].b.bits.address
connect portsBIO_filtered[0].bits.source, out[0].b.bits.source
connect portsBIO_filtered[0].bits.size, out[0].b.bits.size
connect portsBIO_filtered[0].bits.param, out[0].b.bits.param
connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[1].bits.data, out[0].b.bits.data
connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[1].bits.address, out[0].b.bits.address
connect portsBIO_filtered[1].bits.source, out[0].b.bits.source
connect portsBIO_filtered[1].bits.size, out[0].b.bits.size
connect portsBIO_filtered[1].bits.param, out[0].b.bits.param
connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1)
wire _portsBIO_out_0_b_ready_WIRE : UInt<1>
connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2
connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered_1[0].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[0].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[0].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[0].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[0].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[0].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[0].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[0].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect portsBIO_filtered_1[1].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[1].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[1].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[1].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[1].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[1].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[1].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[1].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_1_valid_T_2)
connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3
node _portsBIO_out_1_b_ready_T = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_1 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_2 = or(_portsBIO_out_1_b_ready_T, _portsBIO_out_1_b_ready_T_1)
wire _portsBIO_out_1_b_ready_WIRE : UInt<1>
connect _portsBIO_out_1_b_ready_WIRE, _portsBIO_out_1_b_ready_T_2
connect out[1].b.ready, _portsBIO_out_1_b_ready_WIRE
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered[0].bits, in[0].c.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, in[0].c.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
node _portsCOI_in_0_c_ready_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_2 = or(_portsCOI_in_0_c_ready_T, _portsCOI_in_0_c_ready_T_1)
wire _portsCOI_in_0_c_ready_WIRE : UInt<1>
connect _portsCOI_in_0_c_ready_WIRE, _portsCOI_in_0_c_ready_T_2
connect in[0].c.ready, _portsCOI_in_0_c_ready_WIRE
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_1[0].bits, in[1].c.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect portsCOI_filtered_1[1].bits, in[1].c.bits
node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_1_valid_T_2)
connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3
node _portsCOI_in_1_c_ready_T = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_1 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_2 = or(_portsCOI_in_1_c_ready_T, _portsCOI_in_1_c_ready_T_1)
wire _portsCOI_in_1_c_ready_WIRE : UInt<1>
connect _portsCOI_in_1_c_ready_WIRE, _portsCOI_in_1_c_ready_T_2
connect in[1].c.ready, _portsCOI_in_1_c_ready_WIRE
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2)
connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3
node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_2 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1)
wire _portsDIO_out_1_d_ready_WIRE : UInt<1>
connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_2
connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered[0].bits, in[0].e.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, in[0].e.bits
node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
node _portsEOI_in_0_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_2 = or(_portsEOI_in_0_e_ready_T, _portsEOI_in_0_e_ready_T_1)
wire _portsEOI_in_0_e_ready_WIRE : UInt<1>
connect _portsEOI_in_0_e_ready_WIRE, _portsEOI_in_0_e_ready_T_2
connect in[0].e.ready, _portsEOI_in_0_e_ready_WIRE
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_1[0].bits, in[1].e.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect portsEOI_filtered_1[1].bits, in[1].e.bits
node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_1_valid_T_2)
connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3
node _portsEOI_in_1_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_1 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_2 = or(_portsEOI_in_1_e_ready_T, _portsEOI_in_1_e_ready_T_1)
wire _portsEOI_in_1_e_ready_WIRE : UInt<1>
connect _portsEOI_in_1_e_ready_WIRE, _portsEOI_in_1_e_ready_T_2
connect in[1].e.ready, _portsEOI_in_1_e_ready_WIRE
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<6>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].e.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft_1, UInt<1>(0h0))
node latch_1 = and(idle_1, out[1].a.ready)
node _readys_T_10 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid)
node readys_valid_1 = bits(_readys_T_10, 1, 0)
node _readys_T_11 = eq(readys_valid_1, _readys_T_10)
node _readys_T_12 = asUInt(reset)
node _readys_T_13 = eq(_readys_T_12, UInt<1>(0h0))
when _readys_T_13 :
node _readys_T_14 = eq(_readys_T_11, UInt<1>(0h0))
when _readys_T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1
assert(clock, _readys_T_11, UInt<1>(0h1), "") : readys_assert_1
regreset readys_mask_1 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_2 = not(readys_mask_1)
node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2)
node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1)
node _readys_unready_T_5 = shr(readys_filter_1, 1)
node _readys_unready_T_6 = or(readys_filter_1, _readys_unready_T_5)
node _readys_unready_T_7 = bits(_readys_unready_T_6, 3, 0)
node _readys_unready_T_8 = shr(_readys_unready_T_7, 1)
node _readys_unready_T_9 = shl(readys_mask_1, 2)
node readys_unready_1 = or(_readys_unready_T_8, _readys_unready_T_9)
node _readys_readys_T_3 = shr(readys_unready_1, 2)
node _readys_readys_T_4 = bits(readys_unready_1, 1, 0)
node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4)
node readys_readys_1 = not(_readys_readys_T_5)
node _readys_T_15 = orr(readys_valid_1)
node _readys_T_16 = and(latch_1, _readys_T_15)
when _readys_T_16 :
node _readys_mask_T_5 = and(readys_readys_1, readys_valid_1)
node _readys_mask_T_6 = shl(_readys_mask_T_5, 1)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 1, 0)
node _readys_mask_T_8 = or(_readys_mask_T_5, _readys_mask_T_7)
node _readys_mask_T_9 = bits(_readys_mask_T_8, 1, 0)
connect readys_mask_1, _readys_mask_T_9
node _readys_T_17 = bits(readys_readys_1, 1, 0)
node _readys_T_18 = bits(_readys_T_17, 0, 0)
node _readys_T_19 = bits(_readys_T_17, 1, 1)
wire readys_1 : UInt<1>[2]
connect readys_1[0], _readys_T_18
connect readys_1[1], _readys_T_19
node _winner_T_2 = and(readys_1[0], portsAOI_filtered[1].valid)
node _winner_T_3 = and(readys_1[1], portsAOI_filtered_1[1].valid)
wire winner_1 : UInt<1>[2]
connect winner_1[0], _winner_T_2
connect winner_1[1], _winner_T_3
node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0])
node _prefixOR_T_1 = or(prefixOR_1_1, winner_1[1])
node _T_17 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_18 = eq(winner_1[0], UInt<1>(0h0))
node _T_19 = or(_T_17, _T_18)
node _T_20 = eq(prefixOR_1_1, UInt<1>(0h0))
node _T_21 = eq(winner_1[1], UInt<1>(0h0))
node _T_22 = or(_T_20, _T_21)
node _T_23 = and(_T_19, _T_22)
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2
assert(clock, _T_23, UInt<1>(0h1), "") : assert_2
node _T_27 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _T_28 = eq(_T_27, UInt<1>(0h0))
node _T_29 = or(winner_1[0], winner_1[1])
node _T_30 = or(_T_28, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3
assert(clock, _T_30, UInt<1>(0h1), "") : assert_3
node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0))
node initBeats_1 = or(maskedBeats_0_1, maskedBeats_1_1)
node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid)
node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4)
node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1)
node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6)
connect beatsLeft_1, _beatsLeft_T_7
wire _state_WIRE_1 : UInt<1>[2]
connect _state_WIRE_1[0], UInt<1>(0h0)
connect _state_WIRE_1[1], UInt<1>(0h0)
regreset state_1 : UInt<1>[2], clock, reset, _state_WIRE_1
node muxState_1 = mux(idle_1, winner_1, state_1)
connect state_1, muxState_1
node allowed_1 = mux(idle_1, readys_1, state_1)
node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0])
connect portsAOI_filtered[1].ready, _filtered_1_ready_T
node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1])
connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1
node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _out_1_a_valid_T_1 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_2 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_1, _out_1_a_valid_T_2)
wire _out_1_a_valid_WIRE : UInt<1>
connect _out_1_a_valid_WIRE, _out_1_a_valid_T_3
node _out_1_a_valid_T_4 = mux(idle_1, _out_1_a_valid_T, _out_1_a_valid_WIRE)
connect out[1].a.valid, _out_1_a_valid_T_4
wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_2 = or(_out_1_a_bits_T, _out_1_a_bits_T_1)
wire _out_1_a_bits_WIRE_1 : UInt<1>
connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_2
connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1
node _out_1_a_bits_T_3 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_4 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_5 = or(_out_1_a_bits_T_3, _out_1_a_bits_T_4)
wire _out_1_a_bits_WIRE_2 : UInt<64>
connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_5
connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2
node _out_1_a_bits_T_6 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_7 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_6, _out_1_a_bits_T_7)
wire _out_1_a_bits_WIRE_3 : UInt<8>
connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_8
connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3
wire _out_1_a_bits_WIRE_4 : { }
connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4
wire _out_1_a_bits_WIRE_5 : { }
connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5
node _out_1_a_bits_T_9 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_10 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_11 = or(_out_1_a_bits_T_9, _out_1_a_bits_T_10)
wire _out_1_a_bits_WIRE_6 : UInt<32>
connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_11
connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6
node _out_1_a_bits_T_12 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_13 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_12, _out_1_a_bits_T_13)
wire _out_1_a_bits_WIRE_7 : UInt<6>
connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_14
connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7
node _out_1_a_bits_T_15 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_16 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_17 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_16)
wire _out_1_a_bits_WIRE_8 : UInt<4>
connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_17
connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8
node _out_1_a_bits_T_18 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_19 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_20 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_19)
wire _out_1_a_bits_WIRE_9 : UInt<3>
connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_20
connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9
node _out_1_a_bits_T_21 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_22 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_21, _out_1_a_bits_T_22)
wire _out_1_a_bits_WIRE_10 : UInt<3>
connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_23
connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10
connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt
connect out[1].a.bits.data, _out_1_a_bits_WIRE.data
connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask
connect out[1].a.bits.address, _out_1_a_bits_WIRE.address
connect out[1].a.bits.source, _out_1_a_bits_WIRE.source
connect out[1].a.bits.size, _out_1_a_bits_WIRE.size
connect out[1].a.bits.param, _out_1_a_bits_WIRE.param
connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode
connect out[1].c, portsCOI_filtered_1[1]
connect out[1].e, portsEOI_filtered_1[1]
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0)
node idle_2 = eq(beatsLeft_2, UInt<1>(0h0))
node latch_2 = and(idle_2, in[0].d.ready)
node _readys_T_20 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid)
node readys_valid_2 = bits(_readys_T_20, 1, 0)
node _readys_T_21 = eq(readys_valid_2, _readys_T_20)
node _readys_T_22 = asUInt(reset)
node _readys_T_23 = eq(_readys_T_22, UInt<1>(0h0))
when _readys_T_23 :
node _readys_T_24 = eq(_readys_T_21, UInt<1>(0h0))
when _readys_T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2
assert(clock, _readys_T_21, UInt<1>(0h1), "") : readys_assert_2
regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_4 = not(readys_mask_2)
node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4)
node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2)
node _readys_unready_T_10 = shr(readys_filter_2, 1)
node _readys_unready_T_11 = or(readys_filter_2, _readys_unready_T_10)
node _readys_unready_T_12 = bits(_readys_unready_T_11, 3, 0)
node _readys_unready_T_13 = shr(_readys_unready_T_12, 1)
node _readys_unready_T_14 = shl(readys_mask_2, 2)
node readys_unready_2 = or(_readys_unready_T_13, _readys_unready_T_14)
node _readys_readys_T_6 = shr(readys_unready_2, 2)
node _readys_readys_T_7 = bits(readys_unready_2, 1, 0)
node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7)
node readys_readys_2 = not(_readys_readys_T_8)
node _readys_T_25 = orr(readys_valid_2)
node _readys_T_26 = and(latch_2, _readys_T_25)
when _readys_T_26 :
node _readys_mask_T_10 = and(readys_readys_2, readys_valid_2)
node _readys_mask_T_11 = shl(_readys_mask_T_10, 1)
node _readys_mask_T_12 = bits(_readys_mask_T_11, 1, 0)
node _readys_mask_T_13 = or(_readys_mask_T_10, _readys_mask_T_12)
node _readys_mask_T_14 = bits(_readys_mask_T_13, 1, 0)
connect readys_mask_2, _readys_mask_T_14
node _readys_T_27 = bits(readys_readys_2, 1, 0)
node _readys_T_28 = bits(_readys_T_27, 0, 0)
node _readys_T_29 = bits(_readys_T_27, 1, 1)
wire readys_2 : UInt<1>[2]
connect readys_2[0], _readys_T_28
connect readys_2[1], _readys_T_29
node _winner_T_4 = and(readys_2[0], portsDIO_filtered[0].valid)
node _winner_T_5 = and(readys_2[1], portsDIO_filtered_1[0].valid)
wire winner_2 : UInt<1>[2]
connect winner_2[0], _winner_T_4
connect winner_2[1], _winner_T_5
node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0])
node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1])
node _T_34 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_35 = eq(winner_2[0], UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = eq(prefixOR_1_2, UInt<1>(0h0))
node _T_38 = eq(winner_2[1], UInt<1>(0h0))
node _T_39 = or(_T_37, _T_38)
node _T_40 = and(_T_36, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4
assert(clock, _T_40, UInt<1>(0h1), "") : assert_4
node _T_44 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_45 = eq(_T_44, UInt<1>(0h0))
node _T_46 = or(winner_2[0], winner_2[1])
node _T_47 = or(_T_45, _T_46)
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
node _T_50 = eq(_T_47, UInt<1>(0h0))
when _T_50 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5
assert(clock, _T_47, UInt<1>(0h1), "") : assert_5
node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0))
node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2)
node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8)
node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1)
node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10)
connect beatsLeft_2, _beatsLeft_T_11
wire _state_WIRE_2 : UInt<1>[2]
connect _state_WIRE_2[0], UInt<1>(0h0)
connect _state_WIRE_2[1], UInt<1>(0h0)
regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2
node muxState_2 = mux(idle_2, winner_2, state_2)
connect state_2, muxState_2
node allowed_2 = mux(idle_2, readys_2, state_2)
node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed_2[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T_2
node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed_2[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_3
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3
node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_4
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10)
wire _in_0_d_bits_WIRE_6 : UInt<3>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13)
wire _in_0_d_bits_WIRE_7 : UInt<6>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
wire _in_0_d_bits_WIRE_8 : UInt<4>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
connect in[1].b, portsBIO_filtered_1[1]
regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0)
node idle_3 = eq(beatsLeft_3, UInt<1>(0h0))
node latch_3 = and(idle_3, in[1].d.ready)
node _readys_T_30 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid)
node readys_valid_3 = bits(_readys_T_30, 1, 0)
node _readys_T_31 = eq(readys_valid_3, _readys_T_30)
node _readys_T_32 = asUInt(reset)
node _readys_T_33 = eq(_readys_T_32, UInt<1>(0h0))
when _readys_T_33 :
node _readys_T_34 = eq(_readys_T_31, UInt<1>(0h0))
when _readys_T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3
assert(clock, _readys_T_31, UInt<1>(0h1), "") : readys_assert_3
regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_6 = not(readys_mask_3)
node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6)
node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3)
node _readys_unready_T_15 = shr(readys_filter_3, 1)
node _readys_unready_T_16 = or(readys_filter_3, _readys_unready_T_15)
node _readys_unready_T_17 = bits(_readys_unready_T_16, 3, 0)
node _readys_unready_T_18 = shr(_readys_unready_T_17, 1)
node _readys_unready_T_19 = shl(readys_mask_3, 2)
node readys_unready_3 = or(_readys_unready_T_18, _readys_unready_T_19)
node _readys_readys_T_9 = shr(readys_unready_3, 2)
node _readys_readys_T_10 = bits(readys_unready_3, 1, 0)
node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10)
node readys_readys_3 = not(_readys_readys_T_11)
node _readys_T_35 = orr(readys_valid_3)
node _readys_T_36 = and(latch_3, _readys_T_35)
when _readys_T_36 :
node _readys_mask_T_15 = and(readys_readys_3, readys_valid_3)
node _readys_mask_T_16 = shl(_readys_mask_T_15, 1)
node _readys_mask_T_17 = bits(_readys_mask_T_16, 1, 0)
node _readys_mask_T_18 = or(_readys_mask_T_15, _readys_mask_T_17)
node _readys_mask_T_19 = bits(_readys_mask_T_18, 1, 0)
connect readys_mask_3, _readys_mask_T_19
node _readys_T_37 = bits(readys_readys_3, 1, 0)
node _readys_T_38 = bits(_readys_T_37, 0, 0)
node _readys_T_39 = bits(_readys_T_37, 1, 1)
wire readys_3 : UInt<1>[2]
connect readys_3[0], _readys_T_38
connect readys_3[1], _readys_T_39
node _winner_T_6 = and(readys_3[0], portsDIO_filtered[1].valid)
node _winner_T_7 = and(readys_3[1], portsDIO_filtered_1[1].valid)
wire winner_3 : UInt<1>[2]
connect winner_3[0], _winner_T_6
connect winner_3[1], _winner_T_7
node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0])
node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1])
node _T_51 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_52 = eq(winner_3[0], UInt<1>(0h0))
node _T_53 = or(_T_51, _T_52)
node _T_54 = eq(prefixOR_1_3, UInt<1>(0h0))
node _T_55 = eq(winner_3[1], UInt<1>(0h0))
node _T_56 = or(_T_54, _T_55)
node _T_57 = and(_T_53, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_6
assert(clock, _T_57, UInt<1>(0h1), "") : assert_6
node _T_61 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _T_62 = eq(_T_61, UInt<1>(0h0))
node _T_63 = or(winner_3[0], winner_3[1])
node _T_64 = or(_T_62, _T_63)
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_7
assert(clock, _T_64, UInt<1>(0h1), "") : assert_7
node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0))
node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3)
node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid)
node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12)
node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1)
node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14)
connect beatsLeft_3, _beatsLeft_T_15
wire _state_WIRE_3 : UInt<1>[2]
connect _state_WIRE_3[0], UInt<1>(0h0)
connect _state_WIRE_3[1], UInt<1>(0h0)
regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3
node muxState_3 = mux(idle_3, winner_3, state_3)
connect state_3, muxState_3
node allowed_3 = mux(idle_3, readys_3, state_3)
node _filtered_1_ready_T_2 = and(in[1].d.ready, allowed_3[0])
connect portsDIO_filtered[1].ready, _filtered_1_ready_T_2
node _filtered_1_ready_T_3 = and(in[1].d.ready, allowed_3[1])
connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_3
node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2)
wire _in_1_d_valid_WIRE : UInt<1>
connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3
node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE)
connect in[1].d.valid, _in_1_d_valid_T_4
wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1)
wire _in_1_d_bits_WIRE_1 : UInt<1>
connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2
connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1
node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4)
wire _in_1_d_bits_WIRE_2 : UInt<64>
connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5
connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2
wire _in_1_d_bits_WIRE_3 : { }
connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3
wire _in_1_d_bits_WIRE_4 : { }
connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4
node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7)
wire _in_1_d_bits_WIRE_5 : UInt<1>
connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8
connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5
node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10)
wire _in_1_d_bits_WIRE_6 : UInt<3>
connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11
connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6
node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13)
wire _in_1_d_bits_WIRE_7 : UInt<6>
connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14
connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7
node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16)
wire _in_1_d_bits_WIRE_8 : UInt<4>
connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17
connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8
node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19)
wire _in_1_d_bits_WIRE_9 : UInt<2>
connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20
connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9
node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22)
wire _in_1_d_bits_WIRE_10 : UInt<3>
connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23
connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10
connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt
connect in[1].d.bits.data, _in_1_d_bits_WIRE.data
connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied
connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink
connect in[1].d.bits.source, _in_1_d_bits_WIRE.source
connect in[1].d.bits.size, _in_1_d_bits_WIRE.size
connect in[1].d.bits.param, _in_1_d_bits_WIRE.param
connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode
connect portsBIO_filtered[1].ready, UInt<1>(0h0) | module TLXbar_sbus_i2_o2_a32d64s6k3z4c( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [2:0] out_1_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [5:0] in_1_c_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_b_ready_0 = auto_anon_in_1_b_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_1_c_valid_0 = auto_anon_in_1_c_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_c_bits_opcode_0 = auto_anon_in_1_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_c_bits_param_0 = auto_anon_in_1_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_c_bits_size_0 = auto_anon_in_1_c_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_c_bits_source_0 = auto_anon_in_1_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_c_bits_address_0 = auto_anon_in_1_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_c_bits_data_0 = auto_anon_in_1_c_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_c_bits_corrupt_0 = auto_anon_in_1_c_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_1_e_valid_0 = auto_anon_in_1_e_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_e_bits_sink_0 = auto_anon_in_1_e_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_b_valid_0 = auto_anon_out_1_b_valid; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_1_b_bits_param_0 = auto_anon_out_1_b_bits_param; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_1_b_bits_address_0 = auto_anon_out_1_b_bits_address; // @[Xbar.scala:74:9]
wire auto_anon_out_1_c_ready_0 = auto_anon_out_1_c_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_12 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_22 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_32 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_b_bits_size = 3'h6; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_1_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [3:0] auto_anon_in_1_b_bits_size = 4'h6; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] in_1_b_bits_size = 4'h6; // @[Xbar.scala:159:18]
wire [3:0] out_1_b_bits_size = 4'h6; // @[Xbar.scala:216:19]
wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_1_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [1:0] auto_anon_in_1_b_bits_source = 2'h1; // @[Xbar.scala:74:9]
wire [1:0] anonIn_1_b_bits_source = 2'h1; // @[MixedNode.scala:551:17]
wire [1:0] _anonIn_b_bits_source_T = 2'h1; // @[Xbar.scala:156:69]
wire [1:0] requestBOI_uncommonBits_3 = 2'h1; // @[Parameters.scala:52:56]
wire [7:0] auto_anon_in_1_b_bits_mask = 8'hFF; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_b_bits_mask = 8'hFF; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] x1_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] in_1_b_bits_mask = 8'hFF; // @[Xbar.scala:159:18]
wire [7:0] out_1_b_bits_mask = 8'hFF; // @[Xbar.scala:216:19]
wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_1_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [63:0] auto_anon_in_1_b_bits_data = 64'h0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_b_bits_data = 64'h0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] x1_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] in_0_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_0_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] out_0_b_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] out_0_c_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] out_1_b_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire auto_anon_in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire in_0_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_0_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire out_0_b_ready = 1'h0; // @[Xbar.scala:216:19]
wire out_0_b_valid = 1'h0; // @[Xbar.scala:216:19]
wire out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_0_c_valid = 1'h0; // @[Xbar.scala:216:19]
wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_0_e_valid = 1'h0; // @[Xbar.scala:216:19]
wire out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_T_6 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_8 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_11 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_13 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_0 = 1'h0; // @[Parameters.scala:56:48]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire beatsBO_opdata_1 = 1'h0; // @[Edges.scala:97:28]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_out_0_b_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_out_1_b_ready_T = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_0_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_0_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_0_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_0_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_in_1_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_0_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_0_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_0_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_0_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_1_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34]
wire auto_anon_in_1_e_ready = 1'h1; // @[Xbar.scala:74:9]
wire auto_anon_out_1_e_ready = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_1_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire in_0_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_1_e_ready = 1'h1; // @[Xbar.scala:159:18]
wire out_0_c_ready = 1'h1; // @[Xbar.scala:216:19]
wire out_0_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire out_1_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_10 = 1'h1; // @[Parameters.scala:54:10]
wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_16 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_18 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_1_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_1 = 1'h1; // @[Parameters.scala:56:48]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire _beatsBO_opdata_T_1 = 1'h1; // @[Edges.scala:97:37]
wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire portsEOI_filtered_1_1_ready = 1'h1; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_in_1_e_ready_T_1 = 1'h1; // @[Mux.scala:30:73]
wire _portsEOI_in_1_e_ready_T_2 = 1'h1; // @[Mux.scala:30:73]
wire _portsEOI_in_1_e_ready_WIRE = 1'h1; // @[Mux.scala:30:73]
wire [5:0] auto_anon_out_1_b_bits_source = 6'h21; // @[Xbar.scala:74:9]
wire [5:0] x1_anonOut_b_bits_source = 6'h21; // @[MixedNode.scala:542:17]
wire [5:0] in_1_b_bits_source = 6'h21; // @[Xbar.scala:159:18]
wire [5:0] out_1_b_bits_source = 6'h21; // @[Xbar.scala:216:19]
wire [5:0] _requestBOI_uncommonBits_T_2 = 6'h21; // @[Parameters.scala:52:29]
wire [5:0] _requestBOI_uncommonBits_T_3 = 6'h21; // @[Parameters.scala:52:29]
wire [5:0] portsBIO_filtered_1_0_bits_source = 6'h21; // @[Xbar.scala:352:24]
wire [5:0] portsBIO_filtered_1_1_bits_source = 6'h21; // @[Xbar.scala:352:24]
wire [2:0] in_0_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] out_0_b_bits_opcode = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] out_0_c_bits_opcode = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] out_0_c_bits_param = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] out_0_e_bits_sink = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] _requestEIO_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [31:0] in_0_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_0_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] out_0_b_bits_address = 32'h0; // @[Xbar.scala:216:19]
wire [31:0] out_0_c_bits_address = 32'h0; // @[Xbar.scala:216:19]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [5:0] in_0_b_bits_source = 6'h0; // @[Xbar.scala:159:18]
wire [5:0] in_0_c_bits_source = 6'h0; // @[Xbar.scala:159:18]
wire [5:0] out_0_b_bits_source = 6'h0; // @[Xbar.scala:216:19]
wire [5:0] out_0_c_bits_source = 6'h0; // @[Xbar.scala:216:19]
wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29]
wire [5:0] _requestBOI_uncommonBits_T_1 = 6'h0; // @[Parameters.scala:52:29]
wire [5:0] _beatsBO_decode_T_4 = 6'h0; // @[package.scala:243:76]
wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] portsBIO_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] portsCOI_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [3:0] in_0_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_0_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] out_0_b_bits_size = 4'h0; // @[Xbar.scala:216:19]
wire [3:0] out_0_c_bits_size = 4'h0; // @[Xbar.scala:216:19]
wire [3:0] _requestBOI_T_5 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [7:0] in_0_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] out_0_b_bits_mask = 8'h0; // @[Xbar.scala:216:19]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [1:0] in_0_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] out_0_b_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] requestBOI_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] beatsBO_decode_1 = 3'h7; // @[Edges.scala:220:59]
wire [5:0] _beatsBO_decode_T_5 = 6'h3F; // @[package.scala:243:46]
wire [20:0] _beatsBO_decode_T_3 = 21'hFC0; // @[package.scala:243:71]
wire [3:0] _requestBOI_T_15 = 4'h8; // @[Parameters.scala:54:10]
wire [4:0] requestBOI_uncommonBits_2 = 5'h1; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_b_ready = auto_anon_in_1_b_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_b_valid; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_b_bits_param; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_1_b_bits_address; // @[MixedNode.scala:551:17]
wire anonIn_1_c_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_c_valid = auto_anon_in_1_c_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_c_bits_opcode = auto_anon_in_1_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_c_bits_param = auto_anon_in_1_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_c_bits_size = auto_anon_in_1_c_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_1_c_bits_source = auto_anon_in_1_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_c_bits_address = auto_anon_in_1_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_c_bits_data = auto_anon_in_1_c_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_c_bits_corrupt = auto_anon_in_1_c_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_1_e_valid = auto_anon_in_1_e_valid_0; // @[Xbar.scala:74:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_e_bits_sink = auto_anon_in_1_e_bits_sink_0; // @[Xbar.scala:74:9]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_b_valid = auto_anon_out_1_b_valid_0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_b_bits_param = auto_anon_out_1_b_bits_param_0; // @[Xbar.scala:74:9]
wire [31:0] x1_anonOut_b_bits_address = auto_anon_out_1_b_bits_address_0; // @[Xbar.scala:74:9]
wire x1_anonOut_c_ready = auto_anon_out_1_c_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire x1_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_b_bits_param_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_b_bits_address_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_b_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_c_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_b_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_c_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_c_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_1_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_1_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_c_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_c_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_c_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_e_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_e_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [28:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_b_ready = anonIn_1_b_ready; // @[Xbar.scala:159:18]
wire in_1_b_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_valid_0 = anonIn_1_b_valid; // @[Xbar.scala:74:9]
wire [1:0] in_1_b_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_param_0 = anonIn_1_b_bits_param; // @[Xbar.scala:74:9]
wire [31:0] in_1_b_bits_address; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_address_0 = anonIn_1_b_bits_address; // @[Xbar.scala:74:9]
wire in_1_c_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_c_ready_0 = anonIn_1_c_ready; // @[Xbar.scala:74:9]
wire in_1_c_valid = anonIn_1_c_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_opcode = anonIn_1_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_param = anonIn_1_c_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_c_bits_size = anonIn_1_c_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_1_c_bits_address = anonIn_1_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] in_1_c_bits_data = anonIn_1_c_bits_data; // @[Xbar.scala:159:18]
wire in_1_c_bits_corrupt = anonIn_1_c_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_e_valid = anonIn_1_e_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_e_bits_sink = anonIn_1_e_bits_sink; // @[Xbar.scala:159:18]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_1_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [5:0] out_1_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_1_b_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_1_b_ready_0 = x1_anonOut_b_ready; // @[Xbar.scala:74:9]
wire out_1_b_valid = x1_anonOut_b_valid; // @[Xbar.scala:216:19]
wire [1:0] out_1_b_bits_param = x1_anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [31:0] out_1_b_bits_address = x1_anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire out_1_c_ready = x1_anonOut_c_ready; // @[Xbar.scala:216:19]
wire out_1_c_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_valid_0 = x1_anonOut_c_valid; // @[Xbar.scala:74:9]
wire [2:0] out_1_c_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_opcode_0 = x1_anonOut_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_1_c_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_param_0 = x1_anonOut_c_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_1_c_bits_size_0 = x1_anonOut_c_bits_size; // @[Xbar.scala:74:9]
wire [5:0] out_1_c_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_source_0 = x1_anonOut_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_1_c_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_address_0 = x1_anonOut_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] out_1_c_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_data_0 = x1_anonOut_c_bits_data; // @[Xbar.scala:74:9]
wire out_1_c_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_corrupt_0 = x1_anonOut_c_bits_corrupt; // @[Xbar.scala:74:9]
wire out_1_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [5:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_1_e_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_e_valid_0 = x1_anonOut_e_valid; // @[Xbar.scala:74:9]
wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign auto_anon_out_1_e_bits_sink_0 = x1_anonOut_e_bits_sink; // @[Xbar.scala:74:9]
wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_1_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_1_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [5:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_1_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_1_1_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_28 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_1_1_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_1_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_1_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_1_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_1_1_ready = in_1_b_ready; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_1_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_b_valid = in_1_b_valid; // @[Xbar.scala:159:18]
wire [1:0] portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_param = in_1_b_bits_param; // @[Xbar.scala:159:18]
wire [31:0] portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_address = in_1_b_bits_address; // @[Xbar.scala:159:18]
wire _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_1_c_ready = in_1_c_ready; // @[Xbar.scala:159:18]
wire _portsCOI_filtered_0_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40]
wire _portsCOI_filtered_1_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_1_1_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_1_1_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [5:0] _in_1_c_bits_source_T; // @[Xbar.scala:187:55]
wire [3:0] portsCOI_filtered_1_0_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsCOI_filtered_1_1_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsCOI_filtered_1_0_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsCOI_filtered_1_1_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestCIO_T_10 = in_1_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] _requestCIO_T_15 = in_1_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsCOI_filtered_1_0_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsCOI_filtered_1_1_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsCOI_filtered_1_0_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsCOI_filtered_1_1_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsCOI_filtered_1_0_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsCOI_filtered_1_1_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_1_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsEOI_filtered_1_valid_T_3 = in_1_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] _requestEIO_uncommonBits_T_1 = in_1_e_bits_sink; // @[Xbar.scala:159:18]
wire [2:0] portsEOI_filtered_1_0_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsEOI_filtered_1_1_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign _in_1_a_bits_source_T = {4'h8, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55]
assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _in_1_c_bits_source_T = {4'h8, anonIn_1_c_bits_source}; // @[Xbar.scala:187:55]
assign in_1_c_bits_source = _in_1_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [5:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [5:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [5:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [5:0] portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _out_1_a_valid_T_4; // @[Arbiter.scala:96:24]
assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73]
wire [5:0] _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19]
wire [7:0] _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19]
wire _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73]
assign x1_anonOut_b_ready = out_1_b_ready; // @[Xbar.scala:216:19]
wire _portsBIO_filtered_1_valid_T_3 = out_1_b_valid; // @[Xbar.scala:216:19, :355:40]
wire [1:0] portsBIO_filtered_1_0_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_1_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_0_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_1_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_1_1_ready = out_1_c_ready; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_c_valid = out_1_c_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_opcode = out_1_c_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_param = out_1_c_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_source = out_1_c_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_address = out_1_c_bits_address; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_data = out_1_c_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_corrupt = out_1_c_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73]
assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19]
wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_1_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_1_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_1_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] _requestDOI_uncommonBits_T_2 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [5:0] _requestDOI_uncommonBits_T_3 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [5:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [5:0] portsDIO_filtered_1_1_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_1_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_1_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_1_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_1_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsEOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_e_valid = out_1_e_valid; // @[Xbar.scala:216:19]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign _anonOut_e_bits_sink_T = out_1_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_1_c_bits_size; // @[Xbar.scala:216:19]
assign anonOut_a_bits_address = out_0_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41]
assign out_0_d_bits_sink = {2'h0, _out_0_d_bits_sink_T}; // @[Xbar.scala:216:19, :251:{28,53}]
assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_c_bits_size = out_1_c_bits_size[2:0]; // @[Xbar.scala:216:19, :241:41]
assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign x1_anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46]
wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46]
wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46]
wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_15 = _requestAIO_T_4 | _requestAIO_T_9; // @[Xbar.scala:291:92]
wire _requestAIO_T_16 = _requestAIO_T_15 | _requestAIO_T_14; // @[Xbar.scala:291:92]
wire requestAIO_0_0 = _requestAIO_T_16; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_17 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_18 = {1'h0, _requestAIO_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_19 = _requestAIO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_20 = _requestAIO_T_19; // @[Parameters.scala:137:46]
wire _requestAIO_T_21 = _requestAIO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_22 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_23 = {1'h0, _requestAIO_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_24 = _requestAIO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_25 = _requestAIO_T_24; // @[Parameters.scala:137:46]
wire _requestAIO_T_26 = _requestAIO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_27 = _requestAIO_T_21 | _requestAIO_T_26; // @[Xbar.scala:291:92]
wire requestAIO_0_1 = _requestAIO_T_27; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_29 = {1'h0, _requestAIO_T_28}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_30 = _requestAIO_T_29 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_31 = _requestAIO_T_30; // @[Parameters.scala:137:46]
wire _requestAIO_T_32 = _requestAIO_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_33 = {in_1_a_bits_address[31:17], in_1_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_34 = {1'h0, _requestAIO_T_33}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_35 = _requestAIO_T_34 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_36 = _requestAIO_T_35; // @[Parameters.scala:137:46]
wire _requestAIO_T_37 = _requestAIO_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_38 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_39 = {1'h0, _requestAIO_T_38}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_40 = _requestAIO_T_39 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_41 = _requestAIO_T_40; // @[Parameters.scala:137:46]
wire _requestAIO_T_42 = _requestAIO_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_43 = _requestAIO_T_32 | _requestAIO_T_37; // @[Xbar.scala:291:92]
wire _requestAIO_T_44 = _requestAIO_T_43 | _requestAIO_T_42; // @[Xbar.scala:291:92]
wire requestAIO_1_0 = _requestAIO_T_44; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_2 = requestAIO_1_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_45 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_46 = {1'h0, _requestAIO_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_47 = _requestAIO_T_46 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_48 = _requestAIO_T_47; // @[Parameters.scala:137:46]
wire _requestAIO_T_49 = _requestAIO_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_50 = in_1_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_51 = {1'h0, _requestAIO_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_52 = _requestAIO_T_51 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_53 = _requestAIO_T_52; // @[Parameters.scala:137:46]
wire _requestAIO_T_54 = _requestAIO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_55 = _requestAIO_T_49 | _requestAIO_T_54; // @[Xbar.scala:291:92]
wire requestAIO_1_1 = _requestAIO_T_55; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_2 = requestAIO_1_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestCIO_T_11 = {1'h0, _requestCIO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestCIO_T_16 = {1'h0, _requestCIO_T_15}; // @[Parameters.scala:137:{31,41}]
wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[5]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _requestDOI_T_5 = out_0_d_bits_source[5:2]; // @[Xbar.scala:216:19]
wire _requestDOI_T_6 = _requestDOI_T_5 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_10 = out_1_d_bits_source[5]; // @[Xbar.scala:216:19]
wire _requestDOI_T_11 = ~_requestDOI_T_10; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_13 = _requestDOI_T_11; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_0 = _requestDOI_T_13; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T_2 = requestDOI_1_0; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _requestDOI_T_15 = out_1_d_bits_source[5:2]; // @[Xbar.scala:216:19]
wire _requestDOI_T_16 = _requestDOI_T_15 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_18 = _requestDOI_T_16; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_1 = _requestDOI_T_18; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T_2 = requestDOI_1_1; // @[Xbar.scala:355:54]
wire [2:0] requestEIO_uncommonBits_1 = _requestEIO_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF << in_1_c_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsCI_decode_T_4 = _beatsCI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsCI_decode_T_5 = ~_beatsCI_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] beatsCI_decode_1 = _beatsCI_decode_T_5[11:3]; // @[package.scala:243:46]
wire beatsCI_opdata_1 = in_1_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [8:0] beatsCI_1 = beatsCI_opdata_1 ? beatsCI_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73]
assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:355:40]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_3 = in_1_a_valid & _portsAOI_filtered_0_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_3 = in_1_a_valid & _portsAOI_filtered_1_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_1_valid = _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_1_a_ready_T = requestAIO_1_0 & portsAOI_filtered_1_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_1_a_ready_T_1 = requestAIO_1_1 & portsAOI_filtered_1_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_1_a_ready_T_2 = _portsAOI_in_1_a_ready_T | _portsAOI_in_1_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_1_a_ready_WIRE = _portsAOI_in_1_a_ready_T_2; // @[Mux.scala:30:73]
assign in_1_a_ready = _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_1 = portsBIO_filtered_1_1_ready; // @[Mux.scala:30:73]
assign in_1_b_valid = portsBIO_filtered_1_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_param = portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_address = portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:159:18, :352:24]
assign portsBIO_filtered_1_1_valid = _portsBIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_out_1_b_ready_T_2 = _portsBIO_out_1_b_ready_T_1; // @[Mux.scala:30:73]
assign _portsBIO_out_1_b_ready_WIRE = _portsBIO_out_1_b_ready_T_2; // @[Mux.scala:30:73]
assign out_1_b_ready = _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73]
wire _portsCOI_in_1_c_ready_T_1 = portsCOI_filtered_1_1_ready; // @[Mux.scala:30:73]
assign out_1_c_valid = portsCOI_filtered_1_1_valid; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_opcode = portsCOI_filtered_1_1_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_param = portsCOI_filtered_1_1_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_size = portsCOI_filtered_1_1_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_source = portsCOI_filtered_1_1_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_address = portsCOI_filtered_1_1_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_data = portsCOI_filtered_1_1_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_corrupt = portsCOI_filtered_1_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsCOI_filtered_1_0_valid = _portsCOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign portsCOI_filtered_1_1_valid = _portsCOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsCOI_in_1_c_ready_T_2 = _portsCOI_in_1_c_ready_T_1; // @[Mux.scala:30:73]
assign _portsCOI_in_1_c_ready_WIRE = _portsCOI_in_1_c_ready_T_2; // @[Mux.scala:30:73]
assign in_1_c_ready = _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_2; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_3; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_1_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24]
assign _portsDIO_filtered_0_valid_T_3 = out_1_d_valid & _portsDIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_3 = out_1_d_valid & _portsDIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_1_valid = _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_1_d_ready_T = requestDOI_1_0 & portsDIO_filtered_1_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_1 = requestDOI_1_1 & portsDIO_filtered_1_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_2 = _portsDIO_out_1_d_ready_T | _portsDIO_out_1_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_1_d_ready_WIRE = _portsDIO_out_1_d_ready_T_2; // @[Mux.scala:30:73]
assign out_1_d_ready = _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73]
assign out_1_e_valid = portsEOI_filtered_1_1_valid; // @[Xbar.scala:216:19, :352:24]
assign out_1_e_bits_sink = portsEOI_filtered_1_1_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_1_1_valid = _portsEOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0 = winner_0 ? beatsAI_0 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_1 = winner_1 ? beatsAI_1 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T = out_0_a_ready & out_0_a_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_0_ready_T = out_0_a_ready & allowed_0; // @[Xbar.scala:216:19]
assign portsAOI_filtered_0_ready = _filtered_0_ready_T; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_1 = out_0_a_ready & allowed_1; // @[Xbar.scala:216:19]
assign portsAOI_filtered_1_0_ready = _filtered_0_ready_T_1; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_1 = state_0 & portsAOI_filtered_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_2 = state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_3 = _out_0_a_valid_T_1 | _out_0_a_valid_T_2; // @[Mux.scala:30:73]
wire _out_0_a_valid_WIRE = _out_0_a_valid_T_3; // @[Mux.scala:30:73]
assign _out_0_a_valid_T_4 = idle ? _out_0_a_valid_T : _out_0_a_valid_WIRE; // @[Mux.scala:30:73]
assign out_0_a_valid = _out_0_a_valid_T_4; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73]
assign out_0_a_bits_opcode = _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73]
assign out_0_a_bits_param = _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73]
assign out_0_a_bits_size = _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
wire [5:0] _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73]
assign out_0_a_bits_source = _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73]
assign out_0_a_bits_address = _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73]
assign out_0_a_bits_mask = _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73]
assign out_0_a_bits_data = _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
wire _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73]
assign out_0_a_bits_corrupt = _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T = muxState_0 & portsAOI_filtered_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_1 = muxState_1 & portsAOI_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_2 = _out_0_a_bits_T | _out_0_a_bits_T_1; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_1 = _out_0_a_bits_T_2; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_corrupt = _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_3 = muxState_0 ? portsAOI_filtered_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_4 = muxState_1 ? portsAOI_filtered_1_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_5 = _out_0_a_bits_T_3 | _out_0_a_bits_T_4; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_2 = _out_0_a_bits_T_5; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_data = _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_6 = muxState_0 ? portsAOI_filtered_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_7 = muxState_1 ? portsAOI_filtered_1_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_8 = _out_0_a_bits_T_6 | _out_0_a_bits_T_7; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_3 = _out_0_a_bits_T_8; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_mask = _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_9 = muxState_0 ? portsAOI_filtered_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_10 = muxState_1 ? portsAOI_filtered_1_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_11 = _out_0_a_bits_T_9 | _out_0_a_bits_T_10; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_6 = _out_0_a_bits_T_11; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_address = _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73]
wire [5:0] _out_0_a_bits_T_12 = muxState_0 ? portsAOI_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _out_0_a_bits_T_13 = muxState_1 ? portsAOI_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _out_0_a_bits_T_14 = _out_0_a_bits_T_12 | _out_0_a_bits_T_13; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_7 = _out_0_a_bits_T_14; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_source = _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_15 = muxState_0 ? portsAOI_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_16 = muxState_1 ? portsAOI_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_17 = _out_0_a_bits_T_15 | _out_0_a_bits_T_16; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_8 = _out_0_a_bits_T_17; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_size = _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_18 = muxState_0 ? portsAOI_filtered_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_19 = muxState_1 ? portsAOI_filtered_1_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_20 = _out_0_a_bits_T_18 | _out_0_a_bits_T_19; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_9 = _out_0_a_bits_T_20; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_param = _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_21 = muxState_0 ? portsAOI_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_22 = muxState_1 ? portsAOI_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_23 = _out_0_a_bits_T_21 | _out_0_a_bits_T_22; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_10 = _out_0_a_bits_T_23; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_opcode = _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_1; // @[Arbiter.scala:60:30]
wire idle_1 = beatsLeft_1 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_1 = idle_1 & out_1_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T_10 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_1 = _readys_T_10; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_11 = readys_valid_1 == _readys_T_10; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_13 = ~_readys_T_12; // @[Arbiter.scala:22:12]
wire _readys_T_14 = ~_readys_T_11; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_1; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_2 = ~readys_mask_1; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_3 = readys_valid_1 & _readys_filter_T_2; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_1 = {_readys_filter_T_3, readys_valid_1}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_5 = readys_filter_1[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_6 = {readys_filter_1[3], readys_filter_1[2:0] | _readys_unready_T_5}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_7 = _readys_unready_T_6; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_8 = _readys_unready_T_7[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_9 = {readys_mask_1, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_1 = {1'h0, _readys_unready_T_8} | _readys_unready_T_9; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_3 = readys_unready_1[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_4 = readys_unready_1[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_5 = _readys_readys_T_3 & _readys_readys_T_4; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_1 = ~_readys_readys_T_5; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_17 = readys_readys_1; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_15 = |readys_valid_1; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_16 = latch_1 & _readys_T_15; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_5 = readys_readys_1 & readys_valid_1; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_6 = {_readys_mask_T_5, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_7 = _readys_mask_T_6[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_8 = _readys_mask_T_5 | _readys_mask_T_7; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_9 = _readys_mask_T_8; // @[package.scala:253:43, :254:17]
wire _readys_T_18 = _readys_T_17[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_0 = _readys_T_18; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_19 = _readys_T_17[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_1 = _readys_T_19; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_2 = readys_1_0 & portsAOI_filtered_1_valid; // @[Xbar.scala:352:24]
wire winner_1_0 = _winner_T_2; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_3 = readys_1_1 & portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire winner_1_1 = _winner_T_3; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_1 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_1 = winner_1_0 ? beatsAI_0 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_1_1 = winner_1_1 ? beatsAI_1 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_1 = maskedBeats_0_1 | maskedBeats_1_1; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_4 = out_1_a_ready & out_1_a_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {9'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_6 = _beatsLeft_T_5[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_1_0; // @[Arbiter.scala:88:26]
reg state_1_1; // @[Arbiter.scala:88:26]
wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_1_ready_T = out_1_a_ready & allowed_1_0; // @[Xbar.scala:216:19]
assign portsAOI_filtered_1_ready = _filtered_1_ready_T; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_1 = out_1_a_ready & allowed_1_1; // @[Xbar.scala:216:19]
assign portsAOI_filtered_1_1_ready = _filtered_1_ready_T_1; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_1 = state_1_0 & portsAOI_filtered_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_2 = state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_3 = _out_1_a_valid_T_1 | _out_1_a_valid_T_2; // @[Mux.scala:30:73]
wire _out_1_a_valid_WIRE = _out_1_a_valid_T_3; // @[Mux.scala:30:73]
assign _out_1_a_valid_T_4 = idle_1 ? _out_1_a_valid_T : _out_1_a_valid_WIRE; // @[Mux.scala:30:73]
assign out_1_a_valid = _out_1_a_valid_T_4; // @[Xbar.scala:216:19]
wire [2:0] _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73]
assign out_1_a_bits_opcode = _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73]
assign out_1_a_bits_param = _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73]
assign out_1_a_bits_size = _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73]
wire [5:0] _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73]
assign out_1_a_bits_source = _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73]
assign out_1_a_bits_address = _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73]
assign out_1_a_bits_mask = _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73]
assign out_1_a_bits_data = _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73]
wire _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73]
assign out_1_a_bits_corrupt = _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T = muxState_1_0 & portsAOI_filtered_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_1 = muxState_1_1 & portsAOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_2 = _out_1_a_bits_T | _out_1_a_bits_T_1; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_1 = _out_1_a_bits_T_2; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_corrupt = _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_3 = muxState_1_0 ? portsAOI_filtered_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_4 = muxState_1_1 ? portsAOI_filtered_1_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_5 = _out_1_a_bits_T_3 | _out_1_a_bits_T_4; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_2 = _out_1_a_bits_T_5; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_data = _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_6 = muxState_1_0 ? portsAOI_filtered_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_7 = muxState_1_1 ? portsAOI_filtered_1_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_8 = _out_1_a_bits_T_6 | _out_1_a_bits_T_7; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_3 = _out_1_a_bits_T_8; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_mask = _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_9 = muxState_1_0 ? portsAOI_filtered_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_10 = muxState_1_1 ? portsAOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_11 = _out_1_a_bits_T_9 | _out_1_a_bits_T_10; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_6 = _out_1_a_bits_T_11; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_address = _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73]
wire [5:0] _out_1_a_bits_T_12 = muxState_1_0 ? portsAOI_filtered_1_bits_source : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _out_1_a_bits_T_13 = muxState_1_1 ? portsAOI_filtered_1_1_bits_source : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _out_1_a_bits_T_14 = _out_1_a_bits_T_12 | _out_1_a_bits_T_13; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_7 = _out_1_a_bits_T_14; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_source = _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_15 = muxState_1_0 ? portsAOI_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_16 = muxState_1_1 ? portsAOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_17 = _out_1_a_bits_T_15 | _out_1_a_bits_T_16; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_8 = _out_1_a_bits_T_17; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_size = _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_18 = muxState_1_0 ? portsAOI_filtered_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_19 = muxState_1_1 ? portsAOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_20 = _out_1_a_bits_T_18 | _out_1_a_bits_T_19; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_9 = _out_1_a_bits_T_20; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_param = _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_21 = muxState_1_0 ? portsAOI_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_22 = muxState_1_1 ? portsAOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_23 = _out_1_a_bits_T_21 | _out_1_a_bits_T_22; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_10 = _out_1_a_bits_T_23; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_opcode = _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_2; // @[Arbiter.scala:60:30]
wire idle_2 = beatsLeft_2 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_2 = idle_2 & in_0_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_20 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_2 = _readys_T_20; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_21 = readys_valid_2 == _readys_T_20; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_23 = ~_readys_T_22; // @[Arbiter.scala:22:12]
wire _readys_T_24 = ~_readys_T_21; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_4 = ~readys_mask_2; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_5 = readys_valid_2 & _readys_filter_T_4; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_2 = {_readys_filter_T_5, readys_valid_2}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_10 = readys_filter_2[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_11 = {readys_filter_2[3], readys_filter_2[2:0] | _readys_unready_T_10}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_12 = _readys_unready_T_11; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_13 = _readys_unready_T_12[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_14 = {readys_mask_2, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_2 = {1'h0, _readys_unready_T_13} | _readys_unready_T_14; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_6 = readys_unready_2[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_7 = readys_unready_2[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_8 = _readys_readys_T_6 & _readys_readys_T_7; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_2 = ~_readys_readys_T_8; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_27 = readys_readys_2; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_25 = |readys_valid_2; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_26 = latch_2 & _readys_T_25; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_10 = readys_readys_2 & readys_valid_2; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_11 = {_readys_mask_T_10, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_12 = _readys_mask_T_11[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_13 = _readys_mask_T_10 | _readys_mask_T_12; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_14 = _readys_mask_T_13; // @[package.scala:253:43, :254:17]
wire _readys_T_28 = _readys_T_27[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2_0 = _readys_T_28; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_29 = _readys_T_27[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2_1 = _readys_T_29; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_4 = readys_2_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_2_0 = _winner_T_4; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_5 = readys_2_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_2_1 = _winner_T_5; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_2 = prefixOR_1_2 | winner_2_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_2 = winner_2_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_2 = winner_2_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_2 = {maskedBeats_0_2[8:3], maskedBeats_0_2[2:0] | maskedBeats_1_2}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_8 = in_0_d_ready & in_0_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {9'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_10 = _beatsLeft_T_9[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_2_0; // @[Arbiter.scala:88:26]
reg state_2_1; // @[Arbiter.scala:88:26]
wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_0_ready_T_2 = in_0_d_ready & allowed_2_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_0_ready = _filtered_0_ready_T_2; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_3 = in_0_d_ready & allowed_2_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_0_ready = _filtered_0_ready_T_3; // @[Xbar.scala:352:24]
wire _in_0_d_valid_T_1 = state_2_0 & portsDIO_filtered_0_valid; // @[Mux.scala:30:73]
wire _in_0_d_valid_T_2 = state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73]
wire _in_0_d_valid_T_3 = _in_0_d_valid_T_1 | _in_0_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_0_d_valid_WIRE = _in_0_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_0_d_valid_T_4 = idle_2 ? _in_0_d_valid_T : _in_0_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_0_d_valid = _in_0_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_0_d_bits_opcode = _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_0_d_bits_param = _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_0_d_bits_size = _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [5:0] _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_0_d_bits_source = _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_0_d_bits_sink = _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_0_d_bits_denied = _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_0_d_bits_data = _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_0_d_bits_corrupt = _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T = muxState_2_0 & portsDIO_filtered_0_bits_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_1 = muxState_2_1 & portsDIO_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_2 = _in_0_d_bits_T | _in_0_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_1 = _in_0_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_corrupt = _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_T_3 = muxState_2_0 ? portsDIO_filtered_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_T_4 = muxState_2_1 ? portsDIO_filtered_1_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_T_5 = _in_0_d_bits_T_3 | _in_0_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_2 = _in_0_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_data = _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_6 = muxState_2_0 & portsDIO_filtered_0_bits_denied; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_7 = muxState_2_1 & portsDIO_filtered_1_0_bits_denied; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_8 = _in_0_d_bits_T_6 | _in_0_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_5 = _in_0_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_denied = _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_9 = muxState_2_0 ? portsDIO_filtered_0_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_10 = muxState_2_1 ? portsDIO_filtered_1_0_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_11 = _in_0_d_bits_T_9 | _in_0_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_6 = _in_0_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_sink = _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [5:0] _in_0_d_bits_T_12 = muxState_2_0 ? portsDIO_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _in_0_d_bits_T_13 = muxState_2_1 ? portsDIO_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _in_0_d_bits_T_14 = _in_0_d_bits_T_12 | _in_0_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_7 = _in_0_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_source = _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_15 = muxState_2_0 ? portsDIO_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_16 = muxState_2_1 ? portsDIO_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_17 = _in_0_d_bits_T_15 | _in_0_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_8 = _in_0_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_size = _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_18 = muxState_2_0 ? portsDIO_filtered_0_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_19 = muxState_2_1 ? portsDIO_filtered_1_0_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_20 = _in_0_d_bits_T_18 | _in_0_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_9 = _in_0_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_param = _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_21 = muxState_2_0 ? portsDIO_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_22 = muxState_2_1 ? portsDIO_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_23 = _in_0_d_bits_T_21 | _in_0_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_10 = _in_0_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_opcode = _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_3; // @[Arbiter.scala:60:30]
wire idle_3 = beatsLeft_3 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_3 = idle_3 & in_1_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_30 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_3 = _readys_T_30; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_31 = readys_valid_3 == _readys_T_30; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_33 = ~_readys_T_32; // @[Arbiter.scala:22:12]
wire _readys_T_34 = ~_readys_T_31; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_6 = ~readys_mask_3; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_7 = readys_valid_3 & _readys_filter_T_6; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_3 = {_readys_filter_T_7, readys_valid_3}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_15 = readys_filter_3[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_16 = {readys_filter_3[3], readys_filter_3[2:0] | _readys_unready_T_15}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_17 = _readys_unready_T_16; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_18 = _readys_unready_T_17[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_19 = {readys_mask_3, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_3 = {1'h0, _readys_unready_T_18} | _readys_unready_T_19; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_9 = readys_unready_3[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_10 = readys_unready_3[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_11 = _readys_readys_T_9 & _readys_readys_T_10; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_3 = ~_readys_readys_T_11; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_37 = readys_readys_3; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_35 = |readys_valid_3; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_36 = latch_3 & _readys_T_35; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_15 = readys_readys_3 & readys_valid_3; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_16 = {_readys_mask_T_15, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_17 = _readys_mask_T_16[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_18 = _readys_mask_T_15 | _readys_mask_T_17; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_19 = _readys_mask_T_18; // @[package.scala:253:43, :254:17]
wire _readys_T_38 = _readys_T_37[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_3_0 = _readys_T_38; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_39 = _readys_T_37[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_3_1 = _readys_T_39; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_6 = readys_3_0 & portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
wire winner_3_0 = _winner_T_6; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_7 = readys_3_1 & portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire winner_3_1 = _winner_T_7; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_3 = prefixOR_1_3 | winner_3_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module PE_300 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_44
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_300( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_44 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_23 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_23
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_23
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h12))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_9 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_10 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_11 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_12 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_13 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_14 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_15 :
connect states[7].g, UInt<3>(0h2)
node _T_16 = and(io.router_req.ready, io.router_req.valid)
when _T_16 :
node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_29 = and(io.router_req.ready, io.router_req.valid)
when _T_29 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_31 = or(_T_30, vcalloc_vals[2])
node _T_32 = or(_T_31, vcalloc_vals[3])
node _T_33 = or(_T_32, vcalloc_vals[4])
node _T_34 = or(_T_33, vcalloc_vals[5])
node _T_35 = or(_T_34, vcalloc_vals[6])
node _T_36 = or(_T_35, vcalloc_vals[7])
when _T_36 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8]
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35
node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459)
node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460)
node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461)
node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462)
node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463)
node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464)
node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465)
wire _io_vcalloc_req_bits_WIRE_36 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472
connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477)
node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478)
node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479)
node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487
connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38
wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504)
node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517
connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519)
node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520)
node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521)
node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522)
node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523)
node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532
connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41
node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534)
node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535)
node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536)
node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537)
node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538)
node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539)
node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540)
wire _io_vcalloc_req_bits_WIRE_42 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547
connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553)
node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554)
node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555)
wire _io_vcalloc_req_bits_WIRE_43 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562
connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_44 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577
connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[5]
invalidate vcalloc_reqs[0].vc_sel.`1`[6]
invalidate vcalloc_reqs[0].vc_sel.`1`[7]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[3]
invalidate vcalloc_reqs[0].vc_sel.`2`[4]
invalidate vcalloc_reqs[0].vc_sel.`2`[5]
invalidate vcalloc_reqs[0].vc_sel.`2`[6]
invalidate vcalloc_reqs[0].vc_sel.`2`[7]
invalidate vcalloc_reqs[0].vc_sel.`3`[0]
invalidate vcalloc_reqs[0].vc_sel.`3`[1]
invalidate vcalloc_reqs[0].vc_sel.`3`[2]
invalidate vcalloc_reqs[0].vc_sel.`3`[3]
invalidate vcalloc_reqs[0].vc_sel.`3`[4]
invalidate vcalloc_reqs[0].vc_sel.`3`[5]
invalidate vcalloc_reqs[0].vc_sel.`3`[6]
invalidate vcalloc_reqs[0].vc_sel.`3`[7]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_37 = bits(vcalloc_sel, 1, 1)
node _T_38 = and(vcalloc_vals[1], _T_37)
node _T_39 = and(_T_38, io.vcalloc_req.ready)
when _T_39 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_40 = bits(vcalloc_sel, 2, 2)
node _T_41 = and(vcalloc_vals[2], _T_40)
node _T_42 = and(_T_41, io.vcalloc_req.ready)
when _T_42 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_43 = bits(vcalloc_sel, 3, 3)
node _T_44 = and(vcalloc_vals[3], _T_43)
node _T_45 = and(_T_44, io.vcalloc_req.ready)
when _T_45 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_46 = bits(vcalloc_sel, 4, 4)
node _T_47 = and(vcalloc_vals[4], _T_46)
node _T_48 = and(_T_47, io.vcalloc_req.ready)
when _T_48 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_49 = bits(vcalloc_sel, 5, 5)
node _T_50 = and(vcalloc_vals[5], _T_49)
node _T_51 = and(_T_50, io.vcalloc_req.ready)
when _T_51 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_52 = bits(vcalloc_sel, 6, 6)
node _T_53 = and(vcalloc_vals[6], _T_52)
node _T_54 = and(_T_53, io.vcalloc_req.ready)
when _T_54 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_55 = bits(vcalloc_sel, 7, 7)
node _T_56 = and(vcalloc_vals[7], _T_55)
node _T_57 = and(_T_56, io.vcalloc_req.ready)
when _T_57 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_58 :
node _T_59 = bits(vcalloc_sel, 0, 0)
when _T_59 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_60 = eq(states[0].g, UInt<3>(0h2))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_60, UInt<1>(0h1), "") : assert_3
node _T_64 = bits(vcalloc_sel, 1, 1)
when _T_64 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_65 = eq(states[1].g, UInt<3>(0h2))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_65, UInt<1>(0h1), "") : assert_4
node _T_69 = bits(vcalloc_sel, 2, 2)
when _T_69 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_70 = eq(states[2].g, UInt<3>(0h2))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_70, UInt<1>(0h1), "") : assert_5
node _T_74 = bits(vcalloc_sel, 3, 3)
when _T_74 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_75 = eq(states[3].g, UInt<3>(0h2))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_75, UInt<1>(0h1), "") : assert_6
node _T_79 = bits(vcalloc_sel, 4, 4)
when _T_79 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_80 = eq(states[4].g, UInt<3>(0h2))
node _T_81 = asUInt(reset)
node _T_82 = eq(_T_81, UInt<1>(0h0))
when _T_82 :
node _T_83 = eq(_T_80, UInt<1>(0h0))
when _T_83 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_80, UInt<1>(0h1), "") : assert_7
node _T_84 = bits(vcalloc_sel, 5, 5)
when _T_84 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_85 = eq(states[5].g, UInt<3>(0h2))
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_85, UInt<1>(0h1), "") : assert_8
node _T_89 = bits(vcalloc_sel, 6, 6)
when _T_89 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_90 = eq(states[6].g, UInt<3>(0h2))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = bits(vcalloc_sel, 7, 7)
when _T_94 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_95 = eq(states[7].g, UInt<3>(0h2))
node _T_96 = asUInt(reset)
node _T_97 = eq(_T_96, UInt<1>(0h0))
when _T_97 :
node _T_98 = eq(_T_95, UInt<1>(0h0))
when _T_98 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_95, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_77
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[7]
node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_hi_3 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4])
node credit_available_hi_hi_3 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail)
when _T_100 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_8 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_9 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_9 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_9 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11)
node credit_available_lo_lo_10 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_10 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_10 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_11 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0])
node credit_available_lo_hi_11 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4])
node credit_available_hi_hi_11 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail)
when _T_102 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_16 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_16 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_16 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_17 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_17 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_17 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21)
node credit_available_lo_lo_18 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_18 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_18 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_19 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0])
node credit_available_lo_hi_19 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4])
node credit_available_hi_hi_19 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6])
node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23)
node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22)
node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27)
node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29)
node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31)
node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail)
when _T_104 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_24 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_25 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31)
node credit_available_lo_lo_26 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32)
node credit_available_lo_lo_27 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0])
node credit_available_lo_hi_27 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4])
node credit_available_hi_hi_27 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33)
node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33)
node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35)
node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38)
node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38)
node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40)
node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39)
node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42)
node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail)
when _T_106 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_32 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_32 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_32 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40)
node credit_available_lo_lo_33 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_33 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_33 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41)
node credit_available_lo_lo_34 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_34 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_34 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42)
node credit_available_lo_lo_35 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0])
node credit_available_lo_hi_35 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4])
node credit_available_hi_hi_35 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6])
node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43)
node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44)
node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44)
node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45)
node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46)
node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48)
node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51)
node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49)
node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53)
node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail)
when _T_108 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_40 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_40 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_40 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50)
node credit_available_lo_lo_41 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_41 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_41 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51)
node credit_available_lo_lo_42 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_42 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_42 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52)
node credit_available_lo_lo_43 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0])
node credit_available_lo_hi_43 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2])
node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4])
node credit_available_hi_hi_43 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53)
node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55)
node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57)
node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54)
node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58)
node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60)
node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62)
node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59)
node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64)
node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail)
when _T_110 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_48 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_48 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48)
node credit_available_hi_lo_48 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_48 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48)
node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60)
node credit_available_lo_lo_49 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_49 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49)
node credit_available_hi_lo_49 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_49 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49)
node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61)
node credit_available_lo_lo_50 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_50 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50)
node credit_available_hi_lo_50 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_50 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50)
node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62)
node credit_available_lo_lo_51 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0])
node credit_available_lo_hi_51 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2])
node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51)
node credit_available_hi_lo_51 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4])
node credit_available_hi_hi_51 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6])
node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51)
node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63)
node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66)
node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64)
node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52)
node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52)
node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65)
node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53)
node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53)
node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66)
node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54)
node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54)
node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67)
node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55)
node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55)
node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68)
node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71)
node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73)
node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69)
node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75)
node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail)
when _T_112 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
wire _vc_sel_WIRE_27 : UInt<1>[8]
node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369)
node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370)
node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371)
node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372)
node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373)
node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_382
connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28
node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384)
node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385)
node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386)
node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387)
node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388)
node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389)
node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_397
connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29
node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401)
node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402)
node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403)
node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404)
node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_412
connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30
node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_427
connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430)
node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_442
connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32
node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444)
node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445)
node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446)
node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447)
node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448)
node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449)
node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450)
wire _vc_sel_WIRE_33 : UInt<1>
connect _vc_sel_WIRE_33, _vc_sel_T_457
connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33
node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459)
node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460)
node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461)
node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462)
node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463)
node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464)
node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465)
wire _vc_sel_WIRE_34 : UInt<1>
connect _vc_sel_WIRE_34, _vc_sel_T_472
connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34
node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477)
node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478)
node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479)
node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480)
wire _vc_sel_WIRE_35 : UInt<1>
connect _vc_sel_WIRE_35, _vc_sel_T_487
connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35
connect vc_sel.`3`, _vc_sel_WIRE_27
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6])
node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2])
node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3)
node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4])
node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6])
node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3)
node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34)
node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_38
node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_113 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`1`[3]
invalidate states[0].vc_sel.`1`[4]
invalidate states[0].vc_sel.`1`[5]
invalidate states[0].vc_sel.`1`[6]
invalidate states[0].vc_sel.`1`[7]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`2`[3]
invalidate states[0].vc_sel.`2`[4]
invalidate states[0].vc_sel.`2`[5]
invalidate states[0].vc_sel.`2`[6]
invalidate states[0].vc_sel.`2`[7]
invalidate states[0].vc_sel.`3`[0]
invalidate states[0].vc_sel.`3`[1]
invalidate states[0].vc_sel.`3`[2]
invalidate states[0].vc_sel.`3`[3]
invalidate states[0].vc_sel.`3`[4]
invalidate states[0].vc_sel.`3`[5]
invalidate states[0].vc_sel.`3`[6]
invalidate states[0].vc_sel.`3`[7]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[3], UInt<1>(0h0)
connect states[1].vc_sel.`1`[4], UInt<1>(0h0)
connect states[1].vc_sel.`1`[5], UInt<1>(0h0)
connect states[1].vc_sel.`1`[6], UInt<1>(0h0)
connect states[1].vc_sel.`1`[7], UInt<1>(0h0)
connect states[1].vc_sel.`2`[0], UInt<1>(0h0)
connect states[1].vc_sel.`2`[1], UInt<1>(0h0)
connect states[1].vc_sel.`2`[2], UInt<1>(0h0)
connect states[1].vc_sel.`2`[3], UInt<1>(0h0)
connect states[1].vc_sel.`2`[4], UInt<1>(0h0)
connect states[1].vc_sel.`2`[5], UInt<1>(0h0)
connect states[1].vc_sel.`2`[6], UInt<1>(0h0)
connect states[1].vc_sel.`2`[7], UInt<1>(0h0)
connect states[1].vc_sel.`3`[0], UInt<1>(0h0)
connect states[1].vc_sel.`3`[2], UInt<1>(0h0)
connect states[1].vc_sel.`3`[3], UInt<1>(0h0)
connect states[1].vc_sel.`3`[4], UInt<1>(0h0)
connect states[1].vc_sel.`3`[5], UInt<1>(0h0)
connect states[1].vc_sel.`3`[6], UInt<1>(0h0)
connect states[1].vc_sel.`3`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[2].vc_sel.`2`[1], UInt<1>(0h0)
connect states[2].vc_sel.`2`[2], UInt<1>(0h0)
connect states[2].vc_sel.`2`[3], UInt<1>(0h0)
connect states[2].vc_sel.`2`[4], UInt<1>(0h0)
connect states[2].vc_sel.`2`[5], UInt<1>(0h0)
connect states[2].vc_sel.`2`[6], UInt<1>(0h0)
connect states[2].vc_sel.`2`[7], UInt<1>(0h0)
connect states[2].vc_sel.`3`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`2`[0], UInt<1>(0h0)
connect states[3].vc_sel.`2`[1], UInt<1>(0h0)
connect states[3].vc_sel.`2`[2], UInt<1>(0h0)
connect states[3].vc_sel.`2`[3], UInt<1>(0h0)
connect states[3].vc_sel.`2`[4], UInt<1>(0h0)
connect states[3].vc_sel.`2`[5], UInt<1>(0h0)
connect states[3].vc_sel.`2`[6], UInt<1>(0h0)
connect states[3].vc_sel.`2`[7], UInt<1>(0h0)
connect states[3].vc_sel.`3`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`2`[0], UInt<1>(0h0)
connect states[4].vc_sel.`2`[1], UInt<1>(0h0)
connect states[4].vc_sel.`2`[2], UInt<1>(0h0)
connect states[4].vc_sel.`2`[3], UInt<1>(0h0)
connect states[4].vc_sel.`2`[4], UInt<1>(0h0)
connect states[4].vc_sel.`2`[5], UInt<1>(0h0)
connect states[4].vc_sel.`2`[6], UInt<1>(0h0)
connect states[4].vc_sel.`2`[7], UInt<1>(0h0)
connect states[4].vc_sel.`3`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`2`[0], UInt<1>(0h0)
connect states[5].vc_sel.`2`[1], UInt<1>(0h0)
connect states[5].vc_sel.`2`[2], UInt<1>(0h0)
connect states[5].vc_sel.`2`[3], UInt<1>(0h0)
connect states[5].vc_sel.`2`[4], UInt<1>(0h0)
connect states[5].vc_sel.`2`[5], UInt<1>(0h0)
connect states[5].vc_sel.`2`[6], UInt<1>(0h0)
connect states[5].vc_sel.`2`[7], UInt<1>(0h0)
connect states[5].vc_sel.`3`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`2`[0], UInt<1>(0h0)
connect states[6].vc_sel.`2`[1], UInt<1>(0h0)
connect states[6].vc_sel.`2`[2], UInt<1>(0h0)
connect states[6].vc_sel.`2`[3], UInt<1>(0h0)
connect states[6].vc_sel.`2`[4], UInt<1>(0h0)
connect states[6].vc_sel.`2`[5], UInt<1>(0h0)
connect states[6].vc_sel.`2`[6], UInt<1>(0h0)
connect states[6].vc_sel.`2`[7], UInt<1>(0h0)
connect states[6].vc_sel.`3`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`2`[0], UInt<1>(0h0)
connect states[7].vc_sel.`2`[1], UInt<1>(0h0)
connect states[7].vc_sel.`2`[2], UInt<1>(0h0)
connect states[7].vc_sel.`2`[3], UInt<1>(0h0)
connect states[7].vc_sel.`2`[4], UInt<1>(0h0)
connect states[7].vc_sel.`2`[5], UInt<1>(0h0)
connect states[7].vc_sel.`2`[6], UInt<1>(0h0)
connect states[7].vc_sel.`2`[7], UInt<1>(0h0)
connect states[7].vc_sel.`3`[0], UInt<1>(0h0)
node _T_114 = asUInt(reset)
when _T_114 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_23( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_34 = and(_T_32, _T_33)
node _T_35 = or(UInt<1>(0h0), _T_34)
node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_37 = cvt(_T_36)
node _T_38 = and(_T_37, asSInt(UInt<17>(0h100c0)))
node _T_39 = asSInt(_T_38)
node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0)))
node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_42 = cvt(_T_41)
node _T_43 = and(_T_42, asSInt(UInt<29>(0h100000c0)))
node _T_44 = asSInt(_T_43)
node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0)))
node _T_46 = or(_T_40, _T_45)
node _T_47 = and(_T_35, _T_46)
node _T_48 = or(UInt<1>(0h0), _T_47)
node _T_49 = and(_T_31, _T_48)
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_49, UInt<1>(0h1), "") : assert_2
node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_56 = and(_T_54, _T_55)
node _T_57 = or(UInt<1>(0h0), _T_56)
node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<17>(0h100c0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<29>(0h100000c0)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = or(_T_62, _T_67)
node _T_69 = and(_T_57, _T_68)
node _T_70 = or(UInt<1>(0h0), _T_69)
node _T_71 = and(_T_53, _T_70)
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(_T_71, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_71, UInt<1>(0h1), "") : assert_3
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_78, UInt<1>(0h1), "") : assert_5
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(is_aligned, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_85, UInt<1>(0h1), "") : assert_7
node _T_89 = not(io.in.a.bits.mask)
node _T_90 = eq(_T_89, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_90, UInt<1>(0h1), "") : assert_8
node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_98 :
node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_101 = and(_T_99, _T_100)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_102 = shr(io.in.a.bits.source, 4)
node _T_103 = eq(_T_102, UInt<1>(0h0))
node _T_104 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_105 = and(_T_103, _T_104)
node _T_106 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_107 = and(_T_105, _T_106)
node _T_108 = and(_T_101, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_112 = and(_T_110, _T_111)
node _T_113 = or(UInt<1>(0h0), _T_112)
node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<17>(0h100c0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_120 = cvt(_T_119)
node _T_121 = and(_T_120, asSInt(UInt<29>(0h100000c0)))
node _T_122 = asSInt(_T_121)
node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = or(_T_118, _T_123)
node _T_125 = and(_T_113, _T_124)
node _T_126 = or(UInt<1>(0h0), _T_125)
node _T_127 = and(_T_109, _T_126)
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(_T_127, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_127, UInt<1>(0h1), "") : assert_10
node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_134 = and(_T_132, _T_133)
node _T_135 = or(UInt<1>(0h0), _T_134)
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h100c0)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<29>(0h100000c0)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = or(_T_140, _T_145)
node _T_147 = and(_T_135, _T_146)
node _T_148 = or(UInt<1>(0h0), _T_147)
node _T_149 = and(_T_131, _T_148)
node _T_150 = asUInt(reset)
node _T_151 = eq(_T_150, UInt<1>(0h0))
when _T_151 :
node _T_152 = eq(_T_149, UInt<1>(0h0))
when _T_152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_149, UInt<1>(0h1), "") : assert_11
node _T_153 = asUInt(reset)
node _T_154 = eq(_T_153, UInt<1>(0h0))
when _T_154 :
node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_156, UInt<1>(0h1), "") : assert_13
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(is_aligned, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_163, UInt<1>(0h1), "") : assert_15
node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_168 = asUInt(reset)
node _T_169 = eq(_T_168, UInt<1>(0h0))
when _T_169 :
node _T_170 = eq(_T_167, UInt<1>(0h0))
when _T_170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_167, UInt<1>(0h1), "") : assert_16
node _T_171 = not(io.in.a.bits.mask)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_172, UInt<1>(0h1), "") : assert_17
node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_176, UInt<1>(0h1), "") : assert_18
node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_180 :
node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_183 = and(_T_181, _T_182)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_184 = shr(io.in.a.bits.source, 4)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_187 = and(_T_185, _T_186)
node _T_188 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_189 = and(_T_187, _T_188)
node _T_190 = and(_T_183, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_191, UInt<1>(0h1), "") : assert_19
node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_197 = and(_T_195, _T_196)
node _T_198 = or(UInt<1>(0h0), _T_197)
node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<17>(0h100c0)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<29>(0h100000c0)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_203, _T_208)
node _T_210 = and(_T_198, _T_209)
node _T_211 = or(UInt<1>(0h0), _T_210)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_211, UInt<1>(0h1), "") : assert_20
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(is_aligned, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_221, UInt<1>(0h1), "") : assert_23
node _T_225 = eq(io.in.a.bits.mask, mask)
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_225, UInt<1>(0h1), "") : assert_24
node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_229, UInt<1>(0h1), "") : assert_25
node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_233 :
node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_237 = shr(io.in.a.bits.source, 4)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_242 = and(_T_240, _T_241)
node _T_243 = and(_T_236, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_247 = and(_T_245, _T_246)
node _T_248 = or(UInt<1>(0h0), _T_247)
node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<17>(0h100c0)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<29>(0h100000c0)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = or(_T_253, _T_258)
node _T_260 = and(_T_248, _T_259)
node _T_261 = or(UInt<1>(0h0), _T_260)
node _T_262 = and(_T_244, _T_261)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_262, UInt<1>(0h1), "") : assert_26
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(is_aligned, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_272, UInt<1>(0h1), "") : assert_29
node _T_276 = eq(io.in.a.bits.mask, mask)
node _T_277 = asUInt(reset)
node _T_278 = eq(_T_277, UInt<1>(0h0))
when _T_278 :
node _T_279 = eq(_T_276, UInt<1>(0h0))
when _T_279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_276, UInt<1>(0h1), "") : assert_30
node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_280 :
node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_284 = shr(io.in.a.bits.source, 4)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_289 = and(_T_287, _T_288)
node _T_290 = and(_T_283, _T_289)
node _T_291 = or(UInt<1>(0h0), _T_290)
node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_294 = and(_T_292, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h100c0)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h100000c0)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = and(_T_291, _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_309, UInt<1>(0h1), "") : assert_31
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(is_aligned, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(_T_319, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_319, UInt<1>(0h1), "") : assert_34
node _T_323 = not(mask)
node _T_324 = and(io.in.a.bits.mask, _T_323)
node _T_325 = eq(_T_324, UInt<1>(0h0))
node _T_326 = asUInt(reset)
node _T_327 = eq(_T_326, UInt<1>(0h0))
when _T_327 :
node _T_328 = eq(_T_325, UInt<1>(0h0))
when _T_328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_325, UInt<1>(0h1), "") : assert_35
node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_329 :
node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_333 = shr(io.in.a.bits.source, 4)
node _T_334 = eq(_T_333, UInt<1>(0h0))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_338 = and(_T_336, _T_337)
node _T_339 = and(_T_332, _T_338)
node _T_340 = or(UInt<1>(0h0), _T_339)
node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<17>(0h100c0)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<29>(0h100000c0)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = or(_T_346, _T_351)
node _T_353 = and(_T_341, _T_352)
node _T_354 = or(UInt<1>(0h0), _T_353)
node _T_355 = and(_T_340, _T_354)
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_355, UInt<1>(0h1), "") : assert_36
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(is_aligned, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_365, UInt<1>(0h1), "") : assert_39
node _T_369 = eq(io.in.a.bits.mask, mask)
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_369, UInt<1>(0h1), "") : assert_40
node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_373 :
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_377 = shr(io.in.a.bits.source, 4)
node _T_378 = eq(_T_377, UInt<1>(0h0))
node _T_379 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_380 = and(_T_378, _T_379)
node _T_381 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_382 = and(_T_380, _T_381)
node _T_383 = and(_T_376, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_387 = cvt(_T_386)
node _T_388 = and(_T_387, asSInt(UInt<17>(0h100c0)))
node _T_389 = asSInt(_T_388)
node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0)))
node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_392 = cvt(_T_391)
node _T_393 = and(_T_392, asSInt(UInt<29>(0h100000c0)))
node _T_394 = asSInt(_T_393)
node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0)))
node _T_396 = or(_T_390, _T_395)
node _T_397 = and(_T_385, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = and(_T_384, _T_398)
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_399, UInt<1>(0h1), "") : assert_41
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(is_aligned, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_409, UInt<1>(0h1), "") : assert_44
node _T_413 = eq(io.in.a.bits.mask, mask)
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_413, UInt<1>(0h1), "") : assert_45
node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_417 :
node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_421 = shr(io.in.a.bits.source, 4)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_426 = and(_T_424, _T_425)
node _T_427 = and(_T_420, _T_426)
node _T_428 = or(UInt<1>(0h0), _T_427)
node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_431 = cvt(_T_430)
node _T_432 = and(_T_431, asSInt(UInt<17>(0h100c0)))
node _T_433 = asSInt(_T_432)
node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0)))
node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_436 = cvt(_T_435)
node _T_437 = and(_T_436, asSInt(UInt<29>(0h100000c0)))
node _T_438 = asSInt(_T_437)
node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0)))
node _T_440 = or(_T_434, _T_439)
node _T_441 = and(_T_429, _T_440)
node _T_442 = or(UInt<1>(0h0), _T_441)
node _T_443 = and(_T_428, _T_442)
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_443, UInt<1>(0h1), "") : assert_46
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(is_aligned, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_453, UInt<1>(0h1), "") : assert_49
node _T_457 = eq(io.in.a.bits.mask, mask)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_457, UInt<1>(0h1), "") : assert_50
node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_461, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_465, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_469 :
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_473, UInt<1>(0h1), "") : assert_54
node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_477, UInt<1>(0h1), "") : assert_55
node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_481, UInt<1>(0h1), "") : assert_56
node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_485, UInt<1>(0h1), "") : assert_57
node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_489 :
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(sink_ok, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_496, UInt<1>(0h1), "") : assert_60
node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_500, UInt<1>(0h1), "") : assert_61
node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_504, UInt<1>(0h1), "") : assert_62
node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_509 = asUInt(reset)
node _T_510 = eq(_T_509, UInt<1>(0h0))
when _T_510 :
node _T_511 = eq(_T_508, UInt<1>(0h0))
when _T_511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_508, UInt<1>(0h1), "") : assert_63
node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_513 = or(UInt<1>(0h1), _T_512)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_513, UInt<1>(0h1), "") : assert_64
node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_517 :
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(sink_ok, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_524, UInt<1>(0h1), "") : assert_67
node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_528, UInt<1>(0h1), "") : assert_68
node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_532, UInt<1>(0h1), "") : assert_69
node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_537 = or(_T_536, io.in.d.bits.corrupt)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_537, UInt<1>(0h1), "") : assert_70
node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_542 = or(UInt<1>(0h1), _T_541)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_542, UInt<1>(0h1), "") : assert_71
node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_546 :
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_550, UInt<1>(0h1), "") : assert_73
node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_554, UInt<1>(0h1), "") : assert_74
node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_559 = or(UInt<1>(0h1), _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_559, UInt<1>(0h1), "") : assert_75
node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_563 :
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_567, UInt<1>(0h1), "") : assert_77
node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_572 = or(_T_571, io.in.d.bits.corrupt)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_572, UInt<1>(0h1), "") : assert_78
node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_577 = or(UInt<1>(0h1), _T_576)
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_577, UInt<1>(0h1), "") : assert_79
node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_581 :
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_585, UInt<1>(0h1), "") : assert_81
node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_589, UInt<1>(0h1), "") : assert_82
node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_594 = or(UInt<1>(0h1), _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_594, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_598, UInt<1>(0h1), "") : assert_84
node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<4>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0)
node _T_602 = shr(io.in.b.bits.source, 4)
node _T_603 = eq(_T_602, UInt<1>(0h0))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_9, UInt<4>(0h9))
node _T_607 = and(_T_605, _T_606)
node _T_608 = eq(_T_607, UInt<1>(0h0))
node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<1>(0h0)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_608, _T_613)
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_614, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0)
node _legal_source_T = shr(io.in.b.bits.source, 4)
node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0))
node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2)
node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h9))
node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4)
wire _legal_source_WIRE : UInt<1>[1]
connect _legal_source_WIRE[0], _legal_source_T_5
node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source)
node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_618 :
node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_622 = and(_T_620, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h100c0)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<29>(0h100000c0)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = or(_T_628, _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = or(UInt<1>(0h0), _T_635)
node _T_637 = and(_T_619, _T_636)
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(_T_637, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_637, UInt<1>(0h1), "") : assert_86
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(address_ok, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(legal_source, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(is_aligned_1, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_650, UInt<1>(0h1), "") : assert_90
node _T_654 = eq(io.in.b.bits.mask, mask_1)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_654, UInt<1>(0h1), "") : assert_91
node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_659 = asUInt(reset)
node _T_660 = eq(_T_659, UInt<1>(0h0))
when _T_660 :
node _T_661 = eq(_T_658, UInt<1>(0h0))
when _T_661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_658, UInt<1>(0h1), "") : assert_92
node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_662 :
node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_665 = and(_T_663, _T_664)
node _T_666 = or(UInt<1>(0h0), _T_665)
node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_668 = cvt(_T_667)
node _T_669 = and(_T_668, asSInt(UInt<17>(0h100c0)))
node _T_670 = asSInt(_T_669)
node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0)))
node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_673 = cvt(_T_672)
node _T_674 = and(_T_673, asSInt(UInt<29>(0h100000c0)))
node _T_675 = asSInt(_T_674)
node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0)))
node _T_677 = or(_T_671, _T_676)
node _T_678 = and(_T_666, _T_677)
node _T_679 = or(UInt<1>(0h0), _T_678)
node _T_680 = and(UInt<1>(0h0), _T_679)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_680, UInt<1>(0h1), "") : assert_93
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(address_ok, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(legal_source, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(is_aligned_1, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_693, UInt<1>(0h1), "") : assert_97
node _T_697 = eq(io.in.b.bits.mask, mask_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_697, UInt<1>(0h1), "") : assert_98
node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_701, UInt<1>(0h1), "") : assert_99
node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_705 :
node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_708 = and(_T_706, _T_707)
node _T_709 = or(UInt<1>(0h0), _T_708)
node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<17>(0h100c0)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<29>(0h100000c0)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = or(_T_714, _T_719)
node _T_721 = and(_T_709, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = and(UInt<1>(0h0), _T_722)
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(_T_723, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_723, UInt<1>(0h1), "") : assert_100
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(address_ok, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(legal_source, UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned_1, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_736, UInt<1>(0h1), "") : assert_104
node _T_740 = eq(io.in.b.bits.mask, mask_1)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_740, UInt<1>(0h1), "") : assert_105
node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = or(UInt<1>(0h0), _T_747)
node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_750 = cvt(_T_749)
node _T_751 = and(_T_750, asSInt(UInt<17>(0h100c0)))
node _T_752 = asSInt(_T_751)
node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0)))
node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<29>(0h100000c0)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = or(_T_753, _T_758)
node _T_760 = and(_T_748, _T_759)
node _T_761 = or(UInt<1>(0h0), _T_760)
node _T_762 = and(UInt<1>(0h0), _T_761)
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_762, UInt<1>(0h1), "") : assert_106
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(address_ok, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(legal_source, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(is_aligned_1, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_775, UInt<1>(0h1), "") : assert_110
node _T_779 = not(mask_1)
node _T_780 = and(io.in.b.bits.mask, _T_779)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_781, UInt<1>(0h1), "") : assert_111
node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_785 :
node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<17>(0h100c0)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h100000c0)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_794, _T_799)
node _T_801 = and(_T_789, _T_800)
node _T_802 = or(UInt<1>(0h0), _T_801)
node _T_803 = and(UInt<1>(0h0), _T_802)
node _T_804 = asUInt(reset)
node _T_805 = eq(_T_804, UInt<1>(0h0))
when _T_805 :
node _T_806 = eq(_T_803, UInt<1>(0h0))
when _T_806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_803, UInt<1>(0h1), "") : assert_112
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(address_ok, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(legal_source, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(is_aligned_1, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(_T_816, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_816, UInt<1>(0h1), "") : assert_116
node _T_820 = eq(io.in.b.bits.mask, mask_1)
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_820, UInt<1>(0h1), "") : assert_117
node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_824 :
node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_827 = and(_T_825, _T_826)
node _T_828 = or(UInt<1>(0h0), _T_827)
node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<17>(0h100c0)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<29>(0h100000c0)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = or(_T_833, _T_838)
node _T_840 = and(_T_828, _T_839)
node _T_841 = or(UInt<1>(0h0), _T_840)
node _T_842 = and(UInt<1>(0h0), _T_841)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_842, UInt<1>(0h1), "") : assert_118
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(address_ok, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_849 = asUInt(reset)
node _T_850 = eq(_T_849, UInt<1>(0h0))
when _T_850 :
node _T_851 = eq(legal_source, UInt<1>(0h0))
when _T_851 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(is_aligned_1, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_855, UInt<1>(0h1), "") : assert_122
node _T_859 = eq(io.in.b.bits.mask, mask_1)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_859, UInt<1>(0h1), "") : assert_123
node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_863 :
node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_866 = and(_T_864, _T_865)
node _T_867 = or(UInt<1>(0h0), _T_866)
node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<17>(0h100c0)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<29>(0h100000c0)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = or(_T_872, _T_877)
node _T_879 = and(_T_867, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_879)
node _T_881 = and(UInt<1>(0h0), _T_880)
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_881, UInt<1>(0h1), "") : assert_124
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(address_ok, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(legal_source, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(is_aligned_1, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_894 = eq(io.in.b.bits.mask, mask_1)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_894, UInt<1>(0h1), "") : assert_128
node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_898, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_902, UInt<1>(0h1), "") : assert_130
node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0)
node _source_ok_T_12 = shr(io.in.c.bits.source, 4)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
wire _source_ok_WIRE_2 : UInt<1>[1]
connect _source_ok_WIRE_2[0], _source_ok_T_17
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_906 = shr(io.in.c.bits.source, 4)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_909 = and(_T_907, _T_908)
node _T_910 = leq(uncommonBits_10, UInt<4>(0h9))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(_T_911, UInt<1>(0h0))
node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_914 = cvt(_T_913)
node _T_915 = and(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = asSInt(_T_915)
node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0)))
node _T_918 = or(_T_912, _T_917)
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_918, UInt<1>(0h1), "") : assert_131
node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_922 :
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(address_ok_1, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133
node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_929, UInt<1>(0h1), "") : assert_134
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(is_aligned_2, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(_T_936, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_936, UInt<1>(0h1), "") : assert_136
node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_940, UInt<1>(0h1), "") : assert_137
node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_944 :
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(address_ok_1, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139
node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_951, UInt<1>(0h1), "") : assert_140
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(is_aligned_2, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_958, UInt<1>(0h1), "") : assert_142
node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_962 :
node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_965 = and(_T_963, _T_964)
node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_966 = shr(io.in.c.bits.source, 4)
node _T_967 = eq(_T_966, UInt<1>(0h0))
node _T_968 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_969 = and(_T_967, _T_968)
node _T_970 = leq(uncommonBits_11, UInt<4>(0h9))
node _T_971 = and(_T_969, _T_970)
node _T_972 = and(_T_965, _T_971)
node _T_973 = or(UInt<1>(0h0), _T_972)
node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_976 = and(_T_974, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_979 = cvt(_T_978)
node _T_980 = and(_T_979, asSInt(UInt<17>(0h100c0)))
node _T_981 = asSInt(_T_980)
node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0)))
node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_984 = cvt(_T_983)
node _T_985 = and(_T_984, asSInt(UInt<29>(0h100000c0)))
node _T_986 = asSInt(_T_985)
node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0)))
node _T_988 = or(_T_982, _T_987)
node _T_989 = and(_T_977, _T_988)
node _T_990 = or(UInt<1>(0h0), _T_989)
node _T_991 = and(_T_973, _T_990)
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_991, UInt<1>(0h1), "") : assert_143
node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_998 = and(_T_996, _T_997)
node _T_999 = or(UInt<1>(0h0), _T_998)
node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_1001 = cvt(_T_1000)
node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h100c0)))
node _T_1003 = asSInt(_T_1002)
node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0)))
node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_1006 = cvt(_T_1005)
node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h100000c0)))
node _T_1008 = asSInt(_T_1007)
node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0)))
node _T_1010 = or(_T_1004, _T_1009)
node _T_1011 = and(_T_999, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = and(_T_995, _T_1012)
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145
node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148
node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149
node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1035 :
node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1038 = and(_T_1036, _T_1037)
node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0)
node _T_1039 = shr(io.in.c.bits.source, 4)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = leq(uncommonBits_12, UInt<4>(0h9))
node _T_1044 = and(_T_1042, _T_1043)
node _T_1045 = and(_T_1038, _T_1044)
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = or(UInt<1>(0h0), _T_1049)
node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_1052 = cvt(_T_1051)
node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h100c0)))
node _T_1054 = asSInt(_T_1053)
node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0)))
node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_1057 = cvt(_T_1056)
node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h100000c0)))
node _T_1059 = asSInt(_T_1058)
node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0)))
node _T_1061 = or(_T_1055, _T_1060)
node _T_1062 = and(_T_1050, _T_1061)
node _T_1063 = or(UInt<1>(0h0), _T_1062)
node _T_1064 = and(_T_1046, _T_1063)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150
node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = or(UInt<1>(0h0), _T_1071)
node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_1074 = cvt(_T_1073)
node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h100c0)))
node _T_1076 = asSInt(_T_1075)
node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0)))
node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_1079 = cvt(_T_1078)
node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h100000c0)))
node _T_1081 = asSInt(_T_1080)
node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0)))
node _T_1083 = or(_T_1077, _T_1082)
node _T_1084 = and(_T_1072, _T_1083)
node _T_1085 = or(UInt<1>(0h0), _T_1084)
node _T_1086 = and(_T_1068, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152
node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155
node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(address_ok_1, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159
node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160
node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_1122 :
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(address_ok_1, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164
node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_1136 :
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(address_ok_1, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168
node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(sink_ok_1, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1157 = eq(a_first, UInt<1>(0h0))
node _T_1158 = and(io.in.a.valid, _T_1157)
when _T_1158 :
node _T_1159 = eq(io.in.a.bits.opcode, opcode)
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171
node _T_1163 = eq(io.in.a.bits.param, param)
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172
node _T_1167 = eq(io.in.a.bits.size, size)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173
node _T_1171 = eq(io.in.a.bits.source, source)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174
node _T_1175 = eq(io.in.a.bits.address, address)
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175
node _T_1179 = and(io.in.a.ready, io.in.a.valid)
node _T_1180 = and(_T_1179, a_first)
when _T_1180 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1181 = eq(d_first, UInt<1>(0h0))
node _T_1182 = and(io.in.d.valid, _T_1181)
when _T_1182 :
node _T_1183 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(_T_1183, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176
node _T_1187 = eq(io.in.d.bits.param, param_1)
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177
node _T_1191 = eq(io.in.d.bits.size, size_1)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178
node _T_1195 = eq(io.in.d.bits.source, source_1)
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179
node _T_1199 = eq(io.in.d.bits.sink, sink)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180
node _T_1203 = eq(io.in.d.bits.denied, denied)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181
node _T_1207 = and(io.in.d.ready, io.in.d.valid)
node _T_1208 = and(_T_1207, d_first)
when _T_1208 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_1209 = eq(b_first, UInt<1>(0h0))
node _T_1210 = and(io.in.b.valid, _T_1209)
when _T_1210 :
node _T_1211 = eq(io.in.b.bits.opcode, opcode_2)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182
node _T_1215 = eq(io.in.b.bits.param, param_2)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183
node _T_1219 = eq(io.in.b.bits.size, size_2)
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184
node _T_1223 = eq(io.in.b.bits.source, source_2)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185
node _T_1227 = eq(io.in.b.bits.address, address_1)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186
node _T_1231 = and(io.in.b.ready, io.in.b.valid)
node _T_1232 = and(_T_1231, b_first)
when _T_1232 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_1233 = eq(c_first, UInt<1>(0h0))
node _T_1234 = and(io.in.c.valid, _T_1233)
when _T_1234 :
node _T_1235 = eq(io.in.c.bits.opcode, opcode_3)
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187
node _T_1239 = eq(io.in.c.bits.param, param_3)
node _T_1240 = asUInt(reset)
node _T_1241 = eq(_T_1240, UInt<1>(0h0))
when _T_1241 :
node _T_1242 = eq(_T_1239, UInt<1>(0h0))
when _T_1242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188
node _T_1243 = eq(io.in.c.bits.size, size_3)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189
node _T_1247 = eq(io.in.c.bits.source, source_3)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190
node _T_1251 = eq(io.in.c.bits.address, address_2)
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191
node _T_1255 = and(io.in.c.ready, io.in.c.valid)
node _T_1256 = and(_T_1255, c_first)
when _T_1256 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1257 = and(io.in.a.valid, a_first_1)
node _T_1258 = and(_T_1257, UInt<1>(0h1))
when _T_1258 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1259 = and(io.in.a.ready, io.in.a.valid)
node _T_1260 = and(_T_1259, a_first_1)
node _T_1261 = and(_T_1260, UInt<1>(0h1))
when _T_1261 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1262 = dshr(inflight, io.in.a.bits.source)
node _T_1263 = bits(_T_1262, 0, 0)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1268 = and(io.in.d.valid, d_first_1)
node _T_1269 = and(_T_1268, UInt<1>(0h1))
node _T_1270 = eq(d_release_ack, UInt<1>(0h0))
node _T_1271 = and(_T_1269, _T_1270)
when _T_1271 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1272 = and(io.in.d.ready, io.in.d.valid)
node _T_1273 = and(_T_1272, d_first_1)
node _T_1274 = and(_T_1273, UInt<1>(0h1))
node _T_1275 = eq(d_release_ack, UInt<1>(0h0))
node _T_1276 = and(_T_1274, _T_1275)
when _T_1276 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1277 = and(io.in.d.valid, d_first_1)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = eq(d_release_ack, UInt<1>(0h0))
node _T_1280 = and(_T_1278, _T_1279)
when _T_1280 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1281 = dshr(inflight, io.in.d.bits.source)
node _T_1282 = bits(_T_1281, 0, 0)
node _T_1283 = or(_T_1282, same_cycle_resp)
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194
node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195
else :
node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1299 = or(_T_1297, _T_1298)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196
node _T_1303 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197
node _T_1307 = and(io.in.d.valid, d_first_1)
node _T_1308 = and(_T_1307, a_first_1)
node _T_1309 = and(_T_1308, io.in.a.valid)
node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = eq(d_release_ack, UInt<1>(0h0))
node _T_1313 = and(_T_1311, _T_1312)
when _T_1313 :
node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1315 = or(_T_1314, io.in.a.ready)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198
node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1320 = orr(a_set_wo_ready)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
node _T_1322 = or(_T_1319, _T_1321)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_152
node _T_1326 = orr(inflight)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1329 = or(_T_1327, _T_1328)
node _T_1330 = lt(watchdog, plusarg_reader.out)
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1335 = and(io.in.a.ready, io.in.a.valid)
node _T_1336 = and(io.in.d.ready, io.in.d.valid)
node _T_1337 = or(_T_1335, _T_1336)
when _T_1337 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_1338 = and(io.in.c.valid, c_first_1)
node _T_1339 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1340 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1341 = and(_T_1339, _T_1340)
node _T_1342 = and(_T_1338, _T_1341)
when _T_1342 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_1343 = and(io.in.c.ready, io.in.c.valid)
node _T_1344 = and(_T_1343, c_first_1)
node _T_1345 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1346 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1347 = and(_T_1345, _T_1346)
node _T_1348 = and(_T_1344, _T_1347)
when _T_1348 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_1349 = dshr(inflight_1, io.in.c.bits.source)
node _T_1350 = bits(_T_1349, 0, 0)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1355 = and(io.in.d.valid, d_first_2)
node _T_1356 = and(_T_1355, UInt<1>(0h1))
node _T_1357 = and(_T_1356, d_release_ack_1)
when _T_1357 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1358 = and(io.in.d.ready, io.in.d.valid)
node _T_1359 = and(_T_1358, d_first_2)
node _T_1360 = and(_T_1359, UInt<1>(0h1))
node _T_1361 = and(_T_1360, d_release_ack_1)
when _T_1361 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1362 = and(io.in.d.valid, d_first_2)
node _T_1363 = and(_T_1362, UInt<1>(0h1))
node _T_1364 = and(_T_1363, d_release_ack_1)
when _T_1364 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1365 = dshr(inflight_1, io.in.d.bits.source)
node _T_1366 = bits(_T_1365, 0, 0)
node _T_1367 = or(_T_1366, same_cycle_resp_1)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203
else :
node _T_1375 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204
node _T_1379 = and(io.in.d.valid, d_first_2)
node _T_1380 = and(_T_1379, c_first_1)
node _T_1381 = and(_T_1380, io.in.c.valid)
node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_1383 = and(_T_1381, _T_1382)
node _T_1384 = and(_T_1383, d_release_ack_1)
node _T_1385 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1386 = and(_T_1384, _T_1385)
when _T_1386 :
node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1388 = or(_T_1387, io.in.c.ready)
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205
node _T_1392 = orr(c_set_wo_ready)
when _T_1392 :
node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_153
node _T_1397 = orr(inflight_1)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1400 = or(_T_1398, _T_1399)
node _T_1401 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_1406 = and(io.in.c.ready, io.in.c.valid)
node _T_1407 = and(io.in.d.ready, io.in.d.valid)
node _T_1408 = or(_T_1406, _T_1407)
when _T_1408 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = and(_T_1409, d_first_3)
node _T_1411 = bits(io.in.d.bits.opcode, 2, 2)
node _T_1412 = bits(io.in.d.bits.opcode, 1, 1)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
node _T_1414 = and(_T_1411, _T_1413)
node _T_1415 = and(_T_1410, _T_1414)
when _T_1415 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_1416 = dshr(inflight_2, io.in.d.bits.sink)
node _T_1417 = bits(_T_1416, 0, 0)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_1422 = and(io.in.e.ready, io.in.e.valid)
node _T_1423 = and(_T_1422, UInt<1>(0h1))
node _T_1424 = and(_T_1423, UInt<1>(0h1))
when _T_1424 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_1425 = or(d_set, inflight_2)
node _T_1426 = dshr(_T_1425, io.in.e.bits.sink)
node _T_1427 = bits(_T_1426, 0, 0)
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_154 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_155 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_60( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [3:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_1 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_4 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [15:0] _GEN_6 = {12'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module BoomNonBlockingDCache :
input clock : Clock
input reset : Reset
output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
output io : { errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, flip lsu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1]}, s1_kill : UInt<1>[1], flip s1_nack_advisory : UInt<1>[1], flip resp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}[1], flip store_ack : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], flip nack : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], flip ll_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, exception : UInt<1>, rob_pnr_idx : UInt<6>, rob_head_idx : UInt<6>, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, force_order : UInt<1>, flip ordered : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>}}}
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
invalidate io.errors.bus.bits
invalidate io.errors.bus.valid
inst wb of BoomWritebackUnit
connect wb.clock, clock
connect wb.reset, reset
inst prober of BoomProbeUnit
connect prober.clock, clock
connect prober.reset, reset
inst mshrs of BoomMSHRFile
connect mshrs.clock, clock
connect mshrs.reset, reset
connect mshrs.io.clear_all, io.lsu.force_order
connect mshrs.io.brupdate.b2.target_offset, io.lsu.brupdate.b2.target_offset
connect mshrs.io.brupdate.b2.jalr_target, io.lsu.brupdate.b2.jalr_target
connect mshrs.io.brupdate.b2.pc_sel, io.lsu.brupdate.b2.pc_sel
connect mshrs.io.brupdate.b2.cfi_type, io.lsu.brupdate.b2.cfi_type
connect mshrs.io.brupdate.b2.taken, io.lsu.brupdate.b2.taken
connect mshrs.io.brupdate.b2.mispredict, io.lsu.brupdate.b2.mispredict
connect mshrs.io.brupdate.b2.uop.debug_tsrc, io.lsu.brupdate.b2.uop.debug_tsrc
connect mshrs.io.brupdate.b2.uop.debug_fsrc, io.lsu.brupdate.b2.uop.debug_fsrc
connect mshrs.io.brupdate.b2.uop.bp_xcpt_if, io.lsu.brupdate.b2.uop.bp_xcpt_if
connect mshrs.io.brupdate.b2.uop.bp_debug_if, io.lsu.brupdate.b2.uop.bp_debug_if
connect mshrs.io.brupdate.b2.uop.xcpt_ma_if, io.lsu.brupdate.b2.uop.xcpt_ma_if
connect mshrs.io.brupdate.b2.uop.xcpt_ae_if, io.lsu.brupdate.b2.uop.xcpt_ae_if
connect mshrs.io.brupdate.b2.uop.xcpt_pf_if, io.lsu.brupdate.b2.uop.xcpt_pf_if
connect mshrs.io.brupdate.b2.uop.fp_typ, io.lsu.brupdate.b2.uop.fp_typ
connect mshrs.io.brupdate.b2.uop.fp_rm, io.lsu.brupdate.b2.uop.fp_rm
connect mshrs.io.brupdate.b2.uop.fp_val, io.lsu.brupdate.b2.uop.fp_val
connect mshrs.io.brupdate.b2.uop.fcn_op, io.lsu.brupdate.b2.uop.fcn_op
connect mshrs.io.brupdate.b2.uop.fcn_dw, io.lsu.brupdate.b2.uop.fcn_dw
connect mshrs.io.brupdate.b2.uop.frs3_en, io.lsu.brupdate.b2.uop.frs3_en
connect mshrs.io.brupdate.b2.uop.lrs2_rtype, io.lsu.brupdate.b2.uop.lrs2_rtype
connect mshrs.io.brupdate.b2.uop.lrs1_rtype, io.lsu.brupdate.b2.uop.lrs1_rtype
connect mshrs.io.brupdate.b2.uop.dst_rtype, io.lsu.brupdate.b2.uop.dst_rtype
connect mshrs.io.brupdate.b2.uop.lrs3, io.lsu.brupdate.b2.uop.lrs3
connect mshrs.io.brupdate.b2.uop.lrs2, io.lsu.brupdate.b2.uop.lrs2
connect mshrs.io.brupdate.b2.uop.lrs1, io.lsu.brupdate.b2.uop.lrs1
connect mshrs.io.brupdate.b2.uop.ldst, io.lsu.brupdate.b2.uop.ldst
connect mshrs.io.brupdate.b2.uop.ldst_is_rs1, io.lsu.brupdate.b2.uop.ldst_is_rs1
connect mshrs.io.brupdate.b2.uop.csr_cmd, io.lsu.brupdate.b2.uop.csr_cmd
connect mshrs.io.brupdate.b2.uop.flush_on_commit, io.lsu.brupdate.b2.uop.flush_on_commit
connect mshrs.io.brupdate.b2.uop.is_unique, io.lsu.brupdate.b2.uop.is_unique
connect mshrs.io.brupdate.b2.uop.uses_stq, io.lsu.brupdate.b2.uop.uses_stq
connect mshrs.io.brupdate.b2.uop.uses_ldq, io.lsu.brupdate.b2.uop.uses_ldq
connect mshrs.io.brupdate.b2.uop.mem_signed, io.lsu.brupdate.b2.uop.mem_signed
connect mshrs.io.brupdate.b2.uop.mem_size, io.lsu.brupdate.b2.uop.mem_size
connect mshrs.io.brupdate.b2.uop.mem_cmd, io.lsu.brupdate.b2.uop.mem_cmd
connect mshrs.io.brupdate.b2.uop.exc_cause, io.lsu.brupdate.b2.uop.exc_cause
connect mshrs.io.brupdate.b2.uop.exception, io.lsu.brupdate.b2.uop.exception
connect mshrs.io.brupdate.b2.uop.stale_pdst, io.lsu.brupdate.b2.uop.stale_pdst
connect mshrs.io.brupdate.b2.uop.ppred_busy, io.lsu.brupdate.b2.uop.ppred_busy
connect mshrs.io.brupdate.b2.uop.prs3_busy, io.lsu.brupdate.b2.uop.prs3_busy
connect mshrs.io.brupdate.b2.uop.prs2_busy, io.lsu.brupdate.b2.uop.prs2_busy
connect mshrs.io.brupdate.b2.uop.prs1_busy, io.lsu.brupdate.b2.uop.prs1_busy
connect mshrs.io.brupdate.b2.uop.ppred, io.lsu.brupdate.b2.uop.ppred
connect mshrs.io.brupdate.b2.uop.prs3, io.lsu.brupdate.b2.uop.prs3
connect mshrs.io.brupdate.b2.uop.prs2, io.lsu.brupdate.b2.uop.prs2
connect mshrs.io.brupdate.b2.uop.prs1, io.lsu.brupdate.b2.uop.prs1
connect mshrs.io.brupdate.b2.uop.pdst, io.lsu.brupdate.b2.uop.pdst
connect mshrs.io.brupdate.b2.uop.rxq_idx, io.lsu.brupdate.b2.uop.rxq_idx
connect mshrs.io.brupdate.b2.uop.stq_idx, io.lsu.brupdate.b2.uop.stq_idx
connect mshrs.io.brupdate.b2.uop.ldq_idx, io.lsu.brupdate.b2.uop.ldq_idx
connect mshrs.io.brupdate.b2.uop.rob_idx, io.lsu.brupdate.b2.uop.rob_idx
connect mshrs.io.brupdate.b2.uop.fp_ctrl.vec, io.lsu.brupdate.b2.uop.fp_ctrl.vec
connect mshrs.io.brupdate.b2.uop.fp_ctrl.wflags, io.lsu.brupdate.b2.uop.fp_ctrl.wflags
connect mshrs.io.brupdate.b2.uop.fp_ctrl.sqrt, io.lsu.brupdate.b2.uop.fp_ctrl.sqrt
connect mshrs.io.brupdate.b2.uop.fp_ctrl.div, io.lsu.brupdate.b2.uop.fp_ctrl.div
connect mshrs.io.brupdate.b2.uop.fp_ctrl.fma, io.lsu.brupdate.b2.uop.fp_ctrl.fma
connect mshrs.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.lsu.brupdate.b2.uop.fp_ctrl.fastpipe
connect mshrs.io.brupdate.b2.uop.fp_ctrl.toint, io.lsu.brupdate.b2.uop.fp_ctrl.toint
connect mshrs.io.brupdate.b2.uop.fp_ctrl.fromint, io.lsu.brupdate.b2.uop.fp_ctrl.fromint
connect mshrs.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.lsu.brupdate.b2.uop.fp_ctrl.typeTagOut
connect mshrs.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.lsu.brupdate.b2.uop.fp_ctrl.typeTagIn
connect mshrs.io.brupdate.b2.uop.fp_ctrl.swap23, io.lsu.brupdate.b2.uop.fp_ctrl.swap23
connect mshrs.io.brupdate.b2.uop.fp_ctrl.swap12, io.lsu.brupdate.b2.uop.fp_ctrl.swap12
connect mshrs.io.brupdate.b2.uop.fp_ctrl.ren3, io.lsu.brupdate.b2.uop.fp_ctrl.ren3
connect mshrs.io.brupdate.b2.uop.fp_ctrl.ren2, io.lsu.brupdate.b2.uop.fp_ctrl.ren2
connect mshrs.io.brupdate.b2.uop.fp_ctrl.ren1, io.lsu.brupdate.b2.uop.fp_ctrl.ren1
connect mshrs.io.brupdate.b2.uop.fp_ctrl.wen, io.lsu.brupdate.b2.uop.fp_ctrl.wen
connect mshrs.io.brupdate.b2.uop.fp_ctrl.ldst, io.lsu.brupdate.b2.uop.fp_ctrl.ldst
connect mshrs.io.brupdate.b2.uop.op2_sel, io.lsu.brupdate.b2.uop.op2_sel
connect mshrs.io.brupdate.b2.uop.op1_sel, io.lsu.brupdate.b2.uop.op1_sel
connect mshrs.io.brupdate.b2.uop.imm_packed, io.lsu.brupdate.b2.uop.imm_packed
connect mshrs.io.brupdate.b2.uop.pimm, io.lsu.brupdate.b2.uop.pimm
connect mshrs.io.brupdate.b2.uop.imm_sel, io.lsu.brupdate.b2.uop.imm_sel
connect mshrs.io.brupdate.b2.uop.imm_rename, io.lsu.brupdate.b2.uop.imm_rename
connect mshrs.io.brupdate.b2.uop.taken, io.lsu.brupdate.b2.uop.taken
connect mshrs.io.brupdate.b2.uop.pc_lob, io.lsu.brupdate.b2.uop.pc_lob
connect mshrs.io.brupdate.b2.uop.edge_inst, io.lsu.brupdate.b2.uop.edge_inst
connect mshrs.io.brupdate.b2.uop.ftq_idx, io.lsu.brupdate.b2.uop.ftq_idx
connect mshrs.io.brupdate.b2.uop.is_mov, io.lsu.brupdate.b2.uop.is_mov
connect mshrs.io.brupdate.b2.uop.is_rocc, io.lsu.brupdate.b2.uop.is_rocc
connect mshrs.io.brupdate.b2.uop.is_sys_pc2epc, io.lsu.brupdate.b2.uop.is_sys_pc2epc
connect mshrs.io.brupdate.b2.uop.is_eret, io.lsu.brupdate.b2.uop.is_eret
connect mshrs.io.brupdate.b2.uop.is_amo, io.lsu.brupdate.b2.uop.is_amo
connect mshrs.io.brupdate.b2.uop.is_sfence, io.lsu.brupdate.b2.uop.is_sfence
connect mshrs.io.brupdate.b2.uop.is_fencei, io.lsu.brupdate.b2.uop.is_fencei
connect mshrs.io.brupdate.b2.uop.is_fence, io.lsu.brupdate.b2.uop.is_fence
connect mshrs.io.brupdate.b2.uop.is_sfb, io.lsu.brupdate.b2.uop.is_sfb
connect mshrs.io.brupdate.b2.uop.br_type, io.lsu.brupdate.b2.uop.br_type
connect mshrs.io.brupdate.b2.uop.br_tag, io.lsu.brupdate.b2.uop.br_tag
connect mshrs.io.brupdate.b2.uop.br_mask, io.lsu.brupdate.b2.uop.br_mask
connect mshrs.io.brupdate.b2.uop.dis_col_sel, io.lsu.brupdate.b2.uop.dis_col_sel
connect mshrs.io.brupdate.b2.uop.iw_p3_bypass_hint, io.lsu.brupdate.b2.uop.iw_p3_bypass_hint
connect mshrs.io.brupdate.b2.uop.iw_p2_bypass_hint, io.lsu.brupdate.b2.uop.iw_p2_bypass_hint
connect mshrs.io.brupdate.b2.uop.iw_p1_bypass_hint, io.lsu.brupdate.b2.uop.iw_p1_bypass_hint
connect mshrs.io.brupdate.b2.uop.iw_p2_speculative_child, io.lsu.brupdate.b2.uop.iw_p2_speculative_child
connect mshrs.io.brupdate.b2.uop.iw_p1_speculative_child, io.lsu.brupdate.b2.uop.iw_p1_speculative_child
connect mshrs.io.brupdate.b2.uop.iw_issued_partial_dgen, io.lsu.brupdate.b2.uop.iw_issued_partial_dgen
connect mshrs.io.brupdate.b2.uop.iw_issued_partial_agen, io.lsu.brupdate.b2.uop.iw_issued_partial_agen
connect mshrs.io.brupdate.b2.uop.iw_issued, io.lsu.brupdate.b2.uop.iw_issued
connect mshrs.io.brupdate.b2.uop.fu_code[0], io.lsu.brupdate.b2.uop.fu_code[0]
connect mshrs.io.brupdate.b2.uop.fu_code[1], io.lsu.brupdate.b2.uop.fu_code[1]
connect mshrs.io.brupdate.b2.uop.fu_code[2], io.lsu.brupdate.b2.uop.fu_code[2]
connect mshrs.io.brupdate.b2.uop.fu_code[3], io.lsu.brupdate.b2.uop.fu_code[3]
connect mshrs.io.brupdate.b2.uop.fu_code[4], io.lsu.brupdate.b2.uop.fu_code[4]
connect mshrs.io.brupdate.b2.uop.fu_code[5], io.lsu.brupdate.b2.uop.fu_code[5]
connect mshrs.io.brupdate.b2.uop.fu_code[6], io.lsu.brupdate.b2.uop.fu_code[6]
connect mshrs.io.brupdate.b2.uop.fu_code[7], io.lsu.brupdate.b2.uop.fu_code[7]
connect mshrs.io.brupdate.b2.uop.fu_code[8], io.lsu.brupdate.b2.uop.fu_code[8]
connect mshrs.io.brupdate.b2.uop.fu_code[9], io.lsu.brupdate.b2.uop.fu_code[9]
connect mshrs.io.brupdate.b2.uop.iq_type[0], io.lsu.brupdate.b2.uop.iq_type[0]
connect mshrs.io.brupdate.b2.uop.iq_type[1], io.lsu.brupdate.b2.uop.iq_type[1]
connect mshrs.io.brupdate.b2.uop.iq_type[2], io.lsu.brupdate.b2.uop.iq_type[2]
connect mshrs.io.brupdate.b2.uop.iq_type[3], io.lsu.brupdate.b2.uop.iq_type[3]
connect mshrs.io.brupdate.b2.uop.debug_pc, io.lsu.brupdate.b2.uop.debug_pc
connect mshrs.io.brupdate.b2.uop.is_rvc, io.lsu.brupdate.b2.uop.is_rvc
connect mshrs.io.brupdate.b2.uop.debug_inst, io.lsu.brupdate.b2.uop.debug_inst
connect mshrs.io.brupdate.b2.uop.inst, io.lsu.brupdate.b2.uop.inst
connect mshrs.io.brupdate.b1.mispredict_mask, io.lsu.brupdate.b1.mispredict_mask
connect mshrs.io.brupdate.b1.resolve_mask, io.lsu.brupdate.b1.resolve_mask
connect mshrs.io.exception, io.lsu.exception
connect mshrs.io.rob_pnr_idx, io.lsu.rob_pnr_idx
connect mshrs.io.rob_head_idx, io.lsu.rob_head_idx
inst meta_0 of L1MetadataArray
connect meta_0.clock, clock
connect meta_0.reset, reset
inst metaWriteArb of Arbiter2_L1MetaWriteReq_1
connect metaWriteArb.clock, clock
connect metaWriteArb.reset, reset
inst metaReadArb of Arbiter6_BoomL1MetaReadReq
connect metaReadArb.clock, clock
connect metaReadArb.reset, reset
invalidate metaReadArb.io.in[0].bits.req[0].tag
invalidate metaReadArb.io.in[0].bits.req[0].way_en
invalidate metaReadArb.io.in[0].bits.req[0].idx
invalidate metaReadArb.io.in[0].valid
invalidate metaReadArb.io.in[0].ready
invalidate metaReadArb.io.in[1].bits.req[0].tag
invalidate metaReadArb.io.in[1].bits.req[0].way_en
invalidate metaReadArb.io.in[1].bits.req[0].idx
invalidate metaReadArb.io.in[1].valid
invalidate metaReadArb.io.in[1].ready
invalidate metaReadArb.io.in[2].bits.req[0].tag
invalidate metaReadArb.io.in[2].bits.req[0].way_en
invalidate metaReadArb.io.in[2].bits.req[0].idx
invalidate metaReadArb.io.in[2].valid
invalidate metaReadArb.io.in[2].ready
invalidate metaReadArb.io.in[3].bits.req[0].tag
invalidate metaReadArb.io.in[3].bits.req[0].way_en
invalidate metaReadArb.io.in[3].bits.req[0].idx
invalidate metaReadArb.io.in[3].valid
invalidate metaReadArb.io.in[3].ready
invalidate metaReadArb.io.in[4].bits.req[0].tag
invalidate metaReadArb.io.in[4].bits.req[0].way_en
invalidate metaReadArb.io.in[4].bits.req[0].idx
invalidate metaReadArb.io.in[4].valid
invalidate metaReadArb.io.in[4].ready
invalidate metaReadArb.io.in[5].bits.req[0].tag
invalidate metaReadArb.io.in[5].bits.req[0].way_en
invalidate metaReadArb.io.in[5].bits.req[0].idx
invalidate metaReadArb.io.in[5].valid
invalidate metaReadArb.io.in[5].ready
node _meta_0_io_write_valid_T = and(metaWriteArb.io.out.ready, metaWriteArb.io.out.valid)
connect meta_0.io.write.valid, _meta_0_io_write_valid_T
connect meta_0.io.write.bits.data.tag, metaWriteArb.io.out.bits.data.tag
connect meta_0.io.write.bits.data.coh.state, metaWriteArb.io.out.bits.data.coh.state
connect meta_0.io.write.bits.tag, metaWriteArb.io.out.bits.tag
connect meta_0.io.write.bits.way_en, metaWriteArb.io.out.bits.way_en
connect meta_0.io.write.bits.idx, metaWriteArb.io.out.bits.idx
connect meta_0.io.read.valid, metaReadArb.io.out.valid
connect meta_0.io.read.bits.tag, metaReadArb.io.out.bits.req[0].tag
connect meta_0.io.read.bits.way_en, metaReadArb.io.out.bits.req[0].way_en
connect meta_0.io.read.bits.idx, metaReadArb.io.out.bits.req[0].idx
connect metaReadArb.io.out.ready, meta_0.io.read.ready
connect metaWriteArb.io.out.ready, meta_0.io.write.ready
inst data of BoomDuplicatedDataArray
connect data.clock, clock
connect data.reset, reset
inst dataWriteArb of Arbiter2_L1DataWriteReq_1
connect dataWriteArb.clock, clock
connect dataWriteArb.reset, reset
inst dataReadArb of Arbiter3_BoomL1DataReadReq
connect dataReadArb.clock, clock
connect dataReadArb.reset, reset
invalidate dataReadArb.io.in[0].bits.valid[0]
invalidate dataReadArb.io.in[0].bits.req[0].addr
invalidate dataReadArb.io.in[0].bits.req[0].way_en
invalidate dataReadArb.io.in[0].valid
invalidate dataReadArb.io.in[0].ready
invalidate dataReadArb.io.in[1].bits.valid[0]
invalidate dataReadArb.io.in[1].bits.req[0].addr
invalidate dataReadArb.io.in[1].bits.req[0].way_en
invalidate dataReadArb.io.in[1].valid
invalidate dataReadArb.io.in[1].ready
invalidate dataReadArb.io.in[2].bits.valid[0]
invalidate dataReadArb.io.in[2].bits.req[0].addr
invalidate dataReadArb.io.in[2].bits.req[0].way_en
invalidate dataReadArb.io.in[2].valid
invalidate dataReadArb.io.in[2].ready
node _data_io_read_0_valid_T = and(dataReadArb.io.out.bits.valid[0], dataReadArb.io.out.valid)
connect data.io.read[0].valid, _data_io_read_0_valid_T
connect data.io.read[0].bits.addr, dataReadArb.io.out.bits.req[0].addr
connect data.io.read[0].bits.way_en, dataReadArb.io.out.bits.req[0].way_en
connect dataReadArb.io.out.ready, UInt<1>(0h1)
node _data_io_write_valid_T = and(dataWriteArb.io.out.ready, dataWriteArb.io.out.valid)
connect data.io.write.valid, _data_io_write_valid_T
connect data.io.write.bits.data, dataWriteArb.io.out.bits.data
connect data.io.write.bits.wmask, dataWriteArb.io.out.bits.wmask
connect data.io.write.bits.addr, dataWriteArb.io.out.bits.addr
connect data.io.write.bits.way_en, dataWriteArb.io.out.bits.way_en
connect dataWriteArb.io.out.ready, UInt<1>(0h1)
node singlePortedDCacheWrite = and(data.io.write.valid, UInt<1>(0h0))
node block_incoming_reqs = and(UInt<1>(0h1), mshrs.io.resp.valid)
node _io_lsu_req_ready_T = and(metaReadArb.io.in[4].ready, dataReadArb.io.in[2].ready)
node _io_lsu_req_ready_T_1 = eq(block_incoming_reqs, UInt<1>(0h0))
node _io_lsu_req_ready_T_2 = and(_io_lsu_req_ready_T, _io_lsu_req_ready_T_1)
connect io.lsu.req.ready, _io_lsu_req_ready_T_2
node _metaReadArb_io_in_4_valid_T = eq(block_incoming_reqs, UInt<1>(0h0))
node _metaReadArb_io_in_4_valid_T_1 = and(io.lsu.req.valid, _metaReadArb_io_in_4_valid_T)
connect metaReadArb.io.in[4].valid, _metaReadArb_io_in_4_valid_T_1
node _dataReadArb_io_in_2_valid_T = eq(block_incoming_reqs, UInt<1>(0h0))
node _dataReadArb_io_in_2_valid_T_1 = and(io.lsu.req.valid, _dataReadArb_io_in_2_valid_T)
connect dataReadArb.io.in[2].valid, _dataReadArb_io_in_2_valid_T_1
node _metaReadArb_io_in_4_bits_req_0_idx_T = shr(io.lsu.req.bits[0].bits.addr, 6)
connect metaReadArb.io.in[4].bits.req[0].idx, _metaReadArb_io_in_4_bits_req_0_idx_T
invalidate metaReadArb.io.in[4].bits.req[0].way_en
invalidate metaReadArb.io.in[4].bits.req[0].tag
connect dataReadArb.io.in[2].bits.valid[0], io.lsu.req.bits[0].valid
connect dataReadArb.io.in[2].bits.req[0].addr, io.lsu.req.bits[0].bits.addr
node _dataReadArb_io_in_2_bits_req_0_way_en_T = not(UInt<4>(0h0))
connect dataReadArb.io.in[2].bits.req[0].way_en, _dataReadArb_io_in_2_bits_req_0_way_en_T
wire replay_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate replay_req[0].is_hella
invalidate replay_req[0].data
invalidate replay_req[0].addr
invalidate replay_req[0].uop.debug_tsrc
invalidate replay_req[0].uop.debug_fsrc
invalidate replay_req[0].uop.bp_xcpt_if
invalidate replay_req[0].uop.bp_debug_if
invalidate replay_req[0].uop.xcpt_ma_if
invalidate replay_req[0].uop.xcpt_ae_if
invalidate replay_req[0].uop.xcpt_pf_if
invalidate replay_req[0].uop.fp_typ
invalidate replay_req[0].uop.fp_rm
invalidate replay_req[0].uop.fp_val
invalidate replay_req[0].uop.fcn_op
invalidate replay_req[0].uop.fcn_dw
invalidate replay_req[0].uop.frs3_en
invalidate replay_req[0].uop.lrs2_rtype
invalidate replay_req[0].uop.lrs1_rtype
invalidate replay_req[0].uop.dst_rtype
invalidate replay_req[0].uop.lrs3
invalidate replay_req[0].uop.lrs2
invalidate replay_req[0].uop.lrs1
invalidate replay_req[0].uop.ldst
invalidate replay_req[0].uop.ldst_is_rs1
invalidate replay_req[0].uop.csr_cmd
invalidate replay_req[0].uop.flush_on_commit
invalidate replay_req[0].uop.is_unique
invalidate replay_req[0].uop.uses_stq
invalidate replay_req[0].uop.uses_ldq
invalidate replay_req[0].uop.mem_signed
invalidate replay_req[0].uop.mem_size
invalidate replay_req[0].uop.mem_cmd
invalidate replay_req[0].uop.exc_cause
invalidate replay_req[0].uop.exception
invalidate replay_req[0].uop.stale_pdst
invalidate replay_req[0].uop.ppred_busy
invalidate replay_req[0].uop.prs3_busy
invalidate replay_req[0].uop.prs2_busy
invalidate replay_req[0].uop.prs1_busy
invalidate replay_req[0].uop.ppred
invalidate replay_req[0].uop.prs3
invalidate replay_req[0].uop.prs2
invalidate replay_req[0].uop.prs1
invalidate replay_req[0].uop.pdst
invalidate replay_req[0].uop.rxq_idx
invalidate replay_req[0].uop.stq_idx
invalidate replay_req[0].uop.ldq_idx
invalidate replay_req[0].uop.rob_idx
invalidate replay_req[0].uop.fp_ctrl.vec
invalidate replay_req[0].uop.fp_ctrl.wflags
invalidate replay_req[0].uop.fp_ctrl.sqrt
invalidate replay_req[0].uop.fp_ctrl.div
invalidate replay_req[0].uop.fp_ctrl.fma
invalidate replay_req[0].uop.fp_ctrl.fastpipe
invalidate replay_req[0].uop.fp_ctrl.toint
invalidate replay_req[0].uop.fp_ctrl.fromint
invalidate replay_req[0].uop.fp_ctrl.typeTagOut
invalidate replay_req[0].uop.fp_ctrl.typeTagIn
invalidate replay_req[0].uop.fp_ctrl.swap23
invalidate replay_req[0].uop.fp_ctrl.swap12
invalidate replay_req[0].uop.fp_ctrl.ren3
invalidate replay_req[0].uop.fp_ctrl.ren2
invalidate replay_req[0].uop.fp_ctrl.ren1
invalidate replay_req[0].uop.fp_ctrl.wen
invalidate replay_req[0].uop.fp_ctrl.ldst
invalidate replay_req[0].uop.op2_sel
invalidate replay_req[0].uop.op1_sel
invalidate replay_req[0].uop.imm_packed
invalidate replay_req[0].uop.pimm
invalidate replay_req[0].uop.imm_sel
invalidate replay_req[0].uop.imm_rename
invalidate replay_req[0].uop.taken
invalidate replay_req[0].uop.pc_lob
invalidate replay_req[0].uop.edge_inst
invalidate replay_req[0].uop.ftq_idx
invalidate replay_req[0].uop.is_mov
invalidate replay_req[0].uop.is_rocc
invalidate replay_req[0].uop.is_sys_pc2epc
invalidate replay_req[0].uop.is_eret
invalidate replay_req[0].uop.is_amo
invalidate replay_req[0].uop.is_sfence
invalidate replay_req[0].uop.is_fencei
invalidate replay_req[0].uop.is_fence
invalidate replay_req[0].uop.is_sfb
invalidate replay_req[0].uop.br_type
invalidate replay_req[0].uop.br_tag
invalidate replay_req[0].uop.br_mask
invalidate replay_req[0].uop.dis_col_sel
invalidate replay_req[0].uop.iw_p3_bypass_hint
invalidate replay_req[0].uop.iw_p2_bypass_hint
invalidate replay_req[0].uop.iw_p1_bypass_hint
invalidate replay_req[0].uop.iw_p2_speculative_child
invalidate replay_req[0].uop.iw_p1_speculative_child
invalidate replay_req[0].uop.iw_issued_partial_dgen
invalidate replay_req[0].uop.iw_issued_partial_agen
invalidate replay_req[0].uop.iw_issued
invalidate replay_req[0].uop.fu_code[0]
invalidate replay_req[0].uop.fu_code[1]
invalidate replay_req[0].uop.fu_code[2]
invalidate replay_req[0].uop.fu_code[3]
invalidate replay_req[0].uop.fu_code[4]
invalidate replay_req[0].uop.fu_code[5]
invalidate replay_req[0].uop.fu_code[6]
invalidate replay_req[0].uop.fu_code[7]
invalidate replay_req[0].uop.fu_code[8]
invalidate replay_req[0].uop.fu_code[9]
invalidate replay_req[0].uop.iq_type[0]
invalidate replay_req[0].uop.iq_type[1]
invalidate replay_req[0].uop.iq_type[2]
invalidate replay_req[0].uop.iq_type[3]
invalidate replay_req[0].uop.debug_pc
invalidate replay_req[0].uop.is_rvc
invalidate replay_req[0].uop.debug_inst
invalidate replay_req[0].uop.inst
connect replay_req[0].uop, mshrs.io.replay.bits.uop
connect replay_req[0].addr, mshrs.io.replay.bits.addr
connect replay_req[0].data, mshrs.io.replay.bits.data
connect replay_req[0].is_hella, mshrs.io.replay.bits.is_hella
node _mshrs_io_replay_ready_T = and(metaReadArb.io.in[0].ready, dataReadArb.io.in[0].ready)
node _mshrs_io_replay_ready_T_1 = eq(singlePortedDCacheWrite, UInt<1>(0h0))
node _mshrs_io_replay_ready_T_2 = and(_mshrs_io_replay_ready_T, _mshrs_io_replay_ready_T_1)
connect mshrs.io.replay.ready, _mshrs_io_replay_ready_T_2
node _metaReadArb_io_in_0_valid_T = eq(singlePortedDCacheWrite, UInt<1>(0h0))
node _metaReadArb_io_in_0_valid_T_1 = and(mshrs.io.replay.valid, _metaReadArb_io_in_0_valid_T)
connect metaReadArb.io.in[0].valid, _metaReadArb_io_in_0_valid_T_1
node _metaReadArb_io_in_0_bits_req_0_idx_T = shr(mshrs.io.replay.bits.addr, 6)
connect metaReadArb.io.in[0].bits.req[0].idx, _metaReadArb_io_in_0_bits_req_0_idx_T
invalidate metaReadArb.io.in[0].bits.req[0].way_en
invalidate metaReadArb.io.in[0].bits.req[0].tag
node _dataReadArb_io_in_0_valid_T = eq(singlePortedDCacheWrite, UInt<1>(0h0))
node _dataReadArb_io_in_0_valid_T_1 = and(mshrs.io.replay.valid, _dataReadArb_io_in_0_valid_T)
connect dataReadArb.io.in[0].valid, _dataReadArb_io_in_0_valid_T_1
connect dataReadArb.io.in[0].bits.req[0].addr, mshrs.io.replay.bits.addr
connect dataReadArb.io.in[0].bits.req[0].way_en, mshrs.io.replay.bits.way_en
wire _WIRE : UInt<1>[1]
connect _WIRE[0], UInt<1>(0h1)
connect dataReadArb.io.in[0].bits.valid[0], _WIRE[0]
wire mshr_read_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate mshr_read_req[0].is_hella
invalidate mshr_read_req[0].data
invalidate mshr_read_req[0].addr
invalidate mshr_read_req[0].uop.debug_tsrc
invalidate mshr_read_req[0].uop.debug_fsrc
invalidate mshr_read_req[0].uop.bp_xcpt_if
invalidate mshr_read_req[0].uop.bp_debug_if
invalidate mshr_read_req[0].uop.xcpt_ma_if
invalidate mshr_read_req[0].uop.xcpt_ae_if
invalidate mshr_read_req[0].uop.xcpt_pf_if
invalidate mshr_read_req[0].uop.fp_typ
invalidate mshr_read_req[0].uop.fp_rm
invalidate mshr_read_req[0].uop.fp_val
invalidate mshr_read_req[0].uop.fcn_op
invalidate mshr_read_req[0].uop.fcn_dw
invalidate mshr_read_req[0].uop.frs3_en
invalidate mshr_read_req[0].uop.lrs2_rtype
invalidate mshr_read_req[0].uop.lrs1_rtype
invalidate mshr_read_req[0].uop.dst_rtype
invalidate mshr_read_req[0].uop.lrs3
invalidate mshr_read_req[0].uop.lrs2
invalidate mshr_read_req[0].uop.lrs1
invalidate mshr_read_req[0].uop.ldst
invalidate mshr_read_req[0].uop.ldst_is_rs1
invalidate mshr_read_req[0].uop.csr_cmd
invalidate mshr_read_req[0].uop.flush_on_commit
invalidate mshr_read_req[0].uop.is_unique
invalidate mshr_read_req[0].uop.uses_stq
invalidate mshr_read_req[0].uop.uses_ldq
invalidate mshr_read_req[0].uop.mem_signed
invalidate mshr_read_req[0].uop.mem_size
invalidate mshr_read_req[0].uop.mem_cmd
invalidate mshr_read_req[0].uop.exc_cause
invalidate mshr_read_req[0].uop.exception
invalidate mshr_read_req[0].uop.stale_pdst
invalidate mshr_read_req[0].uop.ppred_busy
invalidate mshr_read_req[0].uop.prs3_busy
invalidate mshr_read_req[0].uop.prs2_busy
invalidate mshr_read_req[0].uop.prs1_busy
invalidate mshr_read_req[0].uop.ppred
invalidate mshr_read_req[0].uop.prs3
invalidate mshr_read_req[0].uop.prs2
invalidate mshr_read_req[0].uop.prs1
invalidate mshr_read_req[0].uop.pdst
invalidate mshr_read_req[0].uop.rxq_idx
invalidate mshr_read_req[0].uop.stq_idx
invalidate mshr_read_req[0].uop.ldq_idx
invalidate mshr_read_req[0].uop.rob_idx
invalidate mshr_read_req[0].uop.fp_ctrl.vec
invalidate mshr_read_req[0].uop.fp_ctrl.wflags
invalidate mshr_read_req[0].uop.fp_ctrl.sqrt
invalidate mshr_read_req[0].uop.fp_ctrl.div
invalidate mshr_read_req[0].uop.fp_ctrl.fma
invalidate mshr_read_req[0].uop.fp_ctrl.fastpipe
invalidate mshr_read_req[0].uop.fp_ctrl.toint
invalidate mshr_read_req[0].uop.fp_ctrl.fromint
invalidate mshr_read_req[0].uop.fp_ctrl.typeTagOut
invalidate mshr_read_req[0].uop.fp_ctrl.typeTagIn
invalidate mshr_read_req[0].uop.fp_ctrl.swap23
invalidate mshr_read_req[0].uop.fp_ctrl.swap12
invalidate mshr_read_req[0].uop.fp_ctrl.ren3
invalidate mshr_read_req[0].uop.fp_ctrl.ren2
invalidate mshr_read_req[0].uop.fp_ctrl.ren1
invalidate mshr_read_req[0].uop.fp_ctrl.wen
invalidate mshr_read_req[0].uop.fp_ctrl.ldst
invalidate mshr_read_req[0].uop.op2_sel
invalidate mshr_read_req[0].uop.op1_sel
invalidate mshr_read_req[0].uop.imm_packed
invalidate mshr_read_req[0].uop.pimm
invalidate mshr_read_req[0].uop.imm_sel
invalidate mshr_read_req[0].uop.imm_rename
invalidate mshr_read_req[0].uop.taken
invalidate mshr_read_req[0].uop.pc_lob
invalidate mshr_read_req[0].uop.edge_inst
invalidate mshr_read_req[0].uop.ftq_idx
invalidate mshr_read_req[0].uop.is_mov
invalidate mshr_read_req[0].uop.is_rocc
invalidate mshr_read_req[0].uop.is_sys_pc2epc
invalidate mshr_read_req[0].uop.is_eret
invalidate mshr_read_req[0].uop.is_amo
invalidate mshr_read_req[0].uop.is_sfence
invalidate mshr_read_req[0].uop.is_fencei
invalidate mshr_read_req[0].uop.is_fence
invalidate mshr_read_req[0].uop.is_sfb
invalidate mshr_read_req[0].uop.br_type
invalidate mshr_read_req[0].uop.br_tag
invalidate mshr_read_req[0].uop.br_mask
invalidate mshr_read_req[0].uop.dis_col_sel
invalidate mshr_read_req[0].uop.iw_p3_bypass_hint
invalidate mshr_read_req[0].uop.iw_p2_bypass_hint
invalidate mshr_read_req[0].uop.iw_p1_bypass_hint
invalidate mshr_read_req[0].uop.iw_p2_speculative_child
invalidate mshr_read_req[0].uop.iw_p1_speculative_child
invalidate mshr_read_req[0].uop.iw_issued_partial_dgen
invalidate mshr_read_req[0].uop.iw_issued_partial_agen
invalidate mshr_read_req[0].uop.iw_issued
invalidate mshr_read_req[0].uop.fu_code[0]
invalidate mshr_read_req[0].uop.fu_code[1]
invalidate mshr_read_req[0].uop.fu_code[2]
invalidate mshr_read_req[0].uop.fu_code[3]
invalidate mshr_read_req[0].uop.fu_code[4]
invalidate mshr_read_req[0].uop.fu_code[5]
invalidate mshr_read_req[0].uop.fu_code[6]
invalidate mshr_read_req[0].uop.fu_code[7]
invalidate mshr_read_req[0].uop.fu_code[8]
invalidate mshr_read_req[0].uop.fu_code[9]
invalidate mshr_read_req[0].uop.iq_type[0]
invalidate mshr_read_req[0].uop.iq_type[1]
invalidate mshr_read_req[0].uop.iq_type[2]
invalidate mshr_read_req[0].uop.iq_type[3]
invalidate mshr_read_req[0].uop.debug_pc
invalidate mshr_read_req[0].uop.is_rvc
invalidate mshr_read_req[0].uop.debug_inst
invalidate mshr_read_req[0].uop.inst
wire _mshr_read_req_0_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect _mshr_read_req_0_uop_WIRE.debug_tsrc, UInt<3>(0h0)
connect _mshr_read_req_0_uop_WIRE.debug_fsrc, UInt<3>(0h0)
connect _mshr_read_req_0_uop_WIRE.bp_xcpt_if, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.bp_debug_if, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.xcpt_ma_if, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.xcpt_ae_if, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.xcpt_pf_if, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_typ, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_rm, UInt<3>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_val, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fcn_op, UInt<5>(0h0)
connect _mshr_read_req_0_uop_WIRE.fcn_dw, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.frs3_en, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.lrs2_rtype, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.lrs1_rtype, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.dst_rtype, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.lrs3, UInt<6>(0h0)
connect _mshr_read_req_0_uop_WIRE.lrs2, UInt<6>(0h0)
connect _mshr_read_req_0_uop_WIRE.lrs1, UInt<6>(0h0)
connect _mshr_read_req_0_uop_WIRE.ldst, UInt<6>(0h0)
connect _mshr_read_req_0_uop_WIRE.ldst_is_rs1, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.csr_cmd, UInt<3>(0h0)
connect _mshr_read_req_0_uop_WIRE.flush_on_commit, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_unique, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.uses_stq, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.uses_ldq, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.mem_signed, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.mem_size, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.mem_cmd, UInt<5>(0h0)
connect _mshr_read_req_0_uop_WIRE.exc_cause, UInt<64>(0h0)
connect _mshr_read_req_0_uop_WIRE.exception, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.stale_pdst, UInt<7>(0h0)
connect _mshr_read_req_0_uop_WIRE.ppred_busy, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.prs3_busy, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.prs2_busy, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.prs1_busy, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.ppred, UInt<5>(0h0)
connect _mshr_read_req_0_uop_WIRE.prs3, UInt<7>(0h0)
connect _mshr_read_req_0_uop_WIRE.prs2, UInt<7>(0h0)
connect _mshr_read_req_0_uop_WIRE.prs1, UInt<7>(0h0)
connect _mshr_read_req_0_uop_WIRE.pdst, UInt<7>(0h0)
connect _mshr_read_req_0_uop_WIRE.rxq_idx, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.stq_idx, UInt<4>(0h0)
connect _mshr_read_req_0_uop_WIRE.ldq_idx, UInt<4>(0h0)
connect _mshr_read_req_0_uop_WIRE.rob_idx, UInt<6>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.div, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.op2_sel, UInt<3>(0h0)
connect _mshr_read_req_0_uop_WIRE.op1_sel, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.imm_packed, UInt<20>(0h0)
connect _mshr_read_req_0_uop_WIRE.pimm, UInt<5>(0h0)
connect _mshr_read_req_0_uop_WIRE.imm_sel, UInt<3>(0h0)
connect _mshr_read_req_0_uop_WIRE.imm_rename, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.taken, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.pc_lob, UInt<6>(0h0)
connect _mshr_read_req_0_uop_WIRE.edge_inst, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.ftq_idx, UInt<5>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_mov, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_rocc, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_eret, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_amo, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_sfence, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_fencei, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_fence, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_sfb, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.br_type, UInt<4>(0h0)
connect _mshr_read_req_0_uop_WIRE.br_tag, UInt<4>(0h0)
connect _mshr_read_req_0_uop_WIRE.br_mask, UInt<12>(0h0)
connect _mshr_read_req_0_uop_WIRE.dis_col_sel, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_p2_speculative_child, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_p1_speculative_child, UInt<2>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iw_issued, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[0], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[1], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[2], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[3], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[4], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[5], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[6], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[7], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[8], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.fu_code[9], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iq_type[0], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iq_type[1], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iq_type[2], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.iq_type[3], UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.debug_pc, UInt<40>(0h0)
connect _mshr_read_req_0_uop_WIRE.is_rvc, UInt<1>(0h0)
connect _mshr_read_req_0_uop_WIRE.debug_inst, UInt<32>(0h0)
connect _mshr_read_req_0_uop_WIRE.inst, UInt<32>(0h0)
connect mshr_read_req[0].uop, _mshr_read_req_0_uop_WIRE
node _mshr_read_req_0_addr_T = cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx)
node _mshr_read_req_0_addr_T_1 = shl(_mshr_read_req_0_addr_T, 6)
connect mshr_read_req[0].addr, _mshr_read_req_0_addr_T_1
invalidate mshr_read_req[0].data
connect mshr_read_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[3].valid, mshrs.io.meta_read.valid
connect metaReadArb.io.in[3].bits.req[0].tag, mshrs.io.meta_read.bits.tag
connect metaReadArb.io.in[3].bits.req[0].way_en, mshrs.io.meta_read.bits.way_en
connect metaReadArb.io.in[3].bits.req[0].idx, mshrs.io.meta_read.bits.idx
connect mshrs.io.meta_read.ready, metaReadArb.io.in[3].ready
node _wb_fire_T = and(wb.io.meta_read.ready, wb.io.meta_read.valid)
node _wb_fire_T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid)
node wb_fire = and(_wb_fire_T, _wb_fire_T_1)
wire wb_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate wb_req[0].is_hella
invalidate wb_req[0].data
invalidate wb_req[0].addr
invalidate wb_req[0].uop.debug_tsrc
invalidate wb_req[0].uop.debug_fsrc
invalidate wb_req[0].uop.bp_xcpt_if
invalidate wb_req[0].uop.bp_debug_if
invalidate wb_req[0].uop.xcpt_ma_if
invalidate wb_req[0].uop.xcpt_ae_if
invalidate wb_req[0].uop.xcpt_pf_if
invalidate wb_req[0].uop.fp_typ
invalidate wb_req[0].uop.fp_rm
invalidate wb_req[0].uop.fp_val
invalidate wb_req[0].uop.fcn_op
invalidate wb_req[0].uop.fcn_dw
invalidate wb_req[0].uop.frs3_en
invalidate wb_req[0].uop.lrs2_rtype
invalidate wb_req[0].uop.lrs1_rtype
invalidate wb_req[0].uop.dst_rtype
invalidate wb_req[0].uop.lrs3
invalidate wb_req[0].uop.lrs2
invalidate wb_req[0].uop.lrs1
invalidate wb_req[0].uop.ldst
invalidate wb_req[0].uop.ldst_is_rs1
invalidate wb_req[0].uop.csr_cmd
invalidate wb_req[0].uop.flush_on_commit
invalidate wb_req[0].uop.is_unique
invalidate wb_req[0].uop.uses_stq
invalidate wb_req[0].uop.uses_ldq
invalidate wb_req[0].uop.mem_signed
invalidate wb_req[0].uop.mem_size
invalidate wb_req[0].uop.mem_cmd
invalidate wb_req[0].uop.exc_cause
invalidate wb_req[0].uop.exception
invalidate wb_req[0].uop.stale_pdst
invalidate wb_req[0].uop.ppred_busy
invalidate wb_req[0].uop.prs3_busy
invalidate wb_req[0].uop.prs2_busy
invalidate wb_req[0].uop.prs1_busy
invalidate wb_req[0].uop.ppred
invalidate wb_req[0].uop.prs3
invalidate wb_req[0].uop.prs2
invalidate wb_req[0].uop.prs1
invalidate wb_req[0].uop.pdst
invalidate wb_req[0].uop.rxq_idx
invalidate wb_req[0].uop.stq_idx
invalidate wb_req[0].uop.ldq_idx
invalidate wb_req[0].uop.rob_idx
invalidate wb_req[0].uop.fp_ctrl.vec
invalidate wb_req[0].uop.fp_ctrl.wflags
invalidate wb_req[0].uop.fp_ctrl.sqrt
invalidate wb_req[0].uop.fp_ctrl.div
invalidate wb_req[0].uop.fp_ctrl.fma
invalidate wb_req[0].uop.fp_ctrl.fastpipe
invalidate wb_req[0].uop.fp_ctrl.toint
invalidate wb_req[0].uop.fp_ctrl.fromint
invalidate wb_req[0].uop.fp_ctrl.typeTagOut
invalidate wb_req[0].uop.fp_ctrl.typeTagIn
invalidate wb_req[0].uop.fp_ctrl.swap23
invalidate wb_req[0].uop.fp_ctrl.swap12
invalidate wb_req[0].uop.fp_ctrl.ren3
invalidate wb_req[0].uop.fp_ctrl.ren2
invalidate wb_req[0].uop.fp_ctrl.ren1
invalidate wb_req[0].uop.fp_ctrl.wen
invalidate wb_req[0].uop.fp_ctrl.ldst
invalidate wb_req[0].uop.op2_sel
invalidate wb_req[0].uop.op1_sel
invalidate wb_req[0].uop.imm_packed
invalidate wb_req[0].uop.pimm
invalidate wb_req[0].uop.imm_sel
invalidate wb_req[0].uop.imm_rename
invalidate wb_req[0].uop.taken
invalidate wb_req[0].uop.pc_lob
invalidate wb_req[0].uop.edge_inst
invalidate wb_req[0].uop.ftq_idx
invalidate wb_req[0].uop.is_mov
invalidate wb_req[0].uop.is_rocc
invalidate wb_req[0].uop.is_sys_pc2epc
invalidate wb_req[0].uop.is_eret
invalidate wb_req[0].uop.is_amo
invalidate wb_req[0].uop.is_sfence
invalidate wb_req[0].uop.is_fencei
invalidate wb_req[0].uop.is_fence
invalidate wb_req[0].uop.is_sfb
invalidate wb_req[0].uop.br_type
invalidate wb_req[0].uop.br_tag
invalidate wb_req[0].uop.br_mask
invalidate wb_req[0].uop.dis_col_sel
invalidate wb_req[0].uop.iw_p3_bypass_hint
invalidate wb_req[0].uop.iw_p2_bypass_hint
invalidate wb_req[0].uop.iw_p1_bypass_hint
invalidate wb_req[0].uop.iw_p2_speculative_child
invalidate wb_req[0].uop.iw_p1_speculative_child
invalidate wb_req[0].uop.iw_issued_partial_dgen
invalidate wb_req[0].uop.iw_issued_partial_agen
invalidate wb_req[0].uop.iw_issued
invalidate wb_req[0].uop.fu_code[0]
invalidate wb_req[0].uop.fu_code[1]
invalidate wb_req[0].uop.fu_code[2]
invalidate wb_req[0].uop.fu_code[3]
invalidate wb_req[0].uop.fu_code[4]
invalidate wb_req[0].uop.fu_code[5]
invalidate wb_req[0].uop.fu_code[6]
invalidate wb_req[0].uop.fu_code[7]
invalidate wb_req[0].uop.fu_code[8]
invalidate wb_req[0].uop.fu_code[9]
invalidate wb_req[0].uop.iq_type[0]
invalidate wb_req[0].uop.iq_type[1]
invalidate wb_req[0].uop.iq_type[2]
invalidate wb_req[0].uop.iq_type[3]
invalidate wb_req[0].uop.debug_pc
invalidate wb_req[0].uop.is_rvc
invalidate wb_req[0].uop.debug_inst
invalidate wb_req[0].uop.inst
wire _wb_req_0_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect _wb_req_0_uop_WIRE.debug_tsrc, UInt<3>(0h0)
connect _wb_req_0_uop_WIRE.debug_fsrc, UInt<3>(0h0)
connect _wb_req_0_uop_WIRE.bp_xcpt_if, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.bp_debug_if, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.xcpt_ma_if, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.xcpt_ae_if, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.xcpt_pf_if, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_typ, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.fp_rm, UInt<3>(0h0)
connect _wb_req_0_uop_WIRE.fp_val, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fcn_op, UInt<5>(0h0)
connect _wb_req_0_uop_WIRE.fcn_dw, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.frs3_en, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.lrs2_rtype, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.lrs1_rtype, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.dst_rtype, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.lrs3, UInt<6>(0h0)
connect _wb_req_0_uop_WIRE.lrs2, UInt<6>(0h0)
connect _wb_req_0_uop_WIRE.lrs1, UInt<6>(0h0)
connect _wb_req_0_uop_WIRE.ldst, UInt<6>(0h0)
connect _wb_req_0_uop_WIRE.ldst_is_rs1, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.csr_cmd, UInt<3>(0h0)
connect _wb_req_0_uop_WIRE.flush_on_commit, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_unique, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.uses_stq, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.uses_ldq, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.mem_signed, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.mem_size, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.mem_cmd, UInt<5>(0h0)
connect _wb_req_0_uop_WIRE.exc_cause, UInt<64>(0h0)
connect _wb_req_0_uop_WIRE.exception, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.stale_pdst, UInt<7>(0h0)
connect _wb_req_0_uop_WIRE.ppred_busy, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.prs3_busy, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.prs2_busy, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.prs1_busy, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.ppred, UInt<5>(0h0)
connect _wb_req_0_uop_WIRE.prs3, UInt<7>(0h0)
connect _wb_req_0_uop_WIRE.prs2, UInt<7>(0h0)
connect _wb_req_0_uop_WIRE.prs1, UInt<7>(0h0)
connect _wb_req_0_uop_WIRE.pdst, UInt<7>(0h0)
connect _wb_req_0_uop_WIRE.rxq_idx, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.stq_idx, UInt<4>(0h0)
connect _wb_req_0_uop_WIRE.ldq_idx, UInt<4>(0h0)
connect _wb_req_0_uop_WIRE.rob_idx, UInt<6>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.div, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.op2_sel, UInt<3>(0h0)
connect _wb_req_0_uop_WIRE.op1_sel, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.imm_packed, UInt<20>(0h0)
connect _wb_req_0_uop_WIRE.pimm, UInt<5>(0h0)
connect _wb_req_0_uop_WIRE.imm_sel, UInt<3>(0h0)
connect _wb_req_0_uop_WIRE.imm_rename, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.taken, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.pc_lob, UInt<6>(0h0)
connect _wb_req_0_uop_WIRE.edge_inst, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.ftq_idx, UInt<5>(0h0)
connect _wb_req_0_uop_WIRE.is_mov, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_rocc, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_eret, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_amo, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_sfence, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_fencei, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_fence, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.is_sfb, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.br_type, UInt<4>(0h0)
connect _wb_req_0_uop_WIRE.br_tag, UInt<4>(0h0)
connect _wb_req_0_uop_WIRE.br_mask, UInt<12>(0h0)
connect _wb_req_0_uop_WIRE.dis_col_sel, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iw_p2_speculative_child, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.iw_p1_speculative_child, UInt<2>(0h0)
connect _wb_req_0_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iw_issued, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[0], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[1], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[2], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[3], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[4], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[5], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[6], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[7], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[8], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.fu_code[9], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iq_type[0], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iq_type[1], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iq_type[2], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.iq_type[3], UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.debug_pc, UInt<40>(0h0)
connect _wb_req_0_uop_WIRE.is_rvc, UInt<1>(0h0)
connect _wb_req_0_uop_WIRE.debug_inst, UInt<32>(0h0)
connect _wb_req_0_uop_WIRE.inst, UInt<32>(0h0)
connect wb_req[0].uop, _wb_req_0_uop_WIRE
node _wb_req_0_addr_T = cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)
connect wb_req[0].addr, _wb_req_0_addr_T
invalidate wb_req[0].data
connect wb_req[0].is_hella, UInt<1>(0h0)
node _metaReadArb_io_in_2_valid_T = eq(singlePortedDCacheWrite, UInt<1>(0h0))
node _metaReadArb_io_in_2_valid_T_1 = and(wb.io.meta_read.valid, _metaReadArb_io_in_2_valid_T)
connect metaReadArb.io.in[2].valid, _metaReadArb_io_in_2_valid_T_1
connect metaReadArb.io.in[2].bits.req[0].tag, wb.io.meta_read.bits.tag
connect metaReadArb.io.in[2].bits.req[0].way_en, wb.io.meta_read.bits.way_en
connect metaReadArb.io.in[2].bits.req[0].idx, wb.io.meta_read.bits.idx
node _wb_io_meta_read_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready)
node _wb_io_meta_read_ready_T_1 = eq(singlePortedDCacheWrite, UInt<1>(0h0))
node _wb_io_meta_read_ready_T_2 = and(_wb_io_meta_read_ready_T, _wb_io_meta_read_ready_T_1)
connect wb.io.meta_read.ready, _wb_io_meta_read_ready_T_2
node _dataReadArb_io_in_1_valid_T = eq(singlePortedDCacheWrite, UInt<1>(0h0))
node _dataReadArb_io_in_1_valid_T_1 = and(wb.io.data_req.valid, _dataReadArb_io_in_1_valid_T)
connect dataReadArb.io.in[1].valid, _dataReadArb_io_in_1_valid_T_1
connect dataReadArb.io.in[1].bits.req[0].addr, wb.io.data_req.bits.addr
connect dataReadArb.io.in[1].bits.req[0].way_en, wb.io.data_req.bits.way_en
wire _WIRE_1 : UInt<1>[1]
connect _WIRE_1[0], UInt<1>(0h1)
connect dataReadArb.io.in[1].bits.valid[0], _WIRE_1[0]
node _wb_io_data_req_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready)
node _wb_io_data_req_ready_T_1 = eq(singlePortedDCacheWrite, UInt<1>(0h0))
node _wb_io_data_req_ready_T_2 = and(_wb_io_data_req_ready_T, _wb_io_data_req_ready_T_1)
connect wb.io.data_req.ready, _wb_io_data_req_ready_T_2
node _T = and(wb.io.meta_read.ready, wb.io.meta_read.valid)
node _T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid)
node _T_2 = xor(_T, _T_1)
node _T_3 = eq(_T_2, UInt<1>(0h0))
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:581 assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node prober_fire = and(prober.io.meta_read.ready, prober.io.meta_read.valid)
wire prober_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate prober_req[0].is_hella
invalidate prober_req[0].data
invalidate prober_req[0].addr
invalidate prober_req[0].uop.debug_tsrc
invalidate prober_req[0].uop.debug_fsrc
invalidate prober_req[0].uop.bp_xcpt_if
invalidate prober_req[0].uop.bp_debug_if
invalidate prober_req[0].uop.xcpt_ma_if
invalidate prober_req[0].uop.xcpt_ae_if
invalidate prober_req[0].uop.xcpt_pf_if
invalidate prober_req[0].uop.fp_typ
invalidate prober_req[0].uop.fp_rm
invalidate prober_req[0].uop.fp_val
invalidate prober_req[0].uop.fcn_op
invalidate prober_req[0].uop.fcn_dw
invalidate prober_req[0].uop.frs3_en
invalidate prober_req[0].uop.lrs2_rtype
invalidate prober_req[0].uop.lrs1_rtype
invalidate prober_req[0].uop.dst_rtype
invalidate prober_req[0].uop.lrs3
invalidate prober_req[0].uop.lrs2
invalidate prober_req[0].uop.lrs1
invalidate prober_req[0].uop.ldst
invalidate prober_req[0].uop.ldst_is_rs1
invalidate prober_req[0].uop.csr_cmd
invalidate prober_req[0].uop.flush_on_commit
invalidate prober_req[0].uop.is_unique
invalidate prober_req[0].uop.uses_stq
invalidate prober_req[0].uop.uses_ldq
invalidate prober_req[0].uop.mem_signed
invalidate prober_req[0].uop.mem_size
invalidate prober_req[0].uop.mem_cmd
invalidate prober_req[0].uop.exc_cause
invalidate prober_req[0].uop.exception
invalidate prober_req[0].uop.stale_pdst
invalidate prober_req[0].uop.ppred_busy
invalidate prober_req[0].uop.prs3_busy
invalidate prober_req[0].uop.prs2_busy
invalidate prober_req[0].uop.prs1_busy
invalidate prober_req[0].uop.ppred
invalidate prober_req[0].uop.prs3
invalidate prober_req[0].uop.prs2
invalidate prober_req[0].uop.prs1
invalidate prober_req[0].uop.pdst
invalidate prober_req[0].uop.rxq_idx
invalidate prober_req[0].uop.stq_idx
invalidate prober_req[0].uop.ldq_idx
invalidate prober_req[0].uop.rob_idx
invalidate prober_req[0].uop.fp_ctrl.vec
invalidate prober_req[0].uop.fp_ctrl.wflags
invalidate prober_req[0].uop.fp_ctrl.sqrt
invalidate prober_req[0].uop.fp_ctrl.div
invalidate prober_req[0].uop.fp_ctrl.fma
invalidate prober_req[0].uop.fp_ctrl.fastpipe
invalidate prober_req[0].uop.fp_ctrl.toint
invalidate prober_req[0].uop.fp_ctrl.fromint
invalidate prober_req[0].uop.fp_ctrl.typeTagOut
invalidate prober_req[0].uop.fp_ctrl.typeTagIn
invalidate prober_req[0].uop.fp_ctrl.swap23
invalidate prober_req[0].uop.fp_ctrl.swap12
invalidate prober_req[0].uop.fp_ctrl.ren3
invalidate prober_req[0].uop.fp_ctrl.ren2
invalidate prober_req[0].uop.fp_ctrl.ren1
invalidate prober_req[0].uop.fp_ctrl.wen
invalidate prober_req[0].uop.fp_ctrl.ldst
invalidate prober_req[0].uop.op2_sel
invalidate prober_req[0].uop.op1_sel
invalidate prober_req[0].uop.imm_packed
invalidate prober_req[0].uop.pimm
invalidate prober_req[0].uop.imm_sel
invalidate prober_req[0].uop.imm_rename
invalidate prober_req[0].uop.taken
invalidate prober_req[0].uop.pc_lob
invalidate prober_req[0].uop.edge_inst
invalidate prober_req[0].uop.ftq_idx
invalidate prober_req[0].uop.is_mov
invalidate prober_req[0].uop.is_rocc
invalidate prober_req[0].uop.is_sys_pc2epc
invalidate prober_req[0].uop.is_eret
invalidate prober_req[0].uop.is_amo
invalidate prober_req[0].uop.is_sfence
invalidate prober_req[0].uop.is_fencei
invalidate prober_req[0].uop.is_fence
invalidate prober_req[0].uop.is_sfb
invalidate prober_req[0].uop.br_type
invalidate prober_req[0].uop.br_tag
invalidate prober_req[0].uop.br_mask
invalidate prober_req[0].uop.dis_col_sel
invalidate prober_req[0].uop.iw_p3_bypass_hint
invalidate prober_req[0].uop.iw_p2_bypass_hint
invalidate prober_req[0].uop.iw_p1_bypass_hint
invalidate prober_req[0].uop.iw_p2_speculative_child
invalidate prober_req[0].uop.iw_p1_speculative_child
invalidate prober_req[0].uop.iw_issued_partial_dgen
invalidate prober_req[0].uop.iw_issued_partial_agen
invalidate prober_req[0].uop.iw_issued
invalidate prober_req[0].uop.fu_code[0]
invalidate prober_req[0].uop.fu_code[1]
invalidate prober_req[0].uop.fu_code[2]
invalidate prober_req[0].uop.fu_code[3]
invalidate prober_req[0].uop.fu_code[4]
invalidate prober_req[0].uop.fu_code[5]
invalidate prober_req[0].uop.fu_code[6]
invalidate prober_req[0].uop.fu_code[7]
invalidate prober_req[0].uop.fu_code[8]
invalidate prober_req[0].uop.fu_code[9]
invalidate prober_req[0].uop.iq_type[0]
invalidate prober_req[0].uop.iq_type[1]
invalidate prober_req[0].uop.iq_type[2]
invalidate prober_req[0].uop.iq_type[3]
invalidate prober_req[0].uop.debug_pc
invalidate prober_req[0].uop.is_rvc
invalidate prober_req[0].uop.debug_inst
invalidate prober_req[0].uop.inst
wire _prober_req_0_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect _prober_req_0_uop_WIRE.debug_tsrc, UInt<3>(0h0)
connect _prober_req_0_uop_WIRE.debug_fsrc, UInt<3>(0h0)
connect _prober_req_0_uop_WIRE.bp_xcpt_if, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.bp_debug_if, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.xcpt_ma_if, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.xcpt_ae_if, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.xcpt_pf_if, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_typ, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.fp_rm, UInt<3>(0h0)
connect _prober_req_0_uop_WIRE.fp_val, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fcn_op, UInt<5>(0h0)
connect _prober_req_0_uop_WIRE.fcn_dw, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.frs3_en, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.lrs2_rtype, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.lrs1_rtype, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.dst_rtype, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.lrs3, UInt<6>(0h0)
connect _prober_req_0_uop_WIRE.lrs2, UInt<6>(0h0)
connect _prober_req_0_uop_WIRE.lrs1, UInt<6>(0h0)
connect _prober_req_0_uop_WIRE.ldst, UInt<6>(0h0)
connect _prober_req_0_uop_WIRE.ldst_is_rs1, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.csr_cmd, UInt<3>(0h0)
connect _prober_req_0_uop_WIRE.flush_on_commit, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_unique, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.uses_stq, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.uses_ldq, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.mem_signed, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.mem_size, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.mem_cmd, UInt<5>(0h0)
connect _prober_req_0_uop_WIRE.exc_cause, UInt<64>(0h0)
connect _prober_req_0_uop_WIRE.exception, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.stale_pdst, UInt<7>(0h0)
connect _prober_req_0_uop_WIRE.ppred_busy, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.prs3_busy, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.prs2_busy, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.prs1_busy, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.ppred, UInt<5>(0h0)
connect _prober_req_0_uop_WIRE.prs3, UInt<7>(0h0)
connect _prober_req_0_uop_WIRE.prs2, UInt<7>(0h0)
connect _prober_req_0_uop_WIRE.prs1, UInt<7>(0h0)
connect _prober_req_0_uop_WIRE.pdst, UInt<7>(0h0)
connect _prober_req_0_uop_WIRE.rxq_idx, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.stq_idx, UInt<4>(0h0)
connect _prober_req_0_uop_WIRE.ldq_idx, UInt<4>(0h0)
connect _prober_req_0_uop_WIRE.rob_idx, UInt<6>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.div, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.op2_sel, UInt<3>(0h0)
connect _prober_req_0_uop_WIRE.op1_sel, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.imm_packed, UInt<20>(0h0)
connect _prober_req_0_uop_WIRE.pimm, UInt<5>(0h0)
connect _prober_req_0_uop_WIRE.imm_sel, UInt<3>(0h0)
connect _prober_req_0_uop_WIRE.imm_rename, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.taken, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.pc_lob, UInt<6>(0h0)
connect _prober_req_0_uop_WIRE.edge_inst, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.ftq_idx, UInt<5>(0h0)
connect _prober_req_0_uop_WIRE.is_mov, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_rocc, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_eret, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_amo, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_sfence, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_fencei, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_fence, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.is_sfb, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.br_type, UInt<4>(0h0)
connect _prober_req_0_uop_WIRE.br_tag, UInt<4>(0h0)
connect _prober_req_0_uop_WIRE.br_mask, UInt<12>(0h0)
connect _prober_req_0_uop_WIRE.dis_col_sel, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iw_p2_speculative_child, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.iw_p1_speculative_child, UInt<2>(0h0)
connect _prober_req_0_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iw_issued, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[0], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[1], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[2], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[3], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[4], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[5], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[6], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[7], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[8], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.fu_code[9], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iq_type[0], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iq_type[1], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iq_type[2], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.iq_type[3], UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.debug_pc, UInt<40>(0h0)
connect _prober_req_0_uop_WIRE.is_rvc, UInt<1>(0h0)
connect _prober_req_0_uop_WIRE.debug_inst, UInt<32>(0h0)
connect _prober_req_0_uop_WIRE.inst, UInt<32>(0h0)
connect prober_req[0].uop, _prober_req_0_uop_WIRE
node _prober_req_0_addr_T = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx)
node _prober_req_0_addr_T_1 = shl(_prober_req_0_addr_T, 6)
connect prober_req[0].addr, _prober_req_0_addr_T_1
invalidate prober_req[0].data
connect prober_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[1].valid, prober.io.meta_read.valid
connect metaReadArb.io.in[1].bits.req[0].tag, prober.io.meta_read.bits.tag
connect metaReadArb.io.in[1].bits.req[0].way_en, prober.io.meta_read.bits.way_en
connect metaReadArb.io.in[1].bits.req[0].idx, prober.io.meta_read.bits.idx
connect prober.io.meta_read.ready, metaReadArb.io.in[1].ready
node prefetch_fire = and(mshrs.io.prefetch.ready, mshrs.io.prefetch.valid)
wire prefetch_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate prefetch_req[0].is_hella
invalidate prefetch_req[0].data
invalidate prefetch_req[0].addr
invalidate prefetch_req[0].uop.debug_tsrc
invalidate prefetch_req[0].uop.debug_fsrc
invalidate prefetch_req[0].uop.bp_xcpt_if
invalidate prefetch_req[0].uop.bp_debug_if
invalidate prefetch_req[0].uop.xcpt_ma_if
invalidate prefetch_req[0].uop.xcpt_ae_if
invalidate prefetch_req[0].uop.xcpt_pf_if
invalidate prefetch_req[0].uop.fp_typ
invalidate prefetch_req[0].uop.fp_rm
invalidate prefetch_req[0].uop.fp_val
invalidate prefetch_req[0].uop.fcn_op
invalidate prefetch_req[0].uop.fcn_dw
invalidate prefetch_req[0].uop.frs3_en
invalidate prefetch_req[0].uop.lrs2_rtype
invalidate prefetch_req[0].uop.lrs1_rtype
invalidate prefetch_req[0].uop.dst_rtype
invalidate prefetch_req[0].uop.lrs3
invalidate prefetch_req[0].uop.lrs2
invalidate prefetch_req[0].uop.lrs1
invalidate prefetch_req[0].uop.ldst
invalidate prefetch_req[0].uop.ldst_is_rs1
invalidate prefetch_req[0].uop.csr_cmd
invalidate prefetch_req[0].uop.flush_on_commit
invalidate prefetch_req[0].uop.is_unique
invalidate prefetch_req[0].uop.uses_stq
invalidate prefetch_req[0].uop.uses_ldq
invalidate prefetch_req[0].uop.mem_signed
invalidate prefetch_req[0].uop.mem_size
invalidate prefetch_req[0].uop.mem_cmd
invalidate prefetch_req[0].uop.exc_cause
invalidate prefetch_req[0].uop.exception
invalidate prefetch_req[0].uop.stale_pdst
invalidate prefetch_req[0].uop.ppred_busy
invalidate prefetch_req[0].uop.prs3_busy
invalidate prefetch_req[0].uop.prs2_busy
invalidate prefetch_req[0].uop.prs1_busy
invalidate prefetch_req[0].uop.ppred
invalidate prefetch_req[0].uop.prs3
invalidate prefetch_req[0].uop.prs2
invalidate prefetch_req[0].uop.prs1
invalidate prefetch_req[0].uop.pdst
invalidate prefetch_req[0].uop.rxq_idx
invalidate prefetch_req[0].uop.stq_idx
invalidate prefetch_req[0].uop.ldq_idx
invalidate prefetch_req[0].uop.rob_idx
invalidate prefetch_req[0].uop.fp_ctrl.vec
invalidate prefetch_req[0].uop.fp_ctrl.wflags
invalidate prefetch_req[0].uop.fp_ctrl.sqrt
invalidate prefetch_req[0].uop.fp_ctrl.div
invalidate prefetch_req[0].uop.fp_ctrl.fma
invalidate prefetch_req[0].uop.fp_ctrl.fastpipe
invalidate prefetch_req[0].uop.fp_ctrl.toint
invalidate prefetch_req[0].uop.fp_ctrl.fromint
invalidate prefetch_req[0].uop.fp_ctrl.typeTagOut
invalidate prefetch_req[0].uop.fp_ctrl.typeTagIn
invalidate prefetch_req[0].uop.fp_ctrl.swap23
invalidate prefetch_req[0].uop.fp_ctrl.swap12
invalidate prefetch_req[0].uop.fp_ctrl.ren3
invalidate prefetch_req[0].uop.fp_ctrl.ren2
invalidate prefetch_req[0].uop.fp_ctrl.ren1
invalidate prefetch_req[0].uop.fp_ctrl.wen
invalidate prefetch_req[0].uop.fp_ctrl.ldst
invalidate prefetch_req[0].uop.op2_sel
invalidate prefetch_req[0].uop.op1_sel
invalidate prefetch_req[0].uop.imm_packed
invalidate prefetch_req[0].uop.pimm
invalidate prefetch_req[0].uop.imm_sel
invalidate prefetch_req[0].uop.imm_rename
invalidate prefetch_req[0].uop.taken
invalidate prefetch_req[0].uop.pc_lob
invalidate prefetch_req[0].uop.edge_inst
invalidate prefetch_req[0].uop.ftq_idx
invalidate prefetch_req[0].uop.is_mov
invalidate prefetch_req[0].uop.is_rocc
invalidate prefetch_req[0].uop.is_sys_pc2epc
invalidate prefetch_req[0].uop.is_eret
invalidate prefetch_req[0].uop.is_amo
invalidate prefetch_req[0].uop.is_sfence
invalidate prefetch_req[0].uop.is_fencei
invalidate prefetch_req[0].uop.is_fence
invalidate prefetch_req[0].uop.is_sfb
invalidate prefetch_req[0].uop.br_type
invalidate prefetch_req[0].uop.br_tag
invalidate prefetch_req[0].uop.br_mask
invalidate prefetch_req[0].uop.dis_col_sel
invalidate prefetch_req[0].uop.iw_p3_bypass_hint
invalidate prefetch_req[0].uop.iw_p2_bypass_hint
invalidate prefetch_req[0].uop.iw_p1_bypass_hint
invalidate prefetch_req[0].uop.iw_p2_speculative_child
invalidate prefetch_req[0].uop.iw_p1_speculative_child
invalidate prefetch_req[0].uop.iw_issued_partial_dgen
invalidate prefetch_req[0].uop.iw_issued_partial_agen
invalidate prefetch_req[0].uop.iw_issued
invalidate prefetch_req[0].uop.fu_code[0]
invalidate prefetch_req[0].uop.fu_code[1]
invalidate prefetch_req[0].uop.fu_code[2]
invalidate prefetch_req[0].uop.fu_code[3]
invalidate prefetch_req[0].uop.fu_code[4]
invalidate prefetch_req[0].uop.fu_code[5]
invalidate prefetch_req[0].uop.fu_code[6]
invalidate prefetch_req[0].uop.fu_code[7]
invalidate prefetch_req[0].uop.fu_code[8]
invalidate prefetch_req[0].uop.fu_code[9]
invalidate prefetch_req[0].uop.iq_type[0]
invalidate prefetch_req[0].uop.iq_type[1]
invalidate prefetch_req[0].uop.iq_type[2]
invalidate prefetch_req[0].uop.iq_type[3]
invalidate prefetch_req[0].uop.debug_pc
invalidate prefetch_req[0].uop.is_rvc
invalidate prefetch_req[0].uop.debug_inst
invalidate prefetch_req[0].uop.inst
connect prefetch_req[0], mshrs.io.prefetch.bits
connect metaReadArb.io.in[5].valid, mshrs.io.prefetch.valid
node _metaReadArb_io_in_5_bits_req_0_idx_T = shr(mshrs.io.prefetch.bits.addr, 6)
connect metaReadArb.io.in[5].bits.req[0].idx, _metaReadArb_io_in_5_bits_req_0_idx_T
invalidate metaReadArb.io.in[5].bits.req[0].way_en
invalidate metaReadArb.io.in[5].bits.req[0].tag
connect mshrs.io.prefetch.ready, metaReadArb.io.in[5].ready
node _s0_valid_T = and(io.lsu.req.ready, io.lsu.req.valid)
wire _s0_valid_WIRE : UInt<1>[1]
connect _s0_valid_WIRE[0], io.lsu.req.bits[0].valid
node _s0_valid_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid)
node _s0_valid_T_2 = or(_s0_valid_T_1, wb_fire)
node _s0_valid_T_3 = or(_s0_valid_T_2, prober_fire)
node _s0_valid_T_4 = or(_s0_valid_T_3, prefetch_fire)
node _s0_valid_T_5 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_valid_T_6 = or(_s0_valid_T_4, _s0_valid_T_5)
wire _s0_valid_WIRE_1 : UInt<1>[1]
connect _s0_valid_WIRE_1[0], UInt<1>(0h1)
wire _s0_valid_WIRE_2 : UInt<1>[1]
connect _s0_valid_WIRE_2[0], UInt<1>(0h0)
node _s0_valid_T_7 = mux(_s0_valid_T_6, _s0_valid_WIRE_1, _s0_valid_WIRE_2)
node s0_valid = mux(_s0_valid_T, _s0_valid_WIRE, _s0_valid_T_7)
node _s0_req_T = and(io.lsu.req.ready, io.lsu.req.valid)
wire _s0_req_WIRE : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
connect _s0_req_WIRE[0], io.lsu.req.bits[0].bits
node _s0_req_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_req_T_2 = mux(_s0_req_T_1, mshr_read_req, replay_req)
node _s0_req_T_3 = mux(prefetch_fire, prefetch_req, _s0_req_T_2)
node _s0_req_T_4 = mux(prober_fire, prober_req, _s0_req_T_3)
node _s0_req_T_5 = mux(wb_fire, wb_req, _s0_req_T_4)
node s0_req = mux(_s0_req_T, _s0_req_WIRE, _s0_req_T_5)
node _s0_type_T = and(io.lsu.req.ready, io.lsu.req.valid)
node _s0_type_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_type_T_2 = mux(_s0_type_T_1, UInt<3>(0h3), UInt<3>(0h0))
node _s0_type_T_3 = mux(prefetch_fire, UInt<3>(0h5), _s0_type_T_2)
node _s0_type_T_4 = mux(prober_fire, UInt<3>(0h1), _s0_type_T_3)
node _s0_type_T_5 = mux(wb_fire, UInt<3>(0h2), _s0_type_T_4)
node s0_type = mux(_s0_type_T, UInt<3>(0h4), _s0_type_T_5)
node _s0_send_resp_or_nack_T = and(io.lsu.req.ready, io.lsu.req.valid)
node _s0_send_resp_or_nack_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid)
node _s0_send_resp_or_nack_T_2 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<1>(0h0))
node _s0_send_resp_or_nack_T_3 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<5>(0h10))
node _s0_send_resp_or_nack_T_4 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h6))
node _s0_send_resp_or_nack_T_5 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h7))
node _s0_send_resp_or_nack_T_6 = or(_s0_send_resp_or_nack_T_2, _s0_send_resp_or_nack_T_3)
node _s0_send_resp_or_nack_T_7 = or(_s0_send_resp_or_nack_T_6, _s0_send_resp_or_nack_T_4)
node _s0_send_resp_or_nack_T_8 = or(_s0_send_resp_or_nack_T_7, _s0_send_resp_or_nack_T_5)
node _s0_send_resp_or_nack_T_9 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h4))
node _s0_send_resp_or_nack_T_10 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h9))
node _s0_send_resp_or_nack_T_11 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0ha))
node _s0_send_resp_or_nack_T_12 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hb))
node _s0_send_resp_or_nack_T_13 = or(_s0_send_resp_or_nack_T_9, _s0_send_resp_or_nack_T_10)
node _s0_send_resp_or_nack_T_14 = or(_s0_send_resp_or_nack_T_13, _s0_send_resp_or_nack_T_11)
node _s0_send_resp_or_nack_T_15 = or(_s0_send_resp_or_nack_T_14, _s0_send_resp_or_nack_T_12)
node _s0_send_resp_or_nack_T_16 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h8))
node _s0_send_resp_or_nack_T_17 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hc))
node _s0_send_resp_or_nack_T_18 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hd))
node _s0_send_resp_or_nack_T_19 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0he))
node _s0_send_resp_or_nack_T_20 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hf))
node _s0_send_resp_or_nack_T_21 = or(_s0_send_resp_or_nack_T_16, _s0_send_resp_or_nack_T_17)
node _s0_send_resp_or_nack_T_22 = or(_s0_send_resp_or_nack_T_21, _s0_send_resp_or_nack_T_18)
node _s0_send_resp_or_nack_T_23 = or(_s0_send_resp_or_nack_T_22, _s0_send_resp_or_nack_T_19)
node _s0_send_resp_or_nack_T_24 = or(_s0_send_resp_or_nack_T_23, _s0_send_resp_or_nack_T_20)
node _s0_send_resp_or_nack_T_25 = or(_s0_send_resp_or_nack_T_15, _s0_send_resp_or_nack_T_24)
node _s0_send_resp_or_nack_T_26 = or(_s0_send_resp_or_nack_T_8, _s0_send_resp_or_nack_T_25)
node _s0_send_resp_or_nack_T_27 = and(_s0_send_resp_or_nack_T_1, _s0_send_resp_or_nack_T_26)
node _s0_send_resp_or_nack_T_28 = mux(_s0_send_resp_or_nack_T_27, UInt<1>(0h1), UInt<1>(0h0))
node _s0_send_resp_or_nack_T_29 = bits(_s0_send_resp_or_nack_T_28, 0, 0)
wire _s0_send_resp_or_nack_WIRE : UInt<1>[1]
connect _s0_send_resp_or_nack_WIRE[0], _s0_send_resp_or_nack_T_29
node s0_send_resp_or_nack = mux(_s0_send_resp_or_nack_T, s0_valid, _s0_send_resp_or_nack_WIRE)
reg s1_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1], clock
connect s1_req, s0_req
node _s1_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _s1_req_0_uop_br_mask_T_1 = and(s0_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T)
connect s1_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T_1
wire s2_store_failed : UInt<1>
node _s1_valid_T = and(io.lsu.brupdate.b1.mispredict_mask, s0_req[0].uop.br_mask)
node _s1_valid_T_1 = neq(_s1_valid_T, UInt<1>(0h0))
node _s1_valid_T_2 = or(_s1_valid_T_1, UInt<1>(0h0))
node _s1_valid_T_3 = eq(_s1_valid_T_2, UInt<1>(0h0))
node _s1_valid_T_4 = and(s0_valid[0], _s1_valid_T_3)
node _s1_valid_T_5 = and(io.lsu.exception, s0_req[0].uop.uses_ldq)
node _s1_valid_T_6 = eq(_s1_valid_T_5, UInt<1>(0h0))
node _s1_valid_T_7 = and(_s1_valid_T_4, _s1_valid_T_6)
node _s1_valid_T_8 = and(io.lsu.req.ready, io.lsu.req.valid)
node _s1_valid_T_9 = and(s2_store_failed, _s1_valid_T_8)
node _s1_valid_T_10 = and(_s1_valid_T_9, s0_req[0].uop.uses_stq)
node _s1_valid_T_11 = eq(_s1_valid_T_10, UInt<1>(0h0))
node _s1_valid_T_12 = and(_s1_valid_T_7, _s1_valid_T_11)
regreset s1_valid_REG : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_valid_REG, _s1_valid_T_12
wire s1_valid : UInt<1>[1]
connect s1_valid[0], s1_valid_REG
node _T_7 = and(io.lsu.req.ready, io.lsu.req.valid)
reg REG : UInt<1>, clock
connect REG, _T_7
node _T_8 = eq(REG, UInt<1>(0h0))
node _T_9 = and(io.lsu.s1_kill[0], _T_8)
reg REG_1 : UInt<1>, clock
connect REG_1, io.lsu.req.bits[0].valid
node _T_10 = eq(REG_1, UInt<1>(0h0))
node _T_11 = and(_T_9, _T_10)
node _T_12 = eq(_T_11, UInt<1>(0h0))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:645 assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))\n") : printf_1
assert(clock, _T_12, UInt<1>(0h1), "") : assert_1
node _s1_nack_T = bits(s1_req[0].addr, 11, 6)
node _s1_nack_T_1 = eq(_s1_nack_T, prober.io.meta_write.bits.idx)
node _s1_nack_T_2 = eq(prober.io.req.ready, UInt<1>(0h0))
node s1_nack_0 = and(_s1_nack_T_1, _s1_nack_T_2)
reg s1_send_resp_or_nack : UInt<1>[1], clock
connect s1_send_resp_or_nack, s0_send_resp_or_nack
reg s1_type : UInt, clock
connect s1_type, s0_type
reg s1_mshr_meta_read_way_en : UInt, clock
connect s1_mshr_meta_read_way_en, mshrs.io.meta_read.bits.way_en
reg s1_replay_way_en : UInt, clock
connect s1_replay_way_en, mshrs.io.replay.bits.way_en
reg s1_wb_way_en : UInt, clock
connect s1_wb_way_en, wb.io.data_req.bits.way_en
node _s1_tag_eq_way_T = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_1 = eq(meta_0.io.resp[0].tag, _s1_tag_eq_way_T)
node _s1_tag_eq_way_T_2 = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_3 = eq(meta_0.io.resp[1].tag, _s1_tag_eq_way_T_2)
node _s1_tag_eq_way_T_4 = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_5 = eq(meta_0.io.resp[2].tag, _s1_tag_eq_way_T_4)
node _s1_tag_eq_way_T_6 = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_7 = eq(meta_0.io.resp[3].tag, _s1_tag_eq_way_T_6)
wire _s1_tag_eq_way_WIRE : UInt<1>[4]
connect _s1_tag_eq_way_WIRE[0], _s1_tag_eq_way_T_1
connect _s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_T_3
connect _s1_tag_eq_way_WIRE[2], _s1_tag_eq_way_T_5
connect _s1_tag_eq_way_WIRE[3], _s1_tag_eq_way_T_7
node s1_tag_eq_way_lo = cat(_s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_WIRE[0])
node s1_tag_eq_way_hi = cat(_s1_tag_eq_way_WIRE[3], _s1_tag_eq_way_WIRE[2])
node _s1_tag_eq_way_T_8 = cat(s1_tag_eq_way_hi, s1_tag_eq_way_lo)
wire s1_tag_eq_way : UInt<4>[1]
connect s1_tag_eq_way[0], _s1_tag_eq_way_T_8
node _s1_tag_match_way_T = eq(s1_type, UInt<3>(0h0))
node _s1_tag_match_way_T_1 = eq(s1_type, UInt<3>(0h2))
node _s1_tag_match_way_T_2 = eq(s1_type, UInt<3>(0h3))
node _s1_tag_match_way_T_3 = bits(s1_tag_eq_way[0], 0, 0)
node _s1_tag_match_way_T_4 = gt(meta_0.io.resp[0].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_5 = and(_s1_tag_match_way_T_3, _s1_tag_match_way_T_4)
node _s1_tag_match_way_T_6 = bits(s1_tag_eq_way[0], 1, 1)
node _s1_tag_match_way_T_7 = gt(meta_0.io.resp[1].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_8 = and(_s1_tag_match_way_T_6, _s1_tag_match_way_T_7)
node _s1_tag_match_way_T_9 = bits(s1_tag_eq_way[0], 2, 2)
node _s1_tag_match_way_T_10 = gt(meta_0.io.resp[2].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_11 = and(_s1_tag_match_way_T_9, _s1_tag_match_way_T_10)
node _s1_tag_match_way_T_12 = bits(s1_tag_eq_way[0], 3, 3)
node _s1_tag_match_way_T_13 = gt(meta_0.io.resp[3].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_14 = and(_s1_tag_match_way_T_12, _s1_tag_match_way_T_13)
wire _s1_tag_match_way_WIRE : UInt<1>[4]
connect _s1_tag_match_way_WIRE[0], _s1_tag_match_way_T_5
connect _s1_tag_match_way_WIRE[1], _s1_tag_match_way_T_8
connect _s1_tag_match_way_WIRE[2], _s1_tag_match_way_T_11
connect _s1_tag_match_way_WIRE[3], _s1_tag_match_way_T_14
node s1_tag_match_way_lo = cat(_s1_tag_match_way_WIRE[1], _s1_tag_match_way_WIRE[0])
node s1_tag_match_way_hi = cat(_s1_tag_match_way_WIRE[3], _s1_tag_match_way_WIRE[2])
node _s1_tag_match_way_T_15 = cat(s1_tag_match_way_hi, s1_tag_match_way_lo)
node _s1_tag_match_way_T_16 = mux(_s1_tag_match_way_T_2, s1_mshr_meta_read_way_en, _s1_tag_match_way_T_15)
node _s1_tag_match_way_T_17 = mux(_s1_tag_match_way_T_1, s1_wb_way_en, _s1_tag_match_way_T_16)
node _s1_tag_match_way_T_18 = mux(_s1_tag_match_way_T, s1_replay_way_en, _s1_tag_match_way_T_17)
wire s1_tag_match_way : UInt[1]
connect s1_tag_match_way[0], _s1_tag_match_way_T_18
node _s1_wb_idx_matches_T = bits(s1_req[0].addr, 11, 6)
node _s1_wb_idx_matches_T_1 = eq(_s1_wb_idx_matches_T, wb.io.idx.bits)
node _s1_wb_idx_matches_T_2 = and(_s1_wb_idx_matches_T_1, wb.io.idx.valid)
wire s1_wb_idx_matches : UInt<1>[1]
connect s1_wb_idx_matches[0], _s1_wb_idx_matches_T_2
connect io.lsu.s1_nack_advisory[0], data.io.s1_nacks[0]
reg s2_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1], clock
connect s2_req, s1_req
reg s2_type : UInt, clock
connect s2_type, s1_type
node _s2_valid_T = eq(io.lsu.s1_kill[0], UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid[0], _s2_valid_T)
node _s2_valid_T_2 = and(io.lsu.brupdate.b1.mispredict_mask, s1_req[0].uop.br_mask)
node _s2_valid_T_3 = neq(_s2_valid_T_2, UInt<1>(0h0))
node _s2_valid_T_4 = or(_s2_valid_T_3, UInt<1>(0h0))
node _s2_valid_T_5 = eq(_s2_valid_T_4, UInt<1>(0h0))
node _s2_valid_T_6 = and(_s2_valid_T_1, _s2_valid_T_5)
node _s2_valid_T_7 = and(io.lsu.exception, s1_req[0].uop.uses_ldq)
node _s2_valid_T_8 = eq(_s2_valid_T_7, UInt<1>(0h0))
node _s2_valid_T_9 = and(_s2_valid_T_6, _s2_valid_T_8)
node _s2_valid_T_10 = eq(s1_type, UInt<3>(0h4))
node _s2_valid_T_11 = and(s2_store_failed, _s2_valid_T_10)
node _s2_valid_T_12 = and(_s2_valid_T_11, s1_req[0].uop.uses_stq)
node _s2_valid_T_13 = eq(_s2_valid_T_12, UInt<1>(0h0))
node _s2_valid_T_14 = and(_s2_valid_T_9, _s2_valid_T_13)
reg s2_valid_REG : UInt<1>, clock
connect s2_valid_REG, _s2_valid_T_14
wire s2_valid : UInt<1>[1]
connect s2_valid[0], s2_valid_REG
node _s2_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _s2_req_0_uop_br_mask_T_1 = and(s1_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T)
connect s2_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T_1
reg s2_tag_match_way : UInt[1], clock
connect s2_tag_match_way, s1_tag_match_way
node s2_tag_match_0 = orr(s2_tag_match_way[0])
reg s2_hit_state_REG : { state : UInt<2>}, clock
connect s2_hit_state_REG, meta_0.io.resp[0].coh
reg s2_hit_state_REG_1 : { state : UInt<2>}, clock
connect s2_hit_state_REG_1, meta_0.io.resp[1].coh
reg s2_hit_state_REG_2 : { state : UInt<2>}, clock
connect s2_hit_state_REG_2, meta_0.io.resp[2].coh
reg s2_hit_state_REG_3 : { state : UInt<2>}, clock
connect s2_hit_state_REG_3, meta_0.io.resp[3].coh
wire _s2_hit_state_WIRE : { state : UInt<2>}[4]
connect _s2_hit_state_WIRE[0], s2_hit_state_REG
connect _s2_hit_state_WIRE[1], s2_hit_state_REG_1
connect _s2_hit_state_WIRE[2], s2_hit_state_REG_2
connect _s2_hit_state_WIRE[3], s2_hit_state_REG_3
node _s2_hit_state_T = bits(s2_tag_match_way[0], 0, 0)
node _s2_hit_state_T_1 = bits(s2_tag_match_way[0], 1, 1)
node _s2_hit_state_T_2 = bits(s2_tag_match_way[0], 2, 2)
node _s2_hit_state_T_3 = bits(s2_tag_match_way[0], 3, 3)
wire _s2_hit_state_WIRE_1 : { state : UInt<2>}
node _s2_hit_state_T_4 = mux(_s2_hit_state_T, _s2_hit_state_WIRE[0].state, UInt<1>(0h0))
node _s2_hit_state_T_5 = mux(_s2_hit_state_T_1, _s2_hit_state_WIRE[1].state, UInt<1>(0h0))
node _s2_hit_state_T_6 = mux(_s2_hit_state_T_2, _s2_hit_state_WIRE[2].state, UInt<1>(0h0))
node _s2_hit_state_T_7 = mux(_s2_hit_state_T_3, _s2_hit_state_WIRE[3].state, UInt<1>(0h0))
node _s2_hit_state_T_8 = or(_s2_hit_state_T_4, _s2_hit_state_T_5)
node _s2_hit_state_T_9 = or(_s2_hit_state_T_8, _s2_hit_state_T_6)
node _s2_hit_state_T_10 = or(_s2_hit_state_T_9, _s2_hit_state_T_7)
wire _s2_hit_state_WIRE_2 : UInt<2>
connect _s2_hit_state_WIRE_2, _s2_hit_state_T_10
connect _s2_hit_state_WIRE_1.state, _s2_hit_state_WIRE_2
wire s2_hit_state : { state : UInt<2>}[1]
connect s2_hit_state[0], _s2_hit_state_WIRE_1
node _s2_has_permission_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_has_permission_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_has_permission_r_c_cat_T_2 = or(_s2_has_permission_r_c_cat_T, _s2_has_permission_r_c_cat_T_1)
node _s2_has_permission_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_has_permission_r_c_cat_T_4 = or(_s2_has_permission_r_c_cat_T_2, _s2_has_permission_r_c_cat_T_3)
node _s2_has_permission_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_has_permission_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_has_permission_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_has_permission_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_has_permission_r_c_cat_T_9 = or(_s2_has_permission_r_c_cat_T_5, _s2_has_permission_r_c_cat_T_6)
node _s2_has_permission_r_c_cat_T_10 = or(_s2_has_permission_r_c_cat_T_9, _s2_has_permission_r_c_cat_T_7)
node _s2_has_permission_r_c_cat_T_11 = or(_s2_has_permission_r_c_cat_T_10, _s2_has_permission_r_c_cat_T_8)
node _s2_has_permission_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_has_permission_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_has_permission_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_has_permission_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_has_permission_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_has_permission_r_c_cat_T_17 = or(_s2_has_permission_r_c_cat_T_12, _s2_has_permission_r_c_cat_T_13)
node _s2_has_permission_r_c_cat_T_18 = or(_s2_has_permission_r_c_cat_T_17, _s2_has_permission_r_c_cat_T_14)
node _s2_has_permission_r_c_cat_T_19 = or(_s2_has_permission_r_c_cat_T_18, _s2_has_permission_r_c_cat_T_15)
node _s2_has_permission_r_c_cat_T_20 = or(_s2_has_permission_r_c_cat_T_19, _s2_has_permission_r_c_cat_T_16)
node _s2_has_permission_r_c_cat_T_21 = or(_s2_has_permission_r_c_cat_T_11, _s2_has_permission_r_c_cat_T_20)
node _s2_has_permission_r_c_cat_T_22 = or(_s2_has_permission_r_c_cat_T_4, _s2_has_permission_r_c_cat_T_21)
node _s2_has_permission_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_has_permission_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_has_permission_r_c_cat_T_25 = or(_s2_has_permission_r_c_cat_T_23, _s2_has_permission_r_c_cat_T_24)
node _s2_has_permission_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_has_permission_r_c_cat_T_27 = or(_s2_has_permission_r_c_cat_T_25, _s2_has_permission_r_c_cat_T_26)
node _s2_has_permission_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_has_permission_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_has_permission_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_has_permission_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_has_permission_r_c_cat_T_32 = or(_s2_has_permission_r_c_cat_T_28, _s2_has_permission_r_c_cat_T_29)
node _s2_has_permission_r_c_cat_T_33 = or(_s2_has_permission_r_c_cat_T_32, _s2_has_permission_r_c_cat_T_30)
node _s2_has_permission_r_c_cat_T_34 = or(_s2_has_permission_r_c_cat_T_33, _s2_has_permission_r_c_cat_T_31)
node _s2_has_permission_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_has_permission_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_has_permission_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_has_permission_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_has_permission_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_has_permission_r_c_cat_T_40 = or(_s2_has_permission_r_c_cat_T_35, _s2_has_permission_r_c_cat_T_36)
node _s2_has_permission_r_c_cat_T_41 = or(_s2_has_permission_r_c_cat_T_40, _s2_has_permission_r_c_cat_T_37)
node _s2_has_permission_r_c_cat_T_42 = or(_s2_has_permission_r_c_cat_T_41, _s2_has_permission_r_c_cat_T_38)
node _s2_has_permission_r_c_cat_T_43 = or(_s2_has_permission_r_c_cat_T_42, _s2_has_permission_r_c_cat_T_39)
node _s2_has_permission_r_c_cat_T_44 = or(_s2_has_permission_r_c_cat_T_34, _s2_has_permission_r_c_cat_T_43)
node _s2_has_permission_r_c_cat_T_45 = or(_s2_has_permission_r_c_cat_T_27, _s2_has_permission_r_c_cat_T_44)
node _s2_has_permission_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _s2_has_permission_r_c_cat_T_47 = or(_s2_has_permission_r_c_cat_T_45, _s2_has_permission_r_c_cat_T_46)
node _s2_has_permission_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_has_permission_r_c_cat_T_49 = or(_s2_has_permission_r_c_cat_T_47, _s2_has_permission_r_c_cat_T_48)
node s2_has_permission_r_c = cat(_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49)
node _s2_has_permission_r_T = cat(s2_has_permission_r_c, s2_hit_state[0].state)
node _s2_has_permission_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_2 = cat(_s2_has_permission_r_T_1, UInt<2>(0h3))
node _s2_has_permission_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_4 = cat(_s2_has_permission_r_T_3, UInt<2>(0h2))
node _s2_has_permission_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_6 = cat(_s2_has_permission_r_T_5, UInt<2>(0h1))
node _s2_has_permission_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_8 = cat(_s2_has_permission_r_T_7, UInt<2>(0h3))
node _s2_has_permission_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_10 = cat(_s2_has_permission_r_T_9, UInt<2>(0h2))
node _s2_has_permission_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_12 = cat(_s2_has_permission_r_T_11, UInt<2>(0h3))
node _s2_has_permission_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_14 = cat(_s2_has_permission_r_T_13, UInt<2>(0h2))
node _s2_has_permission_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_16 = cat(_s2_has_permission_r_T_15, UInt<2>(0h0))
node _s2_has_permission_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_18 = cat(_s2_has_permission_r_T_17, UInt<2>(0h1))
node _s2_has_permission_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_20 = cat(_s2_has_permission_r_T_19, UInt<2>(0h0))
node _s2_has_permission_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_22 = cat(_s2_has_permission_r_T_21, UInt<2>(0h1))
node _s2_has_permission_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_24 = cat(_s2_has_permission_r_T_23, UInt<2>(0h0))
node _s2_has_permission_r_T_25 = eq(_s2_has_permission_r_T_24, _s2_has_permission_r_T)
node _s2_has_permission_r_T_26 = mux(_s2_has_permission_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_27 = mux(_s2_has_permission_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _s2_has_permission_r_T_28 = eq(_s2_has_permission_r_T_22, _s2_has_permission_r_T)
node _s2_has_permission_r_T_29 = mux(_s2_has_permission_r_T_28, UInt<1>(0h0), _s2_has_permission_r_T_26)
node _s2_has_permission_r_T_30 = mux(_s2_has_permission_r_T_28, UInt<2>(0h2), _s2_has_permission_r_T_27)
node _s2_has_permission_r_T_31 = eq(_s2_has_permission_r_T_20, _s2_has_permission_r_T)
node _s2_has_permission_r_T_32 = mux(_s2_has_permission_r_T_31, UInt<1>(0h0), _s2_has_permission_r_T_29)
node _s2_has_permission_r_T_33 = mux(_s2_has_permission_r_T_31, UInt<2>(0h1), _s2_has_permission_r_T_30)
node _s2_has_permission_r_T_34 = eq(_s2_has_permission_r_T_18, _s2_has_permission_r_T)
node _s2_has_permission_r_T_35 = mux(_s2_has_permission_r_T_34, UInt<1>(0h0), _s2_has_permission_r_T_32)
node _s2_has_permission_r_T_36 = mux(_s2_has_permission_r_T_34, UInt<2>(0h2), _s2_has_permission_r_T_33)
node _s2_has_permission_r_T_37 = eq(_s2_has_permission_r_T_16, _s2_has_permission_r_T)
node _s2_has_permission_r_T_38 = mux(_s2_has_permission_r_T_37, UInt<1>(0h0), _s2_has_permission_r_T_35)
node _s2_has_permission_r_T_39 = mux(_s2_has_permission_r_T_37, UInt<2>(0h0), _s2_has_permission_r_T_36)
node _s2_has_permission_r_T_40 = eq(_s2_has_permission_r_T_14, _s2_has_permission_r_T)
node _s2_has_permission_r_T_41 = mux(_s2_has_permission_r_T_40, UInt<1>(0h1), _s2_has_permission_r_T_38)
node _s2_has_permission_r_T_42 = mux(_s2_has_permission_r_T_40, UInt<2>(0h3), _s2_has_permission_r_T_39)
node _s2_has_permission_r_T_43 = eq(_s2_has_permission_r_T_12, _s2_has_permission_r_T)
node _s2_has_permission_r_T_44 = mux(_s2_has_permission_r_T_43, UInt<1>(0h1), _s2_has_permission_r_T_41)
node _s2_has_permission_r_T_45 = mux(_s2_has_permission_r_T_43, UInt<2>(0h3), _s2_has_permission_r_T_42)
node _s2_has_permission_r_T_46 = eq(_s2_has_permission_r_T_10, _s2_has_permission_r_T)
node _s2_has_permission_r_T_47 = mux(_s2_has_permission_r_T_46, UInt<1>(0h1), _s2_has_permission_r_T_44)
node _s2_has_permission_r_T_48 = mux(_s2_has_permission_r_T_46, UInt<2>(0h2), _s2_has_permission_r_T_45)
node _s2_has_permission_r_T_49 = eq(_s2_has_permission_r_T_8, _s2_has_permission_r_T)
node _s2_has_permission_r_T_50 = mux(_s2_has_permission_r_T_49, UInt<1>(0h1), _s2_has_permission_r_T_47)
node _s2_has_permission_r_T_51 = mux(_s2_has_permission_r_T_49, UInt<2>(0h3), _s2_has_permission_r_T_48)
node _s2_has_permission_r_T_52 = eq(_s2_has_permission_r_T_6, _s2_has_permission_r_T)
node _s2_has_permission_r_T_53 = mux(_s2_has_permission_r_T_52, UInt<1>(0h1), _s2_has_permission_r_T_50)
node _s2_has_permission_r_T_54 = mux(_s2_has_permission_r_T_52, UInt<2>(0h1), _s2_has_permission_r_T_51)
node _s2_has_permission_r_T_55 = eq(_s2_has_permission_r_T_4, _s2_has_permission_r_T)
node _s2_has_permission_r_T_56 = mux(_s2_has_permission_r_T_55, UInt<1>(0h1), _s2_has_permission_r_T_53)
node _s2_has_permission_r_T_57 = mux(_s2_has_permission_r_T_55, UInt<2>(0h2), _s2_has_permission_r_T_54)
node _s2_has_permission_r_T_58 = eq(_s2_has_permission_r_T_2, _s2_has_permission_r_T)
node s2_has_permission_r_1 = mux(_s2_has_permission_r_T_58, UInt<1>(0h1), _s2_has_permission_r_T_56)
node s2_has_permission_r_2 = mux(_s2_has_permission_r_T_58, UInt<2>(0h3), _s2_has_permission_r_T_57)
wire s2_has_permission_meta : { state : UInt<2>}
connect s2_has_permission_meta.state, s2_has_permission_r_2
wire s2_has_permission : UInt<1>[1]
connect s2_has_permission[0], s2_has_permission_r_1
node _s2_new_hit_state_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_new_hit_state_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_new_hit_state_r_c_cat_T_2 = or(_s2_new_hit_state_r_c_cat_T, _s2_new_hit_state_r_c_cat_T_1)
node _s2_new_hit_state_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_new_hit_state_r_c_cat_T_4 = or(_s2_new_hit_state_r_c_cat_T_2, _s2_new_hit_state_r_c_cat_T_3)
node _s2_new_hit_state_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_new_hit_state_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_new_hit_state_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_new_hit_state_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_new_hit_state_r_c_cat_T_9 = or(_s2_new_hit_state_r_c_cat_T_5, _s2_new_hit_state_r_c_cat_T_6)
node _s2_new_hit_state_r_c_cat_T_10 = or(_s2_new_hit_state_r_c_cat_T_9, _s2_new_hit_state_r_c_cat_T_7)
node _s2_new_hit_state_r_c_cat_T_11 = or(_s2_new_hit_state_r_c_cat_T_10, _s2_new_hit_state_r_c_cat_T_8)
node _s2_new_hit_state_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_new_hit_state_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_new_hit_state_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_new_hit_state_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_new_hit_state_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_new_hit_state_r_c_cat_T_17 = or(_s2_new_hit_state_r_c_cat_T_12, _s2_new_hit_state_r_c_cat_T_13)
node _s2_new_hit_state_r_c_cat_T_18 = or(_s2_new_hit_state_r_c_cat_T_17, _s2_new_hit_state_r_c_cat_T_14)
node _s2_new_hit_state_r_c_cat_T_19 = or(_s2_new_hit_state_r_c_cat_T_18, _s2_new_hit_state_r_c_cat_T_15)
node _s2_new_hit_state_r_c_cat_T_20 = or(_s2_new_hit_state_r_c_cat_T_19, _s2_new_hit_state_r_c_cat_T_16)
node _s2_new_hit_state_r_c_cat_T_21 = or(_s2_new_hit_state_r_c_cat_T_11, _s2_new_hit_state_r_c_cat_T_20)
node _s2_new_hit_state_r_c_cat_T_22 = or(_s2_new_hit_state_r_c_cat_T_4, _s2_new_hit_state_r_c_cat_T_21)
node _s2_new_hit_state_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_new_hit_state_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_new_hit_state_r_c_cat_T_25 = or(_s2_new_hit_state_r_c_cat_T_23, _s2_new_hit_state_r_c_cat_T_24)
node _s2_new_hit_state_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_new_hit_state_r_c_cat_T_27 = or(_s2_new_hit_state_r_c_cat_T_25, _s2_new_hit_state_r_c_cat_T_26)
node _s2_new_hit_state_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_new_hit_state_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_new_hit_state_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_new_hit_state_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_new_hit_state_r_c_cat_T_32 = or(_s2_new_hit_state_r_c_cat_T_28, _s2_new_hit_state_r_c_cat_T_29)
node _s2_new_hit_state_r_c_cat_T_33 = or(_s2_new_hit_state_r_c_cat_T_32, _s2_new_hit_state_r_c_cat_T_30)
node _s2_new_hit_state_r_c_cat_T_34 = or(_s2_new_hit_state_r_c_cat_T_33, _s2_new_hit_state_r_c_cat_T_31)
node _s2_new_hit_state_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_new_hit_state_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_new_hit_state_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_new_hit_state_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_new_hit_state_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_new_hit_state_r_c_cat_T_40 = or(_s2_new_hit_state_r_c_cat_T_35, _s2_new_hit_state_r_c_cat_T_36)
node _s2_new_hit_state_r_c_cat_T_41 = or(_s2_new_hit_state_r_c_cat_T_40, _s2_new_hit_state_r_c_cat_T_37)
node _s2_new_hit_state_r_c_cat_T_42 = or(_s2_new_hit_state_r_c_cat_T_41, _s2_new_hit_state_r_c_cat_T_38)
node _s2_new_hit_state_r_c_cat_T_43 = or(_s2_new_hit_state_r_c_cat_T_42, _s2_new_hit_state_r_c_cat_T_39)
node _s2_new_hit_state_r_c_cat_T_44 = or(_s2_new_hit_state_r_c_cat_T_34, _s2_new_hit_state_r_c_cat_T_43)
node _s2_new_hit_state_r_c_cat_T_45 = or(_s2_new_hit_state_r_c_cat_T_27, _s2_new_hit_state_r_c_cat_T_44)
node _s2_new_hit_state_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _s2_new_hit_state_r_c_cat_T_47 = or(_s2_new_hit_state_r_c_cat_T_45, _s2_new_hit_state_r_c_cat_T_46)
node _s2_new_hit_state_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_new_hit_state_r_c_cat_T_49 = or(_s2_new_hit_state_r_c_cat_T_47, _s2_new_hit_state_r_c_cat_T_48)
node s2_new_hit_state_r_c = cat(_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49)
node _s2_new_hit_state_r_T = cat(s2_new_hit_state_r_c, s2_hit_state[0].state)
node _s2_new_hit_state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_2 = cat(_s2_new_hit_state_r_T_1, UInt<2>(0h3))
node _s2_new_hit_state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_4 = cat(_s2_new_hit_state_r_T_3, UInt<2>(0h2))
node _s2_new_hit_state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_6 = cat(_s2_new_hit_state_r_T_5, UInt<2>(0h1))
node _s2_new_hit_state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_8 = cat(_s2_new_hit_state_r_T_7, UInt<2>(0h3))
node _s2_new_hit_state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_10 = cat(_s2_new_hit_state_r_T_9, UInt<2>(0h2))
node _s2_new_hit_state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_12 = cat(_s2_new_hit_state_r_T_11, UInt<2>(0h3))
node _s2_new_hit_state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_14 = cat(_s2_new_hit_state_r_T_13, UInt<2>(0h2))
node _s2_new_hit_state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_16 = cat(_s2_new_hit_state_r_T_15, UInt<2>(0h0))
node _s2_new_hit_state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_18 = cat(_s2_new_hit_state_r_T_17, UInt<2>(0h1))
node _s2_new_hit_state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_20 = cat(_s2_new_hit_state_r_T_19, UInt<2>(0h0))
node _s2_new_hit_state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_22 = cat(_s2_new_hit_state_r_T_21, UInt<2>(0h1))
node _s2_new_hit_state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_24 = cat(_s2_new_hit_state_r_T_23, UInt<2>(0h0))
node _s2_new_hit_state_r_T_25 = eq(_s2_new_hit_state_r_T_24, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_26 = mux(_s2_new_hit_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_27 = mux(_s2_new_hit_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _s2_new_hit_state_r_T_28 = eq(_s2_new_hit_state_r_T_22, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_29 = mux(_s2_new_hit_state_r_T_28, UInt<1>(0h0), _s2_new_hit_state_r_T_26)
node _s2_new_hit_state_r_T_30 = mux(_s2_new_hit_state_r_T_28, UInt<2>(0h2), _s2_new_hit_state_r_T_27)
node _s2_new_hit_state_r_T_31 = eq(_s2_new_hit_state_r_T_20, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_32 = mux(_s2_new_hit_state_r_T_31, UInt<1>(0h0), _s2_new_hit_state_r_T_29)
node _s2_new_hit_state_r_T_33 = mux(_s2_new_hit_state_r_T_31, UInt<2>(0h1), _s2_new_hit_state_r_T_30)
node _s2_new_hit_state_r_T_34 = eq(_s2_new_hit_state_r_T_18, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_35 = mux(_s2_new_hit_state_r_T_34, UInt<1>(0h0), _s2_new_hit_state_r_T_32)
node _s2_new_hit_state_r_T_36 = mux(_s2_new_hit_state_r_T_34, UInt<2>(0h2), _s2_new_hit_state_r_T_33)
node _s2_new_hit_state_r_T_37 = eq(_s2_new_hit_state_r_T_16, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_38 = mux(_s2_new_hit_state_r_T_37, UInt<1>(0h0), _s2_new_hit_state_r_T_35)
node _s2_new_hit_state_r_T_39 = mux(_s2_new_hit_state_r_T_37, UInt<2>(0h0), _s2_new_hit_state_r_T_36)
node _s2_new_hit_state_r_T_40 = eq(_s2_new_hit_state_r_T_14, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_41 = mux(_s2_new_hit_state_r_T_40, UInt<1>(0h1), _s2_new_hit_state_r_T_38)
node _s2_new_hit_state_r_T_42 = mux(_s2_new_hit_state_r_T_40, UInt<2>(0h3), _s2_new_hit_state_r_T_39)
node _s2_new_hit_state_r_T_43 = eq(_s2_new_hit_state_r_T_12, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_44 = mux(_s2_new_hit_state_r_T_43, UInt<1>(0h1), _s2_new_hit_state_r_T_41)
node _s2_new_hit_state_r_T_45 = mux(_s2_new_hit_state_r_T_43, UInt<2>(0h3), _s2_new_hit_state_r_T_42)
node _s2_new_hit_state_r_T_46 = eq(_s2_new_hit_state_r_T_10, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_47 = mux(_s2_new_hit_state_r_T_46, UInt<1>(0h1), _s2_new_hit_state_r_T_44)
node _s2_new_hit_state_r_T_48 = mux(_s2_new_hit_state_r_T_46, UInt<2>(0h2), _s2_new_hit_state_r_T_45)
node _s2_new_hit_state_r_T_49 = eq(_s2_new_hit_state_r_T_8, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_50 = mux(_s2_new_hit_state_r_T_49, UInt<1>(0h1), _s2_new_hit_state_r_T_47)
node _s2_new_hit_state_r_T_51 = mux(_s2_new_hit_state_r_T_49, UInt<2>(0h3), _s2_new_hit_state_r_T_48)
node _s2_new_hit_state_r_T_52 = eq(_s2_new_hit_state_r_T_6, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_53 = mux(_s2_new_hit_state_r_T_52, UInt<1>(0h1), _s2_new_hit_state_r_T_50)
node _s2_new_hit_state_r_T_54 = mux(_s2_new_hit_state_r_T_52, UInt<2>(0h1), _s2_new_hit_state_r_T_51)
node _s2_new_hit_state_r_T_55 = eq(_s2_new_hit_state_r_T_4, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_56 = mux(_s2_new_hit_state_r_T_55, UInt<1>(0h1), _s2_new_hit_state_r_T_53)
node _s2_new_hit_state_r_T_57 = mux(_s2_new_hit_state_r_T_55, UInt<2>(0h2), _s2_new_hit_state_r_T_54)
node _s2_new_hit_state_r_T_58 = eq(_s2_new_hit_state_r_T_2, _s2_new_hit_state_r_T)
node s2_new_hit_state_r_1 = mux(_s2_new_hit_state_r_T_58, UInt<1>(0h1), _s2_new_hit_state_r_T_56)
node s2_new_hit_state_r_2 = mux(_s2_new_hit_state_r_T_58, UInt<2>(0h3), _s2_new_hit_state_r_T_57)
wire s2_new_hit_state_meta : { state : UInt<2>}
connect s2_new_hit_state_meta.state, s2_new_hit_state_r_2
wire s2_new_hit_state : { state : UInt<2>}[1]
connect s2_new_hit_state[0], s2_new_hit_state_meta
node _s2_hit_T = and(s2_tag_match_0, s2_has_permission[0])
node _s2_hit_T_1 = eq(s2_hit_state[0].state, s2_new_hit_state[0].state)
node _s2_hit_T_2 = and(_s2_hit_T, _s2_hit_T_1)
node _s2_hit_T_3 = eq(mshrs.io.block_hit[0], UInt<1>(0h0))
node _s2_hit_T_4 = and(_s2_hit_T_2, _s2_hit_T_3)
node _s2_hit_T_5 = eq(s2_type, UInt<3>(0h0))
node _s2_hit_T_6 = eq(s2_type, UInt<3>(0h2))
node _s2_hit_T_7 = or(_s2_hit_T_5, _s2_hit_T_6)
node _s2_hit_T_8 = or(_s2_hit_T_4, _s2_hit_T_7)
wire s2_hit : UInt<1>[1]
connect s2_hit[0], _s2_hit_T_8
wire s2_nack : UInt<1>[1]
node _T_16 = eq(s2_type, UInt<3>(0h0))
node _T_17 = eq(s2_hit[0], UInt<1>(0h0))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed: Replays should always hit\n at dcache.scala:689 assert(!(s2_type === t_replay && !s2_hit(0)), \"Replays should always hit\")\n") : printf_2
assert(clock, _T_19, UInt<1>(0h1), "") : assert_2
node _T_23 = eq(s2_type, UInt<3>(0h2))
node _T_24 = eq(s2_hit[0], UInt<1>(0h0))
node _T_25 = and(_T_23, _T_24)
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed: Writeback should always see data hit\n at dcache.scala:690 assert(!(s2_type === t_wb && !s2_hit(0)), \"Writeback should always see data hit\")\n") : printf_3
assert(clock, _T_26, UInt<1>(0h1), "") : assert_3
reg s2_wb_idx_matches : UInt<1>[1], clock
connect s2_wb_idx_matches, s1_wb_idx_matches
regreset debug_sc_fail_addr : UInt, clock, reset, UInt<1>(0h0)
regreset debug_sc_fail_cnt : UInt<8>, clock, reset, UInt<8>(0h0)
regreset lrsc_count : UInt<7>, clock, reset, UInt<7>(0h0)
node lrsc_valid = gt(lrsc_count, UInt<2>(0h3))
reg lrsc_addr : UInt, clock
node _s2_lr_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
reg s2_lr_REG : UInt<1>, clock
connect s2_lr_REG, s1_nack_0
node _s2_lr_T_1 = eq(s2_lr_REG, UInt<1>(0h0))
node _s2_lr_T_2 = eq(s2_type, UInt<3>(0h0))
node _s2_lr_T_3 = or(_s2_lr_T_1, _s2_lr_T_2)
node s2_lr = and(_s2_lr_T, _s2_lr_T_3)
node _s2_sc_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
reg s2_sc_REG : UInt<1>, clock
connect s2_sc_REG, s1_nack_0
node _s2_sc_T_1 = eq(s2_sc_REG, UInt<1>(0h0))
node _s2_sc_T_2 = eq(s2_type, UInt<3>(0h0))
node _s2_sc_T_3 = or(_s2_sc_T_1, _s2_sc_T_2)
node s2_sc = and(_s2_sc_T, _s2_sc_T_3)
node _s2_lrsc_addr_match_T = shr(s2_req[0].addr, 6)
node _s2_lrsc_addr_match_T_1 = eq(lrsc_addr, _s2_lrsc_addr_match_T)
node _s2_lrsc_addr_match_T_2 = and(lrsc_valid, _s2_lrsc_addr_match_T_1)
wire s2_lrsc_addr_match : UInt<1>[1]
connect s2_lrsc_addr_match[0], _s2_lrsc_addr_match_T_2
node _s2_sc_fail_T = eq(s2_lrsc_addr_match[0], UInt<1>(0h0))
node s2_sc_fail = and(s2_sc, _s2_sc_fail_T)
node _T_30 = gt(lrsc_count, UInt<1>(0h0))
when _T_30 :
node _lrsc_count_T = sub(lrsc_count, UInt<1>(0h1))
node _lrsc_count_T_1 = tail(_lrsc_count_T, 1)
connect lrsc_count, _lrsc_count_T_1
node _T_31 = eq(s2_type, UInt<3>(0h4))
node _T_32 = and(_T_31, s2_hit[0])
node _T_33 = eq(s2_nack[0], UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(s2_type, UInt<3>(0h0))
node _T_36 = neq(s2_req[0].uop.mem_cmd, UInt<3>(0h5))
node _T_37 = and(_T_35, _T_36)
node _T_38 = or(_T_34, _T_37)
node _T_39 = and(s2_valid[0], _T_38)
when _T_39 :
when s2_lr :
connect lrsc_count, UInt<7>(0h4f)
node _lrsc_addr_T = shr(s2_req[0].addr, 6)
connect lrsc_addr, _lrsc_addr_T
node _T_40 = gt(lrsc_count, UInt<1>(0h0))
when _T_40 :
connect lrsc_count, UInt<1>(0h0)
node _T_41 = eq(s2_type, UInt<3>(0h4))
node _T_42 = and(s2_valid[0], _T_41)
node _T_43 = eq(s2_hit[0], UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = and(s2_has_permission[0], s2_tag_match_0)
node _T_46 = eq(_T_45, UInt<1>(0h0))
node _T_47 = and(_T_44, _T_46)
node _T_48 = and(_T_47, s2_lrsc_addr_match[0])
node _T_49 = eq(s2_nack[0], UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
when _T_50 :
connect lrsc_count, UInt<1>(0h0)
when s2_valid[0] :
node _T_51 = eq(s2_req[0].addr, debug_sc_fail_addr)
when _T_51 :
when s2_sc_fail :
node _debug_sc_fail_cnt_T = add(debug_sc_fail_cnt, UInt<1>(0h1))
node _debug_sc_fail_cnt_T_1 = tail(_debug_sc_fail_cnt_T, 1)
connect debug_sc_fail_cnt, _debug_sc_fail_cnt_T_1
else :
when s2_sc :
connect debug_sc_fail_cnt, UInt<1>(0h0)
else :
when s2_sc_fail :
connect debug_sc_fail_addr, s2_req[0].addr
connect debug_sc_fail_cnt, UInt<1>(0h1)
node _T_52 = lt(debug_sc_fail_cnt, UInt<7>(0h64))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: L1DCache failed too many SCs in a row\n at dcache.scala:741 assert(debug_sc_fail_cnt < 100.U, \"L1DCache failed too many SCs in a row\")\n") : printf_4
assert(clock, _T_52, UInt<1>(0h1), "") : assert_4
wire s2_data : UInt<64>[4][1]
connect s2_data[0][0], data.io.resp[0][0]
connect s2_data[0][1], data.io.resp[0][1]
connect s2_data[0][2], data.io.resp[0][2]
connect s2_data[0][3], data.io.resp[0][3]
node _s2_data_muxed_T = bits(s2_tag_match_way[0], 0, 0)
node _s2_data_muxed_T_1 = bits(s2_tag_match_way[0], 1, 1)
node _s2_data_muxed_T_2 = bits(s2_tag_match_way[0], 2, 2)
node _s2_data_muxed_T_3 = bits(s2_tag_match_way[0], 3, 3)
node _s2_data_muxed_T_4 = mux(_s2_data_muxed_T, s2_data[0][0], UInt<1>(0h0))
node _s2_data_muxed_T_5 = mux(_s2_data_muxed_T_1, s2_data[0][1], UInt<1>(0h0))
node _s2_data_muxed_T_6 = mux(_s2_data_muxed_T_2, s2_data[0][2], UInt<1>(0h0))
node _s2_data_muxed_T_7 = mux(_s2_data_muxed_T_3, s2_data[0][3], UInt<1>(0h0))
node _s2_data_muxed_T_8 = or(_s2_data_muxed_T_4, _s2_data_muxed_T_5)
node _s2_data_muxed_T_9 = or(_s2_data_muxed_T_8, _s2_data_muxed_T_6)
node _s2_data_muxed_T_10 = or(_s2_data_muxed_T_9, _s2_data_muxed_T_7)
wire _s2_data_muxed_WIRE : UInt<64>
connect _s2_data_muxed_WIRE, _s2_data_muxed_T_10
wire s2_data_muxed : UInt<64>[1]
connect s2_data_muxed[0], _s2_data_muxed_WIRE
wire s2_word_idx : UInt<1>[1]
connect s2_word_idx[0], UInt<1>(0h0)
wire replace : UInt<1>
connect replace, UInt<1>(0h0)
inst lfsr_prng of MaxPeriodFibonacciLFSR_1
connect lfsr_prng.clock, clock
connect lfsr_prng.reset, reset
connect lfsr_prng.io.seed.valid, UInt<1>(0h0)
invalidate lfsr_prng.io.seed.bits[0]
invalidate lfsr_prng.io.seed.bits[1]
invalidate lfsr_prng.io.seed.bits[2]
invalidate lfsr_prng.io.seed.bits[3]
invalidate lfsr_prng.io.seed.bits[4]
invalidate lfsr_prng.io.seed.bits[5]
invalidate lfsr_prng.io.seed.bits[6]
invalidate lfsr_prng.io.seed.bits[7]
invalidate lfsr_prng.io.seed.bits[8]
invalidate lfsr_prng.io.seed.bits[9]
invalidate lfsr_prng.io.seed.bits[10]
invalidate lfsr_prng.io.seed.bits[11]
invalidate lfsr_prng.io.seed.bits[12]
invalidate lfsr_prng.io.seed.bits[13]
invalidate lfsr_prng.io.seed.bits[14]
invalidate lfsr_prng.io.seed.bits[15]
connect lfsr_prng.io.increment, replace
node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0])
node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2])
node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo)
node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4])
node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6])
node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo)
node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo)
node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8])
node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10])
node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo)
node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12])
node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14])
node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo)
node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo)
node lfsr = cat(lfsr_hi, lfsr_lo)
node _s1_replaced_way_en_T = bits(lfsr, 1, 0)
node s1_replaced_way_en = dshl(UInt<1>(0h1), _s1_replaced_way_en_T)
node _s2_replaced_way_en_T = bits(lfsr, 1, 0)
reg s2_replaced_way_en_REG : UInt, clock
connect s2_replaced_way_en_REG, _s2_replaced_way_en_T
node s2_replaced_way_en = dshl(UInt<1>(0h1), s2_replaced_way_en_REG)
reg s2_repl_meta_REG : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG, meta_0.io.resp[0]
reg s2_repl_meta_REG_1 : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG_1, meta_0.io.resp[1]
reg s2_repl_meta_REG_2 : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG_2, meta_0.io.resp[2]
reg s2_repl_meta_REG_3 : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG_3, meta_0.io.resp[3]
wire _s2_repl_meta_WIRE : { coh : { state : UInt<2>}, tag : UInt<20>}[4]
connect _s2_repl_meta_WIRE[0], s2_repl_meta_REG
connect _s2_repl_meta_WIRE[1], s2_repl_meta_REG_1
connect _s2_repl_meta_WIRE[2], s2_repl_meta_REG_2
connect _s2_repl_meta_WIRE[3], s2_repl_meta_REG_3
node _s2_repl_meta_T = bits(s2_replaced_way_en, 0, 0)
node _s2_repl_meta_T_1 = bits(s2_replaced_way_en, 1, 1)
node _s2_repl_meta_T_2 = bits(s2_replaced_way_en, 2, 2)
node _s2_repl_meta_T_3 = bits(s2_replaced_way_en, 3, 3)
wire _s2_repl_meta_WIRE_1 : { coh : { state : UInt<2>}, tag : UInt<20>}
node _s2_repl_meta_T_4 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].tag, UInt<1>(0h0))
node _s2_repl_meta_T_5 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].tag, UInt<1>(0h0))
node _s2_repl_meta_T_6 = mux(_s2_repl_meta_T_2, _s2_repl_meta_WIRE[2].tag, UInt<1>(0h0))
node _s2_repl_meta_T_7 = mux(_s2_repl_meta_T_3, _s2_repl_meta_WIRE[3].tag, UInt<1>(0h0))
node _s2_repl_meta_T_8 = or(_s2_repl_meta_T_4, _s2_repl_meta_T_5)
node _s2_repl_meta_T_9 = or(_s2_repl_meta_T_8, _s2_repl_meta_T_6)
node _s2_repl_meta_T_10 = or(_s2_repl_meta_T_9, _s2_repl_meta_T_7)
wire _s2_repl_meta_WIRE_2 : UInt<20>
connect _s2_repl_meta_WIRE_2, _s2_repl_meta_T_10
connect _s2_repl_meta_WIRE_1.tag, _s2_repl_meta_WIRE_2
wire _s2_repl_meta_WIRE_3 : { state : UInt<2>}
node _s2_repl_meta_T_11 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_12 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_13 = mux(_s2_repl_meta_T_2, _s2_repl_meta_WIRE[2].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_14 = mux(_s2_repl_meta_T_3, _s2_repl_meta_WIRE[3].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_15 = or(_s2_repl_meta_T_11, _s2_repl_meta_T_12)
node _s2_repl_meta_T_16 = or(_s2_repl_meta_T_15, _s2_repl_meta_T_13)
node _s2_repl_meta_T_17 = or(_s2_repl_meta_T_16, _s2_repl_meta_T_14)
wire _s2_repl_meta_WIRE_4 : UInt<2>
connect _s2_repl_meta_WIRE_4, _s2_repl_meta_T_17
connect _s2_repl_meta_WIRE_3.state, _s2_repl_meta_WIRE_4
connect _s2_repl_meta_WIRE_1.coh, _s2_repl_meta_WIRE_3
wire s2_repl_meta : { coh : { state : UInt<2>}, tag : UInt<20>}[1]
connect s2_repl_meta[0], _s2_repl_meta_WIRE_1
wire _s2_nack_hit_WIRE : UInt<1>[1]
connect _s2_nack_hit_WIRE[0], s1_nack_0
reg s2_nack_hit : UInt<1>[1], clock
connect s2_nack_hit, _s2_nack_hit_WIRE
node _s2_nack_victim_T = and(s2_valid[0], s2_hit[0])
node _s2_nack_victim_T_1 = and(_s2_nack_victim_T, mshrs.io.secondary_miss[0])
wire s2_nack_victim : UInt<1>[1]
connect s2_nack_victim[0], _s2_nack_victim_T_1
node _s2_nack_miss_T = eq(s2_hit[0], UInt<1>(0h0))
node _s2_nack_miss_T_1 = and(s2_valid[0], _s2_nack_miss_T)
node _s2_nack_miss_T_2 = eq(mshrs.io.req[0].ready, UInt<1>(0h0))
node _s2_nack_miss_T_3 = and(_s2_nack_miss_T_1, _s2_nack_miss_T_2)
wire s2_nack_miss : UInt<1>[1]
connect s2_nack_miss[0], _s2_nack_miss_T_3
reg s2_nack_data_REG : UInt<1>, clock
connect s2_nack_data_REG, data.io.s1_nacks[0]
node _s2_nack_data_T = and(s2_valid[0], s2_nack_data_REG)
wire s2_nack_data : UInt<1>[1]
connect s2_nack_data[0], _s2_nack_data_T
node _s2_nack_wb_T = eq(s2_hit[0], UInt<1>(0h0))
node _s2_nack_wb_T_1 = and(s2_valid[0], _s2_nack_wb_T)
node _s2_nack_wb_T_2 = and(_s2_nack_wb_T_1, s2_wb_idx_matches[0])
wire s2_nack_wb : UInt<1>[1]
connect s2_nack_wb[0], _s2_nack_wb_T_2
node _T_56 = or(s2_nack_miss[0], s2_nack_hit[0])
node _T_57 = or(_T_56, s2_nack_victim[0])
node _T_58 = or(_T_57, s2_nack_data[0])
node _T_59 = or(_T_58, s2_nack_wb[0])
node _T_60 = neq(s2_type, UInt<3>(0h0))
node _T_61 = and(_T_59, _T_60)
wire _WIRE_2 : UInt<1>[1]
connect _WIRE_2[0], _T_61
connect s2_nack, _WIRE_2
node _T_62 = eq(s2_type, UInt<3>(0h0))
node _T_63 = eq(s2_type, UInt<3>(0h2))
node _T_64 = or(_T_62, _T_63)
node _T_65 = and(s2_nack_data[0], _T_64)
node _T_66 = eq(_T_65, UInt<1>(0h0))
node _T_67 = asUInt(reset)
node _T_68 = eq(_T_67, UInt<1>(0h0))
when _T_68 :
node _T_69 = eq(_T_66, UInt<1>(0h0))
when _T_69 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:771 assert(!(s2_nack_data.reduce(_||_) && s2_type.isOneOf(t_replay, t_wb)))\n") : printf_5
assert(clock, _T_66, UInt<1>(0h1), "") : assert_5
reg s2_send_resp_REG : UInt<1>, clock
connect s2_send_resp_REG, s1_send_resp_or_nack[0]
node _s2_send_resp_T = or(s2_nack_hit[0], s2_nack_victim[0])
node _s2_send_resp_T_1 = or(_s2_send_resp_T, s2_nack_data[0])
node _s2_send_resp_T_2 = eq(_s2_send_resp_T_1, UInt<1>(0h0))
node _s2_send_resp_T_3 = eq(s2_type, UInt<3>(0h0))
node _s2_send_resp_T_4 = or(_s2_send_resp_T_2, _s2_send_resp_T_3)
node _s2_send_resp_T_5 = and(s2_send_resp_REG, _s2_send_resp_T_4)
node _s2_send_resp_T_6 = and(_s2_send_resp_T_5, s2_hit[0])
node _s2_send_resp_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0))
node _s2_send_resp_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10))
node _s2_send_resp_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_send_resp_T_10 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_send_resp_T_11 = or(_s2_send_resp_T_7, _s2_send_resp_T_8)
node _s2_send_resp_T_12 = or(_s2_send_resp_T_11, _s2_send_resp_T_9)
node _s2_send_resp_T_13 = or(_s2_send_resp_T_12, _s2_send_resp_T_10)
node _s2_send_resp_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_send_resp_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_send_resp_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_send_resp_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_send_resp_T_18 = or(_s2_send_resp_T_14, _s2_send_resp_T_15)
node _s2_send_resp_T_19 = or(_s2_send_resp_T_18, _s2_send_resp_T_16)
node _s2_send_resp_T_20 = or(_s2_send_resp_T_19, _s2_send_resp_T_17)
node _s2_send_resp_T_21 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_send_resp_T_22 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_send_resp_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_send_resp_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_send_resp_T_25 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_send_resp_T_26 = or(_s2_send_resp_T_21, _s2_send_resp_T_22)
node _s2_send_resp_T_27 = or(_s2_send_resp_T_26, _s2_send_resp_T_23)
node _s2_send_resp_T_28 = or(_s2_send_resp_T_27, _s2_send_resp_T_24)
node _s2_send_resp_T_29 = or(_s2_send_resp_T_28, _s2_send_resp_T_25)
node _s2_send_resp_T_30 = or(_s2_send_resp_T_20, _s2_send_resp_T_29)
node _s2_send_resp_T_31 = or(_s2_send_resp_T_13, _s2_send_resp_T_30)
node _s2_send_resp_T_32 = and(_s2_send_resp_T_6, _s2_send_resp_T_31)
wire s2_send_resp : UInt<1>[1]
connect s2_send_resp[0], _s2_send_resp_T_32
reg s2_send_store_ack_REG : UInt<1>, clock
connect s2_send_store_ack_REG, s1_send_resp_or_nack[0]
node _s2_send_store_ack_T = eq(s2_nack[0], UInt<1>(0h0))
node _s2_send_store_ack_T_1 = and(s2_send_store_ack_REG, _s2_send_store_ack_T)
node _s2_send_store_ack_T_2 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_send_store_ack_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_send_store_ack_T_4 = or(_s2_send_store_ack_T_2, _s2_send_store_ack_T_3)
node _s2_send_store_ack_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_send_store_ack_T_6 = or(_s2_send_store_ack_T_4, _s2_send_store_ack_T_5)
node _s2_send_store_ack_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_send_store_ack_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_send_store_ack_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_send_store_ack_T_10 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_send_store_ack_T_11 = or(_s2_send_store_ack_T_7, _s2_send_store_ack_T_8)
node _s2_send_store_ack_T_12 = or(_s2_send_store_ack_T_11, _s2_send_store_ack_T_9)
node _s2_send_store_ack_T_13 = or(_s2_send_store_ack_T_12, _s2_send_store_ack_T_10)
node _s2_send_store_ack_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_send_store_ack_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_send_store_ack_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_send_store_ack_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_send_store_ack_T_18 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_send_store_ack_T_19 = or(_s2_send_store_ack_T_14, _s2_send_store_ack_T_15)
node _s2_send_store_ack_T_20 = or(_s2_send_store_ack_T_19, _s2_send_store_ack_T_16)
node _s2_send_store_ack_T_21 = or(_s2_send_store_ack_T_20, _s2_send_store_ack_T_17)
node _s2_send_store_ack_T_22 = or(_s2_send_store_ack_T_21, _s2_send_store_ack_T_18)
node _s2_send_store_ack_T_23 = or(_s2_send_store_ack_T_13, _s2_send_store_ack_T_22)
node _s2_send_store_ack_T_24 = or(_s2_send_store_ack_T_6, _s2_send_store_ack_T_23)
node _s2_send_store_ack_T_25 = and(_s2_send_store_ack_T_1, _s2_send_store_ack_T_24)
node _s2_send_store_ack_T_26 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid)
node _s2_send_store_ack_T_27 = or(s2_hit[0], _s2_send_store_ack_T_26)
node _s2_send_store_ack_T_28 = and(_s2_send_store_ack_T_25, _s2_send_store_ack_T_27)
wire s2_send_store_ack : UInt<1>[1]
connect s2_send_store_ack[0], _s2_send_store_ack_T_28
reg s2_send_nack_REG : UInt<1>, clock
connect s2_send_nack_REG, s1_send_resp_or_nack[0]
node _s2_send_nack_T = and(s2_send_nack_REG, s2_nack[0])
wire s2_send_nack : UInt<1>[1]
connect s2_send_nack[0], _s2_send_nack_T
node _T_70 = and(s2_send_resp[0], s2_send_nack[0])
node _T_71 = eq(_T_70, UInt<1>(0h0))
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(_T_71, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:782 assert(!(s2_send_resp(w) && s2_send_nack(w)))\n") : printf_6
assert(clock, _T_71, UInt<1>(0h1), "") : assert_6
node _s2_store_failed_T = and(s2_valid[0], s2_nack[0])
node _s2_store_failed_T_1 = and(_s2_store_failed_T, s2_send_nack[0])
node _s2_store_failed_T_2 = and(_s2_store_failed_T_1, s2_req[0].uop.uses_stq)
connect s2_store_failed, _s2_store_failed_T_2
node _mshrs_io_req_0_valid_T = eq(s2_hit[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_1 = and(s2_valid[0], _mshrs_io_req_0_valid_T)
node _mshrs_io_req_0_valid_T_2 = eq(s2_nack_hit[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_3 = and(_mshrs_io_req_0_valid_T_1, _mshrs_io_req_0_valid_T_2)
node _mshrs_io_req_0_valid_T_4 = eq(s2_nack_victim[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_5 = and(_mshrs_io_req_0_valid_T_3, _mshrs_io_req_0_valid_T_4)
node _mshrs_io_req_0_valid_T_6 = eq(s2_nack_data[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_7 = and(_mshrs_io_req_0_valid_T_5, _mshrs_io_req_0_valid_T_6)
node _mshrs_io_req_0_valid_T_8 = eq(s2_nack_wb[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_9 = and(_mshrs_io_req_0_valid_T_7, _mshrs_io_req_0_valid_T_8)
node _mshrs_io_req_0_valid_T_10 = eq(s2_type, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_11 = eq(s2_type, UInt<3>(0h5))
node _mshrs_io_req_0_valid_T_12 = or(_mshrs_io_req_0_valid_T_10, _mshrs_io_req_0_valid_T_11)
node _mshrs_io_req_0_valid_T_13 = and(_mshrs_io_req_0_valid_T_9, _mshrs_io_req_0_valid_T_12)
node _mshrs_io_req_0_valid_T_14 = and(io.lsu.exception, s2_req[0].uop.uses_ldq)
node _mshrs_io_req_0_valid_T_15 = eq(_mshrs_io_req_0_valid_T_14, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_16 = and(_mshrs_io_req_0_valid_T_13, _mshrs_io_req_0_valid_T_15)
node _mshrs_io_req_0_valid_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h2))
node _mshrs_io_req_0_valid_T_18 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _mshrs_io_req_0_valid_T_19 = or(_mshrs_io_req_0_valid_T_17, _mshrs_io_req_0_valid_T_18)
node _mshrs_io_req_0_valid_T_20 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_21 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10))
node _mshrs_io_req_0_valid_T_22 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _mshrs_io_req_0_valid_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _mshrs_io_req_0_valid_T_24 = or(_mshrs_io_req_0_valid_T_20, _mshrs_io_req_0_valid_T_21)
node _mshrs_io_req_0_valid_T_25 = or(_mshrs_io_req_0_valid_T_24, _mshrs_io_req_0_valid_T_22)
node _mshrs_io_req_0_valid_T_26 = or(_mshrs_io_req_0_valid_T_25, _mshrs_io_req_0_valid_T_23)
node _mshrs_io_req_0_valid_T_27 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _mshrs_io_req_0_valid_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _mshrs_io_req_0_valid_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _mshrs_io_req_0_valid_T_31 = or(_mshrs_io_req_0_valid_T_27, _mshrs_io_req_0_valid_T_28)
node _mshrs_io_req_0_valid_T_32 = or(_mshrs_io_req_0_valid_T_31, _mshrs_io_req_0_valid_T_29)
node _mshrs_io_req_0_valid_T_33 = or(_mshrs_io_req_0_valid_T_32, _mshrs_io_req_0_valid_T_30)
node _mshrs_io_req_0_valid_T_34 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _mshrs_io_req_0_valid_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _mshrs_io_req_0_valid_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _mshrs_io_req_0_valid_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _mshrs_io_req_0_valid_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _mshrs_io_req_0_valid_T_39 = or(_mshrs_io_req_0_valid_T_34, _mshrs_io_req_0_valid_T_35)
node _mshrs_io_req_0_valid_T_40 = or(_mshrs_io_req_0_valid_T_39, _mshrs_io_req_0_valid_T_36)
node _mshrs_io_req_0_valid_T_41 = or(_mshrs_io_req_0_valid_T_40, _mshrs_io_req_0_valid_T_37)
node _mshrs_io_req_0_valid_T_42 = or(_mshrs_io_req_0_valid_T_41, _mshrs_io_req_0_valid_T_38)
node _mshrs_io_req_0_valid_T_43 = or(_mshrs_io_req_0_valid_T_33, _mshrs_io_req_0_valid_T_42)
node _mshrs_io_req_0_valid_T_44 = or(_mshrs_io_req_0_valid_T_26, _mshrs_io_req_0_valid_T_43)
node _mshrs_io_req_0_valid_T_45 = or(_mshrs_io_req_0_valid_T_19, _mshrs_io_req_0_valid_T_44)
node _mshrs_io_req_0_valid_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _mshrs_io_req_0_valid_T_47 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _mshrs_io_req_0_valid_T_48 = or(_mshrs_io_req_0_valid_T_46, _mshrs_io_req_0_valid_T_47)
node _mshrs_io_req_0_valid_T_49 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _mshrs_io_req_0_valid_T_50 = or(_mshrs_io_req_0_valid_T_48, _mshrs_io_req_0_valid_T_49)
node _mshrs_io_req_0_valid_T_51 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_52 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _mshrs_io_req_0_valid_T_53 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _mshrs_io_req_0_valid_T_54 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _mshrs_io_req_0_valid_T_55 = or(_mshrs_io_req_0_valid_T_51, _mshrs_io_req_0_valid_T_52)
node _mshrs_io_req_0_valid_T_56 = or(_mshrs_io_req_0_valid_T_55, _mshrs_io_req_0_valid_T_53)
node _mshrs_io_req_0_valid_T_57 = or(_mshrs_io_req_0_valid_T_56, _mshrs_io_req_0_valid_T_54)
node _mshrs_io_req_0_valid_T_58 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _mshrs_io_req_0_valid_T_59 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _mshrs_io_req_0_valid_T_60 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _mshrs_io_req_0_valid_T_61 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _mshrs_io_req_0_valid_T_62 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _mshrs_io_req_0_valid_T_63 = or(_mshrs_io_req_0_valid_T_58, _mshrs_io_req_0_valid_T_59)
node _mshrs_io_req_0_valid_T_64 = or(_mshrs_io_req_0_valid_T_63, _mshrs_io_req_0_valid_T_60)
node _mshrs_io_req_0_valid_T_65 = or(_mshrs_io_req_0_valid_T_64, _mshrs_io_req_0_valid_T_61)
node _mshrs_io_req_0_valid_T_66 = or(_mshrs_io_req_0_valid_T_65, _mshrs_io_req_0_valid_T_62)
node _mshrs_io_req_0_valid_T_67 = or(_mshrs_io_req_0_valid_T_57, _mshrs_io_req_0_valid_T_66)
node _mshrs_io_req_0_valid_T_68 = or(_mshrs_io_req_0_valid_T_50, _mshrs_io_req_0_valid_T_67)
node _mshrs_io_req_0_valid_T_69 = or(_mshrs_io_req_0_valid_T_45, _mshrs_io_req_0_valid_T_68)
node _mshrs_io_req_0_valid_T_70 = and(_mshrs_io_req_0_valid_T_16, _mshrs_io_req_0_valid_T_69)
connect mshrs.io.req[0].valid, _mshrs_io_req_0_valid_T_70
node _T_75 = eq(s2_type, UInt<3>(0h0))
node _T_76 = and(mshrs.io.req[0].valid, _T_75)
node _T_77 = eq(_T_76, UInt<1>(0h0))
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(_T_77, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: Replays should not need to go back into MSHRs\n at dcache.scala:802 assert(!(mshrs.io.req(w).valid && s2_type === t_replay), \"Replays should not need to go back into MSHRs\")\n") : printf_7
assert(clock, _T_77, UInt<1>(0h1), "") : assert_7
invalidate mshrs.io.req[0].bits.sdq_id
invalidate mshrs.io.req[0].bits.way_en
invalidate mshrs.io.req[0].bits.old_meta.tag
invalidate mshrs.io.req[0].bits.old_meta.coh.state
invalidate mshrs.io.req[0].bits.tag_match
invalidate mshrs.io.req[0].bits.is_hella
invalidate mshrs.io.req[0].bits.data
invalidate mshrs.io.req[0].bits.addr
invalidate mshrs.io.req[0].bits.uop.debug_tsrc
invalidate mshrs.io.req[0].bits.uop.debug_fsrc
invalidate mshrs.io.req[0].bits.uop.bp_xcpt_if
invalidate mshrs.io.req[0].bits.uop.bp_debug_if
invalidate mshrs.io.req[0].bits.uop.xcpt_ma_if
invalidate mshrs.io.req[0].bits.uop.xcpt_ae_if
invalidate mshrs.io.req[0].bits.uop.xcpt_pf_if
invalidate mshrs.io.req[0].bits.uop.fp_typ
invalidate mshrs.io.req[0].bits.uop.fp_rm
invalidate mshrs.io.req[0].bits.uop.fp_val
invalidate mshrs.io.req[0].bits.uop.fcn_op
invalidate mshrs.io.req[0].bits.uop.fcn_dw
invalidate mshrs.io.req[0].bits.uop.frs3_en
invalidate mshrs.io.req[0].bits.uop.lrs2_rtype
invalidate mshrs.io.req[0].bits.uop.lrs1_rtype
invalidate mshrs.io.req[0].bits.uop.dst_rtype
invalidate mshrs.io.req[0].bits.uop.lrs3
invalidate mshrs.io.req[0].bits.uop.lrs2
invalidate mshrs.io.req[0].bits.uop.lrs1
invalidate mshrs.io.req[0].bits.uop.ldst
invalidate mshrs.io.req[0].bits.uop.ldst_is_rs1
invalidate mshrs.io.req[0].bits.uop.csr_cmd
invalidate mshrs.io.req[0].bits.uop.flush_on_commit
invalidate mshrs.io.req[0].bits.uop.is_unique
invalidate mshrs.io.req[0].bits.uop.uses_stq
invalidate mshrs.io.req[0].bits.uop.uses_ldq
invalidate mshrs.io.req[0].bits.uop.mem_signed
invalidate mshrs.io.req[0].bits.uop.mem_size
invalidate mshrs.io.req[0].bits.uop.mem_cmd
invalidate mshrs.io.req[0].bits.uop.exc_cause
invalidate mshrs.io.req[0].bits.uop.exception
invalidate mshrs.io.req[0].bits.uop.stale_pdst
invalidate mshrs.io.req[0].bits.uop.ppred_busy
invalidate mshrs.io.req[0].bits.uop.prs3_busy
invalidate mshrs.io.req[0].bits.uop.prs2_busy
invalidate mshrs.io.req[0].bits.uop.prs1_busy
invalidate mshrs.io.req[0].bits.uop.ppred
invalidate mshrs.io.req[0].bits.uop.prs3
invalidate mshrs.io.req[0].bits.uop.prs2
invalidate mshrs.io.req[0].bits.uop.prs1
invalidate mshrs.io.req[0].bits.uop.pdst
invalidate mshrs.io.req[0].bits.uop.rxq_idx
invalidate mshrs.io.req[0].bits.uop.stq_idx
invalidate mshrs.io.req[0].bits.uop.ldq_idx
invalidate mshrs.io.req[0].bits.uop.rob_idx
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.vec
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.wflags
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.sqrt
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.div
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.fma
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.fastpipe
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.toint
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.fromint
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.typeTagOut
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.typeTagIn
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.swap23
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.swap12
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.ren3
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.ren2
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.ren1
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.wen
invalidate mshrs.io.req[0].bits.uop.fp_ctrl.ldst
invalidate mshrs.io.req[0].bits.uop.op2_sel
invalidate mshrs.io.req[0].bits.uop.op1_sel
invalidate mshrs.io.req[0].bits.uop.imm_packed
invalidate mshrs.io.req[0].bits.uop.pimm
invalidate mshrs.io.req[0].bits.uop.imm_sel
invalidate mshrs.io.req[0].bits.uop.imm_rename
invalidate mshrs.io.req[0].bits.uop.taken
invalidate mshrs.io.req[0].bits.uop.pc_lob
invalidate mshrs.io.req[0].bits.uop.edge_inst
invalidate mshrs.io.req[0].bits.uop.ftq_idx
invalidate mshrs.io.req[0].bits.uop.is_mov
invalidate mshrs.io.req[0].bits.uop.is_rocc
invalidate mshrs.io.req[0].bits.uop.is_sys_pc2epc
invalidate mshrs.io.req[0].bits.uop.is_eret
invalidate mshrs.io.req[0].bits.uop.is_amo
invalidate mshrs.io.req[0].bits.uop.is_sfence
invalidate mshrs.io.req[0].bits.uop.is_fencei
invalidate mshrs.io.req[0].bits.uop.is_fence
invalidate mshrs.io.req[0].bits.uop.is_sfb
invalidate mshrs.io.req[0].bits.uop.br_type
invalidate mshrs.io.req[0].bits.uop.br_tag
invalidate mshrs.io.req[0].bits.uop.br_mask
invalidate mshrs.io.req[0].bits.uop.dis_col_sel
invalidate mshrs.io.req[0].bits.uop.iw_p3_bypass_hint
invalidate mshrs.io.req[0].bits.uop.iw_p2_bypass_hint
invalidate mshrs.io.req[0].bits.uop.iw_p1_bypass_hint
invalidate mshrs.io.req[0].bits.uop.iw_p2_speculative_child
invalidate mshrs.io.req[0].bits.uop.iw_p1_speculative_child
invalidate mshrs.io.req[0].bits.uop.iw_issued_partial_dgen
invalidate mshrs.io.req[0].bits.uop.iw_issued_partial_agen
invalidate mshrs.io.req[0].bits.uop.iw_issued
invalidate mshrs.io.req[0].bits.uop.fu_code[0]
invalidate mshrs.io.req[0].bits.uop.fu_code[1]
invalidate mshrs.io.req[0].bits.uop.fu_code[2]
invalidate mshrs.io.req[0].bits.uop.fu_code[3]
invalidate mshrs.io.req[0].bits.uop.fu_code[4]
invalidate mshrs.io.req[0].bits.uop.fu_code[5]
invalidate mshrs.io.req[0].bits.uop.fu_code[6]
invalidate mshrs.io.req[0].bits.uop.fu_code[7]
invalidate mshrs.io.req[0].bits.uop.fu_code[8]
invalidate mshrs.io.req[0].bits.uop.fu_code[9]
invalidate mshrs.io.req[0].bits.uop.iq_type[0]
invalidate mshrs.io.req[0].bits.uop.iq_type[1]
invalidate mshrs.io.req[0].bits.uop.iq_type[2]
invalidate mshrs.io.req[0].bits.uop.iq_type[3]
invalidate mshrs.io.req[0].bits.uop.debug_pc
invalidate mshrs.io.req[0].bits.uop.is_rvc
invalidate mshrs.io.req[0].bits.uop.debug_inst
invalidate mshrs.io.req[0].bits.uop.inst
connect mshrs.io.req[0].bits.uop.debug_tsrc, s2_req[0].uop.debug_tsrc
connect mshrs.io.req[0].bits.uop.debug_fsrc, s2_req[0].uop.debug_fsrc
connect mshrs.io.req[0].bits.uop.bp_xcpt_if, s2_req[0].uop.bp_xcpt_if
connect mshrs.io.req[0].bits.uop.bp_debug_if, s2_req[0].uop.bp_debug_if
connect mshrs.io.req[0].bits.uop.xcpt_ma_if, s2_req[0].uop.xcpt_ma_if
connect mshrs.io.req[0].bits.uop.xcpt_ae_if, s2_req[0].uop.xcpt_ae_if
connect mshrs.io.req[0].bits.uop.xcpt_pf_if, s2_req[0].uop.xcpt_pf_if
connect mshrs.io.req[0].bits.uop.fp_typ, s2_req[0].uop.fp_typ
connect mshrs.io.req[0].bits.uop.fp_rm, s2_req[0].uop.fp_rm
connect mshrs.io.req[0].bits.uop.fp_val, s2_req[0].uop.fp_val
connect mshrs.io.req[0].bits.uop.fcn_op, s2_req[0].uop.fcn_op
connect mshrs.io.req[0].bits.uop.fcn_dw, s2_req[0].uop.fcn_dw
connect mshrs.io.req[0].bits.uop.frs3_en, s2_req[0].uop.frs3_en
connect mshrs.io.req[0].bits.uop.lrs2_rtype, s2_req[0].uop.lrs2_rtype
connect mshrs.io.req[0].bits.uop.lrs1_rtype, s2_req[0].uop.lrs1_rtype
connect mshrs.io.req[0].bits.uop.dst_rtype, s2_req[0].uop.dst_rtype
connect mshrs.io.req[0].bits.uop.lrs3, s2_req[0].uop.lrs3
connect mshrs.io.req[0].bits.uop.lrs2, s2_req[0].uop.lrs2
connect mshrs.io.req[0].bits.uop.lrs1, s2_req[0].uop.lrs1
connect mshrs.io.req[0].bits.uop.ldst, s2_req[0].uop.ldst
connect mshrs.io.req[0].bits.uop.ldst_is_rs1, s2_req[0].uop.ldst_is_rs1
connect mshrs.io.req[0].bits.uop.csr_cmd, s2_req[0].uop.csr_cmd
connect mshrs.io.req[0].bits.uop.flush_on_commit, s2_req[0].uop.flush_on_commit
connect mshrs.io.req[0].bits.uop.is_unique, s2_req[0].uop.is_unique
connect mshrs.io.req[0].bits.uop.uses_stq, s2_req[0].uop.uses_stq
connect mshrs.io.req[0].bits.uop.uses_ldq, s2_req[0].uop.uses_ldq
connect mshrs.io.req[0].bits.uop.mem_signed, s2_req[0].uop.mem_signed
connect mshrs.io.req[0].bits.uop.mem_size, s2_req[0].uop.mem_size
connect mshrs.io.req[0].bits.uop.mem_cmd, s2_req[0].uop.mem_cmd
connect mshrs.io.req[0].bits.uop.exc_cause, s2_req[0].uop.exc_cause
connect mshrs.io.req[0].bits.uop.exception, s2_req[0].uop.exception
connect mshrs.io.req[0].bits.uop.stale_pdst, s2_req[0].uop.stale_pdst
connect mshrs.io.req[0].bits.uop.ppred_busy, s2_req[0].uop.ppred_busy
connect mshrs.io.req[0].bits.uop.prs3_busy, s2_req[0].uop.prs3_busy
connect mshrs.io.req[0].bits.uop.prs2_busy, s2_req[0].uop.prs2_busy
connect mshrs.io.req[0].bits.uop.prs1_busy, s2_req[0].uop.prs1_busy
connect mshrs.io.req[0].bits.uop.ppred, s2_req[0].uop.ppred
connect mshrs.io.req[0].bits.uop.prs3, s2_req[0].uop.prs3
connect mshrs.io.req[0].bits.uop.prs2, s2_req[0].uop.prs2
connect mshrs.io.req[0].bits.uop.prs1, s2_req[0].uop.prs1
connect mshrs.io.req[0].bits.uop.pdst, s2_req[0].uop.pdst
connect mshrs.io.req[0].bits.uop.rxq_idx, s2_req[0].uop.rxq_idx
connect mshrs.io.req[0].bits.uop.stq_idx, s2_req[0].uop.stq_idx
connect mshrs.io.req[0].bits.uop.ldq_idx, s2_req[0].uop.ldq_idx
connect mshrs.io.req[0].bits.uop.rob_idx, s2_req[0].uop.rob_idx
connect mshrs.io.req[0].bits.uop.fp_ctrl.vec, s2_req[0].uop.fp_ctrl.vec
connect mshrs.io.req[0].bits.uop.fp_ctrl.wflags, s2_req[0].uop.fp_ctrl.wflags
connect mshrs.io.req[0].bits.uop.fp_ctrl.sqrt, s2_req[0].uop.fp_ctrl.sqrt
connect mshrs.io.req[0].bits.uop.fp_ctrl.div, s2_req[0].uop.fp_ctrl.div
connect mshrs.io.req[0].bits.uop.fp_ctrl.fma, s2_req[0].uop.fp_ctrl.fma
connect mshrs.io.req[0].bits.uop.fp_ctrl.fastpipe, s2_req[0].uop.fp_ctrl.fastpipe
connect mshrs.io.req[0].bits.uop.fp_ctrl.toint, s2_req[0].uop.fp_ctrl.toint
connect mshrs.io.req[0].bits.uop.fp_ctrl.fromint, s2_req[0].uop.fp_ctrl.fromint
connect mshrs.io.req[0].bits.uop.fp_ctrl.typeTagOut, s2_req[0].uop.fp_ctrl.typeTagOut
connect mshrs.io.req[0].bits.uop.fp_ctrl.typeTagIn, s2_req[0].uop.fp_ctrl.typeTagIn
connect mshrs.io.req[0].bits.uop.fp_ctrl.swap23, s2_req[0].uop.fp_ctrl.swap23
connect mshrs.io.req[0].bits.uop.fp_ctrl.swap12, s2_req[0].uop.fp_ctrl.swap12
connect mshrs.io.req[0].bits.uop.fp_ctrl.ren3, s2_req[0].uop.fp_ctrl.ren3
connect mshrs.io.req[0].bits.uop.fp_ctrl.ren2, s2_req[0].uop.fp_ctrl.ren2
connect mshrs.io.req[0].bits.uop.fp_ctrl.ren1, s2_req[0].uop.fp_ctrl.ren1
connect mshrs.io.req[0].bits.uop.fp_ctrl.wen, s2_req[0].uop.fp_ctrl.wen
connect mshrs.io.req[0].bits.uop.fp_ctrl.ldst, s2_req[0].uop.fp_ctrl.ldst
connect mshrs.io.req[0].bits.uop.op2_sel, s2_req[0].uop.op2_sel
connect mshrs.io.req[0].bits.uop.op1_sel, s2_req[0].uop.op1_sel
connect mshrs.io.req[0].bits.uop.imm_packed, s2_req[0].uop.imm_packed
connect mshrs.io.req[0].bits.uop.pimm, s2_req[0].uop.pimm
connect mshrs.io.req[0].bits.uop.imm_sel, s2_req[0].uop.imm_sel
connect mshrs.io.req[0].bits.uop.imm_rename, s2_req[0].uop.imm_rename
connect mshrs.io.req[0].bits.uop.taken, s2_req[0].uop.taken
connect mshrs.io.req[0].bits.uop.pc_lob, s2_req[0].uop.pc_lob
connect mshrs.io.req[0].bits.uop.edge_inst, s2_req[0].uop.edge_inst
connect mshrs.io.req[0].bits.uop.ftq_idx, s2_req[0].uop.ftq_idx
connect mshrs.io.req[0].bits.uop.is_mov, s2_req[0].uop.is_mov
connect mshrs.io.req[0].bits.uop.is_rocc, s2_req[0].uop.is_rocc
connect mshrs.io.req[0].bits.uop.is_sys_pc2epc, s2_req[0].uop.is_sys_pc2epc
connect mshrs.io.req[0].bits.uop.is_eret, s2_req[0].uop.is_eret
connect mshrs.io.req[0].bits.uop.is_amo, s2_req[0].uop.is_amo
connect mshrs.io.req[0].bits.uop.is_sfence, s2_req[0].uop.is_sfence
connect mshrs.io.req[0].bits.uop.is_fencei, s2_req[0].uop.is_fencei
connect mshrs.io.req[0].bits.uop.is_fence, s2_req[0].uop.is_fence
connect mshrs.io.req[0].bits.uop.is_sfb, s2_req[0].uop.is_sfb
connect mshrs.io.req[0].bits.uop.br_type, s2_req[0].uop.br_type
connect mshrs.io.req[0].bits.uop.br_tag, s2_req[0].uop.br_tag
connect mshrs.io.req[0].bits.uop.br_mask, s2_req[0].uop.br_mask
connect mshrs.io.req[0].bits.uop.dis_col_sel, s2_req[0].uop.dis_col_sel
connect mshrs.io.req[0].bits.uop.iw_p3_bypass_hint, s2_req[0].uop.iw_p3_bypass_hint
connect mshrs.io.req[0].bits.uop.iw_p2_bypass_hint, s2_req[0].uop.iw_p2_bypass_hint
connect mshrs.io.req[0].bits.uop.iw_p1_bypass_hint, s2_req[0].uop.iw_p1_bypass_hint
connect mshrs.io.req[0].bits.uop.iw_p2_speculative_child, s2_req[0].uop.iw_p2_speculative_child
connect mshrs.io.req[0].bits.uop.iw_p1_speculative_child, s2_req[0].uop.iw_p1_speculative_child
connect mshrs.io.req[0].bits.uop.iw_issued_partial_dgen, s2_req[0].uop.iw_issued_partial_dgen
connect mshrs.io.req[0].bits.uop.iw_issued_partial_agen, s2_req[0].uop.iw_issued_partial_agen
connect mshrs.io.req[0].bits.uop.iw_issued, s2_req[0].uop.iw_issued
connect mshrs.io.req[0].bits.uop.fu_code[0], s2_req[0].uop.fu_code[0]
connect mshrs.io.req[0].bits.uop.fu_code[1], s2_req[0].uop.fu_code[1]
connect mshrs.io.req[0].bits.uop.fu_code[2], s2_req[0].uop.fu_code[2]
connect mshrs.io.req[0].bits.uop.fu_code[3], s2_req[0].uop.fu_code[3]
connect mshrs.io.req[0].bits.uop.fu_code[4], s2_req[0].uop.fu_code[4]
connect mshrs.io.req[0].bits.uop.fu_code[5], s2_req[0].uop.fu_code[5]
connect mshrs.io.req[0].bits.uop.fu_code[6], s2_req[0].uop.fu_code[6]
connect mshrs.io.req[0].bits.uop.fu_code[7], s2_req[0].uop.fu_code[7]
connect mshrs.io.req[0].bits.uop.fu_code[8], s2_req[0].uop.fu_code[8]
connect mshrs.io.req[0].bits.uop.fu_code[9], s2_req[0].uop.fu_code[9]
connect mshrs.io.req[0].bits.uop.iq_type[0], s2_req[0].uop.iq_type[0]
connect mshrs.io.req[0].bits.uop.iq_type[1], s2_req[0].uop.iq_type[1]
connect mshrs.io.req[0].bits.uop.iq_type[2], s2_req[0].uop.iq_type[2]
connect mshrs.io.req[0].bits.uop.iq_type[3], s2_req[0].uop.iq_type[3]
connect mshrs.io.req[0].bits.uop.debug_pc, s2_req[0].uop.debug_pc
connect mshrs.io.req[0].bits.uop.is_rvc, s2_req[0].uop.is_rvc
connect mshrs.io.req[0].bits.uop.debug_inst, s2_req[0].uop.debug_inst
connect mshrs.io.req[0].bits.uop.inst, s2_req[0].uop.inst
connect mshrs.io.req[0].bits.addr, s2_req[0].addr
connect mshrs.io.req[0].bits.tag_match, s2_tag_match_0
wire mshrs_io_req_0_bits_old_meta_meta : { coh : { state : UInt<2>}, tag : UInt<20>}
connect mshrs_io_req_0_bits_old_meta_meta.tag, s2_repl_meta[0].tag
connect mshrs_io_req_0_bits_old_meta_meta.coh, s2_hit_state[0]
node _mshrs_io_req_0_bits_old_meta_T = mux(s2_tag_match_0, mshrs_io_req_0_bits_old_meta_meta, s2_repl_meta[0])
connect mshrs.io.req[0].bits.old_meta.tag, _mshrs_io_req_0_bits_old_meta_T.tag
connect mshrs.io.req[0].bits.old_meta.coh.state, _mshrs_io_req_0_bits_old_meta_T.coh.state
node _mshrs_io_req_0_bits_way_en_T = mux(s2_tag_match_0, s2_tag_match_way[0], s2_replaced_way_en)
connect mshrs.io.req[0].bits.way_en, _mshrs_io_req_0_bits_way_en_T
connect mshrs.io.req[0].bits.data, s2_req[0].data
connect mshrs.io.req[0].bits.is_hella, s2_req[0].is_hella
node _mshrs_io_req_is_probe_0_T = eq(s2_type, UInt<3>(0h1))
node _mshrs_io_req_is_probe_0_T_1 = and(_mshrs_io_req_is_probe_0_T, s2_valid[0])
connect mshrs.io.req_is_probe[0], _mshrs_io_req_is_probe_0_T_1
node _mshrs_io_meta_resp_valid_T = eq(s2_nack_hit[0], UInt<1>(0h0))
node _mshrs_io_meta_resp_valid_T_1 = or(_mshrs_io_meta_resp_valid_T, prober.io.mshr_wb_rdy)
connect mshrs.io.meta_resp.valid, _mshrs_io_meta_resp_valid_T_1
reg mshrs_io_meta_resp_bits_REG : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock
connect mshrs_io_meta_resp_bits_REG, meta_0.io.resp
node _mshrs_io_meta_resp_bits_T = bits(s2_tag_match_way[0], 0, 0)
node _mshrs_io_meta_resp_bits_T_1 = bits(s2_tag_match_way[0], 1, 1)
node _mshrs_io_meta_resp_bits_T_2 = bits(s2_tag_match_way[0], 2, 2)
node _mshrs_io_meta_resp_bits_T_3 = bits(s2_tag_match_way[0], 3, 3)
wire _mshrs_io_meta_resp_bits_WIRE : { coh : { state : UInt<2>}, tag : UInt<20>}
node _mshrs_io_meta_resp_bits_T_4 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_5 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_6 = mux(_mshrs_io_meta_resp_bits_T_2, mshrs_io_meta_resp_bits_REG[2].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_7 = mux(_mshrs_io_meta_resp_bits_T_3, mshrs_io_meta_resp_bits_REG[3].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_8 = or(_mshrs_io_meta_resp_bits_T_4, _mshrs_io_meta_resp_bits_T_5)
node _mshrs_io_meta_resp_bits_T_9 = or(_mshrs_io_meta_resp_bits_T_8, _mshrs_io_meta_resp_bits_T_6)
node _mshrs_io_meta_resp_bits_T_10 = or(_mshrs_io_meta_resp_bits_T_9, _mshrs_io_meta_resp_bits_T_7)
wire _mshrs_io_meta_resp_bits_WIRE_1 : UInt<20>
connect _mshrs_io_meta_resp_bits_WIRE_1, _mshrs_io_meta_resp_bits_T_10
connect _mshrs_io_meta_resp_bits_WIRE.tag, _mshrs_io_meta_resp_bits_WIRE_1
wire _mshrs_io_meta_resp_bits_WIRE_2 : { state : UInt<2>}
node _mshrs_io_meta_resp_bits_T_11 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_12 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_13 = mux(_mshrs_io_meta_resp_bits_T_2, mshrs_io_meta_resp_bits_REG[2].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_14 = mux(_mshrs_io_meta_resp_bits_T_3, mshrs_io_meta_resp_bits_REG[3].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_15 = or(_mshrs_io_meta_resp_bits_T_11, _mshrs_io_meta_resp_bits_T_12)
node _mshrs_io_meta_resp_bits_T_16 = or(_mshrs_io_meta_resp_bits_T_15, _mshrs_io_meta_resp_bits_T_13)
node _mshrs_io_meta_resp_bits_T_17 = or(_mshrs_io_meta_resp_bits_T_16, _mshrs_io_meta_resp_bits_T_14)
wire _mshrs_io_meta_resp_bits_WIRE_3 : UInt<2>
connect _mshrs_io_meta_resp_bits_WIRE_3, _mshrs_io_meta_resp_bits_T_17
connect _mshrs_io_meta_resp_bits_WIRE_2.state, _mshrs_io_meta_resp_bits_WIRE_3
connect _mshrs_io_meta_resp_bits_WIRE.coh, _mshrs_io_meta_resp_bits_WIRE_2
connect mshrs.io.meta_resp.bits.tag, _mshrs_io_meta_resp_bits_WIRE.tag
connect mshrs.io.meta_resp.bits.coh.state, _mshrs_io_meta_resp_bits_WIRE.coh.state
node _T_81 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid)
when _T_81 :
connect replace, UInt<1>(0h1)
connect nodeOut.a.bits, mshrs.io.mem_acquire.bits
connect nodeOut.a.valid, mshrs.io.mem_acquire.valid
connect mshrs.io.mem_acquire.ready, nodeOut.a.ready
node _prober_io_req_valid_T = eq(lrsc_valid, UInt<1>(0h0))
node _prober_io_req_valid_T_1 = and(nodeOut.b.valid, _prober_io_req_valid_T)
connect prober.io.req.valid, _prober_io_req_valid_T_1
node _nodeOut_b_ready_T = eq(lrsc_valid, UInt<1>(0h0))
node _nodeOut_b_ready_T_1 = and(prober.io.req.ready, _nodeOut_b_ready_T)
connect nodeOut.b.ready, _nodeOut_b_ready_T_1
connect prober.io.req.bits.corrupt, nodeOut.b.bits.corrupt
connect prober.io.req.bits.data, nodeOut.b.bits.data
connect prober.io.req.bits.mask, nodeOut.b.bits.mask
connect prober.io.req.bits.address, nodeOut.b.bits.address
connect prober.io.req.bits.source, nodeOut.b.bits.source
connect prober.io.req.bits.size, nodeOut.b.bits.size
connect prober.io.req.bits.param, nodeOut.b.bits.param
connect prober.io.req.bits.opcode, nodeOut.b.bits.opcode
connect prober.io.way_en, s2_tag_match_way[0]
connect prober.io.block_state.state, s2_hit_state[0].state
connect metaWriteArb.io.in[1], prober.io.meta_write
connect prober.io.mshr_rdy, mshrs.io.probe_rdy
node _prober_io_wb_rdy_T = neq(prober.io.meta_write.bits.idx, wb.io.idx.bits)
node _prober_io_wb_rdy_T_1 = eq(wb.io.idx.valid, UInt<1>(0h0))
node _prober_io_wb_rdy_T_2 = or(_prober_io_wb_rdy_T, _prober_io_wb_rdy_T_1)
connect prober.io.wb_rdy, _prober_io_wb_rdy_T_2
connect mshrs.io.prober_state.bits, prober.io.state.bits
connect mshrs.io.prober_state.valid, prober.io.state.valid
node _T_82 = eq(nodeOut.d.bits.source, UInt<2>(0h2))
when _T_82 :
connect nodeOut.d.ready, UInt<1>(0h1)
connect mshrs.io.mem_grant.valid, UInt<1>(0h0)
invalidate mshrs.io.mem_grant.bits.corrupt
invalidate mshrs.io.mem_grant.bits.data
invalidate mshrs.io.mem_grant.bits.denied
invalidate mshrs.io.mem_grant.bits.sink
invalidate mshrs.io.mem_grant.bits.source
invalidate mshrs.io.mem_grant.bits.size
invalidate mshrs.io.mem_grant.bits.param
invalidate mshrs.io.mem_grant.bits.opcode
else :
connect mshrs.io.mem_grant, nodeOut.d
connect dataWriteArb.io.in[1], mshrs.io.refill
connect metaWriteArb.io.in[0], mshrs.io.meta_write
connect nodeOut.e.bits, mshrs.io.mem_finish.bits
connect nodeOut.e.valid, mshrs.io.mem_finish.valid
connect mshrs.io.mem_finish.ready, nodeOut.e.ready
inst wbArb of Arbiter2_WritebackReq_1
connect wbArb.clock, clock
connect wbArb.reset, reset
connect wbArb.io.in[0], prober.io.wb_req
connect wbArb.io.in[1], mshrs.io.wb_req
connect wb.io.req, wbArb.io.out
connect wb.io.data_resp, s2_data_muxed[0]
connect mshrs.io.wb_resp, wb.io.resp
node _wb_io_mem_grant_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _wb_io_mem_grant_T_1 = eq(nodeOut.d.bits.source, UInt<2>(0h2))
node _wb_io_mem_grant_T_2 = and(_wb_io_mem_grant_T, _wb_io_mem_grant_T_1)
connect wb.io.mem_grant, _wb_io_mem_grant_T_2
inst lsu_release_arb of Arbiter2_TLBundleC_a32d64s2k3z4c
connect lsu_release_arb.clock, clock
connect lsu_release_arb.reset, reset
connect io.lsu.release.bits, lsu_release_arb.io.out.bits
connect io.lsu.release.valid, lsu_release_arb.io.out.valid
connect lsu_release_arb.io.out.ready, io.lsu.release.ready
connect lsu_release_arb.io.in[0], wb.io.lsu_release
connect lsu_release_arb.io.in[1], prober.io.lsu_release
node _decode_T = dshl(UInt<12>(0hfff), wb.io.release.bits.size)
node _decode_T_1 = bits(_decode_T, 11, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node opdata = bits(wb.io.release.bits.opcode, 0, 0)
node _T_83 = mux(opdata, decode, UInt<1>(0h0))
node _decode_T_3 = dshl(UInt<12>(0hfff), prober.io.rep.bits.size)
node _decode_T_4 = bits(_decode_T_3, 11, 0)
node _decode_T_5 = not(_decode_T_4)
node decode_1 = shr(_decode_T_5, 3)
node opdata_1 = bits(prober.io.rep.bits.opcode, 0, 0)
node _T_84 = mux(opdata_1, decode_1, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.c.ready)
node _readys_T = cat(prober.io.rep.valid, wb.io.release.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], wb.io.release.valid)
node _winner_T_1 = and(readys[1], prober.io.rep.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_85 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_86 = eq(winner[0], UInt<1>(0h0))
node _T_87 = or(_T_85, _T_86)
node _T_88 = eq(prefixOR_1, UInt<1>(0h0))
node _T_89 = eq(winner[1], UInt<1>(0h0))
node _T_90 = or(_T_88, _T_89)
node _T_91 = and(_T_87, _T_90)
node _T_92 = asUInt(reset)
node _T_93 = eq(_T_92, UInt<1>(0h0))
when _T_93 :
node _T_94 = eq(_T_91, UInt<1>(0h0))
when _T_94 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_8
assert(clock, _T_91, UInt<1>(0h1), "") : assert_8
node _T_95 = or(wb.io.release.valid, prober.io.rep.valid)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = or(winner[0], winner[1])
node _T_98 = or(_T_96, _T_97)
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_9
assert(clock, _T_98, UInt<1>(0h1), "") : assert_9
node maskedBeats_0 = mux(winner[0], _T_83, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_84, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _wb_io_release_ready_T = and(nodeOut.c.ready, allowed[0])
connect wb.io.release.ready, _wb_io_release_ready_T
node _prober_io_rep_ready_T = and(nodeOut.c.ready, allowed[1])
connect prober.io.rep.ready, _prober_io_rep_ready_T
node _nodeOut_c_valid_T = or(wb.io.release.valid, prober.io.rep.valid)
node _nodeOut_c_valid_T_1 = mux(state[0], wb.io.release.valid, UInt<1>(0h0))
node _nodeOut_c_valid_T_2 = mux(state[1], prober.io.rep.valid, UInt<1>(0h0))
node _nodeOut_c_valid_T_3 = or(_nodeOut_c_valid_T_1, _nodeOut_c_valid_T_2)
wire _nodeOut_c_valid_WIRE : UInt<1>
connect _nodeOut_c_valid_WIRE, _nodeOut_c_valid_T_3
node _nodeOut_c_valid_T_4 = mux(idle, _nodeOut_c_valid_T, _nodeOut_c_valid_WIRE)
connect nodeOut.c.valid, _nodeOut_c_valid_T_4
wire _nodeOut_c_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_c_bits_T = mux(muxState[0], wb.io.release.bits.corrupt, UInt<1>(0h0))
node _nodeOut_c_bits_T_1 = mux(muxState[1], prober.io.rep.bits.corrupt, UInt<1>(0h0))
node _nodeOut_c_bits_T_2 = or(_nodeOut_c_bits_T, _nodeOut_c_bits_T_1)
wire _nodeOut_c_bits_WIRE_1 : UInt<1>
connect _nodeOut_c_bits_WIRE_1, _nodeOut_c_bits_T_2
connect _nodeOut_c_bits_WIRE.corrupt, _nodeOut_c_bits_WIRE_1
node _nodeOut_c_bits_T_3 = mux(muxState[0], wb.io.release.bits.data, UInt<1>(0h0))
node _nodeOut_c_bits_T_4 = mux(muxState[1], prober.io.rep.bits.data, UInt<1>(0h0))
node _nodeOut_c_bits_T_5 = or(_nodeOut_c_bits_T_3, _nodeOut_c_bits_T_4)
wire _nodeOut_c_bits_WIRE_2 : UInt<64>
connect _nodeOut_c_bits_WIRE_2, _nodeOut_c_bits_T_5
connect _nodeOut_c_bits_WIRE.data, _nodeOut_c_bits_WIRE_2
wire _nodeOut_c_bits_WIRE_3 : { }
connect _nodeOut_c_bits_WIRE.echo, _nodeOut_c_bits_WIRE_3
wire _nodeOut_c_bits_WIRE_4 : { }
connect _nodeOut_c_bits_WIRE.user, _nodeOut_c_bits_WIRE_4
node _nodeOut_c_bits_T_6 = mux(muxState[0], wb.io.release.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_T_7 = mux(muxState[1], prober.io.rep.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_T_8 = or(_nodeOut_c_bits_T_6, _nodeOut_c_bits_T_7)
wire _nodeOut_c_bits_WIRE_5 : UInt<32>
connect _nodeOut_c_bits_WIRE_5, _nodeOut_c_bits_T_8
connect _nodeOut_c_bits_WIRE.address, _nodeOut_c_bits_WIRE_5
node _nodeOut_c_bits_T_9 = mux(muxState[0], wb.io.release.bits.source, UInt<1>(0h0))
node _nodeOut_c_bits_T_10 = mux(muxState[1], prober.io.rep.bits.source, UInt<1>(0h0))
node _nodeOut_c_bits_T_11 = or(_nodeOut_c_bits_T_9, _nodeOut_c_bits_T_10)
wire _nodeOut_c_bits_WIRE_6 : UInt<2>
connect _nodeOut_c_bits_WIRE_6, _nodeOut_c_bits_T_11
connect _nodeOut_c_bits_WIRE.source, _nodeOut_c_bits_WIRE_6
node _nodeOut_c_bits_T_12 = mux(muxState[0], wb.io.release.bits.size, UInt<1>(0h0))
node _nodeOut_c_bits_T_13 = mux(muxState[1], prober.io.rep.bits.size, UInt<1>(0h0))
node _nodeOut_c_bits_T_14 = or(_nodeOut_c_bits_T_12, _nodeOut_c_bits_T_13)
wire _nodeOut_c_bits_WIRE_7 : UInt<4>
connect _nodeOut_c_bits_WIRE_7, _nodeOut_c_bits_T_14
connect _nodeOut_c_bits_WIRE.size, _nodeOut_c_bits_WIRE_7
node _nodeOut_c_bits_T_15 = mux(muxState[0], wb.io.release.bits.param, UInt<1>(0h0))
node _nodeOut_c_bits_T_16 = mux(muxState[1], prober.io.rep.bits.param, UInt<1>(0h0))
node _nodeOut_c_bits_T_17 = or(_nodeOut_c_bits_T_15, _nodeOut_c_bits_T_16)
wire _nodeOut_c_bits_WIRE_8 : UInt<3>
connect _nodeOut_c_bits_WIRE_8, _nodeOut_c_bits_T_17
connect _nodeOut_c_bits_WIRE.param, _nodeOut_c_bits_WIRE_8
node _nodeOut_c_bits_T_18 = mux(muxState[0], wb.io.release.bits.opcode, UInt<1>(0h0))
node _nodeOut_c_bits_T_19 = mux(muxState[1], prober.io.rep.bits.opcode, UInt<1>(0h0))
node _nodeOut_c_bits_T_20 = or(_nodeOut_c_bits_T_18, _nodeOut_c_bits_T_19)
wire _nodeOut_c_bits_WIRE_9 : UInt<3>
connect _nodeOut_c_bits_WIRE_9, _nodeOut_c_bits_T_20
connect _nodeOut_c_bits_WIRE.opcode, _nodeOut_c_bits_WIRE_9
connect nodeOut.c.bits.corrupt, _nodeOut_c_bits_WIRE.corrupt
connect nodeOut.c.bits.data, _nodeOut_c_bits_WIRE.data
connect nodeOut.c.bits.address, _nodeOut_c_bits_WIRE.address
connect nodeOut.c.bits.source, _nodeOut_c_bits_WIRE.source
connect nodeOut.c.bits.size, _nodeOut_c_bits_WIRE.size
connect nodeOut.c.bits.param, _nodeOut_c_bits_WIRE.param
connect nodeOut.c.bits.opcode, _nodeOut_c_bits_WIRE.opcode
node _io_lsu_perf_release_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _io_lsu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.c.bits.size)
node _io_lsu_perf_release_beats1_decode_T_1 = bits(_io_lsu_perf_release_beats1_decode_T, 11, 0)
node _io_lsu_perf_release_beats1_decode_T_2 = not(_io_lsu_perf_release_beats1_decode_T_1)
node io_lsu_perf_release_beats1_decode = shr(_io_lsu_perf_release_beats1_decode_T_2, 3)
node io_lsu_perf_release_beats1_opdata = bits(nodeOut.c.bits.opcode, 0, 0)
node io_lsu_perf_release_beats1 = mux(io_lsu_perf_release_beats1_opdata, io_lsu_perf_release_beats1_decode, UInt<1>(0h0))
regreset io_lsu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_lsu_perf_release_counter1_T = sub(io_lsu_perf_release_counter, UInt<1>(0h1))
node io_lsu_perf_release_counter1 = tail(_io_lsu_perf_release_counter1_T, 1)
node io_lsu_perf_release_first = eq(io_lsu_perf_release_counter, UInt<1>(0h0))
node _io_lsu_perf_release_last_T = eq(io_lsu_perf_release_counter, UInt<1>(0h1))
node _io_lsu_perf_release_last_T_1 = eq(io_lsu_perf_release_beats1, UInt<1>(0h0))
node io_lsu_perf_release_last = or(_io_lsu_perf_release_last_T, _io_lsu_perf_release_last_T_1)
node io_lsu_perf_release_done = and(io_lsu_perf_release_last, _io_lsu_perf_release_T)
node _io_lsu_perf_release_count_T = not(io_lsu_perf_release_counter1)
node io_lsu_perf_release_count = and(io_lsu_perf_release_beats1, _io_lsu_perf_release_count_T)
when _io_lsu_perf_release_T :
node _io_lsu_perf_release_counter_T = mux(io_lsu_perf_release_first, io_lsu_perf_release_beats1, io_lsu_perf_release_counter1)
connect io_lsu_perf_release_counter, _io_lsu_perf_release_counter_T
connect io.lsu.perf.release, io_lsu_perf_release_done
node _io_lsu_perf_acquire_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _io_lsu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.a.bits.size)
node _io_lsu_perf_acquire_beats1_decode_T_1 = bits(_io_lsu_perf_acquire_beats1_decode_T, 11, 0)
node _io_lsu_perf_acquire_beats1_decode_T_2 = not(_io_lsu_perf_acquire_beats1_decode_T_1)
node io_lsu_perf_acquire_beats1_decode = shr(_io_lsu_perf_acquire_beats1_decode_T_2, 3)
node _io_lsu_perf_acquire_beats1_opdata_T = bits(nodeOut.a.bits.opcode, 2, 2)
node io_lsu_perf_acquire_beats1_opdata = eq(_io_lsu_perf_acquire_beats1_opdata_T, UInt<1>(0h0))
node io_lsu_perf_acquire_beats1 = mux(io_lsu_perf_acquire_beats1_opdata, io_lsu_perf_acquire_beats1_decode, UInt<1>(0h0))
regreset io_lsu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_lsu_perf_acquire_counter1_T = sub(io_lsu_perf_acquire_counter, UInt<1>(0h1))
node io_lsu_perf_acquire_counter1 = tail(_io_lsu_perf_acquire_counter1_T, 1)
node io_lsu_perf_acquire_first = eq(io_lsu_perf_acquire_counter, UInt<1>(0h0))
node _io_lsu_perf_acquire_last_T = eq(io_lsu_perf_acquire_counter, UInt<1>(0h1))
node _io_lsu_perf_acquire_last_T_1 = eq(io_lsu_perf_acquire_beats1, UInt<1>(0h0))
node io_lsu_perf_acquire_last = or(_io_lsu_perf_acquire_last_T, _io_lsu_perf_acquire_last_T_1)
node io_lsu_perf_acquire_done = and(io_lsu_perf_acquire_last, _io_lsu_perf_acquire_T)
node _io_lsu_perf_acquire_count_T = not(io_lsu_perf_acquire_counter1)
node io_lsu_perf_acquire_count = and(io_lsu_perf_acquire_beats1, _io_lsu_perf_acquire_count_T)
when _io_lsu_perf_acquire_T :
node _io_lsu_perf_acquire_counter_T = mux(io_lsu_perf_acquire_first, io_lsu_perf_acquire_beats1, io_lsu_perf_acquire_counter1)
connect io_lsu_perf_acquire_counter, _io_lsu_perf_acquire_counter_T
connect io.lsu.perf.acquire, io_lsu_perf_acquire_done
node _s2_data_word_prebypass_T = cat(s2_word_idx[0], UInt<6>(0h0))
node _s2_data_word_prebypass_T_1 = dshr(s2_data_muxed[0], _s2_data_word_prebypass_T)
wire s2_data_word_prebypass : UInt<64>[1]
connect s2_data_word_prebypass[0], _s2_data_word_prebypass_T_1
wire s2_data_word : UInt[1]
node _T_102 = and(s2_sc, UInt<1>(0h1))
wire size : UInt<2>
connect size, s2_req[0].uop.mem_size
node size_dat_padded = pad(s2_data_word[0], 64)
node _io_lsu_resp_0_valid_T = and(s2_valid[0], s2_send_resp[0])
connect io.lsu.resp[0].valid, _io_lsu_resp_0_valid_T
connect io.lsu.resp[0].bits.uop, s2_req[0].uop
node _io_lsu_resp_0_bits_data_shifted_T = bits(s2_req[0].addr, 2, 2)
node _io_lsu_resp_0_bits_data_shifted_T_1 = bits(s2_data_word[0], 63, 32)
node _io_lsu_resp_0_bits_data_shifted_T_2 = bits(s2_data_word[0], 31, 0)
node io_lsu_resp_0_bits_data_shifted = mux(_io_lsu_resp_0_bits_data_shifted_T, _io_lsu_resp_0_bits_data_shifted_T_1, _io_lsu_resp_0_bits_data_shifted_T_2)
node io_lsu_resp_0_bits_data_doZero = and(UInt<1>(0h0), _T_102)
node io_lsu_resp_0_bits_data_zeroed = mux(io_lsu_resp_0_bits_data_doZero, UInt<1>(0h0), io_lsu_resp_0_bits_data_shifted)
node _io_lsu_resp_0_bits_data_T = eq(size, UInt<2>(0h2))
node _io_lsu_resp_0_bits_data_T_1 = or(_io_lsu_resp_0_bits_data_T, io_lsu_resp_0_bits_data_doZero)
node _io_lsu_resp_0_bits_data_T_2 = bits(io_lsu_resp_0_bits_data_zeroed, 31, 31)
node _io_lsu_resp_0_bits_data_T_3 = and(s2_req[0].uop.mem_signed, _io_lsu_resp_0_bits_data_T_2)
node _io_lsu_resp_0_bits_data_T_4 = mux(_io_lsu_resp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_lsu_resp_0_bits_data_T_5 = bits(s2_data_word[0], 63, 32)
node _io_lsu_resp_0_bits_data_T_6 = mux(_io_lsu_resp_0_bits_data_T_1, _io_lsu_resp_0_bits_data_T_4, _io_lsu_resp_0_bits_data_T_5)
node _io_lsu_resp_0_bits_data_T_7 = cat(_io_lsu_resp_0_bits_data_T_6, io_lsu_resp_0_bits_data_zeroed)
node _io_lsu_resp_0_bits_data_shifted_T_3 = bits(s2_req[0].addr, 1, 1)
node _io_lsu_resp_0_bits_data_shifted_T_4 = bits(_io_lsu_resp_0_bits_data_T_7, 31, 16)
node _io_lsu_resp_0_bits_data_shifted_T_5 = bits(_io_lsu_resp_0_bits_data_T_7, 15, 0)
node io_lsu_resp_0_bits_data_shifted_1 = mux(_io_lsu_resp_0_bits_data_shifted_T_3, _io_lsu_resp_0_bits_data_shifted_T_4, _io_lsu_resp_0_bits_data_shifted_T_5)
node io_lsu_resp_0_bits_data_doZero_1 = and(UInt<1>(0h0), _T_102)
node io_lsu_resp_0_bits_data_zeroed_1 = mux(io_lsu_resp_0_bits_data_doZero_1, UInt<1>(0h0), io_lsu_resp_0_bits_data_shifted_1)
node _io_lsu_resp_0_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_lsu_resp_0_bits_data_T_9 = or(_io_lsu_resp_0_bits_data_T_8, io_lsu_resp_0_bits_data_doZero_1)
node _io_lsu_resp_0_bits_data_T_10 = bits(io_lsu_resp_0_bits_data_zeroed_1, 15, 15)
node _io_lsu_resp_0_bits_data_T_11 = and(s2_req[0].uop.mem_signed, _io_lsu_resp_0_bits_data_T_10)
node _io_lsu_resp_0_bits_data_T_12 = mux(_io_lsu_resp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_lsu_resp_0_bits_data_T_13 = bits(_io_lsu_resp_0_bits_data_T_7, 63, 16)
node _io_lsu_resp_0_bits_data_T_14 = mux(_io_lsu_resp_0_bits_data_T_9, _io_lsu_resp_0_bits_data_T_12, _io_lsu_resp_0_bits_data_T_13)
node _io_lsu_resp_0_bits_data_T_15 = cat(_io_lsu_resp_0_bits_data_T_14, io_lsu_resp_0_bits_data_zeroed_1)
node _io_lsu_resp_0_bits_data_shifted_T_6 = bits(s2_req[0].addr, 0, 0)
node _io_lsu_resp_0_bits_data_shifted_T_7 = bits(_io_lsu_resp_0_bits_data_T_15, 15, 8)
node _io_lsu_resp_0_bits_data_shifted_T_8 = bits(_io_lsu_resp_0_bits_data_T_15, 7, 0)
node io_lsu_resp_0_bits_data_shifted_2 = mux(_io_lsu_resp_0_bits_data_shifted_T_6, _io_lsu_resp_0_bits_data_shifted_T_7, _io_lsu_resp_0_bits_data_shifted_T_8)
node io_lsu_resp_0_bits_data_doZero_2 = and(UInt<1>(0h1), _T_102)
node io_lsu_resp_0_bits_data_zeroed_2 = mux(io_lsu_resp_0_bits_data_doZero_2, UInt<1>(0h0), io_lsu_resp_0_bits_data_shifted_2)
node _io_lsu_resp_0_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_lsu_resp_0_bits_data_T_17 = or(_io_lsu_resp_0_bits_data_T_16, io_lsu_resp_0_bits_data_doZero_2)
node _io_lsu_resp_0_bits_data_T_18 = bits(io_lsu_resp_0_bits_data_zeroed_2, 7, 7)
node _io_lsu_resp_0_bits_data_T_19 = and(s2_req[0].uop.mem_signed, _io_lsu_resp_0_bits_data_T_18)
node _io_lsu_resp_0_bits_data_T_20 = mux(_io_lsu_resp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_lsu_resp_0_bits_data_T_21 = bits(_io_lsu_resp_0_bits_data_T_15, 63, 8)
node _io_lsu_resp_0_bits_data_T_22 = mux(_io_lsu_resp_0_bits_data_T_17, _io_lsu_resp_0_bits_data_T_20, _io_lsu_resp_0_bits_data_T_21)
node _io_lsu_resp_0_bits_data_T_23 = cat(_io_lsu_resp_0_bits_data_T_22, io_lsu_resp_0_bits_data_zeroed_2)
node _io_lsu_resp_0_bits_data_T_24 = or(_io_lsu_resp_0_bits_data_T_23, s2_sc_fail)
connect io.lsu.resp[0].bits.data, _io_lsu_resp_0_bits_data_T_24
connect io.lsu.resp[0].bits.is_hella, s2_req[0].is_hella
node _io_lsu_nack_0_valid_T = and(s2_valid[0], s2_send_nack[0])
connect io.lsu.nack[0].valid, _io_lsu_nack_0_valid_T
connect io.lsu.nack[0].bits, s2_req[0]
node _T_103 = neq(s2_type, UInt<3>(0h4))
node _T_104 = and(io.lsu.nack[0].valid, _T_103)
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_T_105, UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:886 assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))\n") : printf_10
assert(clock, _T_105, UInt<1>(0h1), "") : assert_10
node _io_lsu_store_ack_0_valid_T = and(s2_valid[0], s2_send_store_ack[0])
node _io_lsu_store_ack_0_valid_T_1 = and(_io_lsu_store_ack_0_valid_T, UInt<1>(0h1))
connect io.lsu.store_ack[0].valid, _io_lsu_store_ack_0_valid_T_1
connect io.lsu.store_ack[0].bits, s2_req[0]
connect io.lsu.ll_resp.bits, mshrs.io.resp.bits
connect io.lsu.ll_resp.valid, mshrs.io.resp.valid
connect mshrs.io.resp.ready, io.lsu.ll_resp.ready
wire s3_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}
reg s3_req_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s3_req_REG, s2_req[0]
connect s3_req, s3_req_REG
node _s3_valid_T = and(s2_valid[0], s2_hit[0])
node _s3_valid_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s3_valid_T_2 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s3_valid_T_3 = or(_s3_valid_T_1, _s3_valid_T_2)
node _s3_valid_T_4 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s3_valid_T_5 = or(_s3_valid_T_3, _s3_valid_T_4)
node _s3_valid_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s3_valid_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s3_valid_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s3_valid_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s3_valid_T_10 = or(_s3_valid_T_6, _s3_valid_T_7)
node _s3_valid_T_11 = or(_s3_valid_T_10, _s3_valid_T_8)
node _s3_valid_T_12 = or(_s3_valid_T_11, _s3_valid_T_9)
node _s3_valid_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s3_valid_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s3_valid_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s3_valid_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s3_valid_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s3_valid_T_18 = or(_s3_valid_T_13, _s3_valid_T_14)
node _s3_valid_T_19 = or(_s3_valid_T_18, _s3_valid_T_15)
node _s3_valid_T_20 = or(_s3_valid_T_19, _s3_valid_T_16)
node _s3_valid_T_21 = or(_s3_valid_T_20, _s3_valid_T_17)
node _s3_valid_T_22 = or(_s3_valid_T_12, _s3_valid_T_21)
node _s3_valid_T_23 = or(_s3_valid_T_5, _s3_valid_T_22)
node _s3_valid_T_24 = and(_s3_valid_T, _s3_valid_T_23)
node _s3_valid_T_25 = eq(s2_sc_fail, UInt<1>(0h0))
node _s3_valid_T_26 = and(_s3_valid_T_24, _s3_valid_T_25)
node _s3_valid_T_27 = and(s2_send_nack[0], s2_nack[0])
node _s3_valid_T_28 = eq(_s3_valid_T_27, UInt<1>(0h0))
node _s3_valid_T_29 = and(_s3_valid_T_26, _s3_valid_T_28)
reg s3_valid : UInt<1>, clock
connect s3_valid, _s3_valid_T_29
reg s3_data_word : UInt, clock
connect s3_data_word, s2_data_word[0]
reg s4_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s4_req, s3_req
reg s4_valid : UInt<1>, clock
connect s4_valid, s3_valid
reg s5_req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s5_req, s4_req
reg s5_valid : UInt<1>, clock
connect s5_valid, s4_valid
node _s3_bypass_T = shr(s2_req[0].addr, 3)
node _s3_bypass_T_1 = shr(s3_req.addr, 3)
node _s3_bypass_T_2 = eq(_s3_bypass_T, _s3_bypass_T_1)
node _s3_bypass_T_3 = and(s3_valid, _s3_bypass_T_2)
wire s3_bypass : UInt<1>[1]
connect s3_bypass[0], _s3_bypass_T_3
node _s4_bypass_T = shr(s2_req[0].addr, 3)
node _s4_bypass_T_1 = shr(s4_req.addr, 3)
node _s4_bypass_T_2 = eq(_s4_bypass_T, _s4_bypass_T_1)
node _s4_bypass_T_3 = and(s4_valid, _s4_bypass_T_2)
wire s4_bypass : UInt<1>[1]
connect s4_bypass[0], _s4_bypass_T_3
node _s5_bypass_T = shr(s2_req[0].addr, 3)
node _s5_bypass_T_1 = shr(s5_req.addr, 3)
node _s5_bypass_T_2 = eq(_s5_bypass_T, _s5_bypass_T_1)
node _s5_bypass_T_3 = and(s5_valid, _s5_bypass_T_2)
wire s5_bypass : UInt<1>[1]
connect s5_bypass[0], _s5_bypass_T_3
node _s2_data_word_0_T = mux(s5_bypass[0], s5_req.data, s2_data_word_prebypass[0])
node _s2_data_word_0_T_1 = mux(s4_bypass[0], s4_req.data, _s2_data_word_0_T)
node _s2_data_word_0_T_2 = mux(s3_bypass[0], s3_req.data, _s2_data_word_0_T_1)
connect s2_data_word[0], _s2_data_word_0_T_2
inst amoalu of AMOALU
connect amoalu.clock, clock
connect amoalu.reset, reset
wire amoalu_io_mask_size : UInt<2>
connect amoalu_io_mask_size, s3_req.uop.mem_size
node _amoalu_io_mask_upper_T = bits(s3_req.addr, 0, 0)
node _amoalu_io_mask_upper_T_1 = mux(_amoalu_io_mask_upper_T, UInt<1>(0h1), UInt<1>(0h0))
node _amoalu_io_mask_upper_T_2 = geq(amoalu_io_mask_size, UInt<1>(0h1))
node _amoalu_io_mask_upper_T_3 = mux(_amoalu_io_mask_upper_T_2, UInt<1>(0h1), UInt<1>(0h0))
node amoalu_io_mask_upper = or(_amoalu_io_mask_upper_T_1, _amoalu_io_mask_upper_T_3)
node _amoalu_io_mask_lower_T = bits(s3_req.addr, 0, 0)
node amoalu_io_mask_lower = mux(_amoalu_io_mask_lower_T, UInt<1>(0h0), UInt<1>(0h1))
node _amoalu_io_mask_T = cat(amoalu_io_mask_upper, amoalu_io_mask_lower)
node _amoalu_io_mask_upper_T_4 = bits(s3_req.addr, 1, 1)
node _amoalu_io_mask_upper_T_5 = mux(_amoalu_io_mask_upper_T_4, _amoalu_io_mask_T, UInt<1>(0h0))
node _amoalu_io_mask_upper_T_6 = geq(amoalu_io_mask_size, UInt<2>(0h2))
node _amoalu_io_mask_upper_T_7 = mux(_amoalu_io_mask_upper_T_6, UInt<2>(0h3), UInt<1>(0h0))
node amoalu_io_mask_upper_1 = or(_amoalu_io_mask_upper_T_5, _amoalu_io_mask_upper_T_7)
node _amoalu_io_mask_lower_T_1 = bits(s3_req.addr, 1, 1)
node amoalu_io_mask_lower_1 = mux(_amoalu_io_mask_lower_T_1, UInt<1>(0h0), _amoalu_io_mask_T)
node _amoalu_io_mask_T_1 = cat(amoalu_io_mask_upper_1, amoalu_io_mask_lower_1)
node _amoalu_io_mask_upper_T_8 = bits(s3_req.addr, 2, 2)
node _amoalu_io_mask_upper_T_9 = mux(_amoalu_io_mask_upper_T_8, _amoalu_io_mask_T_1, UInt<1>(0h0))
node _amoalu_io_mask_upper_T_10 = geq(amoalu_io_mask_size, UInt<2>(0h3))
node _amoalu_io_mask_upper_T_11 = mux(_amoalu_io_mask_upper_T_10, UInt<4>(0hf), UInt<1>(0h0))
node amoalu_io_mask_upper_2 = or(_amoalu_io_mask_upper_T_9, _amoalu_io_mask_upper_T_11)
node _amoalu_io_mask_lower_T_2 = bits(s3_req.addr, 2, 2)
node amoalu_io_mask_lower_2 = mux(_amoalu_io_mask_lower_T_2, UInt<1>(0h0), _amoalu_io_mask_T_1)
node _amoalu_io_mask_T_2 = cat(amoalu_io_mask_upper_2, amoalu_io_mask_lower_2)
connect amoalu.io.mask, _amoalu_io_mask_T_2
connect amoalu.io.cmd, s3_req.uop.mem_cmd
connect amoalu.io.lhs, s3_data_word
reg amoalu_io_rhs_REG : UInt, clock
connect amoalu_io_rhs_REG, s2_req[0].data
connect amoalu.io.rhs, amoalu_io_rhs_REG
connect s3_req.data, amoalu.io.out
reg s3_way : UInt, clock
connect s3_way, s2_tag_match_way[0]
connect dataWriteArb.io.in[0].valid, s3_valid
connect dataWriteArb.io.in[0].bits.addr, s3_req.addr
node _dataWriteArb_io_in_0_bits_wmask_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect dataWriteArb.io.in[0].bits.wmask, _dataWriteArb_io_in_0_bits_wmask_T
connect dataWriteArb.io.in[0].bits.data, s3_req.data
connect dataWriteArb.io.in[0].bits.way_en, s3_way
node _io_lsu_ordered_T = eq(s1_valid[0], UInt<1>(0h0))
node _io_lsu_ordered_T_1 = and(mshrs.io.fence_rdy, _io_lsu_ordered_T)
node _io_lsu_ordered_T_2 = eq(s2_valid[0], UInt<1>(0h0))
node _io_lsu_ordered_T_3 = and(_io_lsu_ordered_T_1, _io_lsu_ordered_T_2)
connect io.lsu.ordered, _io_lsu_ordered_T_3 | module BoomNonBlockingDCache( // @[dcache.scala:438:7]
input clock, // @[dcache.scala:438:7]
input reset, // @[dcache.scala:438:7]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output io_lsu_req_ready, // @[dcache.scala:444:14]
input io_lsu_req_valid, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_valid, // @[dcache.scala:444:14]
input [31:0] io_lsu_req_bits_0_bits_uop_inst, // @[dcache.scala:444:14]
input [31:0] io_lsu_req_bits_0_bits_uop_debug_inst, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_rvc, // @[dcache.scala:444:14]
input [39:0] io_lsu_req_bits_0_bits_uop_debug_pc, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iq_type_0, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iq_type_1, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iq_type_2, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iq_type_3, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_0, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_1, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_2, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_3, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_4, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_5, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_6, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_7, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_8, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fu_code_9, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iw_issued, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14]
input [11:0] io_lsu_req_bits_0_bits_uop_br_mask, // @[dcache.scala:444:14]
input [3:0] io_lsu_req_bits_0_bits_uop_br_tag, // @[dcache.scala:444:14]
input [3:0] io_lsu_req_bits_0_bits_uop_br_type, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_sfb, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_fence, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_fencei, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_sfence, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_amo, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_eret, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_rocc, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_mov, // @[dcache.scala:444:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ftq_idx, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_edge_inst, // @[dcache.scala:444:14]
input [5:0] io_lsu_req_bits_0_bits_uop_pc_lob, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_taken, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_imm_rename, // @[dcache.scala:444:14]
input [2:0] io_lsu_req_bits_0_bits_uop_imm_sel, // @[dcache.scala:444:14]
input [4:0] io_lsu_req_bits_0_bits_uop_pimm, // @[dcache.scala:444:14]
input [19:0] io_lsu_req_bits_0_bits_uop_imm_packed, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_op1_sel, // @[dcache.scala:444:14]
input [2:0] io_lsu_req_bits_0_bits_uop_op2_sel, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14]
input [5:0] io_lsu_req_bits_0_bits_uop_rob_idx, // @[dcache.scala:444:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ldq_idx, // @[dcache.scala:444:14]
input [3:0] io_lsu_req_bits_0_bits_uop_stq_idx, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx, // @[dcache.scala:444:14]
input [6:0] io_lsu_req_bits_0_bits_uop_pdst, // @[dcache.scala:444:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs1, // @[dcache.scala:444:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs2, // @[dcache.scala:444:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs3, // @[dcache.scala:444:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ppred, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_prs1_busy, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_prs2_busy, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_prs3_busy, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_ppred_busy, // @[dcache.scala:444:14]
input [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_exception, // @[dcache.scala:444:14]
input [63:0] io_lsu_req_bits_0_bits_uop_exc_cause, // @[dcache.scala:444:14]
input [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_mem_size, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_mem_signed, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_uses_ldq, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_uses_stq, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_is_unique, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14]
input [2:0] io_lsu_req_bits_0_bits_uop_csr_cmd, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14]
input [5:0] io_lsu_req_bits_0_bits_uop_ldst, // @[dcache.scala:444:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs1, // @[dcache.scala:444:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs2, // @[dcache.scala:444:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs3, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_frs3_en, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fcn_dw, // @[dcache.scala:444:14]
input [4:0] io_lsu_req_bits_0_bits_uop_fcn_op, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_fp_val, // @[dcache.scala:444:14]
input [2:0] io_lsu_req_bits_0_bits_uop_fp_rm, // @[dcache.scala:444:14]
input [1:0] io_lsu_req_bits_0_bits_uop_fp_typ, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14]
input [2:0] io_lsu_req_bits_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14]
input [2:0] io_lsu_req_bits_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14]
input [39:0] io_lsu_req_bits_0_bits_addr, // @[dcache.scala:444:14]
input [63:0] io_lsu_req_bits_0_bits_data, // @[dcache.scala:444:14]
input io_lsu_req_bits_0_bits_is_hella, // @[dcache.scala:444:14]
input io_lsu_s1_kill_0, // @[dcache.scala:444:14]
output io_lsu_resp_0_valid, // @[dcache.scala:444:14]
output [31:0] io_lsu_resp_0_bits_uop_inst, // @[dcache.scala:444:14]
output [31:0] io_lsu_resp_0_bits_uop_debug_inst, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_rvc, // @[dcache.scala:444:14]
output [39:0] io_lsu_resp_0_bits_uop_debug_pc, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iq_type_0, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iq_type_1, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iq_type_2, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iq_type_3, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_0, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_1, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_2, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_3, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_4, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_5, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_6, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_7, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_8, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fu_code_9, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iw_issued, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14]
output [11:0] io_lsu_resp_0_bits_uop_br_mask, // @[dcache.scala:444:14]
output [3:0] io_lsu_resp_0_bits_uop_br_tag, // @[dcache.scala:444:14]
output [3:0] io_lsu_resp_0_bits_uop_br_type, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_sfb, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_fence, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_fencei, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_sfence, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_amo, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_eret, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_rocc, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_mov, // @[dcache.scala:444:14]
output [4:0] io_lsu_resp_0_bits_uop_ftq_idx, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_edge_inst, // @[dcache.scala:444:14]
output [5:0] io_lsu_resp_0_bits_uop_pc_lob, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_taken, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_imm_rename, // @[dcache.scala:444:14]
output [2:0] io_lsu_resp_0_bits_uop_imm_sel, // @[dcache.scala:444:14]
output [4:0] io_lsu_resp_0_bits_uop_pimm, // @[dcache.scala:444:14]
output [19:0] io_lsu_resp_0_bits_uop_imm_packed, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_op1_sel, // @[dcache.scala:444:14]
output [2:0] io_lsu_resp_0_bits_uop_op2_sel, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14]
output [5:0] io_lsu_resp_0_bits_uop_rob_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_resp_0_bits_uop_ldq_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_resp_0_bits_uop_stq_idx, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_rxq_idx, // @[dcache.scala:444:14]
output [6:0] io_lsu_resp_0_bits_uop_pdst, // @[dcache.scala:444:14]
output [6:0] io_lsu_resp_0_bits_uop_prs1, // @[dcache.scala:444:14]
output [6:0] io_lsu_resp_0_bits_uop_prs2, // @[dcache.scala:444:14]
output [6:0] io_lsu_resp_0_bits_uop_prs3, // @[dcache.scala:444:14]
output [4:0] io_lsu_resp_0_bits_uop_ppred, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_prs1_busy, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_prs2_busy, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_prs3_busy, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_ppred_busy, // @[dcache.scala:444:14]
output [6:0] io_lsu_resp_0_bits_uop_stale_pdst, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_exception, // @[dcache.scala:444:14]
output [63:0] io_lsu_resp_0_bits_uop_exc_cause, // @[dcache.scala:444:14]
output [4:0] io_lsu_resp_0_bits_uop_mem_cmd, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_mem_size, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_mem_signed, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_uses_ldq, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_uses_stq, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_is_unique, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14]
output [2:0] io_lsu_resp_0_bits_uop_csr_cmd, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_resp_0_bits_uop_ldst, // @[dcache.scala:444:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs2, // @[dcache.scala:444:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs3, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_dst_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_frs3_en, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fcn_dw, // @[dcache.scala:444:14]
output [4:0] io_lsu_resp_0_bits_uop_fcn_op, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_fp_val, // @[dcache.scala:444:14]
output [2:0] io_lsu_resp_0_bits_uop_fp_rm, // @[dcache.scala:444:14]
output [1:0] io_lsu_resp_0_bits_uop_fp_typ, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14]
output [2:0] io_lsu_resp_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14]
output [2:0] io_lsu_resp_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14]
output [63:0] io_lsu_resp_0_bits_data, // @[dcache.scala:444:14]
output io_lsu_resp_0_bits_is_hella, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_valid, // @[dcache.scala:444:14]
output [31:0] io_lsu_store_ack_0_bits_uop_inst, // @[dcache.scala:444:14]
output [31:0] io_lsu_store_ack_0_bits_uop_debug_inst, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_rvc, // @[dcache.scala:444:14]
output [39:0] io_lsu_store_ack_0_bits_uop_debug_pc, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iq_type_0, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iq_type_1, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iq_type_2, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iq_type_3, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_0, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_1, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_2, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_3, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_4, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_5, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_6, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_7, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_8, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fu_code_9, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iw_issued, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14]
output [11:0] io_lsu_store_ack_0_bits_uop_br_mask, // @[dcache.scala:444:14]
output [3:0] io_lsu_store_ack_0_bits_uop_br_tag, // @[dcache.scala:444:14]
output [3:0] io_lsu_store_ack_0_bits_uop_br_type, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_sfb, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_fence, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_fencei, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_sfence, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_amo, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_eret, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_rocc, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_mov, // @[dcache.scala:444:14]
output [4:0] io_lsu_store_ack_0_bits_uop_ftq_idx, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_edge_inst, // @[dcache.scala:444:14]
output [5:0] io_lsu_store_ack_0_bits_uop_pc_lob, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_taken, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_imm_rename, // @[dcache.scala:444:14]
output [2:0] io_lsu_store_ack_0_bits_uop_imm_sel, // @[dcache.scala:444:14]
output [4:0] io_lsu_store_ack_0_bits_uop_pimm, // @[dcache.scala:444:14]
output [19:0] io_lsu_store_ack_0_bits_uop_imm_packed, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_op1_sel, // @[dcache.scala:444:14]
output [2:0] io_lsu_store_ack_0_bits_uop_op2_sel, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14]
output [5:0] io_lsu_store_ack_0_bits_uop_rob_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_store_ack_0_bits_uop_ldq_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_store_ack_0_bits_uop_stq_idx, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_rxq_idx, // @[dcache.scala:444:14]
output [6:0] io_lsu_store_ack_0_bits_uop_pdst, // @[dcache.scala:444:14]
output [6:0] io_lsu_store_ack_0_bits_uop_prs1, // @[dcache.scala:444:14]
output [6:0] io_lsu_store_ack_0_bits_uop_prs2, // @[dcache.scala:444:14]
output [6:0] io_lsu_store_ack_0_bits_uop_prs3, // @[dcache.scala:444:14]
output [4:0] io_lsu_store_ack_0_bits_uop_ppred, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_prs1_busy, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_prs2_busy, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_prs3_busy, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_ppred_busy, // @[dcache.scala:444:14]
output [6:0] io_lsu_store_ack_0_bits_uop_stale_pdst, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_exception, // @[dcache.scala:444:14]
output [63:0] io_lsu_store_ack_0_bits_uop_exc_cause, // @[dcache.scala:444:14]
output [4:0] io_lsu_store_ack_0_bits_uop_mem_cmd, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_mem_size, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_mem_signed, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_uses_ldq, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_uses_stq, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_is_unique, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14]
output [2:0] io_lsu_store_ack_0_bits_uop_csr_cmd, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_store_ack_0_bits_uop_ldst, // @[dcache.scala:444:14]
output [5:0] io_lsu_store_ack_0_bits_uop_lrs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_store_ack_0_bits_uop_lrs2, // @[dcache.scala:444:14]
output [5:0] io_lsu_store_ack_0_bits_uop_lrs3, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_dst_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_frs3_en, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fcn_dw, // @[dcache.scala:444:14]
output [4:0] io_lsu_store_ack_0_bits_uop_fcn_op, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_fp_val, // @[dcache.scala:444:14]
output [2:0] io_lsu_store_ack_0_bits_uop_fp_rm, // @[dcache.scala:444:14]
output [1:0] io_lsu_store_ack_0_bits_uop_fp_typ, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14]
output [2:0] io_lsu_store_ack_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14]
output [2:0] io_lsu_store_ack_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14]
output [39:0] io_lsu_store_ack_0_bits_addr, // @[dcache.scala:444:14]
output [63:0] io_lsu_store_ack_0_bits_data, // @[dcache.scala:444:14]
output io_lsu_store_ack_0_bits_is_hella, // @[dcache.scala:444:14]
output io_lsu_nack_0_valid, // @[dcache.scala:444:14]
output [31:0] io_lsu_nack_0_bits_uop_inst, // @[dcache.scala:444:14]
output [31:0] io_lsu_nack_0_bits_uop_debug_inst, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_rvc, // @[dcache.scala:444:14]
output [39:0] io_lsu_nack_0_bits_uop_debug_pc, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iq_type_0, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iq_type_1, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iq_type_2, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iq_type_3, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_0, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_1, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_2, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_3, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_4, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_5, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_6, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_7, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_8, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fu_code_9, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iw_issued, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14]
output [11:0] io_lsu_nack_0_bits_uop_br_mask, // @[dcache.scala:444:14]
output [3:0] io_lsu_nack_0_bits_uop_br_tag, // @[dcache.scala:444:14]
output [3:0] io_lsu_nack_0_bits_uop_br_type, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_sfb, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_fence, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_fencei, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_sfence, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_amo, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_eret, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_rocc, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_mov, // @[dcache.scala:444:14]
output [4:0] io_lsu_nack_0_bits_uop_ftq_idx, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_edge_inst, // @[dcache.scala:444:14]
output [5:0] io_lsu_nack_0_bits_uop_pc_lob, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_taken, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_imm_rename, // @[dcache.scala:444:14]
output [2:0] io_lsu_nack_0_bits_uop_imm_sel, // @[dcache.scala:444:14]
output [4:0] io_lsu_nack_0_bits_uop_pimm, // @[dcache.scala:444:14]
output [19:0] io_lsu_nack_0_bits_uop_imm_packed, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_op1_sel, // @[dcache.scala:444:14]
output [2:0] io_lsu_nack_0_bits_uop_op2_sel, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14]
output [5:0] io_lsu_nack_0_bits_uop_rob_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_nack_0_bits_uop_ldq_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_nack_0_bits_uop_stq_idx, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_rxq_idx, // @[dcache.scala:444:14]
output [6:0] io_lsu_nack_0_bits_uop_pdst, // @[dcache.scala:444:14]
output [6:0] io_lsu_nack_0_bits_uop_prs1, // @[dcache.scala:444:14]
output [6:0] io_lsu_nack_0_bits_uop_prs2, // @[dcache.scala:444:14]
output [6:0] io_lsu_nack_0_bits_uop_prs3, // @[dcache.scala:444:14]
output [4:0] io_lsu_nack_0_bits_uop_ppred, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_prs1_busy, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_prs2_busy, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_prs3_busy, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_ppred_busy, // @[dcache.scala:444:14]
output [6:0] io_lsu_nack_0_bits_uop_stale_pdst, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_exception, // @[dcache.scala:444:14]
output [63:0] io_lsu_nack_0_bits_uop_exc_cause, // @[dcache.scala:444:14]
output [4:0] io_lsu_nack_0_bits_uop_mem_cmd, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_mem_size, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_mem_signed, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_uses_ldq, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_uses_stq, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_is_unique, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14]
output [2:0] io_lsu_nack_0_bits_uop_csr_cmd, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_nack_0_bits_uop_ldst, // @[dcache.scala:444:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs2, // @[dcache.scala:444:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs3, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_dst_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_frs3_en, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fcn_dw, // @[dcache.scala:444:14]
output [4:0] io_lsu_nack_0_bits_uop_fcn_op, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_fp_val, // @[dcache.scala:444:14]
output [2:0] io_lsu_nack_0_bits_uop_fp_rm, // @[dcache.scala:444:14]
output [1:0] io_lsu_nack_0_bits_uop_fp_typ, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14]
output [2:0] io_lsu_nack_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14]
output [2:0] io_lsu_nack_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14]
output [39:0] io_lsu_nack_0_bits_addr, // @[dcache.scala:444:14]
output [63:0] io_lsu_nack_0_bits_data, // @[dcache.scala:444:14]
output io_lsu_nack_0_bits_is_hella, // @[dcache.scala:444:14]
input io_lsu_ll_resp_ready, // @[dcache.scala:444:14]
output io_lsu_ll_resp_valid, // @[dcache.scala:444:14]
output [31:0] io_lsu_ll_resp_bits_uop_inst, // @[dcache.scala:444:14]
output [31:0] io_lsu_ll_resp_bits_uop_debug_inst, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_rvc, // @[dcache.scala:444:14]
output [39:0] io_lsu_ll_resp_bits_uop_debug_pc, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iq_type_0, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iq_type_1, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iq_type_2, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iq_type_3, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_0, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_1, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_2, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_3, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_4, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_5, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_6, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_7, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_8, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fu_code_9, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iw_issued, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_dis_col_sel, // @[dcache.scala:444:14]
output [11:0] io_lsu_ll_resp_bits_uop_br_mask, // @[dcache.scala:444:14]
output [3:0] io_lsu_ll_resp_bits_uop_br_tag, // @[dcache.scala:444:14]
output [3:0] io_lsu_ll_resp_bits_uop_br_type, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_sfb, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_fence, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_fencei, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_sfence, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_amo, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_eret, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_rocc, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_mov, // @[dcache.scala:444:14]
output [4:0] io_lsu_ll_resp_bits_uop_ftq_idx, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_edge_inst, // @[dcache.scala:444:14]
output [5:0] io_lsu_ll_resp_bits_uop_pc_lob, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_taken, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_imm_rename, // @[dcache.scala:444:14]
output [2:0] io_lsu_ll_resp_bits_uop_imm_sel, // @[dcache.scala:444:14]
output [4:0] io_lsu_ll_resp_bits_uop_pimm, // @[dcache.scala:444:14]
output [19:0] io_lsu_ll_resp_bits_uop_imm_packed, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_op1_sel, // @[dcache.scala:444:14]
output [2:0] io_lsu_ll_resp_bits_uop_op2_sel, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14]
output [5:0] io_lsu_ll_resp_bits_uop_rob_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_ll_resp_bits_uop_ldq_idx, // @[dcache.scala:444:14]
output [3:0] io_lsu_ll_resp_bits_uop_stq_idx, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_rxq_idx, // @[dcache.scala:444:14]
output [6:0] io_lsu_ll_resp_bits_uop_pdst, // @[dcache.scala:444:14]
output [6:0] io_lsu_ll_resp_bits_uop_prs1, // @[dcache.scala:444:14]
output [6:0] io_lsu_ll_resp_bits_uop_prs2, // @[dcache.scala:444:14]
output [6:0] io_lsu_ll_resp_bits_uop_prs3, // @[dcache.scala:444:14]
output [4:0] io_lsu_ll_resp_bits_uop_ppred, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_prs1_busy, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_prs2_busy, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_prs3_busy, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_ppred_busy, // @[dcache.scala:444:14]
output [6:0] io_lsu_ll_resp_bits_uop_stale_pdst, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_exception, // @[dcache.scala:444:14]
output [63:0] io_lsu_ll_resp_bits_uop_exc_cause, // @[dcache.scala:444:14]
output [4:0] io_lsu_ll_resp_bits_uop_mem_cmd, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_mem_size, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_mem_signed, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_uses_ldq, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_uses_stq, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_is_unique, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_flush_on_commit, // @[dcache.scala:444:14]
output [2:0] io_lsu_ll_resp_bits_uop_csr_cmd, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_ll_resp_bits_uop_ldst, // @[dcache.scala:444:14]
output [5:0] io_lsu_ll_resp_bits_uop_lrs1, // @[dcache.scala:444:14]
output [5:0] io_lsu_ll_resp_bits_uop_lrs2, // @[dcache.scala:444:14]
output [5:0] io_lsu_ll_resp_bits_uop_lrs3, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_dst_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_lrs1_rtype, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_lrs2_rtype, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_frs3_en, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fcn_dw, // @[dcache.scala:444:14]
output [4:0] io_lsu_ll_resp_bits_uop_fcn_op, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_fp_val, // @[dcache.scala:444:14]
output [2:0] io_lsu_ll_resp_bits_uop_fp_rm, // @[dcache.scala:444:14]
output [1:0] io_lsu_ll_resp_bits_uop_fp_typ, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_bp_debug_if, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14]
output [2:0] io_lsu_ll_resp_bits_uop_debug_fsrc, // @[dcache.scala:444:14]
output [2:0] io_lsu_ll_resp_bits_uop_debug_tsrc, // @[dcache.scala:444:14]
output [63:0] io_lsu_ll_resp_bits_data, // @[dcache.scala:444:14]
output io_lsu_ll_resp_bits_is_hella, // @[dcache.scala:444:14]
input [11:0] io_lsu_brupdate_b1_resolve_mask, // @[dcache.scala:444:14]
input [11:0] io_lsu_brupdate_b1_mispredict_mask, // @[dcache.scala:444:14]
input [31:0] io_lsu_brupdate_b2_uop_inst, // @[dcache.scala:444:14]
input [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_rvc, // @[dcache.scala:444:14]
input [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iq_type_0, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iq_type_1, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iq_type_2, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iq_type_3, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_0, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_1, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_2, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_3, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_4, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_5, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_6, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_7, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_8, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fu_code_9, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iw_issued, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iw_issued_partial_agen, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_iw_p1_speculative_child, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_iw_p2_speculative_child, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_dis_col_sel, // @[dcache.scala:444:14]
input [11:0] io_lsu_brupdate_b2_uop_br_mask, // @[dcache.scala:444:14]
input [3:0] io_lsu_brupdate_b2_uop_br_tag, // @[dcache.scala:444:14]
input [3:0] io_lsu_brupdate_b2_uop_br_type, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_sfb, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_fence, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_fencei, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_sfence, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_amo, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_eret, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_rocc, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_mov, // @[dcache.scala:444:14]
input [4:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_edge_inst, // @[dcache.scala:444:14]
input [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_taken, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_imm_rename, // @[dcache.scala:444:14]
input [2:0] io_lsu_brupdate_b2_uop_imm_sel, // @[dcache.scala:444:14]
input [4:0] io_lsu_brupdate_b2_uop_pimm, // @[dcache.scala:444:14]
input [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_op1_sel, // @[dcache.scala:444:14]
input [2:0] io_lsu_brupdate_b2_uop_op2_sel, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_ldst, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_wen, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_ren1, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_ren2, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_ren3, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_swap12, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_swap23, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_fromint, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_toint, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_fma, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_div, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_wflags, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_ctrl_vec, // @[dcache.scala:444:14]
input [5:0] io_lsu_brupdate_b2_uop_rob_idx, // @[dcache.scala:444:14]
input [3:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[dcache.scala:444:14]
input [3:0] io_lsu_brupdate_b2_uop_stq_idx, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[dcache.scala:444:14]
input [6:0] io_lsu_brupdate_b2_uop_pdst, // @[dcache.scala:444:14]
input [6:0] io_lsu_brupdate_b2_uop_prs1, // @[dcache.scala:444:14]
input [6:0] io_lsu_brupdate_b2_uop_prs2, // @[dcache.scala:444:14]
input [6:0] io_lsu_brupdate_b2_uop_prs3, // @[dcache.scala:444:14]
input [4:0] io_lsu_brupdate_b2_uop_ppred, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_prs1_busy, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_prs2_busy, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_prs3_busy, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_ppred_busy, // @[dcache.scala:444:14]
input [6:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_exception, // @[dcache.scala:444:14]
input [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[dcache.scala:444:14]
input [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_mem_signed, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_uses_ldq, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_uses_stq, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_is_unique, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_flush_on_commit, // @[dcache.scala:444:14]
input [2:0] io_lsu_brupdate_b2_uop_csr_cmd, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[dcache.scala:444:14]
input [5:0] io_lsu_brupdate_b2_uop_ldst, // @[dcache.scala:444:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[dcache.scala:444:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[dcache.scala:444:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_frs3_en, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fcn_dw, // @[dcache.scala:444:14]
input [4:0] io_lsu_brupdate_b2_uop_fcn_op, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_fp_val, // @[dcache.scala:444:14]
input [2:0] io_lsu_brupdate_b2_uop_fp_rm, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_uop_fp_typ, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_bp_debug_if, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[dcache.scala:444:14]
input [2:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[dcache.scala:444:14]
input [2:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_mispredict, // @[dcache.scala:444:14]
input io_lsu_brupdate_b2_taken, // @[dcache.scala:444:14]
input [2:0] io_lsu_brupdate_b2_cfi_type, // @[dcache.scala:444:14]
input [1:0] io_lsu_brupdate_b2_pc_sel, // @[dcache.scala:444:14]
input [39:0] io_lsu_brupdate_b2_jalr_target, // @[dcache.scala:444:14]
input [20:0] io_lsu_brupdate_b2_target_offset, // @[dcache.scala:444:14]
input io_lsu_exception, // @[dcache.scala:444:14]
input [5:0] io_lsu_rob_pnr_idx, // @[dcache.scala:444:14]
input [5:0] io_lsu_rob_head_idx, // @[dcache.scala:444:14]
input io_lsu_release_ready, // @[dcache.scala:444:14]
output io_lsu_release_valid, // @[dcache.scala:444:14]
output [2:0] io_lsu_release_bits_opcode, // @[dcache.scala:444:14]
output [2:0] io_lsu_release_bits_param, // @[dcache.scala:444:14]
output [3:0] io_lsu_release_bits_size, // @[dcache.scala:444:14]
output [1:0] io_lsu_release_bits_source, // @[dcache.scala:444:14]
output [31:0] io_lsu_release_bits_address, // @[dcache.scala:444:14]
output [63:0] io_lsu_release_bits_data, // @[dcache.scala:444:14]
input io_lsu_force_order, // @[dcache.scala:444:14]
output io_lsu_ordered, // @[dcache.scala:444:14]
output io_lsu_perf_acquire, // @[dcache.scala:444:14]
output io_lsu_perf_release // @[dcache.scala:444:14]
);
wire [1:0] s3_req_uop_mem_size; // @[dcache.scala:895:22]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire _mshrs_io_replay_ready_T; // @[dcache.scala:534:58]
wire _lsu_release_arb_io_in_0_ready; // @[dcache.scala:857:31]
wire _lsu_release_arb_io_in_1_ready; // @[dcache.scala:857:31]
wire _wbArb_io_in_0_ready; // @[dcache.scala:848:21]
wire _wbArb_io_in_1_ready; // @[dcache.scala:848:21]
wire _wbArb_io_out_valid; // @[dcache.scala:848:21]
wire [19:0] _wbArb_io_out_bits_tag; // @[dcache.scala:848:21]
wire [5:0] _wbArb_io_out_bits_idx; // @[dcache.scala:848:21]
wire [1:0] _wbArb_io_out_bits_source; // @[dcache.scala:848:21]
wire [2:0] _wbArb_io_out_bits_param; // @[dcache.scala:848:21]
wire [3:0] _wbArb_io_out_bits_way_en; // @[dcache.scala:848:21]
wire _wbArb_io_out_bits_voluntary; // @[dcache.scala:848:21]
wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22]
wire _dataReadArb_io_in_1_ready; // @[dcache.scala:490:27]
wire _dataReadArb_io_in_2_ready; // @[dcache.scala:490:27]
wire _dataReadArb_io_out_valid; // @[dcache.scala:490:27]
wire [3:0] _dataReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:490:27]
wire [11:0] _dataReadArb_io_out_bits_req_0_addr; // @[dcache.scala:490:27]
wire _dataReadArb_io_out_bits_valid_0; // @[dcache.scala:490:27]
wire _dataWriteArb_io_in_1_ready; // @[dcache.scala:488:28]
wire [3:0] _dataWriteArb_io_out_bits_way_en; // @[dcache.scala:488:28]
wire [11:0] _dataWriteArb_io_out_bits_addr; // @[dcache.scala:488:28]
wire [63:0] _dataWriteArb_io_out_bits_data; // @[dcache.scala:488:28]
wire _metaReadArb_io_in_1_ready; // @[dcache.scala:472:27]
wire _metaReadArb_io_in_2_ready; // @[dcache.scala:472:27]
wire _metaReadArb_io_in_3_ready; // @[dcache.scala:472:27]
wire _metaReadArb_io_in_4_ready; // @[dcache.scala:472:27]
wire _metaReadArb_io_in_5_ready; // @[dcache.scala:472:27]
wire _metaReadArb_io_out_valid; // @[dcache.scala:472:27]
wire [5:0] _metaReadArb_io_out_bits_req_0_idx; // @[dcache.scala:472:27]
wire [3:0] _metaReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:472:27]
wire [19:0] _metaReadArb_io_out_bits_req_0_tag; // @[dcache.scala:472:27]
wire _metaWriteArb_io_in_0_ready; // @[dcache.scala:470:28]
wire _metaWriteArb_io_in_1_ready; // @[dcache.scala:470:28]
wire _metaWriteArb_io_out_valid; // @[dcache.scala:470:28]
wire [5:0] _metaWriteArb_io_out_bits_idx; // @[dcache.scala:470:28]
wire [3:0] _metaWriteArb_io_out_bits_way_en; // @[dcache.scala:470:28]
wire [19:0] _metaWriteArb_io_out_bits_tag; // @[dcache.scala:470:28]
wire [1:0] _metaWriteArb_io_out_bits_data_coh_state; // @[dcache.scala:470:28]
wire [19:0] _metaWriteArb_io_out_bits_data_tag; // @[dcache.scala:470:28]
wire _meta_0_io_read_ready; // @[dcache.scala:469:41]
wire _meta_0_io_write_ready; // @[dcache.scala:469:41]
wire [1:0] _meta_0_io_resp_0_coh_state; // @[dcache.scala:469:41]
wire [19:0] _meta_0_io_resp_0_tag; // @[dcache.scala:469:41]
wire [1:0] _meta_0_io_resp_1_coh_state; // @[dcache.scala:469:41]
wire [19:0] _meta_0_io_resp_1_tag; // @[dcache.scala:469:41]
wire [1:0] _meta_0_io_resp_2_coh_state; // @[dcache.scala:469:41]
wire [19:0] _meta_0_io_resp_2_tag; // @[dcache.scala:469:41]
wire [1:0] _meta_0_io_resp_3_coh_state; // @[dcache.scala:469:41]
wire [19:0] _meta_0_io_resp_3_tag; // @[dcache.scala:469:41]
wire _mshrs_io_req_0_ready; // @[dcache.scala:460:21]
wire _mshrs_io_resp_valid; // @[dcache.scala:460:21]
wire _mshrs_io_secondary_miss_0; // @[dcache.scala:460:21]
wire _mshrs_io_block_hit_0; // @[dcache.scala:460:21]
wire _mshrs_io_mem_grant_ready; // @[dcache.scala:460:21]
wire _mshrs_io_refill_valid; // @[dcache.scala:460:21]
wire [3:0] _mshrs_io_refill_bits_way_en; // @[dcache.scala:460:21]
wire [11:0] _mshrs_io_refill_bits_addr; // @[dcache.scala:460:21]
wire [63:0] _mshrs_io_refill_bits_data; // @[dcache.scala:460:21]
wire _mshrs_io_meta_write_valid; // @[dcache.scala:460:21]
wire [5:0] _mshrs_io_meta_write_bits_idx; // @[dcache.scala:460:21]
wire [3:0] _mshrs_io_meta_write_bits_way_en; // @[dcache.scala:460:21]
wire [19:0] _mshrs_io_meta_write_bits_tag; // @[dcache.scala:460:21]
wire [1:0] _mshrs_io_meta_write_bits_data_coh_state; // @[dcache.scala:460:21]
wire [19:0] _mshrs_io_meta_write_bits_data_tag; // @[dcache.scala:460:21]
wire _mshrs_io_meta_read_valid; // @[dcache.scala:460:21]
wire [5:0] _mshrs_io_meta_read_bits_idx; // @[dcache.scala:460:21]
wire [3:0] _mshrs_io_meta_read_bits_way_en; // @[dcache.scala:460:21]
wire [19:0] _mshrs_io_meta_read_bits_tag; // @[dcache.scala:460:21]
wire _mshrs_io_replay_valid; // @[dcache.scala:460:21]
wire [4:0] _mshrs_io_replay_bits_uop_mem_cmd; // @[dcache.scala:460:21]
wire [39:0] _mshrs_io_replay_bits_addr; // @[dcache.scala:460:21]
wire [3:0] _mshrs_io_replay_bits_way_en; // @[dcache.scala:460:21]
wire _mshrs_io_wb_req_valid; // @[dcache.scala:460:21]
wire [19:0] _mshrs_io_wb_req_bits_tag; // @[dcache.scala:460:21]
wire [5:0] _mshrs_io_wb_req_bits_idx; // @[dcache.scala:460:21]
wire [1:0] _mshrs_io_wb_req_bits_source; // @[dcache.scala:460:21]
wire [2:0] _mshrs_io_wb_req_bits_param; // @[dcache.scala:460:21]
wire [3:0] _mshrs_io_wb_req_bits_way_en; // @[dcache.scala:460:21]
wire _mshrs_io_fence_rdy; // @[dcache.scala:460:21]
wire _mshrs_io_probe_rdy; // @[dcache.scala:460:21]
wire _prober_io_req_ready; // @[dcache.scala:459:22]
wire _prober_io_rep_valid; // @[dcache.scala:459:22]
wire [2:0] _prober_io_rep_bits_param; // @[dcache.scala:459:22]
wire [3:0] _prober_io_rep_bits_size; // @[dcache.scala:459:22]
wire [1:0] _prober_io_rep_bits_source; // @[dcache.scala:459:22]
wire [31:0] _prober_io_rep_bits_address; // @[dcache.scala:459:22]
wire _prober_io_meta_read_valid; // @[dcache.scala:459:22]
wire [5:0] _prober_io_meta_read_bits_idx; // @[dcache.scala:459:22]
wire [19:0] _prober_io_meta_read_bits_tag; // @[dcache.scala:459:22]
wire _prober_io_meta_write_valid; // @[dcache.scala:459:22]
wire [5:0] _prober_io_meta_write_bits_idx; // @[dcache.scala:459:22]
wire [3:0] _prober_io_meta_write_bits_way_en; // @[dcache.scala:459:22]
wire [19:0] _prober_io_meta_write_bits_tag; // @[dcache.scala:459:22]
wire [1:0] _prober_io_meta_write_bits_data_coh_state; // @[dcache.scala:459:22]
wire [19:0] _prober_io_meta_write_bits_data_tag; // @[dcache.scala:459:22]
wire _prober_io_wb_req_valid; // @[dcache.scala:459:22]
wire [19:0] _prober_io_wb_req_bits_tag; // @[dcache.scala:459:22]
wire [5:0] _prober_io_wb_req_bits_idx; // @[dcache.scala:459:22]
wire [1:0] _prober_io_wb_req_bits_source; // @[dcache.scala:459:22]
wire [2:0] _prober_io_wb_req_bits_param; // @[dcache.scala:459:22]
wire [3:0] _prober_io_wb_req_bits_way_en; // @[dcache.scala:459:22]
wire _prober_io_mshr_wb_rdy; // @[dcache.scala:459:22]
wire _prober_io_lsu_release_valid; // @[dcache.scala:459:22]
wire [2:0] _prober_io_lsu_release_bits_param; // @[dcache.scala:459:22]
wire [3:0] _prober_io_lsu_release_bits_size; // @[dcache.scala:459:22]
wire [1:0] _prober_io_lsu_release_bits_source; // @[dcache.scala:459:22]
wire [31:0] _prober_io_lsu_release_bits_address; // @[dcache.scala:459:22]
wire _prober_io_state_valid; // @[dcache.scala:459:22]
wire [39:0] _prober_io_state_bits; // @[dcache.scala:459:22]
wire _wb_io_req_ready; // @[dcache.scala:458:18]
wire _wb_io_meta_read_valid; // @[dcache.scala:458:18]
wire [5:0] _wb_io_meta_read_bits_idx; // @[dcache.scala:458:18]
wire [19:0] _wb_io_meta_read_bits_tag; // @[dcache.scala:458:18]
wire _wb_io_resp; // @[dcache.scala:458:18]
wire _wb_io_idx_valid; // @[dcache.scala:458:18]
wire [5:0] _wb_io_idx_bits; // @[dcache.scala:458:18]
wire _wb_io_data_req_valid; // @[dcache.scala:458:18]
wire [3:0] _wb_io_data_req_bits_way_en; // @[dcache.scala:458:18]
wire [11:0] _wb_io_data_req_bits_addr; // @[dcache.scala:458:18]
wire _wb_io_release_valid; // @[dcache.scala:458:18]
wire [2:0] _wb_io_release_bits_opcode; // @[dcache.scala:458:18]
wire [2:0] _wb_io_release_bits_param; // @[dcache.scala:458:18]
wire [1:0] _wb_io_release_bits_source; // @[dcache.scala:458:18]
wire [31:0] _wb_io_release_bits_address; // @[dcache.scala:458:18]
wire [63:0] _wb_io_release_bits_data; // @[dcache.scala:458:18]
wire _wb_io_lsu_release_valid; // @[dcache.scala:458:18]
wire [2:0] _wb_io_lsu_release_bits_param; // @[dcache.scala:458:18]
wire [1:0] _wb_io_lsu_release_bits_source; // @[dcache.scala:458:18]
wire [31:0] _wb_io_lsu_release_bits_address; // @[dcache.scala:458:18]
wire [63:0] _wb_io_lsu_release_bits_data; // @[dcache.scala:458:18]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[dcache.scala:438:7]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[dcache.scala:438:7]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[dcache.scala:438:7]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[dcache.scala:438:7]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[dcache.scala:438:7]
wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[dcache.scala:438:7]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[dcache.scala:438:7]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[dcache.scala:438:7]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[dcache.scala:438:7]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[dcache.scala:438:7]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[dcache.scala:438:7]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[dcache.scala:438:7]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[dcache.scala:438:7]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[dcache.scala:438:7]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[dcache.scala:438:7]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[dcache.scala:438:7]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[dcache.scala:438:7]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[dcache.scala:438:7]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[dcache.scala:438:7]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[dcache.scala:438:7]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[dcache.scala:438:7]
wire io_lsu_req_valid_0 = io_lsu_req_valid; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_valid_0 = io_lsu_req_bits_0_valid; // @[dcache.scala:438:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_inst_0 = io_lsu_req_bits_0_bits_uop_inst; // @[dcache.scala:438:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_debug_inst_0 = io_lsu_req_bits_0_bits_uop_debug_inst; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_rvc_0 = io_lsu_req_bits_0_bits_uop_is_rvc; // @[dcache.scala:438:7]
wire [39:0] io_lsu_req_bits_0_bits_uop_debug_pc_0 = io_lsu_req_bits_0_bits_uop_debug_pc; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iq_type_0_0 = io_lsu_req_bits_0_bits_uop_iq_type_0; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iq_type_1_0 = io_lsu_req_bits_0_bits_uop_iq_type_1; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iq_type_2_0 = io_lsu_req_bits_0_bits_uop_iq_type_2; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iq_type_3_0 = io_lsu_req_bits_0_bits_uop_iq_type_3; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_0_0 = io_lsu_req_bits_0_bits_uop_fu_code_0; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_1_0 = io_lsu_req_bits_0_bits_uop_fu_code_1; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_2_0 = io_lsu_req_bits_0_bits_uop_fu_code_2; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_3_0 = io_lsu_req_bits_0_bits_uop_fu_code_3; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_4_0 = io_lsu_req_bits_0_bits_uop_fu_code_4; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_5_0 = io_lsu_req_bits_0_bits_uop_fu_code_5; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_6_0 = io_lsu_req_bits_0_bits_uop_fu_code_6; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_7_0 = io_lsu_req_bits_0_bits_uop_fu_code_7; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_8_0 = io_lsu_req_bits_0_bits_uop_fu_code_8; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fu_code_9_0 = io_lsu_req_bits_0_bits_uop_fu_code_9; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iw_issued_0 = io_lsu_req_bits_0_bits_uop_iw_issued; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_dis_col_sel_0 = io_lsu_req_bits_0_bits_uop_dis_col_sel; // @[dcache.scala:438:7]
wire [11:0] io_lsu_req_bits_0_bits_uop_br_mask_0 = io_lsu_req_bits_0_bits_uop_br_mask; // @[dcache.scala:438:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_br_tag_0 = io_lsu_req_bits_0_bits_uop_br_tag; // @[dcache.scala:438:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_br_type_0 = io_lsu_req_bits_0_bits_uop_br_type; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_sfb_0 = io_lsu_req_bits_0_bits_uop_is_sfb; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_fence_0 = io_lsu_req_bits_0_bits_uop_is_fence; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_fencei_0 = io_lsu_req_bits_0_bits_uop_is_fencei; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_sfence_0 = io_lsu_req_bits_0_bits_uop_is_sfence; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_amo_0 = io_lsu_req_bits_0_bits_uop_is_amo; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_eret_0 = io_lsu_req_bits_0_bits_uop_is_eret; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0 = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_rocc_0 = io_lsu_req_bits_0_bits_uop_is_rocc; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_mov_0 = io_lsu_req_bits_0_bits_uop_is_mov; // @[dcache.scala:438:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ftq_idx_0 = io_lsu_req_bits_0_bits_uop_ftq_idx; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_edge_inst_0 = io_lsu_req_bits_0_bits_uop_edge_inst; // @[dcache.scala:438:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_pc_lob_0 = io_lsu_req_bits_0_bits_uop_pc_lob; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_taken_0 = io_lsu_req_bits_0_bits_uop_taken; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_imm_rename_0 = io_lsu_req_bits_0_bits_uop_imm_rename; // @[dcache.scala:438:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_imm_sel_0 = io_lsu_req_bits_0_bits_uop_imm_sel; // @[dcache.scala:438:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_pimm_0 = io_lsu_req_bits_0_bits_uop_pimm; // @[dcache.scala:438:7]
wire [19:0] io_lsu_req_bits_0_bits_uop_imm_packed_0 = io_lsu_req_bits_0_bits_uop_imm_packed; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_op1_sel_0 = io_lsu_req_bits_0_bits_uop_op1_sel; // @[dcache.scala:438:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_op2_sel_0 = io_lsu_req_bits_0_bits_uop_op2_sel; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_wen_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_wen; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_toint_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_toint; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_fma_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_fma; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_div_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_div; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_ctrl_vec_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_vec; // @[dcache.scala:438:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_rob_idx_0 = io_lsu_req_bits_0_bits_uop_rob_idx; // @[dcache.scala:438:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ldq_idx_0 = io_lsu_req_bits_0_bits_uop_ldq_idx; // @[dcache.scala:438:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_stq_idx_0 = io_lsu_req_bits_0_bits_uop_stq_idx; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx_0 = io_lsu_req_bits_0_bits_uop_rxq_idx; // @[dcache.scala:438:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_pdst_0 = io_lsu_req_bits_0_bits_uop_pdst; // @[dcache.scala:438:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs1_0 = io_lsu_req_bits_0_bits_uop_prs1; // @[dcache.scala:438:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs2_0 = io_lsu_req_bits_0_bits_uop_prs2; // @[dcache.scala:438:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs3_0 = io_lsu_req_bits_0_bits_uop_prs3; // @[dcache.scala:438:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ppred_0 = io_lsu_req_bits_0_bits_uop_ppred; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_prs1_busy_0 = io_lsu_req_bits_0_bits_uop_prs1_busy; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_prs2_busy_0 = io_lsu_req_bits_0_bits_uop_prs2_busy; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_prs3_busy_0 = io_lsu_req_bits_0_bits_uop_prs3_busy; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_ppred_busy_0 = io_lsu_req_bits_0_bits_uop_ppred_busy; // @[dcache.scala:438:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst_0 = io_lsu_req_bits_0_bits_uop_stale_pdst; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_exception_0 = io_lsu_req_bits_0_bits_uop_exception; // @[dcache.scala:438:7]
wire [63:0] io_lsu_req_bits_0_bits_uop_exc_cause_0 = io_lsu_req_bits_0_bits_uop_exc_cause; // @[dcache.scala:438:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd_0 = io_lsu_req_bits_0_bits_uop_mem_cmd; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_mem_size_0 = io_lsu_req_bits_0_bits_uop_mem_size; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_mem_signed_0 = io_lsu_req_bits_0_bits_uop_mem_signed; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_uses_ldq_0 = io_lsu_req_bits_0_bits_uop_uses_ldq; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_uses_stq_0 = io_lsu_req_bits_0_bits_uop_uses_stq; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_is_unique_0 = io_lsu_req_bits_0_bits_uop_is_unique; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_flush_on_commit_0 = io_lsu_req_bits_0_bits_uop_flush_on_commit; // @[dcache.scala:438:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_csr_cmd_0 = io_lsu_req_bits_0_bits_uop_csr_cmd; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1; // @[dcache.scala:438:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_ldst_0 = io_lsu_req_bits_0_bits_uop_ldst; // @[dcache.scala:438:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs1_0 = io_lsu_req_bits_0_bits_uop_lrs1; // @[dcache.scala:438:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs2_0 = io_lsu_req_bits_0_bits_uop_lrs2; // @[dcache.scala:438:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs3_0 = io_lsu_req_bits_0_bits_uop_lrs3; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype_0 = io_lsu_req_bits_0_bits_uop_dst_rtype; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs1_rtype; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs2_rtype; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_frs3_en_0 = io_lsu_req_bits_0_bits_uop_frs3_en; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fcn_dw_0 = io_lsu_req_bits_0_bits_uop_fcn_dw; // @[dcache.scala:438:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_fcn_op_0 = io_lsu_req_bits_0_bits_uop_fcn_op; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_fp_val_0 = io_lsu_req_bits_0_bits_uop_fp_val; // @[dcache.scala:438:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_fp_rm_0 = io_lsu_req_bits_0_bits_uop_fp_rm; // @[dcache.scala:438:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_fp_typ_0 = io_lsu_req_bits_0_bits_uop_fp_typ; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_pf_if; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ae_if; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ma_if; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_bp_debug_if_0 = io_lsu_req_bits_0_bits_uop_bp_debug_if; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0 = io_lsu_req_bits_0_bits_uop_bp_xcpt_if; // @[dcache.scala:438:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_debug_fsrc_0 = io_lsu_req_bits_0_bits_uop_debug_fsrc; // @[dcache.scala:438:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_debug_tsrc_0 = io_lsu_req_bits_0_bits_uop_debug_tsrc; // @[dcache.scala:438:7]
wire [39:0] io_lsu_req_bits_0_bits_addr_0 = io_lsu_req_bits_0_bits_addr; // @[dcache.scala:438:7]
wire [63:0] io_lsu_req_bits_0_bits_data_0 = io_lsu_req_bits_0_bits_data; // @[dcache.scala:438:7]
wire io_lsu_req_bits_0_bits_is_hella_0 = io_lsu_req_bits_0_bits_is_hella; // @[dcache.scala:438:7]
wire io_lsu_s1_kill_0_0 = io_lsu_s1_kill_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_ready_0 = io_lsu_ll_resp_ready; // @[dcache.scala:438:7]
wire [11:0] io_lsu_brupdate_b1_resolve_mask_0 = io_lsu_brupdate_b1_resolve_mask; // @[dcache.scala:438:7]
wire [11:0] io_lsu_brupdate_b1_mispredict_mask_0 = io_lsu_brupdate_b1_mispredict_mask; // @[dcache.scala:438:7]
wire [31:0] io_lsu_brupdate_b2_uop_inst_0 = io_lsu_brupdate_b2_uop_inst; // @[dcache.scala:438:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0 = io_lsu_brupdate_b2_uop_debug_inst; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_rvc_0 = io_lsu_brupdate_b2_uop_is_rvc; // @[dcache.scala:438:7]
wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0 = io_lsu_brupdate_b2_uop_debug_pc; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iq_type_0_0 = io_lsu_brupdate_b2_uop_iq_type_0; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iq_type_1_0 = io_lsu_brupdate_b2_uop_iq_type_1; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iq_type_2_0 = io_lsu_brupdate_b2_uop_iq_type_2; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iq_type_3_0 = io_lsu_brupdate_b2_uop_iq_type_3; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_0_0 = io_lsu_brupdate_b2_uop_fu_code_0; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_1_0 = io_lsu_brupdate_b2_uop_fu_code_1; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_2_0 = io_lsu_brupdate_b2_uop_fu_code_2; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_3_0 = io_lsu_brupdate_b2_uop_fu_code_3; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_4_0 = io_lsu_brupdate_b2_uop_fu_code_4; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_5_0 = io_lsu_brupdate_b2_uop_fu_code_5; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_6_0 = io_lsu_brupdate_b2_uop_fu_code_6; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_7_0 = io_lsu_brupdate_b2_uop_fu_code_7; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_8_0 = io_lsu_brupdate_b2_uop_fu_code_8; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fu_code_9_0 = io_lsu_brupdate_b2_uop_fu_code_9; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iw_issued_0 = io_lsu_brupdate_b2_uop_iw_issued; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iw_issued_partial_agen_0 = io_lsu_brupdate_b2_uop_iw_issued_partial_agen; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_lsu_brupdate_b2_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_p1_speculative_child_0 = io_lsu_brupdate_b2_uop_iw_p1_speculative_child; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_p2_speculative_child_0 = io_lsu_brupdate_b2_uop_iw_p2_speculative_child; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_lsu_brupdate_b2_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_lsu_brupdate_b2_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_lsu_brupdate_b2_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_dis_col_sel_0 = io_lsu_brupdate_b2_uop_dis_col_sel; // @[dcache.scala:438:7]
wire [11:0] io_lsu_brupdate_b2_uop_br_mask_0 = io_lsu_brupdate_b2_uop_br_mask; // @[dcache.scala:438:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0 = io_lsu_brupdate_b2_uop_br_tag; // @[dcache.scala:438:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_type_0 = io_lsu_brupdate_b2_uop_br_type; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_sfb_0 = io_lsu_brupdate_b2_uop_is_sfb; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_fence_0 = io_lsu_brupdate_b2_uop_is_fence; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_fencei_0 = io_lsu_brupdate_b2_uop_is_fencei; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_sfence_0 = io_lsu_brupdate_b2_uop_is_sfence; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_amo_0 = io_lsu_brupdate_b2_uop_is_amo; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_eret_0 = io_lsu_brupdate_b2_uop_is_eret; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_rocc_0 = io_lsu_brupdate_b2_uop_is_rocc; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_mov_0 = io_lsu_brupdate_b2_uop_is_mov; // @[dcache.scala:438:7]
wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0 = io_lsu_brupdate_b2_uop_ftq_idx; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_edge_inst_0 = io_lsu_brupdate_b2_uop_edge_inst; // @[dcache.scala:438:7]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0 = io_lsu_brupdate_b2_uop_pc_lob; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_taken_0 = io_lsu_brupdate_b2_uop_taken; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_imm_rename_0 = io_lsu_brupdate_b2_uop_imm_rename; // @[dcache.scala:438:7]
wire [2:0] io_lsu_brupdate_b2_uop_imm_sel_0 = io_lsu_brupdate_b2_uop_imm_sel; // @[dcache.scala:438:7]
wire [4:0] io_lsu_brupdate_b2_uop_pimm_0 = io_lsu_brupdate_b2_uop_pimm; // @[dcache.scala:438:7]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0 = io_lsu_brupdate_b2_uop_imm_packed; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_op1_sel_0 = io_lsu_brupdate_b2_uop_op1_sel; // @[dcache.scala:438:7]
wire [2:0] io_lsu_brupdate_b2_uop_op2_sel_0 = io_lsu_brupdate_b2_uop_op2_sel; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ldst_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ldst; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_wen_0 = io_lsu_brupdate_b2_uop_fp_ctrl_wen; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ren1_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ren1; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ren2_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ren2; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ren3_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ren3; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_swap12_0 = io_lsu_brupdate_b2_uop_fp_ctrl_swap12; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_swap23_0 = io_lsu_brupdate_b2_uop_fp_ctrl_swap23; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_fromint_0 = io_lsu_brupdate_b2_uop_fp_ctrl_fromint; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_toint_0 = io_lsu_brupdate_b2_uop_fp_ctrl_toint; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_fma_0 = io_lsu_brupdate_b2_uop_fp_ctrl_fma; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_div_0 = io_lsu_brupdate_b2_uop_fp_ctrl_div; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_lsu_brupdate_b2_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_wflags_0 = io_lsu_brupdate_b2_uop_fp_ctrl_wflags; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_vec_0 = io_lsu_brupdate_b2_uop_fp_ctrl_vec; // @[dcache.scala:438:7]
wire [5:0] io_lsu_brupdate_b2_uop_rob_idx_0 = io_lsu_brupdate_b2_uop_rob_idx; // @[dcache.scala:438:7]
wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx_0 = io_lsu_brupdate_b2_uop_ldq_idx; // @[dcache.scala:438:7]
wire [3:0] io_lsu_brupdate_b2_uop_stq_idx_0 = io_lsu_brupdate_b2_uop_stq_idx; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0 = io_lsu_brupdate_b2_uop_rxq_idx; // @[dcache.scala:438:7]
wire [6:0] io_lsu_brupdate_b2_uop_pdst_0 = io_lsu_brupdate_b2_uop_pdst; // @[dcache.scala:438:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs1_0 = io_lsu_brupdate_b2_uop_prs1; // @[dcache.scala:438:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs2_0 = io_lsu_brupdate_b2_uop_prs2; // @[dcache.scala:438:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs3_0 = io_lsu_brupdate_b2_uop_prs3; // @[dcache.scala:438:7]
wire [4:0] io_lsu_brupdate_b2_uop_ppred_0 = io_lsu_brupdate_b2_uop_ppred; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_prs1_busy_0 = io_lsu_brupdate_b2_uop_prs1_busy; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_prs2_busy_0 = io_lsu_brupdate_b2_uop_prs2_busy; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_prs3_busy_0 = io_lsu_brupdate_b2_uop_prs3_busy; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_ppred_busy_0 = io_lsu_brupdate_b2_uop_ppred_busy; // @[dcache.scala:438:7]
wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0 = io_lsu_brupdate_b2_uop_stale_pdst; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_exception_0 = io_lsu_brupdate_b2_uop_exception; // @[dcache.scala:438:7]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0 = io_lsu_brupdate_b2_uop_exc_cause; // @[dcache.scala:438:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0 = io_lsu_brupdate_b2_uop_mem_cmd; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0 = io_lsu_brupdate_b2_uop_mem_size; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_mem_signed_0 = io_lsu_brupdate_b2_uop_mem_signed; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_uses_ldq_0 = io_lsu_brupdate_b2_uop_uses_ldq; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_uses_stq_0 = io_lsu_brupdate_b2_uop_uses_stq; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_is_unique_0 = io_lsu_brupdate_b2_uop_is_unique; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit_0 = io_lsu_brupdate_b2_uop_flush_on_commit; // @[dcache.scala:438:7]
wire [2:0] io_lsu_brupdate_b2_uop_csr_cmd_0 = io_lsu_brupdate_b2_uop_csr_cmd; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[dcache.scala:438:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst_0 = io_lsu_brupdate_b2_uop_ldst; // @[dcache.scala:438:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0 = io_lsu_brupdate_b2_uop_lrs1; // @[dcache.scala:438:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0 = io_lsu_brupdate_b2_uop_lrs2; // @[dcache.scala:438:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0 = io_lsu_brupdate_b2_uop_lrs3; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0 = io_lsu_brupdate_b2_uop_dst_rtype; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0 = io_lsu_brupdate_b2_uop_lrs1_rtype; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0 = io_lsu_brupdate_b2_uop_lrs2_rtype; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_frs3_en_0 = io_lsu_brupdate_b2_uop_frs3_en; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fcn_dw_0 = io_lsu_brupdate_b2_uop_fcn_dw; // @[dcache.scala:438:7]
wire [4:0] io_lsu_brupdate_b2_uop_fcn_op_0 = io_lsu_brupdate_b2_uop_fcn_op; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_fp_val_0 = io_lsu_brupdate_b2_uop_fp_val; // @[dcache.scala:438:7]
wire [2:0] io_lsu_brupdate_b2_uop_fp_rm_0 = io_lsu_brupdate_b2_uop_fp_rm; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_uop_fp_typ_0 = io_lsu_brupdate_b2_uop_fp_typ; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if_0 = io_lsu_brupdate_b2_uop_bp_debug_if; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[dcache.scala:438:7]
wire [2:0] io_lsu_brupdate_b2_uop_debug_fsrc_0 = io_lsu_brupdate_b2_uop_debug_fsrc; // @[dcache.scala:438:7]
wire [2:0] io_lsu_brupdate_b2_uop_debug_tsrc_0 = io_lsu_brupdate_b2_uop_debug_tsrc; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_mispredict_0 = io_lsu_brupdate_b2_mispredict; // @[dcache.scala:438:7]
wire io_lsu_brupdate_b2_taken_0 = io_lsu_brupdate_b2_taken; // @[dcache.scala:438:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type_0 = io_lsu_brupdate_b2_cfi_type; // @[dcache.scala:438:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel_0 = io_lsu_brupdate_b2_pc_sel; // @[dcache.scala:438:7]
wire [39:0] io_lsu_brupdate_b2_jalr_target_0 = io_lsu_brupdate_b2_jalr_target; // @[dcache.scala:438:7]
wire [20:0] io_lsu_brupdate_b2_target_offset_0 = io_lsu_brupdate_b2_target_offset; // @[dcache.scala:438:7]
wire io_lsu_exception_0 = io_lsu_exception; // @[dcache.scala:438:7]
wire [5:0] io_lsu_rob_pnr_idx_0 = io_lsu_rob_pnr_idx; // @[dcache.scala:438:7]
wire [5:0] io_lsu_rob_head_idx_0 = io_lsu_rob_head_idx; // @[dcache.scala:438:7]
wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:438:7]
wire io_lsu_force_order_0 = io_lsu_force_order; // @[dcache.scala:438:7]
wire auto_out_a_bits_corrupt = 1'h0; // @[dcache.scala:438:7]
wire auto_out_c_bits_corrupt = 1'h0; // @[dcache.scala:438:7]
wire io_errors_bus_valid = 1'h0; // @[dcache.scala:438:7]
wire io_lsu_s1_nack_advisory_0 = 1'h0; // @[dcache.scala:438:7]
wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:438:7]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire singlePortedDCacheWrite = 1'h0; // @[dcache.scala:503:53]
wire mshr_read_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_fence = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_amo = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_eret = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_mov = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_taken = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_exception = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_is_unique = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_fp_val = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:549:27]
wire mshr_read_req_0_is_hella = 1'h0; // @[dcache.scala:549:27]
wire _mshr_read_req_0_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57]
wire _mshr_read_req_0_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57]
wire wb_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_fence = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_amo = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_eret = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_mov = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_taken = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_exception = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_is_unique = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_fp_val = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:564:20]
wire wb_req_0_is_hella = 1'h0; // @[dcache.scala:564:20]
wire _wb_req_0_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57]
wire _wb_req_0_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57]
wire prober_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_fence = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_amo = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_eret = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_mov = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_taken = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_exception = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_is_unique = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_fp_val = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:586:26]
wire prober_req_0_is_hella = 1'h0; // @[dcache.scala:586:26]
wire _prober_req_0_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57]
wire _prober_req_0_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57]
wire prefetch_fire = 1'h0; // @[Decoupled.scala:51:35]
wire prefetch_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_fence = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_amo = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_eret = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_mov = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_taken = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_exception = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_is_unique = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_fp_val = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:601:27]
wire prefetch_req_0_is_hella = 1'h0; // @[dcache.scala:601:27]
wire _s0_valid_WIRE_2_0 = 1'h0; // @[dcache.scala:614:82]
wire _s2_has_permission_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire s2_word_idx_0 = 1'h0; // @[dcache.scala:454:49]
wire _s2_nack_data_T = 1'h0; // @[dcache.scala:766:50]
wire s2_nack_data_0 = 1'h0; // @[dcache.scala:454:49]
wire opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _nodeOut_c_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire io_lsu_resp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_lsu_resp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire _mshrs_io_replay_ready_T_1 = 1'h1; // @[dcache.scala:534:91]
wire _metaReadArb_io_in_0_valid_T = 1'h1; // @[dcache.scala:537:71]
wire _dataReadArb_io_in_0_valid_T = 1'h1; // @[dcache.scala:542:71]
wire _metaReadArb_io_in_2_valid_T = 1'h1; // @[dcache.scala:573:65]
wire _wb_io_meta_read_ready_T_1 = 1'h1; // @[dcache.scala:575:88]
wire _dataReadArb_io_in_1_valid_T = 1'h1; // @[dcache.scala:577:64]
wire _wb_io_data_req_ready_T_1 = 1'h1; // @[dcache.scala:580:88]
wire _s0_valid_WIRE_1_0 = 1'h1; // @[dcache.scala:614:48]
wire _mshrs_io_req_0_valid_T_6 = 1'h1; // @[dcache.scala:795:29]
wire [31:0] io_errors_bus_bits = 32'h0; // @[dcache.scala:438:7]
wire [31:0] mshr_read_req_0_uop_inst = 32'h0; // @[dcache.scala:549:27]
wire [31:0] mshr_read_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:549:27]
wire [31:0] _mshr_read_req_0_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57]
wire [31:0] _mshr_read_req_0_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57]
wire [31:0] wb_req_0_uop_inst = 32'h0; // @[dcache.scala:564:20]
wire [31:0] wb_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:564:20]
wire [31:0] _wb_req_0_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57]
wire [31:0] _wb_req_0_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57]
wire [31:0] prober_req_0_uop_inst = 32'h0; // @[dcache.scala:586:26]
wire [31:0] prober_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:586:26]
wire [31:0] _prober_req_0_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57]
wire [31:0] _prober_req_0_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57]
wire [31:0] prefetch_req_0_uop_inst = 32'h0; // @[dcache.scala:601:27]
wire [31:0] prefetch_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:601:27]
wire [6:0] mshr_read_req_0_uop_pdst = 7'h0; // @[dcache.scala:549:27]
wire [6:0] mshr_read_req_0_uop_prs1 = 7'h0; // @[dcache.scala:549:27]
wire [6:0] mshr_read_req_0_uop_prs2 = 7'h0; // @[dcache.scala:549:27]
wire [6:0] mshr_read_req_0_uop_prs3 = 7'h0; // @[dcache.scala:549:27]
wire [6:0] mshr_read_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:549:27]
wire [6:0] _mshr_read_req_0_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57]
wire [6:0] _mshr_read_req_0_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _mshr_read_req_0_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _mshr_read_req_0_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _mshr_read_req_0_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57]
wire [6:0] wb_req_0_uop_pdst = 7'h0; // @[dcache.scala:564:20]
wire [6:0] wb_req_0_uop_prs1 = 7'h0; // @[dcache.scala:564:20]
wire [6:0] wb_req_0_uop_prs2 = 7'h0; // @[dcache.scala:564:20]
wire [6:0] wb_req_0_uop_prs3 = 7'h0; // @[dcache.scala:564:20]
wire [6:0] wb_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:564:20]
wire [6:0] _wb_req_0_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57]
wire [6:0] _wb_req_0_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _wb_req_0_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _wb_req_0_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _wb_req_0_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57]
wire [6:0] prober_req_0_uop_pdst = 7'h0; // @[dcache.scala:586:26]
wire [6:0] prober_req_0_uop_prs1 = 7'h0; // @[dcache.scala:586:26]
wire [6:0] prober_req_0_uop_prs2 = 7'h0; // @[dcache.scala:586:26]
wire [6:0] prober_req_0_uop_prs3 = 7'h0; // @[dcache.scala:586:26]
wire [6:0] prober_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:586:26]
wire [6:0] _prober_req_0_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57]
wire [6:0] _prober_req_0_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _prober_req_0_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _prober_req_0_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57]
wire [6:0] _prober_req_0_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57]
wire [6:0] prefetch_req_0_uop_pdst = 7'h0; // @[dcache.scala:601:27]
wire [6:0] prefetch_req_0_uop_prs1 = 7'h0; // @[dcache.scala:601:27]
wire [6:0] prefetch_req_0_uop_prs2 = 7'h0; // @[dcache.scala:601:27]
wire [6:0] prefetch_req_0_uop_prs3 = 7'h0; // @[dcache.scala:601:27]
wire [6:0] prefetch_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:601:27]
wire [6:0] _s2_data_word_prebypass_T = 7'h0; // @[dcache.scala:868:69]
wire [63:0] mshr_read_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:549:27]
wire [63:0] mshr_read_req_0_data = 64'h0; // @[dcache.scala:549:27]
wire [63:0] _mshr_read_req_0_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57]
wire [63:0] wb_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:564:20]
wire [63:0] wb_req_0_data = 64'h0; // @[dcache.scala:564:20]
wire [63:0] _wb_req_0_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57]
wire [63:0] prober_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:586:26]
wire [63:0] prober_req_0_data = 64'h0; // @[dcache.scala:586:26]
wire [63:0] _prober_req_0_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57]
wire [63:0] prefetch_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:601:27]
wire [63:0] prefetch_req_0_data = 64'h0; // @[dcache.scala:601:27]
wire [63:0] _nodeOut_c_bits_T_4 = 64'h0; // @[Mux.scala:30:73]
wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69]
wire [8:0] decode = 9'h7; // @[Edges.scala:220:59]
wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [3:0] _s2_has_permission_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_new_hit_state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_has_permission_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_new_hit_state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_has_permission_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_new_hit_state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_has_permission_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_new_hit_state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_has_permission_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _s2_new_hit_state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] mshr_read_req_0_uop_br_tag = 4'h0; // @[dcache.scala:549:27]
wire [3:0] mshr_read_req_0_uop_br_type = 4'h0; // @[dcache.scala:549:27]
wire [3:0] mshr_read_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:549:27]
wire [3:0] mshr_read_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:549:27]
wire [3:0] _mshr_read_req_0_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57]
wire [3:0] _mshr_read_req_0_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57]
wire [3:0] _mshr_read_req_0_uop_WIRE_ldq_idx = 4'h0; // @[consts.scala:141:57]
wire [3:0] _mshr_read_req_0_uop_WIRE_stq_idx = 4'h0; // @[consts.scala:141:57]
wire [3:0] wb_req_0_uop_br_tag = 4'h0; // @[dcache.scala:564:20]
wire [3:0] wb_req_0_uop_br_type = 4'h0; // @[dcache.scala:564:20]
wire [3:0] wb_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:564:20]
wire [3:0] wb_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:564:20]
wire [3:0] _wb_req_0_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57]
wire [3:0] _wb_req_0_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57]
wire [3:0] _wb_req_0_uop_WIRE_ldq_idx = 4'h0; // @[consts.scala:141:57]
wire [3:0] _wb_req_0_uop_WIRE_stq_idx = 4'h0; // @[consts.scala:141:57]
wire [3:0] prober_req_0_uop_br_tag = 4'h0; // @[dcache.scala:586:26]
wire [3:0] prober_req_0_uop_br_type = 4'h0; // @[dcache.scala:586:26]
wire [3:0] prober_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:586:26]
wire [3:0] prober_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:586:26]
wire [3:0] _prober_req_0_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57]
wire [3:0] _prober_req_0_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57]
wire [3:0] _prober_req_0_uop_WIRE_ldq_idx = 4'h0; // @[consts.scala:141:57]
wire [3:0] _prober_req_0_uop_WIRE_stq_idx = 4'h0; // @[consts.scala:141:57]
wire [3:0] prefetch_req_0_uop_br_tag = 4'h0; // @[dcache.scala:601:27]
wire [3:0] prefetch_req_0_uop_br_type = 4'h0; // @[dcache.scala:601:27]
wire [3:0] prefetch_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:601:27]
wire [3:0] prefetch_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:601:27]
wire [3:0] _s2_has_permission_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _s2_new_hit_state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [1:0] mshr_read_req_0_uop_iw_p1_speculative_child = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_iw_p2_speculative_child = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_dis_col_sel = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_mem_size = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:549:27]
wire [1:0] mshr_read_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:549:27]
wire [1:0] _mshr_read_req_0_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_dis_col_sel = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _mshr_read_req_0_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57]
wire [1:0] wb_req_0_uop_iw_p1_speculative_child = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_iw_p2_speculative_child = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_dis_col_sel = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_mem_size = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:564:20]
wire [1:0] wb_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:564:20]
wire [1:0] _wb_req_0_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_dis_col_sel = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _wb_req_0_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57]
wire [1:0] prober_req_0_uop_iw_p1_speculative_child = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_iw_p2_speculative_child = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_dis_col_sel = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_mem_size = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:586:26]
wire [1:0] prober_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:586:26]
wire [1:0] _prober_req_0_uop_WIRE_iw_p1_speculative_child = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_iw_p2_speculative_child = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_dis_col_sel = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57]
wire [1:0] _prober_req_0_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57]
wire [1:0] prefetch_req_0_uop_iw_p1_speculative_child = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_iw_p2_speculative_child = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_dis_col_sel = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_mem_size = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:601:27]
wire [1:0] prefetch_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:601:27]
wire [1:0] _s2_has_permission_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [3:0] _s2_has_permission_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _s2_new_hit_state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _dataReadArb_io_in_2_bits_req_0_way_en_T = 4'hF; // @[dcache.scala:522:48]
wire [3:0] _s2_has_permission_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _s2_new_hit_state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _s2_has_permission_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_new_hit_state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_has_permission_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_new_hit_state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_has_permission_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_new_hit_state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_has_permission_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _s2_new_hit_state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [33:0] _metaReadArb_io_in_5_bits_req_0_idx_T = 34'h0; // @[dcache.scala:606:74]
wire [39:0] mshr_read_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:549:27]
wire [39:0] _mshr_read_req_0_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57]
wire [39:0] wb_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:564:20]
wire [39:0] _wb_req_0_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57]
wire [39:0] prober_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:586:26]
wire [39:0] _prober_req_0_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57]
wire [39:0] prefetch_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:601:27]
wire [39:0] prefetch_req_0_addr = 40'h0; // @[dcache.scala:601:27]
wire [2:0] mshr_read_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:549:27]
wire [2:0] mshr_read_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:549:27]
wire [2:0] mshr_read_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:549:27]
wire [2:0] mshr_read_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:549:27]
wire [2:0] mshr_read_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:549:27]
wire [2:0] mshr_read_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:549:27]
wire [2:0] _mshr_read_req_0_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57]
wire [2:0] _mshr_read_req_0_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57]
wire [2:0] _mshr_read_req_0_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57]
wire [2:0] _mshr_read_req_0_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57]
wire [2:0] _mshr_read_req_0_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57]
wire [2:0] _mshr_read_req_0_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57]
wire [2:0] wb_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:564:20]
wire [2:0] wb_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:564:20]
wire [2:0] wb_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:564:20]
wire [2:0] wb_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:564:20]
wire [2:0] wb_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:564:20]
wire [2:0] wb_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:564:20]
wire [2:0] _wb_req_0_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57]
wire [2:0] _wb_req_0_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57]
wire [2:0] _wb_req_0_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57]
wire [2:0] _wb_req_0_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57]
wire [2:0] _wb_req_0_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57]
wire [2:0] _wb_req_0_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57]
wire [2:0] prober_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:586:26]
wire [2:0] prober_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:586:26]
wire [2:0] prober_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:586:26]
wire [2:0] prober_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:586:26]
wire [2:0] prober_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:586:26]
wire [2:0] prober_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:586:26]
wire [2:0] _prober_req_0_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57]
wire [2:0] _prober_req_0_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57]
wire [2:0] _prober_req_0_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57]
wire [2:0] _prober_req_0_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57]
wire [2:0] _prober_req_0_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57]
wire [2:0] _prober_req_0_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57]
wire [2:0] prefetch_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:601:27]
wire [2:0] prefetch_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:601:27]
wire [2:0] prefetch_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:601:27]
wire [2:0] prefetch_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:601:27]
wire [2:0] prefetch_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:601:27]
wire [2:0] prefetch_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:601:27]
wire [4:0] mshr_read_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:549:27]
wire [4:0] mshr_read_req_0_uop_pimm = 5'h0; // @[dcache.scala:549:27]
wire [4:0] mshr_read_req_0_uop_ppred = 5'h0; // @[dcache.scala:549:27]
wire [4:0] mshr_read_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:549:27]
wire [4:0] mshr_read_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:549:27]
wire [4:0] _mshr_read_req_0_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57]
wire [4:0] _mshr_read_req_0_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57]
wire [4:0] _mshr_read_req_0_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57]
wire [4:0] _mshr_read_req_0_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57]
wire [4:0] _mshr_read_req_0_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57]
wire [4:0] wb_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:564:20]
wire [4:0] wb_req_0_uop_pimm = 5'h0; // @[dcache.scala:564:20]
wire [4:0] wb_req_0_uop_ppred = 5'h0; // @[dcache.scala:564:20]
wire [4:0] wb_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:564:20]
wire [4:0] wb_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:564:20]
wire [4:0] _wb_req_0_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57]
wire [4:0] _wb_req_0_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57]
wire [4:0] _wb_req_0_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57]
wire [4:0] _wb_req_0_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57]
wire [4:0] _wb_req_0_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57]
wire [4:0] prober_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:586:26]
wire [4:0] prober_req_0_uop_pimm = 5'h0; // @[dcache.scala:586:26]
wire [4:0] prober_req_0_uop_ppred = 5'h0; // @[dcache.scala:586:26]
wire [4:0] prober_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:586:26]
wire [4:0] prober_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:586:26]
wire [4:0] _prober_req_0_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57]
wire [4:0] _prober_req_0_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57]
wire [4:0] _prober_req_0_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57]
wire [4:0] _prober_req_0_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57]
wire [4:0] _prober_req_0_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57]
wire [4:0] prefetch_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:601:27]
wire [4:0] prefetch_req_0_uop_pimm = 5'h0; // @[dcache.scala:601:27]
wire [4:0] prefetch_req_0_uop_ppred = 5'h0; // @[dcache.scala:601:27]
wire [4:0] prefetch_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:601:27]
wire [4:0] prefetch_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:601:27]
wire [5:0] mshr_read_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:549:27]
wire [5:0] mshr_read_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:549:27]
wire [5:0] mshr_read_req_0_uop_ldst = 6'h0; // @[dcache.scala:549:27]
wire [5:0] mshr_read_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:549:27]
wire [5:0] mshr_read_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:549:27]
wire [5:0] mshr_read_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:549:27]
wire [5:0] _mshr_read_req_0_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57]
wire [5:0] _mshr_read_req_0_uop_WIRE_rob_idx = 6'h0; // @[consts.scala:141:57]
wire [5:0] _mshr_read_req_0_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57]
wire [5:0] _mshr_read_req_0_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57]
wire [5:0] _mshr_read_req_0_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57]
wire [5:0] _mshr_read_req_0_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57]
wire [5:0] wb_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:564:20]
wire [5:0] wb_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:564:20]
wire [5:0] wb_req_0_uop_ldst = 6'h0; // @[dcache.scala:564:20]
wire [5:0] wb_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:564:20]
wire [5:0] wb_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:564:20]
wire [5:0] wb_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:564:20]
wire [5:0] _wb_req_0_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57]
wire [5:0] _wb_req_0_uop_WIRE_rob_idx = 6'h0; // @[consts.scala:141:57]
wire [5:0] _wb_req_0_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57]
wire [5:0] _wb_req_0_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57]
wire [5:0] _wb_req_0_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57]
wire [5:0] _wb_req_0_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57]
wire [5:0] prober_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:586:26]
wire [5:0] prober_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:586:26]
wire [5:0] prober_req_0_uop_ldst = 6'h0; // @[dcache.scala:586:26]
wire [5:0] prober_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:586:26]
wire [5:0] prober_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:586:26]
wire [5:0] prober_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:586:26]
wire [5:0] _prober_req_0_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57]
wire [5:0] _prober_req_0_uop_WIRE_rob_idx = 6'h0; // @[consts.scala:141:57]
wire [5:0] _prober_req_0_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57]
wire [5:0] _prober_req_0_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57]
wire [5:0] _prober_req_0_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57]
wire [5:0] _prober_req_0_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57]
wire [5:0] prefetch_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:601:27]
wire [5:0] prefetch_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:601:27]
wire [5:0] prefetch_req_0_uop_ldst = 6'h0; // @[dcache.scala:601:27]
wire [5:0] prefetch_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:601:27]
wire [5:0] prefetch_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:601:27]
wire [5:0] prefetch_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:601:27]
wire [19:0] mshr_read_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:549:27]
wire [19:0] _mshr_read_req_0_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57]
wire [19:0] wb_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:564:20]
wire [19:0] _wb_req_0_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57]
wire [19:0] prober_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:586:26]
wire [19:0] _prober_req_0_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57]
wire [19:0] prefetch_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:601:27]
wire [11:0] mshr_read_req_0_uop_br_mask = 12'h0; // @[dcache.scala:549:27]
wire [11:0] _mshr_read_req_0_uop_WIRE_br_mask = 12'h0; // @[consts.scala:141:57]
wire [11:0] wb_req_0_uop_br_mask = 12'h0; // @[dcache.scala:564:20]
wire [11:0] _wb_req_0_uop_WIRE_br_mask = 12'h0; // @[consts.scala:141:57]
wire [11:0] prober_req_0_uop_br_mask = 12'h0; // @[dcache.scala:586:26]
wire [11:0] _prober_req_0_uop_WIRE_br_mask = 12'h0; // @[consts.scala:141:57]
wire [11:0] prefetch_req_0_uop_br_mask = 12'h0; // @[dcache.scala:601:27]
wire [1:0] _s2_has_permission_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _dataWriteArb_io_in_0_bits_wmask_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _s2_has_permission_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _io_lsu_req_ready_T_2; // @[dcache.scala:511:80]
wire _s0_valid_WIRE_0 = io_lsu_req_bits_0_valid_0; // @[dcache.scala:438:7, :612:46]
wire [31:0] _s0_req_WIRE_0_uop_inst = io_lsu_req_bits_0_bits_uop_inst_0; // @[dcache.scala:438:7, :615:56]
wire [31:0] _s0_req_WIRE_0_uop_debug_inst = io_lsu_req_bits_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_rvc = io_lsu_req_bits_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7, :615:56]
wire [39:0] _s0_req_WIRE_0_uop_debug_pc = io_lsu_req_bits_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iq_type_0 = io_lsu_req_bits_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iq_type_1 = io_lsu_req_bits_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iq_type_2 = io_lsu_req_bits_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iq_type_3 = io_lsu_req_bits_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_0 = io_lsu_req_bits_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_1 = io_lsu_req_bits_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_2 = io_lsu_req_bits_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_3 = io_lsu_req_bits_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_4 = io_lsu_req_bits_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_5 = io_lsu_req_bits_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_6 = io_lsu_req_bits_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_7 = io_lsu_req_bits_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_8 = io_lsu_req_bits_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fu_code_9 = io_lsu_req_bits_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iw_issued = io_lsu_req_bits_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iw_issued_partial_agen = io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iw_issued_partial_dgen = io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_iw_p1_speculative_child = io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_iw_p2_speculative_child = io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iw_p1_bypass_hint = io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iw_p2_bypass_hint = io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_iw_p3_bypass_hint = io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_dis_col_sel = io_lsu_req_bits_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7, :615:56]
wire [11:0] _s0_req_WIRE_0_uop_br_mask = io_lsu_req_bits_0_bits_uop_br_mask_0; // @[dcache.scala:438:7, :615:56]
wire [3:0] _s0_req_WIRE_0_uop_br_tag = io_lsu_req_bits_0_bits_uop_br_tag_0; // @[dcache.scala:438:7, :615:56]
wire [3:0] _s0_req_WIRE_0_uop_br_type = io_lsu_req_bits_0_bits_uop_br_type_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_sfb = io_lsu_req_bits_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_fence = io_lsu_req_bits_0_bits_uop_is_fence_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_fencei = io_lsu_req_bits_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_sfence = io_lsu_req_bits_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_amo = io_lsu_req_bits_0_bits_uop_is_amo_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_eret = io_lsu_req_bits_0_bits_uop_is_eret_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_sys_pc2epc = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_rocc = io_lsu_req_bits_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_mov = io_lsu_req_bits_0_bits_uop_is_mov_0; // @[dcache.scala:438:7, :615:56]
wire [4:0] _s0_req_WIRE_0_uop_ftq_idx = io_lsu_req_bits_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_edge_inst = io_lsu_req_bits_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7, :615:56]
wire [5:0] _s0_req_WIRE_0_uop_pc_lob = io_lsu_req_bits_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_taken = io_lsu_req_bits_0_bits_uop_taken_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_imm_rename = io_lsu_req_bits_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7, :615:56]
wire [2:0] _s0_req_WIRE_0_uop_imm_sel = io_lsu_req_bits_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7, :615:56]
wire [4:0] _s0_req_WIRE_0_uop_pimm = io_lsu_req_bits_0_bits_uop_pimm_0; // @[dcache.scala:438:7, :615:56]
wire [19:0] _s0_req_WIRE_0_uop_imm_packed = io_lsu_req_bits_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_op1_sel = io_lsu_req_bits_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7, :615:56]
wire [2:0] _s0_req_WIRE_0_uop_op2_sel = io_lsu_req_bits_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_ldst = io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_wen = io_lsu_req_bits_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_ren1 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_ren2 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_ren3 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_swap12 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_swap23 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_fp_ctrl_typeTagIn = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_fp_ctrl_typeTagOut = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_fromint = io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_toint = io_lsu_req_bits_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_fastpipe = io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_fma = io_lsu_req_bits_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_div = io_lsu_req_bits_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_sqrt = io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_wflags = io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_ctrl_vec = io_lsu_req_bits_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7, :615:56]
wire [5:0] _s0_req_WIRE_0_uop_rob_idx = io_lsu_req_bits_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7, :615:56]
wire [3:0] _s0_req_WIRE_0_uop_ldq_idx = io_lsu_req_bits_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7, :615:56]
wire [3:0] _s0_req_WIRE_0_uop_stq_idx = io_lsu_req_bits_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_rxq_idx = io_lsu_req_bits_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7, :615:56]
wire [6:0] _s0_req_WIRE_0_uop_pdst = io_lsu_req_bits_0_bits_uop_pdst_0; // @[dcache.scala:438:7, :615:56]
wire [6:0] _s0_req_WIRE_0_uop_prs1 = io_lsu_req_bits_0_bits_uop_prs1_0; // @[dcache.scala:438:7, :615:56]
wire [6:0] _s0_req_WIRE_0_uop_prs2 = io_lsu_req_bits_0_bits_uop_prs2_0; // @[dcache.scala:438:7, :615:56]
wire [6:0] _s0_req_WIRE_0_uop_prs3 = io_lsu_req_bits_0_bits_uop_prs3_0; // @[dcache.scala:438:7, :615:56]
wire [4:0] _s0_req_WIRE_0_uop_ppred = io_lsu_req_bits_0_bits_uop_ppred_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_prs1_busy = io_lsu_req_bits_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_prs2_busy = io_lsu_req_bits_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_prs3_busy = io_lsu_req_bits_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_ppred_busy = io_lsu_req_bits_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7, :615:56]
wire [6:0] _s0_req_WIRE_0_uop_stale_pdst = io_lsu_req_bits_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_exception = io_lsu_req_bits_0_bits_uop_exception_0; // @[dcache.scala:438:7, :615:56]
wire [63:0] _s0_req_WIRE_0_uop_exc_cause = io_lsu_req_bits_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7, :615:56]
wire [4:0] _s0_req_WIRE_0_uop_mem_cmd = io_lsu_req_bits_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_mem_size = io_lsu_req_bits_0_bits_uop_mem_size_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_mem_signed = io_lsu_req_bits_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_uses_ldq = io_lsu_req_bits_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_uses_stq = io_lsu_req_bits_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_is_unique = io_lsu_req_bits_0_bits_uop_is_unique_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_flush_on_commit = io_lsu_req_bits_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7, :615:56]
wire [2:0] _s0_req_WIRE_0_uop_csr_cmd = io_lsu_req_bits_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_ldst_is_rs1 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7, :615:56]
wire [5:0] _s0_req_WIRE_0_uop_ldst = io_lsu_req_bits_0_bits_uop_ldst_0; // @[dcache.scala:438:7, :615:56]
wire [5:0] _s0_req_WIRE_0_uop_lrs1 = io_lsu_req_bits_0_bits_uop_lrs1_0; // @[dcache.scala:438:7, :615:56]
wire [5:0] _s0_req_WIRE_0_uop_lrs2 = io_lsu_req_bits_0_bits_uop_lrs2_0; // @[dcache.scala:438:7, :615:56]
wire [5:0] _s0_req_WIRE_0_uop_lrs3 = io_lsu_req_bits_0_bits_uop_lrs3_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_dst_rtype = io_lsu_req_bits_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_lrs1_rtype = io_lsu_req_bits_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_lrs2_rtype = io_lsu_req_bits_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_frs3_en = io_lsu_req_bits_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fcn_dw = io_lsu_req_bits_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7, :615:56]
wire [4:0] _s0_req_WIRE_0_uop_fcn_op = io_lsu_req_bits_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_fp_val = io_lsu_req_bits_0_bits_uop_fp_val_0; // @[dcache.scala:438:7, :615:56]
wire [2:0] _s0_req_WIRE_0_uop_fp_rm = io_lsu_req_bits_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7, :615:56]
wire [1:0] _s0_req_WIRE_0_uop_fp_typ = io_lsu_req_bits_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_xcpt_pf_if = io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_xcpt_ae_if = io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_xcpt_ma_if = io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_bp_debug_if = io_lsu_req_bits_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_uop_bp_xcpt_if = io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7, :615:56]
wire [2:0] _s0_req_WIRE_0_uop_debug_fsrc = io_lsu_req_bits_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7, :615:56]
wire [2:0] _s0_req_WIRE_0_uop_debug_tsrc = io_lsu_req_bits_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7, :615:56]
wire [39:0] _s0_req_WIRE_0_addr = io_lsu_req_bits_0_bits_addr_0; // @[dcache.scala:438:7, :615:56]
wire [63:0] _s0_req_WIRE_0_data = io_lsu_req_bits_0_bits_data_0; // @[dcache.scala:438:7, :615:56]
wire _s0_req_WIRE_0_is_hella = io_lsu_req_bits_0_bits_is_hella_0; // @[dcache.scala:438:7, :615:56]
wire _io_lsu_resp_0_valid_T; // @[dcache.scala:877:41]
wire [63:0] _io_lsu_resp_0_bits_data_T_24; // @[dcache.scala:879:49]
wire _io_lsu_store_ack_0_valid_T_1; // @[dcache.scala:888:70]
wire _io_lsu_nack_0_valid_T; // @[dcache.scala:884:41]
wire _io_lsu_ordered_T_3; // @[dcache.scala:941:66]
wire io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [2:0] auto_out_a_bits_opcode_0; // @[dcache.scala:438:7]
wire [2:0] auto_out_a_bits_param_0; // @[dcache.scala:438:7]
wire [3:0] auto_out_a_bits_size_0; // @[dcache.scala:438:7]
wire [1:0] auto_out_a_bits_source_0; // @[dcache.scala:438:7]
wire [31:0] auto_out_a_bits_address_0; // @[dcache.scala:438:7]
wire [7:0] auto_out_a_bits_mask_0; // @[dcache.scala:438:7]
wire [63:0] auto_out_a_bits_data_0; // @[dcache.scala:438:7]
wire auto_out_a_valid_0; // @[dcache.scala:438:7]
wire auto_out_b_ready_0; // @[dcache.scala:438:7]
wire [2:0] auto_out_c_bits_opcode_0; // @[dcache.scala:438:7]
wire [2:0] auto_out_c_bits_param_0; // @[dcache.scala:438:7]
wire [3:0] auto_out_c_bits_size_0; // @[dcache.scala:438:7]
wire [1:0] auto_out_c_bits_source_0; // @[dcache.scala:438:7]
wire [31:0] auto_out_c_bits_address_0; // @[dcache.scala:438:7]
wire [63:0] auto_out_c_bits_data_0; // @[dcache.scala:438:7]
wire auto_out_c_valid_0; // @[dcache.scala:438:7]
wire auto_out_d_ready_0; // @[dcache.scala:438:7]
wire [2:0] auto_out_e_bits_sink_0; // @[dcache.scala:438:7]
wire auto_out_e_valid_0; // @[dcache.scala:438:7]
wire io_lsu_req_ready_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_resp_0_bits_uop_inst_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_resp_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7]
wire [39:0] io_lsu_resp_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7]
wire [11:0] io_lsu_resp_0_bits_uop_br_mask_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_resp_0_bits_uop_br_tag_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_resp_0_bits_uop_br_type_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_fence_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_amo_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_eret_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_mov_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_resp_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_resp_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_taken_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_resp_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_resp_0_bits_uop_pimm_0; // @[dcache.scala:438:7]
wire [19:0] io_lsu_resp_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_resp_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_resp_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_resp_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_resp_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_resp_0_bits_uop_pdst_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs1_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs2_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs3_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_resp_0_bits_uop_ppred_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_resp_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_exception_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_resp_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_resp_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_mem_size_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_is_unique_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_resp_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_resp_0_bits_uop_ldst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs2_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs3_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_resp_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_fp_val_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_resp_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_resp_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_resp_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_resp_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_resp_0_bits_data_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_bits_is_hella_0; // @[dcache.scala:438:7]
wire io_lsu_resp_0_valid_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_store_ack_0_bits_uop_inst_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_store_ack_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7]
wire [39:0] io_lsu_store_ack_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7]
wire [11:0] io_lsu_store_ack_0_bits_uop_br_mask_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_store_ack_0_bits_uop_br_tag_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_store_ack_0_bits_uop_br_type_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_fence_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_amo_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_eret_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_mov_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_store_ack_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_store_ack_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_taken_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_store_ack_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_store_ack_0_bits_uop_pimm_0; // @[dcache.scala:438:7]
wire [19:0] io_lsu_store_ack_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_store_ack_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_store_ack_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_store_ack_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_store_ack_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_store_ack_0_bits_uop_pdst_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_store_ack_0_bits_uop_prs1_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_store_ack_0_bits_uop_prs2_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_store_ack_0_bits_uop_prs3_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_store_ack_0_bits_uop_ppred_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_store_ack_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_exception_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_store_ack_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_store_ack_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_mem_size_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_is_unique_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_store_ack_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_store_ack_0_bits_uop_ldst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_store_ack_0_bits_uop_lrs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_store_ack_0_bits_uop_lrs2_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_store_ack_0_bits_uop_lrs3_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_store_ack_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_fp_val_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_store_ack_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_store_ack_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_store_ack_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_store_ack_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7]
wire [39:0] io_lsu_store_ack_0_bits_addr_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_store_ack_0_bits_data_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_bits_is_hella_0; // @[dcache.scala:438:7]
wire io_lsu_store_ack_0_valid_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_nack_0_bits_uop_inst_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_nack_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7]
wire [39:0] io_lsu_nack_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7]
wire [11:0] io_lsu_nack_0_bits_uop_br_mask_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_nack_0_bits_uop_br_tag_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_nack_0_bits_uop_br_type_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_fence_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_amo_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_eret_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_mov_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_nack_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_nack_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_taken_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_nack_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_nack_0_bits_uop_pimm_0; // @[dcache.scala:438:7]
wire [19:0] io_lsu_nack_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_nack_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_nack_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_nack_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_nack_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_nack_0_bits_uop_pdst_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs1_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs2_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs3_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_nack_0_bits_uop_ppred_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_nack_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_exception_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_nack_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_nack_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_mem_size_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_is_unique_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_nack_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_nack_0_bits_uop_ldst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs2_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs3_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_nack_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_fp_val_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_nack_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_nack_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_nack_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_nack_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7]
wire [39:0] io_lsu_nack_0_bits_addr_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_nack_0_bits_data_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_bits_is_hella_0; // @[dcache.scala:438:7]
wire io_lsu_nack_0_valid_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iq_type_0_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iq_type_1_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iq_type_2_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iq_type_3_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_0_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_1_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_2_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_3_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_4_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_5_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_6_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_7_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_8_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fu_code_9_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_ll_resp_bits_uop_inst_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_ll_resp_bits_uop_debug_inst_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_rvc_0; // @[dcache.scala:438:7]
wire [39:0] io_lsu_ll_resp_bits_uop_debug_pc_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iw_issued_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7]
wire [11:0] io_lsu_ll_resp_bits_uop_br_mask_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_ll_resp_bits_uop_br_tag_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_ll_resp_bits_uop_br_type_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_sfb_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_fence_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_fencei_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_sfence_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_amo_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_eret_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_rocc_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_mov_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_ll_resp_bits_uop_ftq_idx_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_edge_inst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_ll_resp_bits_uop_pc_lob_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_taken_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_imm_rename_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_ll_resp_bits_uop_imm_sel_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_ll_resp_bits_uop_pimm_0; // @[dcache.scala:438:7]
wire [19:0] io_lsu_ll_resp_bits_uop_imm_packed_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_op1_sel_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_ll_resp_bits_uop_op2_sel_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_ll_resp_bits_uop_rob_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_ll_resp_bits_uop_ldq_idx_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_ll_resp_bits_uop_stq_idx_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_rxq_idx_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_ll_resp_bits_uop_pdst_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_ll_resp_bits_uop_prs1_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_ll_resp_bits_uop_prs2_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_ll_resp_bits_uop_prs3_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_ll_resp_bits_uop_ppred_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_prs1_busy_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_prs2_busy_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_prs3_busy_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_ppred_busy_0; // @[dcache.scala:438:7]
wire [6:0] io_lsu_ll_resp_bits_uop_stale_pdst_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_exception_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_ll_resp_bits_uop_exc_cause_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_ll_resp_bits_uop_mem_cmd_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_mem_size_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_mem_signed_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_uses_ldq_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_uses_stq_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_is_unique_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_ll_resp_bits_uop_csr_cmd_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_ll_resp_bits_uop_ldst_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_ll_resp_bits_uop_lrs1_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_ll_resp_bits_uop_lrs2_0; // @[dcache.scala:438:7]
wire [5:0] io_lsu_ll_resp_bits_uop_lrs3_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_dst_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_frs3_en_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fcn_dw_0; // @[dcache.scala:438:7]
wire [4:0] io_lsu_ll_resp_bits_uop_fcn_op_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_fp_val_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_ll_resp_bits_uop_fp_rm_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_ll_resp_bits_uop_fp_typ_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_ll_resp_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_ll_resp_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_ll_resp_bits_data_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_bits_is_hella_0; // @[dcache.scala:438:7]
wire io_lsu_ll_resp_valid_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_release_bits_opcode_0; // @[dcache.scala:438:7]
wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:438:7]
wire [3:0] io_lsu_release_bits_size_0; // @[dcache.scala:438:7]
wire [1:0] io_lsu_release_bits_source_0; // @[dcache.scala:438:7]
wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:438:7]
wire [63:0] io_lsu_release_bits_data_0; // @[dcache.scala:438:7]
wire io_lsu_release_valid_0; // @[dcache.scala:438:7]
wire io_lsu_perf_acquire_0; // @[dcache.scala:438:7]
wire io_lsu_perf_release_0; // @[dcache.scala:438:7]
wire io_lsu_ordered_0; // @[dcache.scala:438:7]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T_1; // @[dcache.scala:822:48]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _meta_0_io_write_valid_T = _meta_0_io_write_ready & _metaWriteArb_io_out_valid; // @[Decoupled.scala:51:35]
wire _data_io_read_0_valid_T = _dataReadArb_io_out_bits_valid_0 & _dataReadArb_io_out_valid; // @[dcache.scala:490:27, :495:63]
wire block_incoming_reqs; // @[dcache.scala:510:47]
wire _io_lsu_req_ready_T = _metaReadArb_io_in_4_ready & _dataReadArb_io_in_2_ready; // @[dcache.scala:472:27, :490:27, :511:50]
wire _io_lsu_req_ready_T_1 = ~block_incoming_reqs; // @[dcache.scala:510:47, :511:83]
assign _io_lsu_req_ready_T_2 = _io_lsu_req_ready_T & _io_lsu_req_ready_T_1; // @[dcache.scala:511:{50,80,83}]
assign io_lsu_req_ready_0 = _io_lsu_req_ready_T_2; // @[dcache.scala:438:7, :511:80]
wire _metaReadArb_io_in_4_valid_T = ~block_incoming_reqs; // @[dcache.scala:510:47, :511:83, :512:53]
wire _metaReadArb_io_in_4_valid_T_1 = io_lsu_req_valid_0 & _metaReadArb_io_in_4_valid_T; // @[dcache.scala:438:7, :512:{50,53}]
wire _dataReadArb_io_in_2_valid_T = ~block_incoming_reqs; // @[dcache.scala:510:47, :511:83, :513:53]
wire _dataReadArb_io_in_2_valid_T_1 = io_lsu_req_valid_0 & _dataReadArb_io_in_2_valid_T; // @[dcache.scala:438:7, :513:{50,53}]
wire [33:0] _metaReadArb_io_in_4_bits_req_0_idx_T = io_lsu_req_bits_0_bits_addr_0[39:6]; // @[dcache.scala:438:7, :516:77]
wire replay_req_0_uop_iq_type_0; // @[dcache.scala:527:24]
wire replay_req_0_uop_iq_type_1; // @[dcache.scala:527:24]
wire replay_req_0_uop_iq_type_2; // @[dcache.scala:527:24]
wire replay_req_0_uop_iq_type_3; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_0; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_1; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_2; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_3; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_4; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_5; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_6; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_7; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_8; // @[dcache.scala:527:24]
wire replay_req_0_uop_fu_code_9; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_wen; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_toint; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_fma; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_div; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_ctrl_vec; // @[dcache.scala:527:24]
wire [31:0] replay_req_0_uop_inst; // @[dcache.scala:527:24]
wire [31:0] replay_req_0_uop_debug_inst; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_rvc; // @[dcache.scala:527:24]
wire [39:0] replay_req_0_uop_debug_pc; // @[dcache.scala:527:24]
wire replay_req_0_uop_iw_issued; // @[dcache.scala:527:24]
wire replay_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:527:24]
wire replay_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:527:24]
wire replay_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:527:24]
wire replay_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:527:24]
wire replay_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_dis_col_sel; // @[dcache.scala:527:24]
wire [11:0] replay_req_0_uop_br_mask; // @[dcache.scala:527:24]
wire [3:0] replay_req_0_uop_br_tag; // @[dcache.scala:527:24]
wire [3:0] replay_req_0_uop_br_type; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_sfb; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_fence; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_fencei; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_sfence; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_amo; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_eret; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_sys_pc2epc; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_rocc; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_mov; // @[dcache.scala:527:24]
wire [4:0] replay_req_0_uop_ftq_idx; // @[dcache.scala:527:24]
wire replay_req_0_uop_edge_inst; // @[dcache.scala:527:24]
wire [5:0] replay_req_0_uop_pc_lob; // @[dcache.scala:527:24]
wire replay_req_0_uop_taken; // @[dcache.scala:527:24]
wire replay_req_0_uop_imm_rename; // @[dcache.scala:527:24]
wire [2:0] replay_req_0_uop_imm_sel; // @[dcache.scala:527:24]
wire [4:0] replay_req_0_uop_pimm; // @[dcache.scala:527:24]
wire [19:0] replay_req_0_uop_imm_packed; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_op1_sel; // @[dcache.scala:527:24]
wire [2:0] replay_req_0_uop_op2_sel; // @[dcache.scala:527:24]
wire [5:0] replay_req_0_uop_rob_idx; // @[dcache.scala:527:24]
wire [3:0] replay_req_0_uop_ldq_idx; // @[dcache.scala:527:24]
wire [3:0] replay_req_0_uop_stq_idx; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_rxq_idx; // @[dcache.scala:527:24]
wire [6:0] replay_req_0_uop_pdst; // @[dcache.scala:527:24]
wire [6:0] replay_req_0_uop_prs1; // @[dcache.scala:527:24]
wire [6:0] replay_req_0_uop_prs2; // @[dcache.scala:527:24]
wire [6:0] replay_req_0_uop_prs3; // @[dcache.scala:527:24]
wire [4:0] replay_req_0_uop_ppred; // @[dcache.scala:527:24]
wire replay_req_0_uop_prs1_busy; // @[dcache.scala:527:24]
wire replay_req_0_uop_prs2_busy; // @[dcache.scala:527:24]
wire replay_req_0_uop_prs3_busy; // @[dcache.scala:527:24]
wire replay_req_0_uop_ppred_busy; // @[dcache.scala:527:24]
wire [6:0] replay_req_0_uop_stale_pdst; // @[dcache.scala:527:24]
wire replay_req_0_uop_exception; // @[dcache.scala:527:24]
wire [63:0] replay_req_0_uop_exc_cause; // @[dcache.scala:527:24]
wire [4:0] replay_req_0_uop_mem_cmd; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_mem_size; // @[dcache.scala:527:24]
wire replay_req_0_uop_mem_signed; // @[dcache.scala:527:24]
wire replay_req_0_uop_uses_ldq; // @[dcache.scala:527:24]
wire replay_req_0_uop_uses_stq; // @[dcache.scala:527:24]
wire replay_req_0_uop_is_unique; // @[dcache.scala:527:24]
wire replay_req_0_uop_flush_on_commit; // @[dcache.scala:527:24]
wire [2:0] replay_req_0_uop_csr_cmd; // @[dcache.scala:527:24]
wire replay_req_0_uop_ldst_is_rs1; // @[dcache.scala:527:24]
wire [5:0] replay_req_0_uop_ldst; // @[dcache.scala:527:24]
wire [5:0] replay_req_0_uop_lrs1; // @[dcache.scala:527:24]
wire [5:0] replay_req_0_uop_lrs2; // @[dcache.scala:527:24]
wire [5:0] replay_req_0_uop_lrs3; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_dst_rtype; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_lrs1_rtype; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_lrs2_rtype; // @[dcache.scala:527:24]
wire replay_req_0_uop_frs3_en; // @[dcache.scala:527:24]
wire replay_req_0_uop_fcn_dw; // @[dcache.scala:527:24]
wire [4:0] replay_req_0_uop_fcn_op; // @[dcache.scala:527:24]
wire replay_req_0_uop_fp_val; // @[dcache.scala:527:24]
wire [2:0] replay_req_0_uop_fp_rm; // @[dcache.scala:527:24]
wire [1:0] replay_req_0_uop_fp_typ; // @[dcache.scala:527:24]
wire replay_req_0_uop_xcpt_pf_if; // @[dcache.scala:527:24]
wire replay_req_0_uop_xcpt_ae_if; // @[dcache.scala:527:24]
wire replay_req_0_uop_xcpt_ma_if; // @[dcache.scala:527:24]
wire replay_req_0_uop_bp_debug_if; // @[dcache.scala:527:24]
wire replay_req_0_uop_bp_xcpt_if; // @[dcache.scala:527:24]
wire [2:0] replay_req_0_uop_debug_fsrc; // @[dcache.scala:527:24]
wire [2:0] replay_req_0_uop_debug_tsrc; // @[dcache.scala:527:24]
wire [39:0] replay_req_0_addr; // @[dcache.scala:527:24]
wire [63:0] replay_req_0_data; // @[dcache.scala:527:24]
wire replay_req_0_is_hella; // @[dcache.scala:527:24]
wire _mshrs_io_replay_ready_T_2 = _mshrs_io_replay_ready_T; // @[dcache.scala:534:{58,88}]
wire [33:0] _metaReadArb_io_in_0_bits_req_0_idx_T = _mshrs_io_replay_bits_addr[39:6]; // @[dcache.scala:460:21, :538:72]
wire [39:0] mshr_read_req_0_addr; // @[dcache.scala:549:27]
wire [25:0] _mshr_read_req_0_addr_T = {_mshrs_io_meta_read_bits_tag, _mshrs_io_meta_read_bits_idx}; // @[dcache.scala:460:21, :552:35]
wire [31:0] _mshr_read_req_0_addr_T_1 = {_mshr_read_req_0_addr_T, 6'h0}; // @[dcache.scala:552:{35,94}]
assign mshr_read_req_0_addr = {8'h0, _mshr_read_req_0_addr_T_1}; // @[dcache.scala:549:27, :552:{29,94}]
wire _wb_io_meta_read_ready_T_2; // @[dcache.scala:575:85]
wire _wb_fire_T = _wb_io_meta_read_ready_T_2 & _wb_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _wb_io_data_req_ready_T_2; // @[dcache.scala:580:85]
wire _wb_fire_T_1 = _wb_io_data_req_ready_T_2 & _wb_io_data_req_valid; // @[Decoupled.scala:51:35]
wire wb_fire = _wb_fire_T & _wb_fire_T_1; // @[Decoupled.scala:51:35]
wire [39:0] wb_req_0_addr; // @[dcache.scala:564:20]
wire [31:0] _wb_req_0_addr_T = {_wb_io_meta_read_bits_tag, _wb_io_data_req_bits_addr}; // @[dcache.scala:458:18, :567:28]
assign wb_req_0_addr = {8'h0, _wb_req_0_addr_T}; // @[dcache.scala:564:20, :567:{22,28}]
wire _GEN = _metaReadArb_io_in_2_ready & _dataReadArb_io_in_1_ready; // @[dcache.scala:472:27, :490:27, :575:55]
wire _wb_io_meta_read_ready_T; // @[dcache.scala:575:55]
assign _wb_io_meta_read_ready_T = _GEN; // @[dcache.scala:575:55]
wire _wb_io_data_req_ready_T; // @[dcache.scala:580:55]
assign _wb_io_data_req_ready_T = _GEN; // @[dcache.scala:575:55, :580:55]
assign _wb_io_meta_read_ready_T_2 = _wb_io_meta_read_ready_T; // @[dcache.scala:575:{55,85}]
assign _wb_io_data_req_ready_T_2 = _wb_io_data_req_ready_T; // @[dcache.scala:580:{55,85}]
wire prober_fire = _metaReadArb_io_in_1_ready & _prober_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire [39:0] prober_req_0_addr; // @[dcache.scala:586:26]
wire [25:0] _prober_req_0_addr_T = {_prober_io_meta_read_bits_tag, _prober_io_meta_read_bits_idx}; // @[dcache.scala:459:22, :589:32]
wire [31:0] _prober_req_0_addr_T_1 = {_prober_req_0_addr_T, 6'h0}; // @[dcache.scala:589:{32,93}]
assign prober_req_0_addr = {8'h0, _prober_req_0_addr_T_1}; // @[dcache.scala:586:26, :589:{26,93}]
wire _T_7 = io_lsu_req_ready_0 & io_lsu_req_valid_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T; // @[Decoupled.scala:51:35]
assign _s0_valid_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_req_T; // @[Decoupled.scala:51:35]
assign _s0_req_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_type_T; // @[Decoupled.scala:51:35]
assign _s0_type_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T = _T_7; // @[Decoupled.scala:51:35]
wire _s1_valid_T_8; // @[Decoupled.scala:51:35]
assign _s1_valid_T_8 = _T_7; // @[Decoupled.scala:51:35]
wire _GEN_0 = _mshrs_io_replay_ready_T_2 & _mshrs_io_replay_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_1; // @[Decoupled.scala:51:35]
assign _s0_valid_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_1; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T_2 = _s0_valid_T_1 | wb_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_3 = _s0_valid_T_2 | prober_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_4 = _s0_valid_T_3; // @[dcache.scala:613:{54,69}]
wire _GEN_1 = _metaReadArb_io_in_3_ready & _mshrs_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_5; // @[Decoupled.scala:51:35]
assign _s0_valid_T_5 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_1; // @[Decoupled.scala:51:35]
assign _s0_req_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_type_T_1; // @[Decoupled.scala:51:35]
assign _s0_type_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_valid_T_6 = _s0_valid_T_4 | _s0_valid_T_5; // @[Decoupled.scala:51:35]
wire _s0_valid_T_7_0 = _s0_valid_T_6; // @[dcache.scala:613:{21,86}]
wire s0_valid_0 = _s0_valid_T ? _s0_valid_WIRE_0 : _s0_valid_T_7_0; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_debug_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_rvc = ~_s0_req_T_1 & replay_req_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_2_0_uop_debug_pc = _s0_req_T_1 ? 40'h0 : replay_req_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iq_type_0 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_0; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iq_type_1 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iq_type_2 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_2; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iq_type_3 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_3; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_0 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_0; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_1 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_2 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_2; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_3 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_3; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_4 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_4; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_5 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_5; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_6 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_6; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_7 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_7; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_8 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_8; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fu_code_9 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_9; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_issued = ~_s0_req_T_1 & replay_req_0_uop_iw_issued; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_issued_partial_agen = ~_s0_req_T_1 & replay_req_0_uop_iw_issued_partial_agen; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_issued_partial_dgen = ~_s0_req_T_1 & replay_req_0_uop_iw_issued_partial_dgen; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_iw_p1_speculative_child = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_iw_p1_speculative_child; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_iw_p2_speculative_child = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_iw_p2_speculative_child; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p1_bypass_hint = ~_s0_req_T_1 & replay_req_0_uop_iw_p1_bypass_hint; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p2_bypass_hint = ~_s0_req_T_1 & replay_req_0_uop_iw_p2_bypass_hint; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p3_bypass_hint = ~_s0_req_T_1 & replay_req_0_uop_iw_p3_bypass_hint; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_dis_col_sel = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_dis_col_sel; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_2_0_uop_br_mask = _s0_req_T_1 ? 12'h0 : replay_req_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_br_tag = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_br_type = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_br_type; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sfb = ~_s0_req_T_1 & replay_req_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fence = ~_s0_req_T_1 & replay_req_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fencei = ~_s0_req_T_1 & replay_req_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sfence = ~_s0_req_T_1 & replay_req_0_uop_is_sfence; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_amo = ~_s0_req_T_1 & replay_req_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_eret = ~_s0_req_T_1 & replay_req_0_uop_is_eret; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sys_pc2epc = ~_s0_req_T_1 & replay_req_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_rocc = ~_s0_req_T_1 & replay_req_0_uop_is_rocc; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_mov = ~_s0_req_T_1 & replay_req_0_uop_is_mov; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ftq_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_edge_inst = ~_s0_req_T_1 & replay_req_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_pc_lob = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_taken = ~_s0_req_T_1 & replay_req_0_uop_taken; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_imm_rename = ~_s0_req_T_1 & replay_req_0_uop_imm_rename; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_imm_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_pimm = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_pimm; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_2_0_uop_imm_packed = _s0_req_T_1 ? 20'h0 : replay_req_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_op1_sel = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_op2_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_op2_sel; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_ldst = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ldst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_wen = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_wen; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_ren1 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ren1; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_ren2 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ren2; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_ren3 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ren3; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_swap12 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_swap12; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_swap23 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_swap23; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_fp_ctrl_typeTagIn = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_fp_ctrl_typeTagOut = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_fromint = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_fromint; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_toint = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_toint; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_fastpipe = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_fma = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_fma; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_div = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_div; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_sqrt = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_sqrt; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_wflags = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_wflags; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_ctrl_vec = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_vec; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_rob_idx = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ldq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_stq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_rxq_idx = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs1 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs2 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs3 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ppred = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs1_busy = ~_s0_req_T_1 & replay_req_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs2_busy = ~_s0_req_T_1 & replay_req_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs3_busy = ~_s0_req_T_1 & replay_req_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ppred_busy = ~_s0_req_T_1 & replay_req_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_stale_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_exception = ~_s0_req_T_1 & replay_req_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_uop_exc_cause = _s0_req_T_1 ? 64'h0 : replay_req_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_mem_cmd = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_mem_size = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_mem_signed = ~_s0_req_T_1 & replay_req_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_ldq = ~_s0_req_T_1 & replay_req_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_stq = ~_s0_req_T_1 & replay_req_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_unique = ~_s0_req_T_1 & replay_req_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_flush_on_commit = ~_s0_req_T_1 & replay_req_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_csr_cmd = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ldst_is_rs1 = ~_s0_req_T_1 & replay_req_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_ldst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs1 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs2 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs3 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_dst_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs1_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs2_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_frs3_en = ~_s0_req_T_1 & replay_req_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fcn_dw = ~_s0_req_T_1 & replay_req_0_uop_fcn_dw; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_fcn_op = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_fcn_op; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_val = ~_s0_req_T_1 & replay_req_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_fp_rm = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_fp_rm; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_fp_typ = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_fp_typ; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_pf_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ae_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ma_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_debug_if = ~_s0_req_T_1 & replay_req_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_xcpt_if = ~_s0_req_T_1 & replay_req_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_debug_fsrc = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_debug_tsrc = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_2_0_addr = _s0_req_T_1 ? mshr_read_req_0_addr : replay_req_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_data = _s0_req_T_1 ? 64'h0 : replay_req_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_is_hella = ~_s0_req_T_1 & replay_req_0_is_hella; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_3_0_uop_inst = _s0_req_T_2_0_uop_inst; // @[dcache.scala:618:21, :619:21]
wire [31:0] _s0_req_T_3_0_uop_debug_inst = _s0_req_T_2_0_uop_debug_inst; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_rvc = _s0_req_T_2_0_uop_is_rvc; // @[dcache.scala:618:21, :619:21]
wire [39:0] _s0_req_T_3_0_uop_debug_pc = _s0_req_T_2_0_uop_debug_pc; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iq_type_0 = _s0_req_T_2_0_uop_iq_type_0; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iq_type_1 = _s0_req_T_2_0_uop_iq_type_1; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iq_type_2 = _s0_req_T_2_0_uop_iq_type_2; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iq_type_3 = _s0_req_T_2_0_uop_iq_type_3; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_0 = _s0_req_T_2_0_uop_fu_code_0; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_1 = _s0_req_T_2_0_uop_fu_code_1; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_2 = _s0_req_T_2_0_uop_fu_code_2; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_3 = _s0_req_T_2_0_uop_fu_code_3; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_4 = _s0_req_T_2_0_uop_fu_code_4; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_5 = _s0_req_T_2_0_uop_fu_code_5; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_6 = _s0_req_T_2_0_uop_fu_code_6; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_7 = _s0_req_T_2_0_uop_fu_code_7; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_8 = _s0_req_T_2_0_uop_fu_code_8; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fu_code_9 = _s0_req_T_2_0_uop_fu_code_9; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iw_issued = _s0_req_T_2_0_uop_iw_issued; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iw_issued_partial_agen = _s0_req_T_2_0_uop_iw_issued_partial_agen; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iw_issued_partial_dgen = _s0_req_T_2_0_uop_iw_issued_partial_dgen; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_iw_p1_speculative_child = _s0_req_T_2_0_uop_iw_p1_speculative_child; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_iw_p2_speculative_child = _s0_req_T_2_0_uop_iw_p2_speculative_child; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iw_p1_bypass_hint = _s0_req_T_2_0_uop_iw_p1_bypass_hint; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iw_p2_bypass_hint = _s0_req_T_2_0_uop_iw_p2_bypass_hint; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_iw_p3_bypass_hint = _s0_req_T_2_0_uop_iw_p3_bypass_hint; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_dis_col_sel = _s0_req_T_2_0_uop_dis_col_sel; // @[dcache.scala:618:21, :619:21]
wire [11:0] _s0_req_T_3_0_uop_br_mask = _s0_req_T_2_0_uop_br_mask; // @[dcache.scala:618:21, :619:21]
wire [3:0] _s0_req_T_3_0_uop_br_tag = _s0_req_T_2_0_uop_br_tag; // @[dcache.scala:618:21, :619:21]
wire [3:0] _s0_req_T_3_0_uop_br_type = _s0_req_T_2_0_uop_br_type; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_sfb = _s0_req_T_2_0_uop_is_sfb; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_fence = _s0_req_T_2_0_uop_is_fence; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_fencei = _s0_req_T_2_0_uop_is_fencei; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_sfence = _s0_req_T_2_0_uop_is_sfence; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_amo = _s0_req_T_2_0_uop_is_amo; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_eret = _s0_req_T_2_0_uop_is_eret; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_sys_pc2epc = _s0_req_T_2_0_uop_is_sys_pc2epc; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_rocc = _s0_req_T_2_0_uop_is_rocc; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_mov = _s0_req_T_2_0_uop_is_mov; // @[dcache.scala:618:21, :619:21]
wire [4:0] _s0_req_T_3_0_uop_ftq_idx = _s0_req_T_2_0_uop_ftq_idx; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_edge_inst = _s0_req_T_2_0_uop_edge_inst; // @[dcache.scala:618:21, :619:21]
wire [5:0] _s0_req_T_3_0_uop_pc_lob = _s0_req_T_2_0_uop_pc_lob; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_taken = _s0_req_T_2_0_uop_taken; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_imm_rename = _s0_req_T_2_0_uop_imm_rename; // @[dcache.scala:618:21, :619:21]
wire [2:0] _s0_req_T_3_0_uop_imm_sel = _s0_req_T_2_0_uop_imm_sel; // @[dcache.scala:618:21, :619:21]
wire [4:0] _s0_req_T_3_0_uop_pimm = _s0_req_T_2_0_uop_pimm; // @[dcache.scala:618:21, :619:21]
wire [19:0] _s0_req_T_3_0_uop_imm_packed = _s0_req_T_2_0_uop_imm_packed; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_op1_sel = _s0_req_T_2_0_uop_op1_sel; // @[dcache.scala:618:21, :619:21]
wire [2:0] _s0_req_T_3_0_uop_op2_sel = _s0_req_T_2_0_uop_op2_sel; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_ldst = _s0_req_T_2_0_uop_fp_ctrl_ldst; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_wen = _s0_req_T_2_0_uop_fp_ctrl_wen; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_ren1 = _s0_req_T_2_0_uop_fp_ctrl_ren1; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_ren2 = _s0_req_T_2_0_uop_fp_ctrl_ren2; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_ren3 = _s0_req_T_2_0_uop_fp_ctrl_ren3; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_swap12 = _s0_req_T_2_0_uop_fp_ctrl_swap12; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_swap23 = _s0_req_T_2_0_uop_fp_ctrl_swap23; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_fp_ctrl_typeTagIn = _s0_req_T_2_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_fp_ctrl_typeTagOut = _s0_req_T_2_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_fromint = _s0_req_T_2_0_uop_fp_ctrl_fromint; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_toint = _s0_req_T_2_0_uop_fp_ctrl_toint; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_fastpipe = _s0_req_T_2_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_fma = _s0_req_T_2_0_uop_fp_ctrl_fma; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_div = _s0_req_T_2_0_uop_fp_ctrl_div; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_sqrt = _s0_req_T_2_0_uop_fp_ctrl_sqrt; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_wflags = _s0_req_T_2_0_uop_fp_ctrl_wflags; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_ctrl_vec = _s0_req_T_2_0_uop_fp_ctrl_vec; // @[dcache.scala:618:21, :619:21]
wire [5:0] _s0_req_T_3_0_uop_rob_idx = _s0_req_T_2_0_uop_rob_idx; // @[dcache.scala:618:21, :619:21]
wire [3:0] _s0_req_T_3_0_uop_ldq_idx = _s0_req_T_2_0_uop_ldq_idx; // @[dcache.scala:618:21, :619:21]
wire [3:0] _s0_req_T_3_0_uop_stq_idx = _s0_req_T_2_0_uop_stq_idx; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_rxq_idx = _s0_req_T_2_0_uop_rxq_idx; // @[dcache.scala:618:21, :619:21]
wire [6:0] _s0_req_T_3_0_uop_pdst = _s0_req_T_2_0_uop_pdst; // @[dcache.scala:618:21, :619:21]
wire [6:0] _s0_req_T_3_0_uop_prs1 = _s0_req_T_2_0_uop_prs1; // @[dcache.scala:618:21, :619:21]
wire [6:0] _s0_req_T_3_0_uop_prs2 = _s0_req_T_2_0_uop_prs2; // @[dcache.scala:618:21, :619:21]
wire [6:0] _s0_req_T_3_0_uop_prs3 = _s0_req_T_2_0_uop_prs3; // @[dcache.scala:618:21, :619:21]
wire [4:0] _s0_req_T_3_0_uop_ppred = _s0_req_T_2_0_uop_ppred; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_prs1_busy = _s0_req_T_2_0_uop_prs1_busy; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_prs2_busy = _s0_req_T_2_0_uop_prs2_busy; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_prs3_busy = _s0_req_T_2_0_uop_prs3_busy; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_ppred_busy = _s0_req_T_2_0_uop_ppred_busy; // @[dcache.scala:618:21, :619:21]
wire [6:0] _s0_req_T_3_0_uop_stale_pdst = _s0_req_T_2_0_uop_stale_pdst; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_exception = _s0_req_T_2_0_uop_exception; // @[dcache.scala:618:21, :619:21]
wire [63:0] _s0_req_T_3_0_uop_exc_cause = _s0_req_T_2_0_uop_exc_cause; // @[dcache.scala:618:21, :619:21]
wire [4:0] _s0_req_T_3_0_uop_mem_cmd = _s0_req_T_2_0_uop_mem_cmd; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_mem_size = _s0_req_T_2_0_uop_mem_size; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_mem_signed = _s0_req_T_2_0_uop_mem_signed; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_uses_ldq = _s0_req_T_2_0_uop_uses_ldq; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_uses_stq = _s0_req_T_2_0_uop_uses_stq; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_is_unique = _s0_req_T_2_0_uop_is_unique; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_flush_on_commit = _s0_req_T_2_0_uop_flush_on_commit; // @[dcache.scala:618:21, :619:21]
wire [2:0] _s0_req_T_3_0_uop_csr_cmd = _s0_req_T_2_0_uop_csr_cmd; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_ldst_is_rs1 = _s0_req_T_2_0_uop_ldst_is_rs1; // @[dcache.scala:618:21, :619:21]
wire [5:0] _s0_req_T_3_0_uop_ldst = _s0_req_T_2_0_uop_ldst; // @[dcache.scala:618:21, :619:21]
wire [5:0] _s0_req_T_3_0_uop_lrs1 = _s0_req_T_2_0_uop_lrs1; // @[dcache.scala:618:21, :619:21]
wire [5:0] _s0_req_T_3_0_uop_lrs2 = _s0_req_T_2_0_uop_lrs2; // @[dcache.scala:618:21, :619:21]
wire [5:0] _s0_req_T_3_0_uop_lrs3 = _s0_req_T_2_0_uop_lrs3; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_dst_rtype = _s0_req_T_2_0_uop_dst_rtype; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_lrs1_rtype = _s0_req_T_2_0_uop_lrs1_rtype; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_lrs2_rtype = _s0_req_T_2_0_uop_lrs2_rtype; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_frs3_en = _s0_req_T_2_0_uop_frs3_en; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fcn_dw = _s0_req_T_2_0_uop_fcn_dw; // @[dcache.scala:618:21, :619:21]
wire [4:0] _s0_req_T_3_0_uop_fcn_op = _s0_req_T_2_0_uop_fcn_op; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_fp_val = _s0_req_T_2_0_uop_fp_val; // @[dcache.scala:618:21, :619:21]
wire [2:0] _s0_req_T_3_0_uop_fp_rm = _s0_req_T_2_0_uop_fp_rm; // @[dcache.scala:618:21, :619:21]
wire [1:0] _s0_req_T_3_0_uop_fp_typ = _s0_req_T_2_0_uop_fp_typ; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_xcpt_pf_if = _s0_req_T_2_0_uop_xcpt_pf_if; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_xcpt_ae_if = _s0_req_T_2_0_uop_xcpt_ae_if; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_xcpt_ma_if = _s0_req_T_2_0_uop_xcpt_ma_if; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_bp_debug_if = _s0_req_T_2_0_uop_bp_debug_if; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_uop_bp_xcpt_if = _s0_req_T_2_0_uop_bp_xcpt_if; // @[dcache.scala:618:21, :619:21]
wire [2:0] _s0_req_T_3_0_uop_debug_fsrc = _s0_req_T_2_0_uop_debug_fsrc; // @[dcache.scala:618:21, :619:21]
wire [2:0] _s0_req_T_3_0_uop_debug_tsrc = _s0_req_T_2_0_uop_debug_tsrc; // @[dcache.scala:618:21, :619:21]
wire [39:0] _s0_req_T_3_0_addr = _s0_req_T_2_0_addr; // @[dcache.scala:618:21, :619:21]
wire [63:0] _s0_req_T_3_0_data = _s0_req_T_2_0_data; // @[dcache.scala:618:21, :619:21]
wire _s0_req_T_3_0_is_hella = _s0_req_T_2_0_is_hella; // @[dcache.scala:618:21, :619:21]
wire [31:0] _s0_req_T_4_0_uop_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_4_0_uop_debug_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_rvc = ~prober_fire & _s0_req_T_3_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_4_0_uop_debug_pc = prober_fire ? 40'h0 : _s0_req_T_3_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iq_type_0 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_0; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iq_type_1 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iq_type_2 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_2; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iq_type_3 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_3; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_0 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_0; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_1 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_2 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_2; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_3 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_3; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_4 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_4; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_5 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_5; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_6 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_6; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_7 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_7; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_8 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_8; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fu_code_9 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_9; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_issued = ~prober_fire & _s0_req_T_3_0_uop_iw_issued; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_issued_partial_agen = ~prober_fire & _s0_req_T_3_0_uop_iw_issued_partial_agen; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_issued_partial_dgen = ~prober_fire & _s0_req_T_3_0_uop_iw_issued_partial_dgen; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_iw_p1_speculative_child = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_iw_p1_speculative_child; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_iw_p2_speculative_child = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_iw_p2_speculative_child; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p1_bypass_hint = ~prober_fire & _s0_req_T_3_0_uop_iw_p1_bypass_hint; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p2_bypass_hint = ~prober_fire & _s0_req_T_3_0_uop_iw_p2_bypass_hint; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p3_bypass_hint = ~prober_fire & _s0_req_T_3_0_uop_iw_p3_bypass_hint; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_dis_col_sel = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_dis_col_sel; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_4_0_uop_br_mask = prober_fire ? 12'h0 : _s0_req_T_3_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_br_tag = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_br_type = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_br_type; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sfb = ~prober_fire & _s0_req_T_3_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fence = ~prober_fire & _s0_req_T_3_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fencei = ~prober_fire & _s0_req_T_3_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sfence = ~prober_fire & _s0_req_T_3_0_uop_is_sfence; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_amo = ~prober_fire & _s0_req_T_3_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_eret = ~prober_fire & _s0_req_T_3_0_uop_is_eret; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sys_pc2epc = ~prober_fire & _s0_req_T_3_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_rocc = ~prober_fire & _s0_req_T_3_0_uop_is_rocc; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_mov = ~prober_fire & _s0_req_T_3_0_uop_is_mov; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ftq_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_edge_inst = ~prober_fire & _s0_req_T_3_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_pc_lob = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_taken = ~prober_fire & _s0_req_T_3_0_uop_taken; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_imm_rename = ~prober_fire & _s0_req_T_3_0_uop_imm_rename; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_imm_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_pimm = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_pimm; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_4_0_uop_imm_packed = prober_fire ? 20'h0 : _s0_req_T_3_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_op1_sel = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_op2_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_op2_sel; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_ldst = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ldst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_wen = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_wen; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_ren1 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ren1; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_ren2 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ren2; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_ren3 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ren3; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_swap12 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_swap12; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_swap23 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_swap23; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_fp_ctrl_typeTagIn = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_fp_ctrl_typeTagOut = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_fromint = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_fromint; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_toint = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_toint; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_fastpipe = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_fma = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_fma; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_div = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_div; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_sqrt = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_sqrt; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_wflags = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_wflags; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_ctrl_vec = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_vec; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_rob_idx = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ldq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_stq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_rxq_idx = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs1 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs2 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs3 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ppred = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs1_busy = ~prober_fire & _s0_req_T_3_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs2_busy = ~prober_fire & _s0_req_T_3_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs3_busy = ~prober_fire & _s0_req_T_3_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ppred_busy = ~prober_fire & _s0_req_T_3_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_stale_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_exception = ~prober_fire & _s0_req_T_3_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_uop_exc_cause = prober_fire ? 64'h0 : _s0_req_T_3_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_mem_cmd = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_mem_size = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_mem_signed = ~prober_fire & _s0_req_T_3_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_ldq = ~prober_fire & _s0_req_T_3_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_stq = ~prober_fire & _s0_req_T_3_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_unique = ~prober_fire & _s0_req_T_3_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_flush_on_commit = ~prober_fire & _s0_req_T_3_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_csr_cmd = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ldst_is_rs1 = ~prober_fire & _s0_req_T_3_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_ldst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs1 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs2 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs3 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_dst_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs1_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs2_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_frs3_en = ~prober_fire & _s0_req_T_3_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fcn_dw = ~prober_fire & _s0_req_T_3_0_uop_fcn_dw; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_fcn_op = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_fcn_op; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_val = ~prober_fire & _s0_req_T_3_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_fp_rm = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_fp_rm; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_fp_typ = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_fp_typ; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_pf_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ae_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ma_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_debug_if = ~prober_fire & _s0_req_T_3_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_xcpt_if = ~prober_fire & _s0_req_T_3_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_debug_fsrc = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_debug_tsrc = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_4_0_addr = prober_fire ? prober_req_0_addr : _s0_req_T_3_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_data = prober_fire ? 64'h0 : _s0_req_T_3_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_is_hella = ~prober_fire & _s0_req_T_3_0_is_hella; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_5_0_uop_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_inst; // @[dcache.scala:563:38, :616:21, :617:21]
wire [31:0] _s0_req_T_5_0_uop_debug_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_debug_inst; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_rvc = ~wb_fire & _s0_req_T_4_0_uop_is_rvc; // @[dcache.scala:563:38, :616:21, :617:21]
wire [39:0] _s0_req_T_5_0_uop_debug_pc = wb_fire ? 40'h0 : _s0_req_T_4_0_uop_debug_pc; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iq_type_0 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_0; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iq_type_1 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_1; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iq_type_2 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_2; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iq_type_3 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_3; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_0 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_0; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_1 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_1; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_2 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_2; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_3 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_3; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_4 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_4; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_5 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_5; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_6 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_6; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_7 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_7; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_8 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_8; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fu_code_9 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_9; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iw_issued = ~wb_fire & _s0_req_T_4_0_uop_iw_issued; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iw_issued_partial_agen = ~wb_fire & _s0_req_T_4_0_uop_iw_issued_partial_agen; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iw_issued_partial_dgen = ~wb_fire & _s0_req_T_4_0_uop_iw_issued_partial_dgen; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_iw_p1_speculative_child = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_iw_p1_speculative_child; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_iw_p2_speculative_child = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_iw_p2_speculative_child; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iw_p1_bypass_hint = ~wb_fire & _s0_req_T_4_0_uop_iw_p1_bypass_hint; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iw_p2_bypass_hint = ~wb_fire & _s0_req_T_4_0_uop_iw_p2_bypass_hint; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_iw_p3_bypass_hint = ~wb_fire & _s0_req_T_4_0_uop_iw_p3_bypass_hint; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_dis_col_sel = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_dis_col_sel; // @[dcache.scala:563:38, :616:21, :617:21]
wire [11:0] _s0_req_T_5_0_uop_br_mask = wb_fire ? 12'h0 : _s0_req_T_4_0_uop_br_mask; // @[dcache.scala:563:38, :616:21, :617:21]
wire [3:0] _s0_req_T_5_0_uop_br_tag = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_br_tag; // @[dcache.scala:563:38, :616:21, :617:21]
wire [3:0] _s0_req_T_5_0_uop_br_type = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_br_type; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_sfb = ~wb_fire & _s0_req_T_4_0_uop_is_sfb; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_fence = ~wb_fire & _s0_req_T_4_0_uop_is_fence; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_fencei = ~wb_fire & _s0_req_T_4_0_uop_is_fencei; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_sfence = ~wb_fire & _s0_req_T_4_0_uop_is_sfence; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_amo = ~wb_fire & _s0_req_T_4_0_uop_is_amo; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_eret = ~wb_fire & _s0_req_T_4_0_uop_is_eret; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_sys_pc2epc = ~wb_fire & _s0_req_T_4_0_uop_is_sys_pc2epc; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_rocc = ~wb_fire & _s0_req_T_4_0_uop_is_rocc; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_mov = ~wb_fire & _s0_req_T_4_0_uop_is_mov; // @[dcache.scala:563:38, :616:21, :617:21]
wire [4:0] _s0_req_T_5_0_uop_ftq_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ftq_idx; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_edge_inst = ~wb_fire & _s0_req_T_4_0_uop_edge_inst; // @[dcache.scala:563:38, :616:21, :617:21]
wire [5:0] _s0_req_T_5_0_uop_pc_lob = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_pc_lob; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_taken = ~wb_fire & _s0_req_T_4_0_uop_taken; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_imm_rename = ~wb_fire & _s0_req_T_4_0_uop_imm_rename; // @[dcache.scala:563:38, :616:21, :617:21]
wire [2:0] _s0_req_T_5_0_uop_imm_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_imm_sel; // @[dcache.scala:563:38, :616:21, :617:21]
wire [4:0] _s0_req_T_5_0_uop_pimm = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_pimm; // @[dcache.scala:563:38, :616:21, :617:21]
wire [19:0] _s0_req_T_5_0_uop_imm_packed = wb_fire ? 20'h0 : _s0_req_T_4_0_uop_imm_packed; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_op1_sel = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_op1_sel; // @[dcache.scala:563:38, :616:21, :617:21]
wire [2:0] _s0_req_T_5_0_uop_op2_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_op2_sel; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_ldst = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ldst; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_wen = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_wen; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_ren1 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ren1; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_ren2 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ren2; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_ren3 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ren3; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_swap12 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_swap12; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_swap23 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_swap23; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_fp_ctrl_typeTagIn = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_fp_ctrl_typeTagOut = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_fromint = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_fromint; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_toint = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_toint; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_fastpipe = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_fma = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_fma; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_div = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_div; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_sqrt = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_sqrt; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_wflags = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_wflags; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_ctrl_vec = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_vec; // @[dcache.scala:563:38, :616:21, :617:21]
wire [5:0] _s0_req_T_5_0_uop_rob_idx = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_rob_idx; // @[dcache.scala:563:38, :616:21, :617:21]
wire [3:0] _s0_req_T_5_0_uop_ldq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ldq_idx; // @[dcache.scala:563:38, :616:21, :617:21]
wire [3:0] _s0_req_T_5_0_uop_stq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_stq_idx; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_rxq_idx = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_rxq_idx; // @[dcache.scala:563:38, :616:21, :617:21]
wire [6:0] _s0_req_T_5_0_uop_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_pdst; // @[dcache.scala:563:38, :616:21, :617:21]
wire [6:0] _s0_req_T_5_0_uop_prs1 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs1; // @[dcache.scala:563:38, :616:21, :617:21]
wire [6:0] _s0_req_T_5_0_uop_prs2 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs2; // @[dcache.scala:563:38, :616:21, :617:21]
wire [6:0] _s0_req_T_5_0_uop_prs3 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs3; // @[dcache.scala:563:38, :616:21, :617:21]
wire [4:0] _s0_req_T_5_0_uop_ppred = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ppred; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_prs1_busy = ~wb_fire & _s0_req_T_4_0_uop_prs1_busy; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_prs2_busy = ~wb_fire & _s0_req_T_4_0_uop_prs2_busy; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_prs3_busy = ~wb_fire & _s0_req_T_4_0_uop_prs3_busy; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_ppred_busy = ~wb_fire & _s0_req_T_4_0_uop_ppred_busy; // @[dcache.scala:563:38, :616:21, :617:21]
wire [6:0] _s0_req_T_5_0_uop_stale_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_stale_pdst; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_exception = ~wb_fire & _s0_req_T_4_0_uop_exception; // @[dcache.scala:563:38, :616:21, :617:21]
wire [63:0] _s0_req_T_5_0_uop_exc_cause = wb_fire ? 64'h0 : _s0_req_T_4_0_uop_exc_cause; // @[dcache.scala:563:38, :616:21, :617:21]
wire [4:0] _s0_req_T_5_0_uop_mem_cmd = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_mem_cmd; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_mem_size = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_mem_size; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_mem_signed = ~wb_fire & _s0_req_T_4_0_uop_mem_signed; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_uses_ldq = ~wb_fire & _s0_req_T_4_0_uop_uses_ldq; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_uses_stq = ~wb_fire & _s0_req_T_4_0_uop_uses_stq; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_is_unique = ~wb_fire & _s0_req_T_4_0_uop_is_unique; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_flush_on_commit = ~wb_fire & _s0_req_T_4_0_uop_flush_on_commit; // @[dcache.scala:563:38, :616:21, :617:21]
wire [2:0] _s0_req_T_5_0_uop_csr_cmd = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_csr_cmd; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_ldst_is_rs1 = ~wb_fire & _s0_req_T_4_0_uop_ldst_is_rs1; // @[dcache.scala:563:38, :616:21, :617:21]
wire [5:0] _s0_req_T_5_0_uop_ldst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_ldst; // @[dcache.scala:563:38, :616:21, :617:21]
wire [5:0] _s0_req_T_5_0_uop_lrs1 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs1; // @[dcache.scala:563:38, :616:21, :617:21]
wire [5:0] _s0_req_T_5_0_uop_lrs2 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs2; // @[dcache.scala:563:38, :616:21, :617:21]
wire [5:0] _s0_req_T_5_0_uop_lrs3 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs3; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_dst_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_dst_rtype; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_lrs1_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs1_rtype; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_lrs2_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs2_rtype; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_frs3_en = ~wb_fire & _s0_req_T_4_0_uop_frs3_en; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fcn_dw = ~wb_fire & _s0_req_T_4_0_uop_fcn_dw; // @[dcache.scala:563:38, :616:21, :617:21]
wire [4:0] _s0_req_T_5_0_uop_fcn_op = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_fcn_op; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_fp_val = ~wb_fire & _s0_req_T_4_0_uop_fp_val; // @[dcache.scala:563:38, :616:21, :617:21]
wire [2:0] _s0_req_T_5_0_uop_fp_rm = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_fp_rm; // @[dcache.scala:563:38, :616:21, :617:21]
wire [1:0] _s0_req_T_5_0_uop_fp_typ = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_fp_typ; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_xcpt_pf_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_pf_if; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_xcpt_ae_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ae_if; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_xcpt_ma_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ma_if; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_bp_debug_if = ~wb_fire & _s0_req_T_4_0_uop_bp_debug_if; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_uop_bp_xcpt_if = ~wb_fire & _s0_req_T_4_0_uop_bp_xcpt_if; // @[dcache.scala:563:38, :616:21, :617:21]
wire [2:0] _s0_req_T_5_0_uop_debug_fsrc = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_debug_fsrc; // @[dcache.scala:563:38, :616:21, :617:21]
wire [2:0] _s0_req_T_5_0_uop_debug_tsrc = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_debug_tsrc; // @[dcache.scala:563:38, :616:21, :617:21]
wire [39:0] _s0_req_T_5_0_addr = wb_fire ? wb_req_0_addr : _s0_req_T_4_0_addr; // @[dcache.scala:563:38, :564:20, :616:21, :617:21]
wire [63:0] _s0_req_T_5_0_data = wb_fire ? 64'h0 : _s0_req_T_4_0_data; // @[dcache.scala:563:38, :616:21, :617:21]
wire _s0_req_T_5_0_is_hella = ~wb_fire & _s0_req_T_4_0_is_hella; // @[dcache.scala:563:38, :616:21, :617:21]
wire [31:0] s0_req_0_uop_inst = _s0_req_T ? _s0_req_WIRE_0_uop_inst : _s0_req_T_5_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] s0_req_0_uop_debug_inst = _s0_req_T ? _s0_req_WIRE_0_uop_debug_inst : _s0_req_T_5_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_rvc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rvc : _s0_req_T_5_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] s0_req_0_uop_debug_pc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_pc : _s0_req_T_5_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iq_type_0 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_0 : _s0_req_T_5_0_uop_iq_type_0; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iq_type_1 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_1 : _s0_req_T_5_0_uop_iq_type_1; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iq_type_2 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_2 : _s0_req_T_5_0_uop_iq_type_2; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iq_type_3 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_3 : _s0_req_T_5_0_uop_iq_type_3; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_0 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_0 : _s0_req_T_5_0_uop_fu_code_0; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_1 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_1 : _s0_req_T_5_0_uop_fu_code_1; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_2 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_2 : _s0_req_T_5_0_uop_fu_code_2; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_3 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_3 : _s0_req_T_5_0_uop_fu_code_3; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_4 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_4 : _s0_req_T_5_0_uop_fu_code_4; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_5 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_5 : _s0_req_T_5_0_uop_fu_code_5; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_6 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_6 : _s0_req_T_5_0_uop_fu_code_6; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_7 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_7 : _s0_req_T_5_0_uop_fu_code_7; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_8 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_8 : _s0_req_T_5_0_uop_fu_code_8; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fu_code_9 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_9 : _s0_req_T_5_0_uop_fu_code_9; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_issued = _s0_req_T ? _s0_req_WIRE_0_uop_iw_issued : _s0_req_T_5_0_uop_iw_issued; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_issued_partial_agen = _s0_req_T ? _s0_req_WIRE_0_uop_iw_issued_partial_agen : _s0_req_T_5_0_uop_iw_issued_partial_agen; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_issued_partial_dgen = _s0_req_T ? _s0_req_WIRE_0_uop_iw_issued_partial_dgen : _s0_req_T_5_0_uop_iw_issued_partial_dgen; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_iw_p1_speculative_child = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_speculative_child : _s0_req_T_5_0_uop_iw_p1_speculative_child; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_iw_p2_speculative_child = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_speculative_child : _s0_req_T_5_0_uop_iw_p2_speculative_child; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p1_bypass_hint = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_bypass_hint : _s0_req_T_5_0_uop_iw_p1_bypass_hint; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p2_bypass_hint = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_bypass_hint : _s0_req_T_5_0_uop_iw_p2_bypass_hint; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p3_bypass_hint = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p3_bypass_hint : _s0_req_T_5_0_uop_iw_p3_bypass_hint; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_dis_col_sel = _s0_req_T ? _s0_req_WIRE_0_uop_dis_col_sel : _s0_req_T_5_0_uop_dis_col_sel; // @[Decoupled.scala:51:35]
wire [11:0] s0_req_0_uop_br_mask = _s0_req_T ? _s0_req_WIRE_0_uop_br_mask : _s0_req_T_5_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_br_tag = _s0_req_T ? _s0_req_WIRE_0_uop_br_tag : _s0_req_T_5_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_br_type = _s0_req_T ? _s0_req_WIRE_0_uop_br_type : _s0_req_T_5_0_uop_br_type; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sfb = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfb : _s0_req_T_5_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fence = _s0_req_T ? _s0_req_WIRE_0_uop_is_fence : _s0_req_T_5_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fencei = _s0_req_T ? _s0_req_WIRE_0_uop_is_fencei : _s0_req_T_5_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sfence = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfence : _s0_req_T_5_0_uop_is_sfence; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_amo = _s0_req_T ? _s0_req_WIRE_0_uop_is_amo : _s0_req_T_5_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_eret = _s0_req_T ? _s0_req_WIRE_0_uop_is_eret : _s0_req_T_5_0_uop_is_eret; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sys_pc2epc = _s0_req_T ? _s0_req_WIRE_0_uop_is_sys_pc2epc : _s0_req_T_5_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_rocc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rocc : _s0_req_T_5_0_uop_is_rocc; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_mov = _s0_req_T ? _s0_req_WIRE_0_uop_is_mov : _s0_req_T_5_0_uop_is_mov; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ftq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ftq_idx : _s0_req_T_5_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_edge_inst = _s0_req_T ? _s0_req_WIRE_0_uop_edge_inst : _s0_req_T_5_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_pc_lob = _s0_req_T ? _s0_req_WIRE_0_uop_pc_lob : _s0_req_T_5_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_taken = _s0_req_T ? _s0_req_WIRE_0_uop_taken : _s0_req_T_5_0_uop_taken; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_imm_rename = _s0_req_T ? _s0_req_WIRE_0_uop_imm_rename : _s0_req_T_5_0_uop_imm_rename; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_imm_sel = _s0_req_T ? _s0_req_WIRE_0_uop_imm_sel : _s0_req_T_5_0_uop_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_pimm = _s0_req_T ? _s0_req_WIRE_0_uop_pimm : _s0_req_T_5_0_uop_pimm; // @[Decoupled.scala:51:35]
wire [19:0] s0_req_0_uop_imm_packed = _s0_req_T ? _s0_req_WIRE_0_uop_imm_packed : _s0_req_T_5_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_op1_sel = _s0_req_T ? _s0_req_WIRE_0_uop_op1_sel : _s0_req_T_5_0_uop_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_op2_sel = _s0_req_T ? _s0_req_WIRE_0_uop_op2_sel : _s0_req_T_5_0_uop_op2_sel; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ldst : _s0_req_T_5_0_uop_fp_ctrl_ldst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_wen = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_wen : _s0_req_T_5_0_uop_fp_ctrl_wen; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_ren1 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ren1 : _s0_req_T_5_0_uop_fp_ctrl_ren1; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_ren2 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ren2 : _s0_req_T_5_0_uop_fp_ctrl_ren2; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_ren3 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ren3 : _s0_req_T_5_0_uop_fp_ctrl_ren3; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_swap12 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_swap12 : _s0_req_T_5_0_uop_fp_ctrl_swap12; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_swap23 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_swap23 : _s0_req_T_5_0_uop_fp_ctrl_swap23; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_fp_ctrl_typeTagIn = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_typeTagIn : _s0_req_T_5_0_uop_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_fp_ctrl_typeTagOut = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_typeTagOut : _s0_req_T_5_0_uop_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_fromint = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_fromint : _s0_req_T_5_0_uop_fp_ctrl_fromint; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_toint = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_toint : _s0_req_T_5_0_uop_fp_ctrl_toint; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_fastpipe = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_fastpipe : _s0_req_T_5_0_uop_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_fma = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_fma : _s0_req_T_5_0_uop_fp_ctrl_fma; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_div = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_div : _s0_req_T_5_0_uop_fp_ctrl_div; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_sqrt = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_sqrt : _s0_req_T_5_0_uop_fp_ctrl_sqrt; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_wflags = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_wflags : _s0_req_T_5_0_uop_fp_ctrl_wflags; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_ctrl_vec = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_vec : _s0_req_T_5_0_uop_fp_ctrl_vec; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_rob_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rob_idx : _s0_req_T_5_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ldq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ldq_idx : _s0_req_T_5_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_stq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_stq_idx : _s0_req_T_5_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_rxq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rxq_idx : _s0_req_T_5_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_pdst : _s0_req_T_5_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs1 = _s0_req_T ? _s0_req_WIRE_0_uop_prs1 : _s0_req_T_5_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs2 = _s0_req_T ? _s0_req_WIRE_0_uop_prs2 : _s0_req_T_5_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs3 = _s0_req_T ? _s0_req_WIRE_0_uop_prs3 : _s0_req_T_5_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ppred = _s0_req_T ? _s0_req_WIRE_0_uop_ppred : _s0_req_T_5_0_uop_ppred; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs1_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs1_busy : _s0_req_T_5_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs2_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs2_busy : _s0_req_T_5_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs3_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs3_busy : _s0_req_T_5_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ppred_busy = _s0_req_T ? _s0_req_WIRE_0_uop_ppred_busy : _s0_req_T_5_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_stale_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_stale_pdst : _s0_req_T_5_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_exception = _s0_req_T ? _s0_req_WIRE_0_uop_exception : _s0_req_T_5_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_uop_exc_cause = _s0_req_T ? _s0_req_WIRE_0_uop_exc_cause : _s0_req_T_5_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_mem_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_mem_cmd : _s0_req_T_5_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_mem_size = _s0_req_T ? _s0_req_WIRE_0_uop_mem_size : _s0_req_T_5_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_mem_signed = _s0_req_T ? _s0_req_WIRE_0_uop_mem_signed : _s0_req_T_5_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_ldq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_ldq : _s0_req_T_5_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_stq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_stq : _s0_req_T_5_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_unique = _s0_req_T ? _s0_req_WIRE_0_uop_is_unique : _s0_req_T_5_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_flush_on_commit = _s0_req_T ? _s0_req_WIRE_0_uop_flush_on_commit : _s0_req_T_5_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_csr_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_csr_cmd : _s0_req_T_5_0_uop_csr_cmd; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ldst_is_rs1 = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_is_rs1 : _s0_req_T_5_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_ldst : _s0_req_T_5_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs1 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1 : _s0_req_T_5_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs2 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2 : _s0_req_T_5_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs3 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs3 : _s0_req_T_5_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_dst_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_dst_rtype : _s0_req_T_5_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs1_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1_rtype : _s0_req_T_5_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs2_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2_rtype : _s0_req_T_5_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_frs3_en = _s0_req_T ? _s0_req_WIRE_0_uop_frs3_en : _s0_req_T_5_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fcn_dw = _s0_req_T ? _s0_req_WIRE_0_uop_fcn_dw : _s0_req_T_5_0_uop_fcn_dw; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_fcn_op = _s0_req_T ? _s0_req_WIRE_0_uop_fcn_op : _s0_req_T_5_0_uop_fcn_op; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_val = _s0_req_T ? _s0_req_WIRE_0_uop_fp_val : _s0_req_T_5_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_fp_rm = _s0_req_T ? _s0_req_WIRE_0_uop_fp_rm : _s0_req_T_5_0_uop_fp_rm; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_fp_typ = _s0_req_T ? _s0_req_WIRE_0_uop_fp_typ : _s0_req_T_5_0_uop_fp_typ; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_pf_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_pf_if : _s0_req_T_5_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ae_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ae_if : _s0_req_T_5_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ma_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ma_if : _s0_req_T_5_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_debug_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_debug_if : _s0_req_T_5_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_xcpt_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_xcpt_if : _s0_req_T_5_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_debug_fsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_fsrc : _s0_req_T_5_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_debug_tsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_tsrc : _s0_req_T_5_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] s0_req_0_addr = _s0_req_T ? _s0_req_WIRE_0_addr : _s0_req_T_5_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_data = _s0_req_T ? _s0_req_WIRE_0_data : _s0_req_T_5_0_data; // @[Decoupled.scala:51:35]
wire s0_req_0_is_hella = _s0_req_T ? _s0_req_WIRE_0_is_hella : _s0_req_T_5_0_is_hella; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_2 = _s0_type_T_1 ? 3'h3 : 3'h0; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_3 = _s0_type_T_2; // @[dcache.scala:624:21, :625:21]
wire [2:0] _s0_type_T_4 = prober_fire ? 3'h1 : _s0_type_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_5 = wb_fire ? 3'h2 : _s0_type_T_4; // @[dcache.scala:563:38, :622:21, :623:21]
wire [2:0] s0_type = _s0_type_T ? 3'h4 : _s0_type_T_5; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_2 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_3 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_4 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_5 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_6 = _s0_send_resp_or_nack_T_2 | _s0_send_resp_or_nack_T_3; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_7 = _s0_send_resp_or_nack_T_6 | _s0_send_resp_or_nack_T_4; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_8 = _s0_send_resp_or_nack_T_7 | _s0_send_resp_or_nack_T_5; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_9 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_10 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_11 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_12 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_13 = _s0_send_resp_or_nack_T_9 | _s0_send_resp_or_nack_T_10; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_14 = _s0_send_resp_or_nack_T_13 | _s0_send_resp_or_nack_T_11; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_15 = _s0_send_resp_or_nack_T_14 | _s0_send_resp_or_nack_T_12; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_16 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_17 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_18 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_19 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_20 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_21 = _s0_send_resp_or_nack_T_16 | _s0_send_resp_or_nack_T_17; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_22 = _s0_send_resp_or_nack_T_21 | _s0_send_resp_or_nack_T_18; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_23 = _s0_send_resp_or_nack_T_22 | _s0_send_resp_or_nack_T_19; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_24 = _s0_send_resp_or_nack_T_23 | _s0_send_resp_or_nack_T_20; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_25 = _s0_send_resp_or_nack_T_15 | _s0_send_resp_or_nack_T_24; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_26 = _s0_send_resp_or_nack_T_8 | _s0_send_resp_or_nack_T_25; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_27 = _s0_send_resp_or_nack_T_1 & _s0_send_resp_or_nack_T_26; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_28 = _s0_send_resp_or_nack_T_27; // @[dcache.scala:630:{16,38}]
wire _s0_send_resp_or_nack_T_29 = _s0_send_resp_or_nack_T_28; // @[dcache.scala:630:{16,117}]
wire _s0_send_resp_or_nack_WIRE_0 = _s0_send_resp_or_nack_T_29; // @[dcache.scala:630:{12,117}]
wire s0_send_resp_or_nack_0 = _s0_send_resp_or_nack_T ? s0_valid_0 : _s0_send_resp_or_nack_WIRE_0; // @[Decoupled.scala:51:35]
reg [31:0] s1_req_0_uop_inst; // @[dcache.scala:633:32]
reg [31:0] s1_req_0_uop_debug_inst; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_rvc; // @[dcache.scala:633:32]
reg [39:0] s1_req_0_uop_debug_pc; // @[dcache.scala:633:32]
reg s1_req_0_uop_iq_type_0; // @[dcache.scala:633:32]
reg s1_req_0_uop_iq_type_1; // @[dcache.scala:633:32]
reg s1_req_0_uop_iq_type_2; // @[dcache.scala:633:32]
reg s1_req_0_uop_iq_type_3; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_0; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_1; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_2; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_3; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_4; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_5; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_6; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_7; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_8; // @[dcache.scala:633:32]
reg s1_req_0_uop_fu_code_9; // @[dcache.scala:633:32]
reg s1_req_0_uop_iw_issued; // @[dcache.scala:633:32]
reg s1_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:633:32]
reg s1_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:633:32]
reg s1_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:633:32]
reg s1_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:633:32]
reg s1_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_dis_col_sel; // @[dcache.scala:633:32]
reg [11:0] s1_req_0_uop_br_mask; // @[dcache.scala:633:32]
reg [3:0] s1_req_0_uop_br_tag; // @[dcache.scala:633:32]
reg [3:0] s1_req_0_uop_br_type; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_sfb; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_fence; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_fencei; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_sfence; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_amo; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_eret; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_sys_pc2epc; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_rocc; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_mov; // @[dcache.scala:633:32]
reg [4:0] s1_req_0_uop_ftq_idx; // @[dcache.scala:633:32]
reg s1_req_0_uop_edge_inst; // @[dcache.scala:633:32]
reg [5:0] s1_req_0_uop_pc_lob; // @[dcache.scala:633:32]
reg s1_req_0_uop_taken; // @[dcache.scala:633:32]
reg s1_req_0_uop_imm_rename; // @[dcache.scala:633:32]
reg [2:0] s1_req_0_uop_imm_sel; // @[dcache.scala:633:32]
reg [4:0] s1_req_0_uop_pimm; // @[dcache.scala:633:32]
reg [19:0] s1_req_0_uop_imm_packed; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_op1_sel; // @[dcache.scala:633:32]
reg [2:0] s1_req_0_uop_op2_sel; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_wen; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_toint; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_fma; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_div; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_ctrl_vec; // @[dcache.scala:633:32]
reg [5:0] s1_req_0_uop_rob_idx; // @[dcache.scala:633:32]
reg [3:0] s1_req_0_uop_ldq_idx; // @[dcache.scala:633:32]
reg [3:0] s1_req_0_uop_stq_idx; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_rxq_idx; // @[dcache.scala:633:32]
reg [6:0] s1_req_0_uop_pdst; // @[dcache.scala:633:32]
reg [6:0] s1_req_0_uop_prs1; // @[dcache.scala:633:32]
reg [6:0] s1_req_0_uop_prs2; // @[dcache.scala:633:32]
reg [6:0] s1_req_0_uop_prs3; // @[dcache.scala:633:32]
reg [4:0] s1_req_0_uop_ppred; // @[dcache.scala:633:32]
reg s1_req_0_uop_prs1_busy; // @[dcache.scala:633:32]
reg s1_req_0_uop_prs2_busy; // @[dcache.scala:633:32]
reg s1_req_0_uop_prs3_busy; // @[dcache.scala:633:32]
reg s1_req_0_uop_ppred_busy; // @[dcache.scala:633:32]
reg [6:0] s1_req_0_uop_stale_pdst; // @[dcache.scala:633:32]
reg s1_req_0_uop_exception; // @[dcache.scala:633:32]
reg [63:0] s1_req_0_uop_exc_cause; // @[dcache.scala:633:32]
reg [4:0] s1_req_0_uop_mem_cmd; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_mem_size; // @[dcache.scala:633:32]
reg s1_req_0_uop_mem_signed; // @[dcache.scala:633:32]
reg s1_req_0_uop_uses_ldq; // @[dcache.scala:633:32]
reg s1_req_0_uop_uses_stq; // @[dcache.scala:633:32]
reg s1_req_0_uop_is_unique; // @[dcache.scala:633:32]
reg s1_req_0_uop_flush_on_commit; // @[dcache.scala:633:32]
reg [2:0] s1_req_0_uop_csr_cmd; // @[dcache.scala:633:32]
reg s1_req_0_uop_ldst_is_rs1; // @[dcache.scala:633:32]
reg [5:0] s1_req_0_uop_ldst; // @[dcache.scala:633:32]
reg [5:0] s1_req_0_uop_lrs1; // @[dcache.scala:633:32]
reg [5:0] s1_req_0_uop_lrs2; // @[dcache.scala:633:32]
reg [5:0] s1_req_0_uop_lrs3; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_dst_rtype; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_lrs1_rtype; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_lrs2_rtype; // @[dcache.scala:633:32]
reg s1_req_0_uop_frs3_en; // @[dcache.scala:633:32]
reg s1_req_0_uop_fcn_dw; // @[dcache.scala:633:32]
reg [4:0] s1_req_0_uop_fcn_op; // @[dcache.scala:633:32]
reg s1_req_0_uop_fp_val; // @[dcache.scala:633:32]
reg [2:0] s1_req_0_uop_fp_rm; // @[dcache.scala:633:32]
reg [1:0] s1_req_0_uop_fp_typ; // @[dcache.scala:633:32]
reg s1_req_0_uop_xcpt_pf_if; // @[dcache.scala:633:32]
reg s1_req_0_uop_xcpt_ae_if; // @[dcache.scala:633:32]
reg s1_req_0_uop_xcpt_ma_if; // @[dcache.scala:633:32]
reg s1_req_0_uop_bp_debug_if; // @[dcache.scala:633:32]
reg s1_req_0_uop_bp_xcpt_if; // @[dcache.scala:633:32]
reg [2:0] s1_req_0_uop_debug_fsrc; // @[dcache.scala:633:32]
reg [2:0] s1_req_0_uop_debug_tsrc; // @[dcache.scala:633:32]
reg [39:0] s1_req_0_addr; // @[dcache.scala:633:32]
reg [63:0] s1_req_0_data; // @[dcache.scala:633:32]
reg s1_req_0_is_hella; // @[dcache.scala:633:32]
wire [11:0] _s1_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
wire [11:0] _s1_req_0_uop_br_mask_T_1 = s0_req_0_uop_br_mask & _s1_req_0_uop_br_mask_T; // @[util.scala:93:{25,27}]
wire _s2_store_failed_T_2; // @[dcache.scala:787:67]
wire s2_store_failed; // @[dcache.scala:636:29]
wire [11:0] _s1_valid_T = io_lsu_brupdate_b1_mispredict_mask_0 & s0_req_0_uop_br_mask; // @[util.scala:126:51]
wire _s1_valid_T_1 = |_s1_valid_T; // @[util.scala:126:{51,59}]
wire _s1_valid_T_2 = _s1_valid_T_1; // @[util.scala:61:61, :126:59]
wire _s1_valid_T_3 = ~_s1_valid_T_2; // @[util.scala:61:61]
wire _s1_valid_T_4 = s0_valid_0 & _s1_valid_T_3; // @[dcache.scala:612:21, :638:74, :639:26]
wire _s1_valid_T_5 = io_lsu_exception_0 & s0_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :615:21, :640:45]
wire _s1_valid_T_6 = ~_s1_valid_T_5; // @[dcache.scala:640:{26,45}]
wire _s1_valid_T_7 = _s1_valid_T_4 & _s1_valid_T_6; // @[dcache.scala:638:74, :639:85, :640:26]
wire _s1_valid_T_9 = s2_store_failed & _s1_valid_T_8; // @[Decoupled.scala:51:35]
wire _s1_valid_T_10 = _s1_valid_T_9 & s0_req_0_uop_uses_stq; // @[dcache.scala:615:21, :641:{44,63}]
wire _s1_valid_T_11 = ~_s1_valid_T_10; // @[dcache.scala:641:{26,63}]
wire _s1_valid_T_12 = _s1_valid_T_7 & _s1_valid_T_11; // @[dcache.scala:639:85, :640:74, :641:26]
reg s1_valid_REG; // @[dcache.scala:638:25]
wire s1_valid_0 = s1_valid_REG; // @[dcache.scala:454:49, :638:25]
reg REG; // @[dcache.scala:645:43]
reg REG_1; // @[dcache.scala:645:72]
wire [5:0] _s1_nack_T = s1_req_0_addr[11:6]; // @[dcache.scala:633:32, :647:43]
wire [5:0] _s1_wb_idx_matches_T = s1_req_0_addr[11:6]; // @[dcache.scala:633:32, :647:43, :664:52]
wire _s1_nack_T_1 = _s1_nack_T == _prober_io_meta_write_bits_idx; // @[dcache.scala:459:22, :647:{43,59}]
wire _s1_nack_T_2 = ~_prober_io_req_ready; // @[dcache.scala:459:22, :647:96]
wire s1_nack_0 = _s1_nack_T_1 & _s1_nack_T_2; // @[dcache.scala:647:{59,93,96}]
wire _s2_nack_hit_WIRE_0 = s1_nack_0; // @[dcache.scala:647:93, :760:39]
reg s1_send_resp_or_nack_0; // @[dcache.scala:648:37]
reg [2:0] s1_type; // @[dcache.scala:649:32]
reg [3:0] s1_mshr_meta_read_way_en; // @[dcache.scala:651:41]
reg [3:0] s1_replay_way_en; // @[dcache.scala:652:41]
reg [3:0] s1_wb_way_en; // @[dcache.scala:653:41]
wire [27:0] _s1_tag_eq_way_T = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95]
wire [27:0] _s1_tag_eq_way_T_2 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95]
wire [27:0] _s1_tag_eq_way_T_4 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95]
wire [27:0] _s1_tag_eq_way_T_6 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95]
wire _s1_tag_eq_way_T_1 = {8'h0, _meta_0_io_resp_0_tag} == _s1_tag_eq_way_T; // @[dcache.scala:469:41, :657:{79,95}]
wire _s1_tag_eq_way_WIRE_0 = _s1_tag_eq_way_T_1; // @[dcache.scala:656:47, :657:79]
wire _s1_tag_eq_way_T_3 = {8'h0, _meta_0_io_resp_1_tag} == _s1_tag_eq_way_T_2; // @[dcache.scala:469:41, :657:{79,95}]
wire _s1_tag_eq_way_WIRE_1 = _s1_tag_eq_way_T_3; // @[dcache.scala:656:47, :657:79]
wire _s1_tag_eq_way_T_5 = {8'h0, _meta_0_io_resp_2_tag} == _s1_tag_eq_way_T_4; // @[dcache.scala:469:41, :657:{79,95}]
wire _s1_tag_eq_way_WIRE_2 = _s1_tag_eq_way_T_5; // @[dcache.scala:656:47, :657:79]
wire _s1_tag_eq_way_T_7 = {8'h0, _meta_0_io_resp_3_tag} == _s1_tag_eq_way_T_6; // @[dcache.scala:469:41, :657:{79,95}]
wire _s1_tag_eq_way_WIRE_3 = _s1_tag_eq_way_T_7; // @[dcache.scala:656:47, :657:79]
wire [1:0] s1_tag_eq_way_lo = {_s1_tag_eq_way_WIRE_1, _s1_tag_eq_way_WIRE_0}; // @[dcache.scala:656:47, :657:110]
wire [1:0] s1_tag_eq_way_hi = {_s1_tag_eq_way_WIRE_3, _s1_tag_eq_way_WIRE_2}; // @[dcache.scala:656:47, :657:110]
wire [3:0] _s1_tag_eq_way_T_8 = {s1_tag_eq_way_hi, s1_tag_eq_way_lo}; // @[dcache.scala:657:110]
wire [3:0] s1_tag_eq_way_0 = _s1_tag_eq_way_T_8; // @[dcache.scala:454:49, :657:110]
wire _s1_tag_match_way_T = s1_type == 3'h0; // @[dcache.scala:649:32, :659:38]
wire _s1_tag_match_way_T_1 = s1_type == 3'h2; // @[dcache.scala:649:32, :660:38]
wire _s1_tag_match_way_T_2 = s1_type == 3'h3; // @[dcache.scala:649:32, :661:38]
wire _s1_tag_match_way_T_3 = s1_tag_eq_way_0[0]; // @[dcache.scala:454:49, :662:63]
wire _s1_tag_match_way_T_4 = |_meta_0_io_resp_0_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_5 = _s1_tag_match_way_T_3 & _s1_tag_match_way_T_4; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_0 = _s1_tag_match_way_T_5; // @[dcache.scala:656:47, :662:67]
wire _s1_tag_match_way_T_6 = s1_tag_eq_way_0[1]; // @[dcache.scala:454:49, :662:63]
wire _s1_tag_match_way_T_7 = |_meta_0_io_resp_1_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_8 = _s1_tag_match_way_T_6 & _s1_tag_match_way_T_7; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_1 = _s1_tag_match_way_T_8; // @[dcache.scala:656:47, :662:67]
wire _s1_tag_match_way_T_9 = s1_tag_eq_way_0[2]; // @[dcache.scala:454:49, :662:63]
wire _s1_tag_match_way_T_10 = |_meta_0_io_resp_2_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_11 = _s1_tag_match_way_T_9 & _s1_tag_match_way_T_10; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_2 = _s1_tag_match_way_T_11; // @[dcache.scala:656:47, :662:67]
wire _s1_tag_match_way_T_12 = s1_tag_eq_way_0[3]; // @[dcache.scala:454:49, :662:63]
wire _s1_tag_match_way_T_13 = |_meta_0_io_resp_3_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_14 = _s1_tag_match_way_T_12 & _s1_tag_match_way_T_13; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_3 = _s1_tag_match_way_T_14; // @[dcache.scala:656:47, :662:67]
wire [1:0] s1_tag_match_way_lo = {_s1_tag_match_way_WIRE_1, _s1_tag_match_way_WIRE_0}; // @[dcache.scala:656:47, :662:104]
wire [1:0] s1_tag_match_way_hi = {_s1_tag_match_way_WIRE_3, _s1_tag_match_way_WIRE_2}; // @[dcache.scala:656:47, :662:104]
wire [3:0] _s1_tag_match_way_T_15 = {s1_tag_match_way_hi, s1_tag_match_way_lo}; // @[dcache.scala:662:104]
wire [3:0] _s1_tag_match_way_T_16 = _s1_tag_match_way_T_2 ? s1_mshr_meta_read_way_en : _s1_tag_match_way_T_15; // @[dcache.scala:651:41, :661:{29,38}, :662:104]
wire [3:0] _s1_tag_match_way_T_17 = _s1_tag_match_way_T_1 ? s1_wb_way_en : _s1_tag_match_way_T_16; // @[dcache.scala:653:41, :660:{29,38}, :661:29]
wire [3:0] _s1_tag_match_way_T_18 = _s1_tag_match_way_T ? s1_replay_way_en : _s1_tag_match_way_T_17; // @[dcache.scala:652:41, :659:{29,38}, :660:29]
wire [3:0] s1_tag_match_way_0 = _s1_tag_match_way_T_18; // @[dcache.scala:454:49, :659:29]
wire _s1_wb_idx_matches_T_1 = _s1_wb_idx_matches_T == _wb_io_idx_bits; // @[dcache.scala:458:18, :664:{52,79}]
wire _s1_wb_idx_matches_T_2 = _s1_wb_idx_matches_T_1 & _wb_io_idx_valid; // @[dcache.scala:458:18, :664:{79,99}]
wire s1_wb_idx_matches_0 = _s1_wb_idx_matches_T_2; // @[dcache.scala:454:49, :664:99]
reg [31:0] s2_req_0_uop_inst; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_inst_0 = s2_req_0_uop_inst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_inst_0 = s2_req_0_uop_inst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_inst_0 = s2_req_0_uop_inst; // @[dcache.scala:438:7, :670:25]
reg [31:0] s2_req_0_uop_debug_inst; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_debug_inst_0 = s2_req_0_uop_debug_inst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_debug_inst_0 = s2_req_0_uop_debug_inst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_debug_inst_0 = s2_req_0_uop_debug_inst; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_rvc; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_rvc_0 = s2_req_0_uop_is_rvc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_rvc_0 = s2_req_0_uop_is_rvc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_rvc_0 = s2_req_0_uop_is_rvc; // @[dcache.scala:438:7, :670:25]
reg [39:0] s2_req_0_uop_debug_pc; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_debug_pc_0 = s2_req_0_uop_debug_pc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_debug_pc_0 = s2_req_0_uop_debug_pc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_debug_pc_0 = s2_req_0_uop_debug_pc; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iq_type_0; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iq_type_0_0 = s2_req_0_uop_iq_type_0; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iq_type_0_0 = s2_req_0_uop_iq_type_0; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iq_type_0_0 = s2_req_0_uop_iq_type_0; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iq_type_1; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iq_type_1_0 = s2_req_0_uop_iq_type_1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iq_type_1_0 = s2_req_0_uop_iq_type_1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iq_type_1_0 = s2_req_0_uop_iq_type_1; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iq_type_2; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iq_type_2_0 = s2_req_0_uop_iq_type_2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iq_type_2_0 = s2_req_0_uop_iq_type_2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iq_type_2_0 = s2_req_0_uop_iq_type_2; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iq_type_3; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iq_type_3_0 = s2_req_0_uop_iq_type_3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iq_type_3_0 = s2_req_0_uop_iq_type_3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iq_type_3_0 = s2_req_0_uop_iq_type_3; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_0; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_0_0 = s2_req_0_uop_fu_code_0; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_0_0 = s2_req_0_uop_fu_code_0; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_0_0 = s2_req_0_uop_fu_code_0; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_1; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_1_0 = s2_req_0_uop_fu_code_1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_1_0 = s2_req_0_uop_fu_code_1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_1_0 = s2_req_0_uop_fu_code_1; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_2; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_2_0 = s2_req_0_uop_fu_code_2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_2_0 = s2_req_0_uop_fu_code_2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_2_0 = s2_req_0_uop_fu_code_2; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_3; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_3_0 = s2_req_0_uop_fu_code_3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_3_0 = s2_req_0_uop_fu_code_3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_3_0 = s2_req_0_uop_fu_code_3; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_4; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_4_0 = s2_req_0_uop_fu_code_4; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_4_0 = s2_req_0_uop_fu_code_4; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_4_0 = s2_req_0_uop_fu_code_4; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_5; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_5_0 = s2_req_0_uop_fu_code_5; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_5_0 = s2_req_0_uop_fu_code_5; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_5_0 = s2_req_0_uop_fu_code_5; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_6; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_6_0 = s2_req_0_uop_fu_code_6; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_6_0 = s2_req_0_uop_fu_code_6; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_6_0 = s2_req_0_uop_fu_code_6; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_7; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_7_0 = s2_req_0_uop_fu_code_7; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_7_0 = s2_req_0_uop_fu_code_7; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_7_0 = s2_req_0_uop_fu_code_7; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_8; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_8_0 = s2_req_0_uop_fu_code_8; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_8_0 = s2_req_0_uop_fu_code_8; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_8_0 = s2_req_0_uop_fu_code_8; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fu_code_9; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fu_code_9_0 = s2_req_0_uop_fu_code_9; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fu_code_9_0 = s2_req_0_uop_fu_code_9; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fu_code_9_0 = s2_req_0_uop_fu_code_9; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iw_issued; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_issued_0 = s2_req_0_uop_iw_issued; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_issued_0 = s2_req_0_uop_iw_issued; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_issued_0 = s2_req_0_uop_iw_issued; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_issued_partial_agen_0 = s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen_0 = s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_issued_partial_agen_0 = s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_issued_partial_dgen_0 = s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen_0 = s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_issued_partial_dgen_0 = s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_p1_speculative_child_0 = s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child_0 = s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_p1_speculative_child_0 = s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_p2_speculative_child_0 = s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child_0 = s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_p2_speculative_child_0 = s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_p1_bypass_hint_0 = s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint_0 = s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_p1_bypass_hint_0 = s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_p2_bypass_hint_0 = s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint_0 = s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_p2_bypass_hint_0 = s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_iw_p3_bypass_hint_0 = s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint_0 = s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_iw_p3_bypass_hint_0 = s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_dis_col_sel; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_dis_col_sel_0 = s2_req_0_uop_dis_col_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_dis_col_sel_0 = s2_req_0_uop_dis_col_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_dis_col_sel_0 = s2_req_0_uop_dis_col_sel; // @[dcache.scala:438:7, :670:25]
reg [11:0] s2_req_0_uop_br_mask; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_br_mask_0 = s2_req_0_uop_br_mask; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_br_mask_0 = s2_req_0_uop_br_mask; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_br_mask_0 = s2_req_0_uop_br_mask; // @[dcache.scala:438:7, :670:25]
reg [3:0] s2_req_0_uop_br_tag; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_br_tag_0 = s2_req_0_uop_br_tag; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_br_tag_0 = s2_req_0_uop_br_tag; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_br_tag_0 = s2_req_0_uop_br_tag; // @[dcache.scala:438:7, :670:25]
reg [3:0] s2_req_0_uop_br_type; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_br_type_0 = s2_req_0_uop_br_type; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_br_type_0 = s2_req_0_uop_br_type; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_br_type_0 = s2_req_0_uop_br_type; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_sfb; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_sfb_0 = s2_req_0_uop_is_sfb; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_sfb_0 = s2_req_0_uop_is_sfb; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_sfb_0 = s2_req_0_uop_is_sfb; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_fence; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_fence_0 = s2_req_0_uop_is_fence; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_fence_0 = s2_req_0_uop_is_fence; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_fence_0 = s2_req_0_uop_is_fence; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_fencei; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_fencei_0 = s2_req_0_uop_is_fencei; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_fencei_0 = s2_req_0_uop_is_fencei; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_fencei_0 = s2_req_0_uop_is_fencei; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_sfence; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_sfence_0 = s2_req_0_uop_is_sfence; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_sfence_0 = s2_req_0_uop_is_sfence; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_sfence_0 = s2_req_0_uop_is_sfence; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_amo; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_amo_0 = s2_req_0_uop_is_amo; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_amo_0 = s2_req_0_uop_is_amo; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_amo_0 = s2_req_0_uop_is_amo; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_eret; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_eret_0 = s2_req_0_uop_is_eret; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_eret_0 = s2_req_0_uop_is_eret; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_eret_0 = s2_req_0_uop_is_eret; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_sys_pc2epc_0 = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_sys_pc2epc_0 = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_sys_pc2epc_0 = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_rocc; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_rocc_0 = s2_req_0_uop_is_rocc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_rocc_0 = s2_req_0_uop_is_rocc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_rocc_0 = s2_req_0_uop_is_rocc; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_mov; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_mov_0 = s2_req_0_uop_is_mov; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_mov_0 = s2_req_0_uop_is_mov; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_mov_0 = s2_req_0_uop_is_mov; // @[dcache.scala:438:7, :670:25]
reg [4:0] s2_req_0_uop_ftq_idx; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_ftq_idx_0 = s2_req_0_uop_ftq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_ftq_idx_0 = s2_req_0_uop_ftq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_ftq_idx_0 = s2_req_0_uop_ftq_idx; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_edge_inst; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_edge_inst_0 = s2_req_0_uop_edge_inst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_edge_inst_0 = s2_req_0_uop_edge_inst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_edge_inst_0 = s2_req_0_uop_edge_inst; // @[dcache.scala:438:7, :670:25]
reg [5:0] s2_req_0_uop_pc_lob; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_pc_lob_0 = s2_req_0_uop_pc_lob; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_pc_lob_0 = s2_req_0_uop_pc_lob; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_pc_lob_0 = s2_req_0_uop_pc_lob; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_taken; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_taken_0 = s2_req_0_uop_taken; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_taken_0 = s2_req_0_uop_taken; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_taken_0 = s2_req_0_uop_taken; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_imm_rename; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_imm_rename_0 = s2_req_0_uop_imm_rename; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_imm_rename_0 = s2_req_0_uop_imm_rename; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_imm_rename_0 = s2_req_0_uop_imm_rename; // @[dcache.scala:438:7, :670:25]
reg [2:0] s2_req_0_uop_imm_sel; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_imm_sel_0 = s2_req_0_uop_imm_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_imm_sel_0 = s2_req_0_uop_imm_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_imm_sel_0 = s2_req_0_uop_imm_sel; // @[dcache.scala:438:7, :670:25]
reg [4:0] s2_req_0_uop_pimm; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_pimm_0 = s2_req_0_uop_pimm; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_pimm_0 = s2_req_0_uop_pimm; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_pimm_0 = s2_req_0_uop_pimm; // @[dcache.scala:438:7, :670:25]
reg [19:0] s2_req_0_uop_imm_packed; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_imm_packed_0 = s2_req_0_uop_imm_packed; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_imm_packed_0 = s2_req_0_uop_imm_packed; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_imm_packed_0 = s2_req_0_uop_imm_packed; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_op1_sel; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_op1_sel_0 = s2_req_0_uop_op1_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_op1_sel_0 = s2_req_0_uop_op1_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_op1_sel_0 = s2_req_0_uop_op1_sel; // @[dcache.scala:438:7, :670:25]
reg [2:0] s2_req_0_uop_op2_sel; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_op2_sel_0 = s2_req_0_uop_op2_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_op2_sel_0 = s2_req_0_uop_op2_sel; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_op2_sel_0 = s2_req_0_uop_op2_sel; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_ldst_0 = s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst_0 = s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_ldst_0 = s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_wen_0 = s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_wen_0 = s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_wen_0 = s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_ren1_0 = s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1_0 = s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_ren1_0 = s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_ren2_0 = s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2_0 = s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_ren2_0 = s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_ren3_0 = s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3_0 = s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_ren3_0 = s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_swap12_0 = s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12_0 = s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_swap12_0 = s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_swap23_0 = s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23_0 = s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_swap23_0 = s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn_0 = s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0 = s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn_0 = s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut_0 = s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0 = s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut_0 = s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_fromint_0 = s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint_0 = s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_fromint_0 = s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_toint_0 = s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_toint_0 = s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_toint_0 = s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe_0 = s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe_0 = s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe_0 = s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_fma_0 = s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_fma_0 = s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_fma_0 = s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_div_0 = s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_div_0 = s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_div_0 = s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_sqrt_0 = s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt_0 = s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_sqrt_0 = s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_wflags_0 = s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags_0 = s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_wflags_0 = s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_ctrl_vec_0 = s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_ctrl_vec_0 = s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_ctrl_vec_0 = s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:438:7, :670:25]
reg [5:0] s2_req_0_uop_rob_idx; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_rob_idx_0 = s2_req_0_uop_rob_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_rob_idx_0 = s2_req_0_uop_rob_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_rob_idx_0 = s2_req_0_uop_rob_idx; // @[dcache.scala:438:7, :670:25]
reg [3:0] s2_req_0_uop_ldq_idx; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_ldq_idx_0 = s2_req_0_uop_ldq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_ldq_idx_0 = s2_req_0_uop_ldq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_ldq_idx_0 = s2_req_0_uop_ldq_idx; // @[dcache.scala:438:7, :670:25]
reg [3:0] s2_req_0_uop_stq_idx; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_stq_idx_0 = s2_req_0_uop_stq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_stq_idx_0 = s2_req_0_uop_stq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_stq_idx_0 = s2_req_0_uop_stq_idx; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_rxq_idx; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_rxq_idx_0 = s2_req_0_uop_rxq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_rxq_idx_0 = s2_req_0_uop_rxq_idx; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_rxq_idx_0 = s2_req_0_uop_rxq_idx; // @[dcache.scala:438:7, :670:25]
reg [6:0] s2_req_0_uop_pdst; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_pdst_0 = s2_req_0_uop_pdst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_pdst_0 = s2_req_0_uop_pdst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_pdst_0 = s2_req_0_uop_pdst; // @[dcache.scala:438:7, :670:25]
reg [6:0] s2_req_0_uop_prs1; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_prs1_0 = s2_req_0_uop_prs1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_prs1_0 = s2_req_0_uop_prs1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_prs1_0 = s2_req_0_uop_prs1; // @[dcache.scala:438:7, :670:25]
reg [6:0] s2_req_0_uop_prs2; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_prs2_0 = s2_req_0_uop_prs2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_prs2_0 = s2_req_0_uop_prs2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_prs2_0 = s2_req_0_uop_prs2; // @[dcache.scala:438:7, :670:25]
reg [6:0] s2_req_0_uop_prs3; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_prs3_0 = s2_req_0_uop_prs3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_prs3_0 = s2_req_0_uop_prs3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_prs3_0 = s2_req_0_uop_prs3; // @[dcache.scala:438:7, :670:25]
reg [4:0] s2_req_0_uop_ppred; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_ppred_0 = s2_req_0_uop_ppred; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_ppred_0 = s2_req_0_uop_ppred; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_ppred_0 = s2_req_0_uop_ppred; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_prs1_busy; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_prs1_busy_0 = s2_req_0_uop_prs1_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_prs1_busy_0 = s2_req_0_uop_prs1_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_prs1_busy_0 = s2_req_0_uop_prs1_busy; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_prs2_busy; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_prs2_busy_0 = s2_req_0_uop_prs2_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_prs2_busy_0 = s2_req_0_uop_prs2_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_prs2_busy_0 = s2_req_0_uop_prs2_busy; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_prs3_busy; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_prs3_busy_0 = s2_req_0_uop_prs3_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_prs3_busy_0 = s2_req_0_uop_prs3_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_prs3_busy_0 = s2_req_0_uop_prs3_busy; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_ppred_busy; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_ppred_busy_0 = s2_req_0_uop_ppred_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_ppred_busy_0 = s2_req_0_uop_ppred_busy; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_ppred_busy_0 = s2_req_0_uop_ppred_busy; // @[dcache.scala:438:7, :670:25]
reg [6:0] s2_req_0_uop_stale_pdst; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_stale_pdst_0 = s2_req_0_uop_stale_pdst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_stale_pdst_0 = s2_req_0_uop_stale_pdst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_stale_pdst_0 = s2_req_0_uop_stale_pdst; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_exception; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_exception_0 = s2_req_0_uop_exception; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_exception_0 = s2_req_0_uop_exception; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_exception_0 = s2_req_0_uop_exception; // @[dcache.scala:438:7, :670:25]
reg [63:0] s2_req_0_uop_exc_cause; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_exc_cause_0 = s2_req_0_uop_exc_cause; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_exc_cause_0 = s2_req_0_uop_exc_cause; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_exc_cause_0 = s2_req_0_uop_exc_cause; // @[dcache.scala:438:7, :670:25]
reg [4:0] s2_req_0_uop_mem_cmd; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_mem_cmd_0 = s2_req_0_uop_mem_cmd; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_mem_cmd_0 = s2_req_0_uop_mem_cmd; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_mem_cmd_0 = s2_req_0_uop_mem_cmd; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_mem_size; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_mem_size_0 = s2_req_0_uop_mem_size; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_mem_size_0 = s2_req_0_uop_mem_size; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_mem_size_0 = s2_req_0_uop_mem_size; // @[dcache.scala:438:7, :670:25]
wire [1:0] size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18]
reg s2_req_0_uop_mem_signed; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_mem_signed_0 = s2_req_0_uop_mem_signed; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_mem_signed_0 = s2_req_0_uop_mem_signed; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_mem_signed_0 = s2_req_0_uop_mem_signed; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_uses_ldq; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_uses_ldq_0 = s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_uses_ldq_0 = s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_uses_ldq_0 = s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_uses_stq; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_uses_stq_0 = s2_req_0_uop_uses_stq; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_uses_stq_0 = s2_req_0_uop_uses_stq; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_uses_stq_0 = s2_req_0_uop_uses_stq; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_is_unique; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_is_unique_0 = s2_req_0_uop_is_unique; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_is_unique_0 = s2_req_0_uop_is_unique; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_is_unique_0 = s2_req_0_uop_is_unique; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_flush_on_commit; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_flush_on_commit_0 = s2_req_0_uop_flush_on_commit; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_flush_on_commit_0 = s2_req_0_uop_flush_on_commit; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_flush_on_commit_0 = s2_req_0_uop_flush_on_commit; // @[dcache.scala:438:7, :670:25]
reg [2:0] s2_req_0_uop_csr_cmd; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_csr_cmd_0 = s2_req_0_uop_csr_cmd; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_csr_cmd_0 = s2_req_0_uop_csr_cmd; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_csr_cmd_0 = s2_req_0_uop_csr_cmd; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_ldst_is_rs1_0 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_ldst_is_rs1_0 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_ldst_is_rs1_0 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:438:7, :670:25]
reg [5:0] s2_req_0_uop_ldst; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_ldst_0 = s2_req_0_uop_ldst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_ldst_0 = s2_req_0_uop_ldst; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_ldst_0 = s2_req_0_uop_ldst; // @[dcache.scala:438:7, :670:25]
reg [5:0] s2_req_0_uop_lrs1; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_lrs1_0 = s2_req_0_uop_lrs1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_lrs1_0 = s2_req_0_uop_lrs1; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_lrs1_0 = s2_req_0_uop_lrs1; // @[dcache.scala:438:7, :670:25]
reg [5:0] s2_req_0_uop_lrs2; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_lrs2_0 = s2_req_0_uop_lrs2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_lrs2_0 = s2_req_0_uop_lrs2; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_lrs2_0 = s2_req_0_uop_lrs2; // @[dcache.scala:438:7, :670:25]
reg [5:0] s2_req_0_uop_lrs3; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_lrs3_0 = s2_req_0_uop_lrs3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_lrs3_0 = s2_req_0_uop_lrs3; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_lrs3_0 = s2_req_0_uop_lrs3; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_dst_rtype; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_dst_rtype_0 = s2_req_0_uop_dst_rtype; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_dst_rtype_0 = s2_req_0_uop_dst_rtype; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_dst_rtype_0 = s2_req_0_uop_dst_rtype; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_lrs1_rtype; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_lrs1_rtype_0 = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_lrs1_rtype_0 = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_lrs1_rtype_0 = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_lrs2_rtype; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_lrs2_rtype_0 = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_lrs2_rtype_0 = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_lrs2_rtype_0 = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_frs3_en; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_frs3_en_0 = s2_req_0_uop_frs3_en; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_frs3_en_0 = s2_req_0_uop_frs3_en; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_frs3_en_0 = s2_req_0_uop_frs3_en; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fcn_dw; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fcn_dw_0 = s2_req_0_uop_fcn_dw; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fcn_dw_0 = s2_req_0_uop_fcn_dw; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fcn_dw_0 = s2_req_0_uop_fcn_dw; // @[dcache.scala:438:7, :670:25]
reg [4:0] s2_req_0_uop_fcn_op; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fcn_op_0 = s2_req_0_uop_fcn_op; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fcn_op_0 = s2_req_0_uop_fcn_op; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fcn_op_0 = s2_req_0_uop_fcn_op; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_fp_val; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_val_0 = s2_req_0_uop_fp_val; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_val_0 = s2_req_0_uop_fp_val; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_val_0 = s2_req_0_uop_fp_val; // @[dcache.scala:438:7, :670:25]
reg [2:0] s2_req_0_uop_fp_rm; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_rm_0 = s2_req_0_uop_fp_rm; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_rm_0 = s2_req_0_uop_fp_rm; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_rm_0 = s2_req_0_uop_fp_rm; // @[dcache.scala:438:7, :670:25]
reg [1:0] s2_req_0_uop_fp_typ; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_fp_typ_0 = s2_req_0_uop_fp_typ; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_fp_typ_0 = s2_req_0_uop_fp_typ; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_fp_typ_0 = s2_req_0_uop_fp_typ; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_xcpt_pf_if_0 = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_xcpt_pf_if_0 = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_xcpt_pf_if_0 = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_xcpt_ae_if_0 = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_xcpt_ae_if_0 = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_xcpt_ae_if_0 = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_xcpt_ma_if_0 = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_xcpt_ma_if_0 = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_xcpt_ma_if_0 = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_bp_debug_if; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_bp_debug_if_0 = s2_req_0_uop_bp_debug_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_bp_debug_if_0 = s2_req_0_uop_bp_debug_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_bp_debug_if_0 = s2_req_0_uop_bp_debug_if; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_bp_xcpt_if_0 = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_bp_xcpt_if_0 = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_bp_xcpt_if_0 = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:438:7, :670:25]
reg [2:0] s2_req_0_uop_debug_fsrc; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_debug_fsrc_0 = s2_req_0_uop_debug_fsrc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_debug_fsrc_0 = s2_req_0_uop_debug_fsrc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_debug_fsrc_0 = s2_req_0_uop_debug_fsrc; // @[dcache.scala:438:7, :670:25]
reg [2:0] s2_req_0_uop_debug_tsrc; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_uop_debug_tsrc_0 = s2_req_0_uop_debug_tsrc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_uop_debug_tsrc_0 = s2_req_0_uop_debug_tsrc; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_uop_debug_tsrc_0 = s2_req_0_uop_debug_tsrc; // @[dcache.scala:438:7, :670:25]
reg [39:0] s2_req_0_addr; // @[dcache.scala:670:25]
assign io_lsu_store_ack_0_bits_addr_0 = s2_req_0_addr; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_addr_0 = s2_req_0_addr; // @[dcache.scala:438:7, :670:25]
reg [63:0] s2_req_0_data; // @[dcache.scala:670:25]
assign io_lsu_store_ack_0_bits_data_0 = s2_req_0_data; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_data_0 = s2_req_0_data; // @[dcache.scala:438:7, :670:25]
reg s2_req_0_is_hella; // @[dcache.scala:670:25]
assign io_lsu_resp_0_bits_is_hella_0 = s2_req_0_is_hella; // @[dcache.scala:438:7, :670:25]
assign io_lsu_store_ack_0_bits_is_hella_0 = s2_req_0_is_hella; // @[dcache.scala:438:7, :670:25]
assign io_lsu_nack_0_bits_is_hella_0 = s2_req_0_is_hella; // @[dcache.scala:438:7, :670:25]
reg [2:0] s2_type; // @[dcache.scala:671:25]
wire _s2_valid_T = ~io_lsu_s1_kill_0_0; // @[dcache.scala:438:7, :674:26]
wire _s2_valid_T_1 = s1_valid_0 & _s2_valid_T; // @[dcache.scala:454:49, :673:39, :674:26]
wire [11:0] _s2_valid_T_2 = io_lsu_brupdate_b1_mispredict_mask_0 & s1_req_0_uop_br_mask; // @[util.scala:126:51]
wire _s2_valid_T_3 = |_s2_valid_T_2; // @[util.scala:126:{51,59}]
wire _s2_valid_T_4 = _s2_valid_T_3; // @[util.scala:61:61, :126:59]
wire _s2_valid_T_5 = ~_s2_valid_T_4; // @[util.scala:61:61]
wire _s2_valid_T_6 = _s2_valid_T_1 & _s2_valid_T_5; // @[dcache.scala:673:39, :674:45, :675:26]
wire _s2_valid_T_7 = io_lsu_exception_0 & s1_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :633:32, :676:45]
wire _s2_valid_T_8 = ~_s2_valid_T_7; // @[dcache.scala:676:{26,45}]
wire _s2_valid_T_9 = _s2_valid_T_6 & _s2_valid_T_8; // @[dcache.scala:674:45, :675:85, :676:26]
wire _s2_valid_T_10 = s1_type == 3'h4; // @[dcache.scala:649:32, :677:56]
wire _s2_valid_T_11 = s2_store_failed & _s2_valid_T_10; // @[dcache.scala:636:29, :677:{44,56}]
wire _s2_valid_T_12 = _s2_valid_T_11 & s1_req_0_uop_uses_stq; // @[dcache.scala:633:32, :677:{44,67}]
wire _s2_valid_T_13 = ~_s2_valid_T_12; // @[dcache.scala:677:{26,67}]
wire _s2_valid_T_14 = _s2_valid_T_9 & _s2_valid_T_13; // @[dcache.scala:675:85, :676:72, :677:26]
reg s2_valid_REG; // @[dcache.scala:673:26]
wire s2_valid_0 = s2_valid_REG; // @[dcache.scala:454:49, :673:26]
wire [11:0] _s2_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
wire [11:0] _s2_req_0_uop_br_mask_T_1 = s1_req_0_uop_br_mask & _s2_req_0_uop_br_mask_T; // @[util.scala:93:{25,27}]
reg [3:0] s2_tag_match_way_0; // @[dcache.scala:681:33]
wire s2_tag_match_0 = |s2_tag_match_way_0; // @[dcache.scala:681:33, :682:49]
reg [1:0] s2_hit_state_REG_state; // @[dcache.scala:683:93]
wire [1:0] _s2_hit_state_WIRE_0_state = s2_hit_state_REG_state; // @[dcache.scala:656:47, :683:93]
reg [1:0] s2_hit_state_REG_1_state; // @[dcache.scala:683:93]
wire [1:0] _s2_hit_state_WIRE_1_state_0 = s2_hit_state_REG_1_state; // @[dcache.scala:656:47, :683:93]
reg [1:0] s2_hit_state_REG_2_state; // @[dcache.scala:683:93]
wire [1:0] _s2_hit_state_WIRE_2_state = s2_hit_state_REG_2_state; // @[dcache.scala:656:47, :683:93]
reg [1:0] s2_hit_state_REG_3_state; // @[dcache.scala:683:93]
wire [1:0] _s2_hit_state_WIRE_3_state = s2_hit_state_REG_3_state; // @[dcache.scala:656:47, :683:93]
wire _s2_hit_state_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire [1:0] _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_hit_state_0_state = _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_4 = _s2_hit_state_T ? _s2_hit_state_WIRE_0_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_5 = _s2_hit_state_T_1 ? _s2_hit_state_WIRE_1_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_6 = _s2_hit_state_T_2 ? _s2_hit_state_WIRE_2_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_7 = _s2_hit_state_T_3 ? _s2_hit_state_WIRE_3_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_8 = _s2_hit_state_T_4 | _s2_hit_state_T_5; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_9 = _s2_hit_state_T_8 | _s2_hit_state_T_6; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_10 = _s2_hit_state_T_9 | _s2_hit_state_T_7; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_2 = _s2_hit_state_T_10; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_1_state = _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] mshrs_io_req_0_bits_old_meta_meta_coh_state = s2_hit_state_0_state; // @[HellaCache.scala:305:20]
wire _GEN_2 = s2_req_0_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_send_store_ack_T_2; // @[Consts.scala:90:32]
assign _s2_send_store_ack_T_2 = _GEN_2; // @[Consts.scala:90:32]
wire _mshrs_io_req_0_valid_T_46; // @[Consts.scala:90:32]
assign _mshrs_io_req_0_valid_T_46 = _GEN_2; // @[Consts.scala:90:32]
wire _s3_valid_T_1; // @[Consts.scala:90:32]
assign _s3_valid_T_1 = _GEN_2; // @[Consts.scala:90:32]
wire _GEN_3 = s2_req_0_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_send_store_ack_T_3; // @[Consts.scala:90:49]
assign _s2_send_store_ack_T_3 = _GEN_3; // @[Consts.scala:90:49]
wire _mshrs_io_req_0_valid_T_47; // @[Consts.scala:90:49]
assign _mshrs_io_req_0_valid_T_47 = _GEN_3; // @[Consts.scala:90:49]
wire _s3_valid_T_2; // @[Consts.scala:90:49]
assign _s3_valid_T_2 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_2 = _s2_has_permission_r_c_cat_T | _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_4 = s2_req_0_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_sc_T; // @[dcache.scala:702:37]
assign _s2_sc_T = _GEN_4; // @[Consts.scala:90:66]
wire _s2_send_resp_T_10; // @[package.scala:16:47]
assign _s2_send_resp_T_10 = _GEN_4; // @[package.scala:16:47]
wire _s2_send_store_ack_T_5; // @[Consts.scala:90:66]
assign _s2_send_store_ack_T_5 = _GEN_4; // @[Consts.scala:90:66]
wire _mshrs_io_req_0_valid_T_23; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_23 = _GEN_4; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_49; // @[Consts.scala:90:66]
assign _mshrs_io_req_0_valid_T_49 = _GEN_4; // @[Consts.scala:90:66]
wire _s3_valid_T_4; // @[Consts.scala:90:66]
assign _s3_valid_T_4 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_4 = _s2_has_permission_r_c_cat_T_2 | _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_5 = s2_req_0_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_resp_T_14; // @[package.scala:16:47]
assign _s2_send_resp_T_14 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_store_ack_T_7; // @[package.scala:16:47]
assign _s2_send_store_ack_T_7 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_27 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_51; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_51 = _GEN_5; // @[package.scala:16:47]
wire _s3_valid_T_6; // @[package.scala:16:47]
assign _s3_valid_T_6 = _GEN_5; // @[package.scala:16:47]
wire _GEN_6 = s2_req_0_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_resp_T_15; // @[package.scala:16:47]
assign _s2_send_resp_T_15 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_store_ack_T_8; // @[package.scala:16:47]
assign _s2_send_store_ack_T_8 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_28; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_28 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_52; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_52 = _GEN_6; // @[package.scala:16:47]
wire _s3_valid_T_7; // @[package.scala:16:47]
assign _s3_valid_T_7 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = s2_req_0_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_resp_T_16; // @[package.scala:16:47]
assign _s2_send_resp_T_16 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_store_ack_T_9; // @[package.scala:16:47]
assign _s2_send_store_ack_T_9 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_29; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_29 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_53; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_53 = _GEN_7; // @[package.scala:16:47]
wire _s3_valid_T_8; // @[package.scala:16:47]
assign _s3_valid_T_8 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = s2_req_0_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_resp_T_17; // @[package.scala:16:47]
assign _s2_send_resp_T_17 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_store_ack_T_10; // @[package.scala:16:47]
assign _s2_send_store_ack_T_10 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_30; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_30 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_54; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_54 = _GEN_8; // @[package.scala:16:47]
wire _s3_valid_T_9; // @[package.scala:16:47]
assign _s3_valid_T_9 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_9 = _s2_has_permission_r_c_cat_T_5 | _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_10 = _s2_has_permission_r_c_cat_T_9 | _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_11 = _s2_has_permission_r_c_cat_T_10 | _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_9 = s2_req_0_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_resp_T_21; // @[package.scala:16:47]
assign _s2_send_resp_T_21 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_store_ack_T_14; // @[package.scala:16:47]
assign _s2_send_store_ack_T_14 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_34 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_58 = _GEN_9; // @[package.scala:16:47]
wire _s3_valid_T_13; // @[package.scala:16:47]
assign _s3_valid_T_13 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = s2_req_0_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_resp_T_22; // @[package.scala:16:47]
assign _s2_send_resp_T_22 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_store_ack_T_15; // @[package.scala:16:47]
assign _s2_send_store_ack_T_15 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_35; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_35 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_59; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_59 = _GEN_10; // @[package.scala:16:47]
wire _s3_valid_T_14; // @[package.scala:16:47]
assign _s3_valid_T_14 = _GEN_10; // @[package.scala:16:47]
wire _GEN_11 = s2_req_0_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_resp_T_23; // @[package.scala:16:47]
assign _s2_send_resp_T_23 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_store_ack_T_16; // @[package.scala:16:47]
assign _s2_send_store_ack_T_16 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_36; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_36 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_60; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_60 = _GEN_11; // @[package.scala:16:47]
wire _s3_valid_T_15; // @[package.scala:16:47]
assign _s3_valid_T_15 = _GEN_11; // @[package.scala:16:47]
wire _GEN_12 = s2_req_0_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_resp_T_24; // @[package.scala:16:47]
assign _s2_send_resp_T_24 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_store_ack_T_17; // @[package.scala:16:47]
assign _s2_send_store_ack_T_17 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_37; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_37 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_61; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_61 = _GEN_12; // @[package.scala:16:47]
wire _s3_valid_T_16; // @[package.scala:16:47]
assign _s3_valid_T_16 = _GEN_12; // @[package.scala:16:47]
wire _GEN_13 = s2_req_0_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_resp_T_25; // @[package.scala:16:47]
assign _s2_send_resp_T_25 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_store_ack_T_18; // @[package.scala:16:47]
assign _s2_send_store_ack_T_18 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_38; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_38 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_62; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_62 = _GEN_13; // @[package.scala:16:47]
wire _s3_valid_T_17; // @[package.scala:16:47]
assign _s3_valid_T_17 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_17 = _s2_has_permission_r_c_cat_T_12 | _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_18 = _s2_has_permission_r_c_cat_T_17 | _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_19 = _s2_has_permission_r_c_cat_T_18 | _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_20 = _s2_has_permission_r_c_cat_T_19 | _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_21 = _s2_has_permission_r_c_cat_T_11 | _s2_has_permission_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_22 = _s2_has_permission_r_c_cat_T_4 | _s2_has_permission_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_has_permission_r_c_cat_T_25 = _s2_has_permission_r_c_cat_T_23 | _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_has_permission_r_c_cat_T_27 = _s2_has_permission_r_c_cat_T_25 | _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_has_permission_r_c_cat_T_32 = _s2_has_permission_r_c_cat_T_28 | _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_33 = _s2_has_permission_r_c_cat_T_32 | _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_34 = _s2_has_permission_r_c_cat_T_33 | _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_40 = _s2_has_permission_r_c_cat_T_35 | _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_41 = _s2_has_permission_r_c_cat_T_40 | _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_42 = _s2_has_permission_r_c_cat_T_41 | _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_43 = _s2_has_permission_r_c_cat_T_42 | _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_44 = _s2_has_permission_r_c_cat_T_34 | _s2_has_permission_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_45 = _s2_has_permission_r_c_cat_T_27 | _s2_has_permission_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_14 = s2_req_0_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_has_permission_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_new_hit_state_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _mshrs_io_req_0_valid_T_18; // @[Consts.scala:88:52]
assign _mshrs_io_req_0_valid_T_18 = _GEN_14; // @[Consts.scala:88:52, :91:54]
wire _s2_has_permission_r_c_cat_T_47 = _s2_has_permission_r_c_cat_T_45 | _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_15 = s2_req_0_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_has_permission_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_new_hit_state_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_lr_T; // @[dcache.scala:701:37]
assign _s2_lr_T = _GEN_15; // @[Consts.scala:91:71]
wire _s2_send_resp_T_9; // @[package.scala:16:47]
assign _s2_send_resp_T_9 = _GEN_15; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_22; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_22 = _GEN_15; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_49 = _s2_has_permission_r_c_cat_T_47 | _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_has_permission_r_c = {_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_has_permission_r_T = {s2_has_permission_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_has_permission_r_T_25 = _s2_has_permission_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_27 = {1'h0, _s2_has_permission_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_28 = _s2_has_permission_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_30 = _s2_has_permission_r_T_28 ? 2'h2 : _s2_has_permission_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_31 = _s2_has_permission_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_33 = _s2_has_permission_r_T_31 ? 2'h1 : _s2_has_permission_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_34 = _s2_has_permission_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_36 = _s2_has_permission_r_T_34 ? 2'h2 : _s2_has_permission_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_37 = _s2_has_permission_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_39 = _s2_has_permission_r_T_37 ? 2'h0 : _s2_has_permission_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_40 = _s2_has_permission_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_41 = _s2_has_permission_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_42 = _s2_has_permission_r_T_40 ? 2'h3 : _s2_has_permission_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_43 = &_s2_has_permission_r_T; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_44 = _s2_has_permission_r_T_43 | _s2_has_permission_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_45 = _s2_has_permission_r_T_43 ? 2'h3 : _s2_has_permission_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_46 = _s2_has_permission_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_47 = _s2_has_permission_r_T_46 | _s2_has_permission_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_48 = _s2_has_permission_r_T_46 ? 2'h2 : _s2_has_permission_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_49 = _s2_has_permission_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_50 = _s2_has_permission_r_T_49 | _s2_has_permission_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_51 = _s2_has_permission_r_T_49 ? 2'h3 : _s2_has_permission_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_52 = _s2_has_permission_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_53 = _s2_has_permission_r_T_52 | _s2_has_permission_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_54 = _s2_has_permission_r_T_52 ? 2'h1 : _s2_has_permission_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_55 = _s2_has_permission_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_56 = _s2_has_permission_r_T_55 | _s2_has_permission_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_57 = _s2_has_permission_r_T_55 ? 2'h2 : _s2_has_permission_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_58 = _s2_has_permission_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_has_permission_r_1 = _s2_has_permission_r_T_58 | _s2_has_permission_r_T_56; // @[Misc.scala:35:9, :49:20]
wire s2_has_permission_0 = s2_has_permission_r_1; // @[Misc.scala:35:9]
wire [1:0] s2_has_permission_r_2 = _s2_has_permission_r_T_58 ? 2'h3 : _s2_has_permission_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_has_permission_meta_state = s2_has_permission_r_2; // @[Misc.scala:35:36]
wire _s2_new_hit_state_r_c_cat_T_2 = _s2_new_hit_state_r_c_cat_T | _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_4 = _s2_new_hit_state_r_c_cat_T_2 | _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_9 = _s2_new_hit_state_r_c_cat_T_5 | _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_10 = _s2_new_hit_state_r_c_cat_T_9 | _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_11 = _s2_new_hit_state_r_c_cat_T_10 | _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_17 = _s2_new_hit_state_r_c_cat_T_12 | _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_18 = _s2_new_hit_state_r_c_cat_T_17 | _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_19 = _s2_new_hit_state_r_c_cat_T_18 | _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_20 = _s2_new_hit_state_r_c_cat_T_19 | _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_21 = _s2_new_hit_state_r_c_cat_T_11 | _s2_new_hit_state_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_22 = _s2_new_hit_state_r_c_cat_T_4 | _s2_new_hit_state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_25 = _s2_new_hit_state_r_c_cat_T_23 | _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_27 = _s2_new_hit_state_r_c_cat_T_25 | _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_32 = _s2_new_hit_state_r_c_cat_T_28 | _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_33 = _s2_new_hit_state_r_c_cat_T_32 | _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_34 = _s2_new_hit_state_r_c_cat_T_33 | _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_40 = _s2_new_hit_state_r_c_cat_T_35 | _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_41 = _s2_new_hit_state_r_c_cat_T_40 | _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_42 = _s2_new_hit_state_r_c_cat_T_41 | _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_43 = _s2_new_hit_state_r_c_cat_T_42 | _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_44 = _s2_new_hit_state_r_c_cat_T_34 | _s2_new_hit_state_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_45 = _s2_new_hit_state_r_c_cat_T_27 | _s2_new_hit_state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_47 = _s2_new_hit_state_r_c_cat_T_45 | _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _s2_new_hit_state_r_c_cat_T_49 = _s2_new_hit_state_r_c_cat_T_47 | _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_new_hit_state_r_c = {_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_new_hit_state_r_T = {s2_new_hit_state_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_new_hit_state_r_T_25 = _s2_new_hit_state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_27 = {1'h0, _s2_new_hit_state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_28 = _s2_new_hit_state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_30 = _s2_new_hit_state_r_T_28 ? 2'h2 : _s2_new_hit_state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_31 = _s2_new_hit_state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_33 = _s2_new_hit_state_r_T_31 ? 2'h1 : _s2_new_hit_state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_34 = _s2_new_hit_state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_36 = _s2_new_hit_state_r_T_34 ? 2'h2 : _s2_new_hit_state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_37 = _s2_new_hit_state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_39 = _s2_new_hit_state_r_T_37 ? 2'h0 : _s2_new_hit_state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_40 = _s2_new_hit_state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_41 = _s2_new_hit_state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_42 = _s2_new_hit_state_r_T_40 ? 2'h3 : _s2_new_hit_state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_43 = &_s2_new_hit_state_r_T; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_44 = _s2_new_hit_state_r_T_43 | _s2_new_hit_state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_45 = _s2_new_hit_state_r_T_43 ? 2'h3 : _s2_new_hit_state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_46 = _s2_new_hit_state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_47 = _s2_new_hit_state_r_T_46 | _s2_new_hit_state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_48 = _s2_new_hit_state_r_T_46 ? 2'h2 : _s2_new_hit_state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_49 = _s2_new_hit_state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_50 = _s2_new_hit_state_r_T_49 | _s2_new_hit_state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_51 = _s2_new_hit_state_r_T_49 ? 2'h3 : _s2_new_hit_state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_52 = _s2_new_hit_state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_53 = _s2_new_hit_state_r_T_52 | _s2_new_hit_state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_54 = _s2_new_hit_state_r_T_52 ? 2'h1 : _s2_new_hit_state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_55 = _s2_new_hit_state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_56 = _s2_new_hit_state_r_T_55 | _s2_new_hit_state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_57 = _s2_new_hit_state_r_T_55 ? 2'h2 : _s2_new_hit_state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_58 = _s2_new_hit_state_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_new_hit_state_r_1 = _s2_new_hit_state_r_T_58 | _s2_new_hit_state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] s2_new_hit_state_r_2 = _s2_new_hit_state_r_T_58 ? 2'h3 : _s2_new_hit_state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_new_hit_state_meta_state = s2_new_hit_state_r_2; // @[Misc.scala:35:36]
wire [1:0] s2_new_hit_state_0_state = s2_new_hit_state_meta_state; // @[Metadata.scala:160:20]
wire _s2_hit_T = s2_tag_match_0 & s2_has_permission_0; // @[dcache.scala:454:49, :682:49, :687:47]
wire _s2_hit_T_1 = s2_hit_state_0_state == s2_new_hit_state_0_state; // @[Metadata.scala:46:46]
wire _s2_hit_T_2 = _s2_hit_T & _s2_hit_T_1; // @[Metadata.scala:46:46]
wire _s2_hit_T_3 = ~_mshrs_io_block_hit_0; // @[dcache.scala:460:21, :687:117]
wire _s2_hit_T_4 = _s2_hit_T_2 & _s2_hit_T_3; // @[dcache.scala:687:{71,114,117}]
wire _T_75 = s2_type == 3'h0; // @[package.scala:16:47]
wire _s2_hit_T_5; // @[package.scala:16:47]
assign _s2_hit_T_5 = _T_75; // @[package.scala:16:47]
wire _s2_lr_T_2; // @[dcache.scala:701:83]
assign _s2_lr_T_2 = _T_75; // @[package.scala:16:47]
wire _s2_sc_T_2; // @[dcache.scala:702:83]
assign _s2_sc_T_2 = _T_75; // @[package.scala:16:47]
wire _s2_send_resp_T_3; // @[dcache.scala:774:77]
assign _s2_send_resp_T_3 = _T_75; // @[package.scala:16:47]
wire _s2_hit_T_6 = s2_type == 3'h2; // @[package.scala:16:47]
wire _s2_hit_T_7 = _s2_hit_T_5 | _s2_hit_T_6; // @[package.scala:16:47, :81:59]
wire _s2_hit_T_8 = _s2_hit_T_4 | _s2_hit_T_7; // @[package.scala:81:59]
wire s2_hit_0 = _s2_hit_T_8; // @[dcache.scala:454:49, :687:141]
wire s2_nack_0; // @[dcache.scala:688:21]
reg s2_wb_idx_matches_0; // @[dcache.scala:692:34]
reg [39:0] debug_sc_fail_addr; // @[dcache.scala:695:35]
reg [7:0] debug_sc_fail_cnt; // @[dcache.scala:696:35]
reg [6:0] lrsc_count; // @[dcache.scala:698:27]
wire lrsc_valid = |(lrsc_count[6:2]); // @[dcache.scala:698:27, :699:31]
reg [33:0] lrsc_addr; // @[dcache.scala:700:23]
reg s2_lr_REG; // @[dcache.scala:701:59]
wire _s2_lr_T_1 = ~s2_lr_REG; // @[dcache.scala:701:{51,59}]
wire _s2_lr_T_3 = _s2_lr_T_1 | _s2_lr_T_2; // @[dcache.scala:701:{51,72,83}]
wire s2_lr = _s2_lr_T & _s2_lr_T_3; // @[dcache.scala:701:{37,47,72}]
reg s2_sc_REG; // @[dcache.scala:702:59]
wire _s2_sc_T_1 = ~s2_sc_REG; // @[dcache.scala:702:{51,59}]
wire _s2_sc_T_3 = _s2_sc_T_1 | _s2_sc_T_2; // @[dcache.scala:702:{51,72,83}]
wire s2_sc = _s2_sc_T & _s2_sc_T_3; // @[dcache.scala:702:{37,47,72}]
wire io_lsu_resp_0_bits_data_doZero_2 = s2_sc; // @[AMOALU.scala:43:31]
wire [33:0] _s2_lrsc_addr_match_T = s2_req_0_addr[39:6]; // @[dcache.scala:670:25, :703:86]
wire [33:0] _lrsc_addr_T = s2_req_0_addr[39:6]; // @[dcache.scala:670:25, :703:86, :710:35]
wire _s2_lrsc_addr_match_T_1 = lrsc_addr == _s2_lrsc_addr_match_T; // @[dcache.scala:700:23, :703:{66,86}]
wire _s2_lrsc_addr_match_T_2 = lrsc_valid & _s2_lrsc_addr_match_T_1; // @[dcache.scala:699:31, :703:{53,66}]
wire s2_lrsc_addr_match_0 = _s2_lrsc_addr_match_T_2; // @[dcache.scala:454:49, :703:53]
wire _s2_sc_fail_T = ~s2_lrsc_addr_match_0; // @[dcache.scala:454:49, :704:29]
wire s2_sc_fail = s2_sc & _s2_sc_fail_T; // @[dcache.scala:702:47, :704:{26,29}]
wire [7:0] _lrsc_count_T = {1'h0, lrsc_count} - 8'h1; // @[dcache.scala:698:27, :705:54]
wire [6:0] _lrsc_count_T_1 = _lrsc_count_T[6:0]; // @[dcache.scala:705:54]
wire _mshrs_io_req_0_valid_T_10 = s2_type == 3'h4; // @[package.scala:16:47]
wire [8:0] _debug_sc_fail_cnt_T = {1'h0, debug_sc_fail_cnt} + 9'h1; // @[dcache.scala:696:35, :730:48]
wire [7:0] _debug_sc_fail_cnt_T_1 = _debug_sc_fail_cnt_T[7:0]; // @[dcache.scala:730:48]
wire [63:0] s2_data_0_0; // @[dcache.scala:743:21]
wire [63:0] s2_data_0_1; // @[dcache.scala:743:21]
wire [63:0] s2_data_0_2; // @[dcache.scala:743:21]
wire [63:0] s2_data_0_3; // @[dcache.scala:743:21]
wire [63:0] _s2_data_muxed_T_4 = _s2_data_muxed_T ? s2_data_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_5 = _s2_data_muxed_T_1 ? s2_data_0_1 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_6 = _s2_data_muxed_T_2 ? s2_data_0_2 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_7 = _s2_data_muxed_T_3 ? s2_data_0_3 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_8 = _s2_data_muxed_T_4 | _s2_data_muxed_T_5; // @[Mux.scala:30:73]
wire [63:0] _s2_data_muxed_T_9 = _s2_data_muxed_T_8 | _s2_data_muxed_T_6; // @[Mux.scala:30:73]
wire [63:0] _s2_data_muxed_T_10 = _s2_data_muxed_T_9 | _s2_data_muxed_T_7; // @[Mux.scala:30:73]
wire [63:0] _s2_data_muxed_WIRE = _s2_data_muxed_T_10; // @[Mux.scala:30:73]
wire [63:0] s2_data_muxed_0 = _s2_data_muxed_WIRE; // @[Mux.scala:30:73]
wire [63:0] _s2_data_word_prebypass_T_1 = s2_data_muxed_0; // @[dcache.scala:454:49, :868:63]
wire replace; // @[Replacement.scala:37:29]
wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17]
wire [1:0] _s1_replaced_way_en_T = lfsr[1:0]; // @[PRNG.scala:95:17]
wire [1:0] _s2_replaced_way_en_T = lfsr[1:0]; // @[PRNG.scala:95:17]
wire [3:0] s1_replaced_way_en = 4'h1 << _s1_replaced_way_en_T; // @[OneHot.scala:58:35]
reg [1:0] s2_replaced_way_en_REG; // @[dcache.scala:756:44]
wire [3:0] s2_replaced_way_en = 4'h1 << s2_replaced_way_en_REG; // @[OneHot.scala:58:35]
reg [1:0] s2_repl_meta_REG_coh_state; // @[dcache.scala:757:88]
wire [1:0] _s2_repl_meta_WIRE_0_coh_state = s2_repl_meta_REG_coh_state; // @[dcache.scala:656:47, :757:88]
reg [19:0] s2_repl_meta_REG_tag; // @[dcache.scala:757:88]
wire [19:0] _s2_repl_meta_WIRE_0_tag = s2_repl_meta_REG_tag; // @[dcache.scala:656:47, :757:88]
reg [1:0] s2_repl_meta_REG_1_coh_state; // @[dcache.scala:757:88]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state_0 = s2_repl_meta_REG_1_coh_state; // @[dcache.scala:656:47, :757:88]
reg [19:0] s2_repl_meta_REG_1_tag; // @[dcache.scala:757:88]
wire [19:0] _s2_repl_meta_WIRE_1_tag_0 = s2_repl_meta_REG_1_tag; // @[dcache.scala:656:47, :757:88]
reg [1:0] s2_repl_meta_REG_2_coh_state; // @[dcache.scala:757:88]
wire [1:0] _s2_repl_meta_WIRE_2_coh_state = s2_repl_meta_REG_2_coh_state; // @[dcache.scala:656:47, :757:88]
reg [19:0] s2_repl_meta_REG_2_tag; // @[dcache.scala:757:88]
wire [19:0] _s2_repl_meta_WIRE_2_tag = s2_repl_meta_REG_2_tag; // @[dcache.scala:656:47, :757:88]
reg [1:0] s2_repl_meta_REG_3_coh_state; // @[dcache.scala:757:88]
wire [1:0] _s2_repl_meta_WIRE_3_coh_state = s2_repl_meta_REG_3_coh_state; // @[dcache.scala:656:47, :757:88]
reg [19:0] s2_repl_meta_REG_3_tag; // @[dcache.scala:757:88]
wire [19:0] _s2_repl_meta_WIRE_3_tag = s2_repl_meta_REG_3_tag; // @[dcache.scala:656:47, :757:88]
wire _s2_repl_meta_T = s2_replaced_way_en[0]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_1 = s2_replaced_way_en[1]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_2 = s2_replaced_way_en[2]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_3 = s2_replaced_way_en[3]; // @[OneHot.scala:58:35]
wire [1:0] _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_repl_meta_0_coh_state = _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [19:0] s2_repl_meta_0_tag = _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_4 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_5 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_tag_0 : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_6 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_7 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_8 = _s2_repl_meta_T_4 | _s2_repl_meta_T_5; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_9 = _s2_repl_meta_T_8 | _s2_repl_meta_T_6; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_10 = _s2_repl_meta_T_9 | _s2_repl_meta_T_7; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_2 = _s2_repl_meta_T_10; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_tag = _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_coh_state = _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_11 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_12 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_coh_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_13 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_14 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_15 = _s2_repl_meta_T_11 | _s2_repl_meta_T_12; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_16 = _s2_repl_meta_T_15 | _s2_repl_meta_T_13; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_17 = _s2_repl_meta_T_16 | _s2_repl_meta_T_14; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_4 = _s2_repl_meta_T_17; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_3_state = _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
wire [19:0] mshrs_io_req_0_bits_old_meta_meta_tag = s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
reg s2_nack_hit_0; // @[dcache.scala:760:31]
wire _GEN_16 = s2_valid_0 & s2_hit_0; // @[dcache.scala:454:49, :762:50]
wire _s2_nack_victim_T; // @[dcache.scala:762:50]
assign _s2_nack_victim_T = _GEN_16; // @[dcache.scala:762:50]
wire _s3_valid_T; // @[dcache.scala:897:38]
assign _s3_valid_T = _GEN_16; // @[dcache.scala:762:50, :897:38]
wire _s2_nack_victim_T_1 = _s2_nack_victim_T & _mshrs_io_secondary_miss_0; // @[dcache.scala:460:21, :762:{50,64}]
wire s2_nack_victim_0 = _s2_nack_victim_T_1; // @[dcache.scala:454:49, :762:64]
wire _s2_nack_miss_T = ~s2_hit_0; // @[dcache.scala:454:49, :689:36, :764:53]
wire _s2_nack_miss_T_1 = s2_valid_0 & _s2_nack_miss_T; // @[dcache.scala:454:49, :764:{50,53}]
wire _s2_nack_miss_T_2 = ~_mshrs_io_req_0_ready; // @[dcache.scala:460:21, :764:67]
wire _s2_nack_miss_T_3 = _s2_nack_miss_T_1 & _s2_nack_miss_T_2; // @[dcache.scala:764:{50,64,67}]
wire s2_nack_miss_0 = _s2_nack_miss_T_3; // @[dcache.scala:454:49, :764:64]
wire _s2_nack_wb_T = ~s2_hit_0; // @[dcache.scala:454:49, :689:36, :768:53]
wire _s2_nack_wb_T_1 = s2_valid_0 & _s2_nack_wb_T; // @[dcache.scala:454:49, :768:{50,53}]
wire _s2_nack_wb_T_2 = _s2_nack_wb_T_1 & s2_wb_idx_matches_0; // @[dcache.scala:692:34, :768:{50,64}]
wire s2_nack_wb_0 = _s2_nack_wb_T_2; // @[dcache.scala:454:49, :768:64]
assign s2_nack_0 = (s2_nack_miss_0 | s2_nack_hit_0 | s2_nack_victim_0 | s2_nack_wb_0) & (|s2_type); // @[dcache.scala:454:49, :671:25, :688:21, :760:31, :770:{55,73,113,131,142}]
reg s2_send_resp_REG; // @[dcache.scala:773:12]
wire _s2_send_resp_T = s2_nack_hit_0 | s2_nack_victim_0; // @[dcache.scala:454:49, :760:31, :774:25]
wire _s2_send_resp_T_1 = _s2_send_resp_T; // @[dcache.scala:774:{25,46}]
wire _s2_send_resp_T_2 = ~_s2_send_resp_T_1; // @[dcache.scala:774:{8,46}]
wire _s2_send_resp_T_4 = _s2_send_resp_T_2 | _s2_send_resp_T_3; // @[dcache.scala:774:{8,66,77}]
wire _s2_send_resp_T_5 = s2_send_resp_REG & _s2_send_resp_T_4; // @[dcache.scala:773:{12,38}, :774:66]
wire _s2_send_resp_T_6 = _s2_send_resp_T_5 & s2_hit_0; // @[dcache.scala:454:49, :773:38, :774:91]
wire _GEN_17 = s2_req_0_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s2_send_resp_T_7; // @[package.scala:16:47]
assign _s2_send_resp_T_7 = _GEN_17; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_20; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_20 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = s2_req_0_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s2_send_resp_T_8; // @[package.scala:16:47]
assign _s2_send_resp_T_8 = _GEN_18; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_21; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_21 = _GEN_18; // @[package.scala:16:47]
wire _s2_send_resp_T_11 = _s2_send_resp_T_7 | _s2_send_resp_T_8; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_12 = _s2_send_resp_T_11 | _s2_send_resp_T_9; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_13 = _s2_send_resp_T_12 | _s2_send_resp_T_10; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_18 = _s2_send_resp_T_14 | _s2_send_resp_T_15; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_19 = _s2_send_resp_T_18 | _s2_send_resp_T_16; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_20 = _s2_send_resp_T_19 | _s2_send_resp_T_17; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_26 = _s2_send_resp_T_21 | _s2_send_resp_T_22; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_27 = _s2_send_resp_T_26 | _s2_send_resp_T_23; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_28 = _s2_send_resp_T_27 | _s2_send_resp_T_24; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_29 = _s2_send_resp_T_28 | _s2_send_resp_T_25; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_30 = _s2_send_resp_T_20 | _s2_send_resp_T_29; // @[package.scala:81:59]
wire _s2_send_resp_T_31 = _s2_send_resp_T_13 | _s2_send_resp_T_30; // @[package.scala:81:59]
wire _s2_send_resp_T_32 = _s2_send_resp_T_6 & _s2_send_resp_T_31; // @[Consts.scala:89:68]
wire s2_send_resp_0 = _s2_send_resp_T_32; // @[dcache.scala:454:49, :775:17]
reg s2_send_store_ack_REG; // @[dcache.scala:778:12]
wire _s2_send_store_ack_T = ~s2_nack_0; // @[dcache.scala:688:21, :706:60, :778:41]
wire _s2_send_store_ack_T_1 = s2_send_store_ack_REG & _s2_send_store_ack_T; // @[dcache.scala:778:{12,38,41}]
wire _s2_send_store_ack_T_4 = _s2_send_store_ack_T_2 | _s2_send_store_ack_T_3; // @[Consts.scala:90:{32,42,49}]
wire _s2_send_store_ack_T_6 = _s2_send_store_ack_T_4 | _s2_send_store_ack_T_5; // @[Consts.scala:90:{42,59,66}]
wire _s2_send_store_ack_T_11 = _s2_send_store_ack_T_7 | _s2_send_store_ack_T_8; // @[package.scala:16:47, :81:59]
wire _s2_send_store_ack_T_12 = _s2_send_store_ack_T_11 | _s2_send_store_ack_T_9; // @[package.scala:16:47, :81:59]
wire _s2_send_store_ack_T_13 = _s2_send_store_ack_T_12 | _s2_send_store_ack_T_10; // @[package.scala:16:47, :81:59]
wire _s2_send_store_ack_T_19 = _s2_send_store_ack_T_14 | _s2_send_store_ack_T_15; // @[package.scala:16:47, :81:59]
wire _s2_send_store_ack_T_20 = _s2_send_store_ack_T_19 | _s2_send_store_ack_T_16; // @[package.scala:16:47, :81:59]
wire _s2_send_store_ack_T_21 = _s2_send_store_ack_T_20 | _s2_send_store_ack_T_17; // @[package.scala:16:47, :81:59]
wire _s2_send_store_ack_T_22 = _s2_send_store_ack_T_21 | _s2_send_store_ack_T_18; // @[package.scala:16:47, :81:59]
wire _s2_send_store_ack_T_23 = _s2_send_store_ack_T_13 | _s2_send_store_ack_T_22; // @[package.scala:81:59]
wire _s2_send_store_ack_T_24 = _s2_send_store_ack_T_6 | _s2_send_store_ack_T_23; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_send_store_ack_T_25 = _s2_send_store_ack_T_1 & _s2_send_store_ack_T_24; // @[Consts.scala:90:76]
wire _mshrs_io_req_0_valid_T_70; // @[dcache.scala:798:77]
wire _T_81 = _mshrs_io_req_0_ready & _mshrs_io_req_0_valid_T_70; // @[Decoupled.scala:51:35]
assign replace = _T_81; // @[Decoupled.scala:51:35]
wire _s2_send_store_ack_T_26; // @[Decoupled.scala:51:35]
assign _s2_send_store_ack_T_26 = _T_81; // @[Decoupled.scala:51:35]
wire _s2_send_store_ack_T_27 = s2_hit_0 | _s2_send_store_ack_T_26; // @[Decoupled.scala:51:35]
wire _s2_send_store_ack_T_28 = _s2_send_store_ack_T_25 & _s2_send_store_ack_T_27; // @[dcache.scala:778:{53,87}, :779:18]
wire s2_send_store_ack_0 = _s2_send_store_ack_T_28; // @[dcache.scala:454:49, :778:87]
reg s2_send_nack_REG; // @[dcache.scala:780:44]
wire _s2_send_nack_T = s2_send_nack_REG & s2_nack_0; // @[dcache.scala:688:21, :780:{44,70}]
wire s2_send_nack_0 = _s2_send_nack_T; // @[dcache.scala:454:49, :780:70]
wire _s2_store_failed_T = s2_valid_0 & s2_nack_0; // @[dcache.scala:454:49, :688:21, :787:34]
wire _s2_store_failed_T_1 = _s2_store_failed_T & s2_send_nack_0; // @[dcache.scala:454:49, :787:{34,48}]
assign _s2_store_failed_T_2 = _s2_store_failed_T_1 & s2_req_0_uop_uses_stq; // @[dcache.scala:670:25, :787:{48,67}]
assign s2_store_failed = _s2_store_failed_T_2; // @[dcache.scala:636:29, :787:67]
wire _mshrs_io_req_0_valid_T = ~s2_hit_0; // @[dcache.scala:454:49, :689:36, :792:29]
wire _mshrs_io_req_0_valid_T_1 = s2_valid_0 & _mshrs_io_req_0_valid_T; // @[dcache.scala:454:49, :791:51, :792:29]
wire _mshrs_io_req_0_valid_T_2 = ~s2_nack_hit_0; // @[dcache.scala:760:31, :793:29]
wire _mshrs_io_req_0_valid_T_3 = _mshrs_io_req_0_valid_T_1 & _mshrs_io_req_0_valid_T_2; // @[dcache.scala:791:51, :792:51, :793:29]
wire _mshrs_io_req_0_valid_T_4 = ~s2_nack_victim_0; // @[dcache.scala:454:49, :794:29]
wire _mshrs_io_req_0_valid_T_5 = _mshrs_io_req_0_valid_T_3 & _mshrs_io_req_0_valid_T_4; // @[dcache.scala:792:51, :793:51, :794:29]
wire _mshrs_io_req_0_valid_T_7 = _mshrs_io_req_0_valid_T_5; // @[dcache.scala:793:51, :794:51]
wire _mshrs_io_req_0_valid_T_8 = ~s2_nack_wb_0; // @[dcache.scala:454:49, :796:29]
wire _mshrs_io_req_0_valid_T_9 = _mshrs_io_req_0_valid_T_7 & _mshrs_io_req_0_valid_T_8; // @[dcache.scala:794:51, :795:51, :796:29]
wire _mshrs_io_req_0_valid_T_11 = s2_type == 3'h5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_12 = _mshrs_io_req_0_valid_T_10 | _mshrs_io_req_0_valid_T_11; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_13 = _mshrs_io_req_0_valid_T_9 & _mshrs_io_req_0_valid_T_12; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_14 = io_lsu_exception_0 & s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25, :798:48]
wire _mshrs_io_req_0_valid_T_15 = ~_mshrs_io_req_0_valid_T_14; // @[dcache.scala:798:{29,48}]
wire _mshrs_io_req_0_valid_T_16 = _mshrs_io_req_0_valid_T_13 & _mshrs_io_req_0_valid_T_15; // @[dcache.scala:796:51, :797:77, :798:29]
wire _mshrs_io_req_0_valid_T_17 = s2_req_0_uop_mem_cmd == 5'h2; // @[Consts.scala:88:35]
wire _mshrs_io_req_0_valid_T_19 = _mshrs_io_req_0_valid_T_17 | _mshrs_io_req_0_valid_T_18; // @[Consts.scala:88:{35,45,52}]
wire _mshrs_io_req_0_valid_T_24 = _mshrs_io_req_0_valid_T_20 | _mshrs_io_req_0_valid_T_21; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_25 = _mshrs_io_req_0_valid_T_24 | _mshrs_io_req_0_valid_T_22; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_26 = _mshrs_io_req_0_valid_T_25 | _mshrs_io_req_0_valid_T_23; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_31 = _mshrs_io_req_0_valid_T_27 | _mshrs_io_req_0_valid_T_28; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_32 = _mshrs_io_req_0_valid_T_31 | _mshrs_io_req_0_valid_T_29; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_33 = _mshrs_io_req_0_valid_T_32 | _mshrs_io_req_0_valid_T_30; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_39 = _mshrs_io_req_0_valid_T_34 | _mshrs_io_req_0_valid_T_35; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_40 = _mshrs_io_req_0_valid_T_39 | _mshrs_io_req_0_valid_T_36; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_41 = _mshrs_io_req_0_valid_T_40 | _mshrs_io_req_0_valid_T_37; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_42 = _mshrs_io_req_0_valid_T_41 | _mshrs_io_req_0_valid_T_38; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_43 = _mshrs_io_req_0_valid_T_33 | _mshrs_io_req_0_valid_T_42; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_44 = _mshrs_io_req_0_valid_T_26 | _mshrs_io_req_0_valid_T_43; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_45 = _mshrs_io_req_0_valid_T_19 | _mshrs_io_req_0_valid_T_44; // @[Consts.scala:88:45, :89:68]
wire _mshrs_io_req_0_valid_T_48 = _mshrs_io_req_0_valid_T_46 | _mshrs_io_req_0_valid_T_47; // @[Consts.scala:90:{32,42,49}]
wire _mshrs_io_req_0_valid_T_50 = _mshrs_io_req_0_valid_T_48 | _mshrs_io_req_0_valid_T_49; // @[Consts.scala:90:{42,59,66}]
wire _mshrs_io_req_0_valid_T_55 = _mshrs_io_req_0_valid_T_51 | _mshrs_io_req_0_valid_T_52; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_56 = _mshrs_io_req_0_valid_T_55 | _mshrs_io_req_0_valid_T_53; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_57 = _mshrs_io_req_0_valid_T_56 | _mshrs_io_req_0_valid_T_54; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_63 = _mshrs_io_req_0_valid_T_58 | _mshrs_io_req_0_valid_T_59; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_64 = _mshrs_io_req_0_valid_T_63 | _mshrs_io_req_0_valid_T_60; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_65 = _mshrs_io_req_0_valid_T_64 | _mshrs_io_req_0_valid_T_61; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_66 = _mshrs_io_req_0_valid_T_65 | _mshrs_io_req_0_valid_T_62; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_67 = _mshrs_io_req_0_valid_T_57 | _mshrs_io_req_0_valid_T_66; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_68 = _mshrs_io_req_0_valid_T_50 | _mshrs_io_req_0_valid_T_67; // @[Consts.scala:87:44, :90:{59,76}]
wire _mshrs_io_req_0_valid_T_69 = _mshrs_io_req_0_valid_T_45 | _mshrs_io_req_0_valid_T_68; // @[Consts.scala:90:76]
assign _mshrs_io_req_0_valid_T_70 = _mshrs_io_req_0_valid_T_16 & _mshrs_io_req_0_valid_T_69; // @[dcache.scala:797:77, :798:77, :800:65]
wire [1:0] _mshrs_io_req_0_bits_old_meta_T_coh_state = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_coh_state : s2_repl_meta_0_coh_state; // @[HellaCache.scala:305:20]
wire [19:0] _mshrs_io_req_0_bits_old_meta_T_tag = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_tag : s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
wire [3:0] _mshrs_io_req_0_bits_way_en_T = s2_tag_match_0 ? s2_tag_match_way_0 : s2_replaced_way_en; // @[OneHot.scala:58:35]
wire _mshrs_io_req_is_probe_0_T = s2_type == 3'h1; // @[dcache.scala:671:25, :812:49]
wire _mshrs_io_req_is_probe_0_T_1 = _mshrs_io_req_is_probe_0_T & s2_valid_0; // @[dcache.scala:454:49, :812:{49,61}]
wire _mshrs_io_meta_resp_valid_T = ~s2_nack_hit_0; // @[dcache.scala:760:31, :793:29, :815:36]
wire _mshrs_io_meta_resp_valid_T_1 = _mshrs_io_meta_resp_valid_T | _prober_io_mshr_wb_rdy; // @[dcache.scala:459:22, :815:{36,52}]
reg [1:0] mshrs_io_meta_resp_bits_REG_0_coh_state; // @[dcache.scala:816:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_0_tag; // @[dcache.scala:816:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_1_coh_state; // @[dcache.scala:816:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_1_tag; // @[dcache.scala:816:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_2_coh_state; // @[dcache.scala:816:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_2_tag; // @[dcache.scala:816:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_3_coh_state; // @[dcache.scala:816:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_3_tag; // @[dcache.scala:816:70]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_4 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_5 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_6 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_7 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_8 = _mshrs_io_meta_resp_bits_T_4 | _mshrs_io_meta_resp_bits_T_5; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_9 = _mshrs_io_meta_resp_bits_T_8 | _mshrs_io_meta_resp_bits_T_6; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_10 = _mshrs_io_meta_resp_bits_T_9 | _mshrs_io_meta_resp_bits_T_7; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_1 = _mshrs_io_meta_resp_bits_T_10; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_WIRE_tag = _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_coh_state = _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_11 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_12 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_13 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_14 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_15 = _mshrs_io_meta_resp_bits_T_11 | _mshrs_io_meta_resp_bits_T_12; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_16 = _mshrs_io_meta_resp_bits_T_15 | _mshrs_io_meta_resp_bits_T_13; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_17 = _mshrs_io_meta_resp_bits_T_16 | _mshrs_io_meta_resp_bits_T_14; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_3 = _mshrs_io_meta_resp_bits_T_17; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_2_state = _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire _prober_io_req_valid_T = ~lrsc_valid; // @[dcache.scala:699:31, :821:46]
wire _prober_io_req_valid_T_1 = nodeOut_b_valid & _prober_io_req_valid_T; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T = ~lrsc_valid; // @[dcache.scala:699:31, :821:46, :822:51]
assign _nodeOut_b_ready_T_1 = _prober_io_req_ready & _nodeOut_b_ready_T; // @[dcache.scala:459:22, :822:{48,51}]
assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[MixedNode.scala:542:17]
wire _prober_io_wb_rdy_T = _prober_io_meta_write_bits_idx != _wb_io_idx_bits; // @[dcache.scala:458:18, :459:22, :828:59]
wire _prober_io_wb_rdy_T_1 = ~_wb_io_idx_valid; // @[dcache.scala:458:18, :828:82]
wire _prober_io_wb_rdy_T_2 = _prober_io_wb_rdy_T | _prober_io_wb_rdy_T_1; // @[dcache.scala:828:{59,79,82}]
wire _wb_io_mem_grant_T_1 = nodeOut_d_bits_source == 2'h2; // @[MixedNode.scala:542:17]
assign nodeOut_d_ready = _wb_io_mem_grant_T_1 | _mshrs_io_mem_grant_ready; // @[MixedNode.scala:542:17]
wire _wb_io_mem_grant_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _wb_io_mem_grant_T_2 = _wb_io_mem_grant_T & _wb_io_mem_grant_T_1; // @[Decoupled.scala:51:35]
wire opdata = _wb_io_release_bits_opcode[0]; // @[Edges.scala:102:36]
wire [26:0] _decode_T_3 = 27'hFFF << _prober_io_rep_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_4 = _decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] decode_1 = _decode_T_5[11:3]; // @[package.scala:243:46]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_c_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {_prober_io_rep_valid, _wb_io_release_valid}; // @[Arbiter.scala:68:51]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & _wb_io_release_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & _prober_io_rep_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_c_valid_T = _wb_io_release_valid | _prober_io_rep_valid; // @[Arbiter.scala:79:31, :96:46]
wire [8:0] maskedBeats_0 = winner_0 & opdata ? 9'h7 : 9'h0; // @[Edges.scala:102:36, :221:14]
wire [8:0] initBeats = maskedBeats_0; // @[Arbiter.scala:82:69, :84:44]
wire _GEN_19 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35]
wire _beatsLeft_T; // @[Decoupled.scala:51:35]
assign _beatsLeft_T = _GEN_19; // @[Decoupled.scala:51:35]
wire _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign _io_lsu_perf_release_T = _GEN_19; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire _wb_io_release_ready_T = nodeOut_c_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31]
wire _prober_io_rep_ready_T = nodeOut_c_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31]
wire _nodeOut_c_valid_T_1 = state_0 & _wb_io_release_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_2 = state_1 & _prober_io_rep_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_3 = _nodeOut_c_valid_T_1 | _nodeOut_c_valid_T_2; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_WIRE = _nodeOut_c_valid_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_valid_T_4 = idle ? _nodeOut_c_valid_T : _nodeOut_c_valid_WIRE; // @[Mux.scala:30:73]
assign nodeOut_c_valid = _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
assign nodeOut_c_bits_opcode = _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
assign nodeOut_c_bits_param = _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
assign nodeOut_c_bits_size = _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
assign nodeOut_c_bits_source = _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
assign nodeOut_c_bits_address = _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
assign nodeOut_c_bits_data = _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_T_3 = muxState_0 ? _wb_io_release_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_T_5 = _nodeOut_c_bits_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_2 = _nodeOut_c_bits_T_5; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_data = _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_6 = muxState_0 ? _wb_io_release_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_7 = muxState_1 ? _prober_io_rep_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_8 = _nodeOut_c_bits_T_6 | _nodeOut_c_bits_T_7; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_5 = _nodeOut_c_bits_T_8; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_address = _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_T_9 = muxState_0 ? _wb_io_release_bits_source : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_T_10 = muxState_1 ? _prober_io_rep_bits_source : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_T_11 = _nodeOut_c_bits_T_9 | _nodeOut_c_bits_T_10; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_6 = _nodeOut_c_bits_T_11; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_source = _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_12 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_13 = muxState_1 ? _prober_io_rep_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_14 = _nodeOut_c_bits_T_12 | _nodeOut_c_bits_T_13; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_7 = _nodeOut_c_bits_T_14; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_size = _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_15 = muxState_0 ? _wb_io_release_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_16 = muxState_1 ? _prober_io_rep_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_17 = _nodeOut_c_bits_T_15 | _nodeOut_c_bits_T_16; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_8 = _nodeOut_c_bits_T_17; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_param = _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_18 = muxState_0 ? _wb_io_release_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_19 = {muxState_1, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_20 = _nodeOut_c_bits_T_18 | _nodeOut_c_bits_T_19; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_9 = _nodeOut_c_bits_T_20; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_opcode = _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
wire [26:0] _io_lsu_perf_release_beats1_decode_T = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_1 = _io_lsu_perf_release_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_2 = ~_io_lsu_perf_release_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] io_lsu_perf_release_beats1_decode = _io_lsu_perf_release_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire io_lsu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36]
wire [8:0] io_lsu_perf_release_beats1 = io_lsu_perf_release_beats1_opdata ? io_lsu_perf_release_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] io_lsu_perf_release_counter; // @[Edges.scala:229:27]
wire [9:0] _io_lsu_perf_release_counter1_T = {1'h0, io_lsu_perf_release_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] io_lsu_perf_release_counter1 = _io_lsu_perf_release_counter1_T[8:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_release_first = io_lsu_perf_release_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_release_last_T = io_lsu_perf_release_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_release_last_T_1 = io_lsu_perf_release_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_release_last = _io_lsu_perf_release_last_T | _io_lsu_perf_release_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_release_done = io_lsu_perf_release_last & _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_release_0 = io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [8:0] _io_lsu_perf_release_count_T = ~io_lsu_perf_release_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] io_lsu_perf_release_count = io_lsu_perf_release_beats1 & _io_lsu_perf_release_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _io_lsu_perf_release_counter_T = io_lsu_perf_release_first ? io_lsu_perf_release_beats1 : io_lsu_perf_release_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _io_lsu_perf_acquire_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] _io_lsu_perf_acquire_beats1_decode_T = 27'hFFF << nodeOut_a_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_1 = _io_lsu_perf_acquire_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_2 = ~_io_lsu_perf_acquire_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] io_lsu_perf_acquire_beats1_decode = _io_lsu_perf_acquire_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _io_lsu_perf_acquire_beats1_opdata_T = nodeOut_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire io_lsu_perf_acquire_beats1_opdata = ~_io_lsu_perf_acquire_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] io_lsu_perf_acquire_beats1 = io_lsu_perf_acquire_beats1_opdata ? io_lsu_perf_acquire_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] io_lsu_perf_acquire_counter; // @[Edges.scala:229:27]
wire [9:0] _io_lsu_perf_acquire_counter1_T = {1'h0, io_lsu_perf_acquire_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] io_lsu_perf_acquire_counter1 = _io_lsu_perf_acquire_counter1_T[8:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_acquire_first = io_lsu_perf_acquire_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_acquire_last_T = io_lsu_perf_acquire_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_acquire_last_T_1 = io_lsu_perf_acquire_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_acquire_last = _io_lsu_perf_acquire_last_T | _io_lsu_perf_acquire_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_acquire_done = io_lsu_perf_acquire_last & _io_lsu_perf_acquire_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_acquire_0 = io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire [8:0] _io_lsu_perf_acquire_count_T = ~io_lsu_perf_acquire_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] io_lsu_perf_acquire_count = io_lsu_perf_acquire_beats1 & _io_lsu_perf_acquire_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _io_lsu_perf_acquire_counter_T = io_lsu_perf_acquire_first ? io_lsu_perf_acquire_beats1 : io_lsu_perf_acquire_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [63:0] s2_data_word_prebypass_0 = _s2_data_word_prebypass_T_1; // @[dcache.scala:454:49, :868:63]
wire [63:0] _s2_data_word_0_T_2; // @[dcache.scala:919:27]
wire [63:0] s2_data_word_0; // @[dcache.scala:869:26]
wire [63:0] size_dat_padded = s2_data_word_0; // @[AMOALU.scala:13:27]
assign _io_lsu_resp_0_valid_T = s2_valid_0 & s2_send_resp_0; // @[dcache.scala:454:49, :877:41]
assign io_lsu_resp_0_valid_0 = _io_lsu_resp_0_valid_T; // @[dcache.scala:438:7, :877:41]
wire _io_lsu_resp_0_bits_data_shifted_T = s2_req_0_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_lsu_resp_0_bits_data_shifted_T_1 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_lsu_resp_0_bits_data_T_5 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_lsu_resp_0_bits_data_shifted_T_2 = s2_data_word_0[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_lsu_resp_0_bits_data_shifted = _io_lsu_resp_0_bits_data_shifted_T ? _io_lsu_resp_0_bits_data_shifted_T_1 : _io_lsu_resp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_lsu_resp_0_bits_data_zeroed = io_lsu_resp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_lsu_resp_0_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_lsu_resp_0_bits_data_T_1 = _io_lsu_resp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_lsu_resp_0_bits_data_T_2 = io_lsu_resp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_lsu_resp_0_bits_data_T_3 = s2_req_0_uop_mem_signed & _io_lsu_resp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_lsu_resp_0_bits_data_T_4 = {32{_io_lsu_resp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_lsu_resp_0_bits_data_T_6 = _io_lsu_resp_0_bits_data_T_1 ? _io_lsu_resp_0_bits_data_T_4 : _io_lsu_resp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_lsu_resp_0_bits_data_T_7 = {_io_lsu_resp_0_bits_data_T_6, io_lsu_resp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_lsu_resp_0_bits_data_shifted_T_3 = s2_req_0_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_lsu_resp_0_bits_data_shifted_T_4 = _io_lsu_resp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_lsu_resp_0_bits_data_shifted_T_5 = _io_lsu_resp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_lsu_resp_0_bits_data_shifted_1 = _io_lsu_resp_0_bits_data_shifted_T_3 ? _io_lsu_resp_0_bits_data_shifted_T_4 : _io_lsu_resp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_lsu_resp_0_bits_data_zeroed_1 = io_lsu_resp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_lsu_resp_0_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_lsu_resp_0_bits_data_T_9 = _io_lsu_resp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_lsu_resp_0_bits_data_T_10 = io_lsu_resp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_lsu_resp_0_bits_data_T_11 = s2_req_0_uop_mem_signed & _io_lsu_resp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_lsu_resp_0_bits_data_T_12 = {48{_io_lsu_resp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_lsu_resp_0_bits_data_T_13 = _io_lsu_resp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_lsu_resp_0_bits_data_T_14 = _io_lsu_resp_0_bits_data_T_9 ? _io_lsu_resp_0_bits_data_T_12 : _io_lsu_resp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_lsu_resp_0_bits_data_T_15 = {_io_lsu_resp_0_bits_data_T_14, io_lsu_resp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_lsu_resp_0_bits_data_shifted_T_6 = s2_req_0_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_lsu_resp_0_bits_data_shifted_T_7 = _io_lsu_resp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_lsu_resp_0_bits_data_shifted_T_8 = _io_lsu_resp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_lsu_resp_0_bits_data_shifted_2 = _io_lsu_resp_0_bits_data_shifted_T_6 ? _io_lsu_resp_0_bits_data_shifted_T_7 : _io_lsu_resp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_lsu_resp_0_bits_data_zeroed_2 = io_lsu_resp_0_bits_data_doZero_2 ? 8'h0 : io_lsu_resp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :43:31, :44:23]
wire _io_lsu_resp_0_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_lsu_resp_0_bits_data_T_17 = _io_lsu_resp_0_bits_data_T_16 | io_lsu_resp_0_bits_data_doZero_2; // @[AMOALU.scala:43:31, :45:{26,34}]
wire _io_lsu_resp_0_bits_data_T_18 = io_lsu_resp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_lsu_resp_0_bits_data_T_19 = s2_req_0_uop_mem_signed & _io_lsu_resp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_lsu_resp_0_bits_data_T_20 = {56{_io_lsu_resp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_lsu_resp_0_bits_data_T_21 = _io_lsu_resp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_lsu_resp_0_bits_data_T_22 = _io_lsu_resp_0_bits_data_T_17 ? _io_lsu_resp_0_bits_data_T_20 : _io_lsu_resp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_lsu_resp_0_bits_data_T_23 = {_io_lsu_resp_0_bits_data_T_22, io_lsu_resp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign _io_lsu_resp_0_bits_data_T_24 = {_io_lsu_resp_0_bits_data_T_23[63:1], _io_lsu_resp_0_bits_data_T_23[0] | s2_sc_fail}; // @[AMOALU.scala:45:16]
assign io_lsu_resp_0_bits_data_0 = _io_lsu_resp_0_bits_data_T_24; // @[dcache.scala:438:7, :879:49]
assign _io_lsu_nack_0_valid_T = s2_valid_0 & s2_send_nack_0; // @[dcache.scala:454:49, :884:41]
assign io_lsu_nack_0_valid_0 = _io_lsu_nack_0_valid_T; // @[dcache.scala:438:7, :884:41] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_75 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_163
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_164
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_165 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_166 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_75( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [8:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_40 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_80
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_40
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = and(io.in.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
invalidate route_buffer.io.enq.bits.flow.egress_node_id
invalidate route_buffer.io.enq.bits.flow.egress_node
invalidate route_buffer.io.enq.bits.flow.ingress_node_id
invalidate route_buffer.io.enq.bits.flow.ingress_node
invalidate route_buffer.io.enq.bits.flow.vnet_id
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h1))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0]
node _T_6 = and(io.in.ready, io.in.valid)
node _T_7 = and(_T_6, io.in.bits.head)
node _T_8 = and(_T_7, at_dest)
when _T_8 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<2>(0h2), io.in.bits.egress_id)
when _T_9 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_10 = eq(UInt<2>(0h3), io.in.bits.egress_id)
when _T_10 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_11 = eq(UInt<3>(0h4), io.in.bits.egress_id)
when _T_11 :
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1)
node _T_12 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_13 = and(route_q.io.enq.valid, _T_12)
node _T_14 = eq(_T_13, UInt<1>(0h0))
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_14, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_81
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_40
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0]
node _T_18 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_19 = and(vcalloc_q.io.enq.valid, _T_18)
node _T_20 = eq(_T_19, UInt<1>(0h0))
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_20, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _c_T = cat(c_hi, c_lo)
node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0])
node _c_T_1 = cat(c_hi_1, c_lo_1)
node c_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2])
node _c_T_2 = cat(c_hi_2, c_lo_2)
node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _c_T_3 = cat(c_hi_3, c_lo_3)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10)
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1
connect io.in.ready, UInt<1>(0h0)
connect io.router_req.valid, UInt<1>(0h0)
invalidate io.router_req.bits.flow.egress_node_id
invalidate io.router_req.bits.flow.egress_node
invalidate io.router_req.bits.flow.ingress_node_id
invalidate io.router_req.bits.flow.ingress_node
invalidate io.router_req.bits.flow.vnet_id
invalidate io.router_req.bits.src_virt_id
connect io.vcalloc_req.valid, UInt<1>(0h0)
invalidate io.vcalloc_req.bits.vc_sel.`0`[0]
invalidate io.vcalloc_req.bits.vc_sel.`0`[1]
invalidate io.vcalloc_req.bits.vc_sel.`0`[2]
invalidate io.vcalloc_req.bits.vc_sel.`0`[3]
invalidate io.vcalloc_req.bits.vc_sel.`0`[4]
invalidate io.vcalloc_req.bits.vc_sel.`1`[0]
invalidate io.vcalloc_req.bits.vc_sel.`2`[0]
invalidate io.vcalloc_req.bits.vc_sel.`3`[0]
invalidate io.vcalloc_req.bits.in_vc
invalidate io.vcalloc_req.bits.flow.egress_node_id
invalidate io.vcalloc_req.bits.flow.egress_node
invalidate io.vcalloc_req.bits.flow.ingress_node_id
invalidate io.vcalloc_req.bits.flow.ingress_node
invalidate io.vcalloc_req.bits.flow.vnet_id
connect io.salloc_req[0].valid, UInt<1>(0h0)
invalidate io.salloc_req[0].bits.tail
invalidate io.salloc_req[0].bits.vc_sel.`0`[0]
invalidate io.salloc_req[0].bits.vc_sel.`0`[1]
invalidate io.salloc_req[0].bits.vc_sel.`0`[2]
invalidate io.salloc_req[0].bits.vc_sel.`0`[3]
invalidate io.salloc_req[0].bits.vc_sel.`0`[4]
invalidate io.salloc_req[0].bits.vc_sel.`1`[0]
invalidate io.salloc_req[0].bits.vc_sel.`2`[0]
invalidate io.salloc_req[0].bits.vc_sel.`3`[0]
connect io.out[0].valid, UInt<1>(0h0)
invalidate io.out[0].bits.out_virt_channel
invalidate io.out[0].bits.flit.virt_channel_id
invalidate io.out[0].bits.flit.flow.egress_node_id
invalidate io.out[0].bits.flit.flow.egress_node
invalidate io.out[0].bits.flit.flow.ingress_node_id
invalidate io.out[0].bits.flit.flow.ingress_node
invalidate io.out[0].bits.flit.flow.vnet_id
invalidate io.out[0].bits.flit.payload
invalidate io.out[0].bits.flit.tail
invalidate io.out[0].bits.flit.head | module IngressUnit_40( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset // @[IngressUnit.scala:11:7]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_37 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_98 = shr(io.in.a.bits.source, 4)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_176 = shr(io.in.a.bits.source, 4)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_276 = shr(io.in.a.bits.source, 4)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_325 = shr(io.in.a.bits.source, 4)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_369 = shr(io.in.a.bits.source, 4)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_413 = shr(io.in.a.bits.source, 4)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_74
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_75
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_37( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ALU :
input clock : Clock
input reset : Reset
output io : { flip dw : UInt<1>, flip fn : UInt<5>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>}
node _in2_inv_T = bits(io.fn, 3, 3)
node _in2_inv_T_1 = not(io.in2)
node in2_inv = mux(_in2_inv_T, _in2_inv_T_1, io.in2)
node in1_xor_in2 = xor(io.in1, in2_inv)
node in1_and_in2 = and(io.in1, in2_inv)
node _io_adder_out_T = add(io.in1, in2_inv)
node _io_adder_out_T_1 = tail(_io_adder_out_T, 1)
node _io_adder_out_T_2 = bits(io.fn, 3, 3)
node _io_adder_out_T_3 = add(_io_adder_out_T_1, _io_adder_out_T_2)
node _io_adder_out_T_4 = tail(_io_adder_out_T_3, 1)
connect io.adder_out, _io_adder_out_T_4
node _slt_T = bits(io.in1, 63, 63)
node _slt_T_1 = bits(io.in2, 63, 63)
node _slt_T_2 = eq(_slt_T, _slt_T_1)
node _slt_T_3 = bits(io.adder_out, 63, 63)
node _slt_T_4 = bits(io.fn, 1, 1)
node _slt_T_5 = bits(io.in2, 63, 63)
node _slt_T_6 = bits(io.in1, 63, 63)
node _slt_T_7 = mux(_slt_T_4, _slt_T_5, _slt_T_6)
node slt = mux(_slt_T_2, _slt_T_3, _slt_T_7)
node _io_cmp_out_T = bits(io.fn, 0, 0)
node _io_cmp_out_T_1 = bits(io.fn, 3, 3)
node _io_cmp_out_T_2 = eq(_io_cmp_out_T_1, UInt<1>(0h0))
node _io_cmp_out_T_3 = eq(in1_xor_in2, UInt<1>(0h0))
node _io_cmp_out_T_4 = mux(_io_cmp_out_T_2, _io_cmp_out_T_3, slt)
node _io_cmp_out_T_5 = xor(_io_cmp_out_T, _io_cmp_out_T_4)
connect io.cmp_out, _io_cmp_out_T_5
node _shin_hi_32_T = bits(io.fn, 3, 3)
node _shin_hi_32_T_1 = bits(io.in1, 31, 31)
node _shin_hi_32_T_2 = and(_shin_hi_32_T, _shin_hi_32_T_1)
node shin_hi_32 = mux(_shin_hi_32_T_2, UInt<32>(0hffffffff), UInt<32>(0h0))
node _shin_hi_T = eq(io.dw, UInt<1>(0h1))
node _shin_hi_T_1 = bits(io.in1, 63, 32)
node shin_hi = mux(_shin_hi_T, _shin_hi_T_1, shin_hi_32)
node _shamt_T = bits(io.in2, 5, 5)
node _shamt_T_1 = eq(io.dw, UInt<1>(0h1))
node _shamt_T_2 = and(_shamt_T, _shamt_T_1)
node _shamt_T_3 = bits(io.in2, 4, 0)
node shamt = cat(_shamt_T_2, _shamt_T_3)
node _T = bits(io.in1, 31, 0)
node shin_r = cat(shin_hi, _T)
node _shin_T = eq(io.fn, UInt<3>(0h5))
node _shin_T_1 = eq(io.fn, UInt<4>(0hb))
node _shin_T_2 = eq(io.fn, UInt<5>(0h12))
node _shin_T_3 = eq(io.fn, UInt<5>(0h13))
node _shin_T_4 = or(_shin_T, _shin_T_1)
node _shin_T_5 = or(_shin_T_4, _shin_T_2)
node _shin_T_6 = or(_shin_T_5, _shin_T_3)
node _shin_T_7 = eq(_shin_T_6, UInt<1>(0h0))
node _shin_T_8 = shl(UInt<32>(0hffffffff), 32)
node _shin_T_9 = xor(UInt<64>(0hffffffffffffffff), _shin_T_8)
node _shin_T_10 = shr(shin_r, 32)
node _shin_T_11 = and(_shin_T_10, _shin_T_9)
node _shin_T_12 = bits(shin_r, 31, 0)
node _shin_T_13 = shl(_shin_T_12, 32)
node _shin_T_14 = not(_shin_T_9)
node _shin_T_15 = and(_shin_T_13, _shin_T_14)
node _shin_T_16 = or(_shin_T_11, _shin_T_15)
node _shin_T_17 = bits(_shin_T_9, 47, 0)
node _shin_T_18 = shl(_shin_T_17, 16)
node _shin_T_19 = xor(_shin_T_9, _shin_T_18)
node _shin_T_20 = shr(_shin_T_16, 16)
node _shin_T_21 = and(_shin_T_20, _shin_T_19)
node _shin_T_22 = bits(_shin_T_16, 47, 0)
node _shin_T_23 = shl(_shin_T_22, 16)
node _shin_T_24 = not(_shin_T_19)
node _shin_T_25 = and(_shin_T_23, _shin_T_24)
node _shin_T_26 = or(_shin_T_21, _shin_T_25)
node _shin_T_27 = bits(_shin_T_19, 55, 0)
node _shin_T_28 = shl(_shin_T_27, 8)
node _shin_T_29 = xor(_shin_T_19, _shin_T_28)
node _shin_T_30 = shr(_shin_T_26, 8)
node _shin_T_31 = and(_shin_T_30, _shin_T_29)
node _shin_T_32 = bits(_shin_T_26, 55, 0)
node _shin_T_33 = shl(_shin_T_32, 8)
node _shin_T_34 = not(_shin_T_29)
node _shin_T_35 = and(_shin_T_33, _shin_T_34)
node _shin_T_36 = or(_shin_T_31, _shin_T_35)
node _shin_T_37 = bits(_shin_T_29, 59, 0)
node _shin_T_38 = shl(_shin_T_37, 4)
node _shin_T_39 = xor(_shin_T_29, _shin_T_38)
node _shin_T_40 = shr(_shin_T_36, 4)
node _shin_T_41 = and(_shin_T_40, _shin_T_39)
node _shin_T_42 = bits(_shin_T_36, 59, 0)
node _shin_T_43 = shl(_shin_T_42, 4)
node _shin_T_44 = not(_shin_T_39)
node _shin_T_45 = and(_shin_T_43, _shin_T_44)
node _shin_T_46 = or(_shin_T_41, _shin_T_45)
node _shin_T_47 = bits(_shin_T_39, 61, 0)
node _shin_T_48 = shl(_shin_T_47, 2)
node _shin_T_49 = xor(_shin_T_39, _shin_T_48)
node _shin_T_50 = shr(_shin_T_46, 2)
node _shin_T_51 = and(_shin_T_50, _shin_T_49)
node _shin_T_52 = bits(_shin_T_46, 61, 0)
node _shin_T_53 = shl(_shin_T_52, 2)
node _shin_T_54 = not(_shin_T_49)
node _shin_T_55 = and(_shin_T_53, _shin_T_54)
node _shin_T_56 = or(_shin_T_51, _shin_T_55)
node _shin_T_57 = bits(_shin_T_49, 62, 0)
node _shin_T_58 = shl(_shin_T_57, 1)
node _shin_T_59 = xor(_shin_T_49, _shin_T_58)
node _shin_T_60 = shr(_shin_T_56, 1)
node _shin_T_61 = and(_shin_T_60, _shin_T_59)
node _shin_T_62 = bits(_shin_T_56, 62, 0)
node _shin_T_63 = shl(_shin_T_62, 1)
node _shin_T_64 = not(_shin_T_59)
node _shin_T_65 = and(_shin_T_63, _shin_T_64)
node _shin_T_66 = or(_shin_T_61, _shin_T_65)
node shin = mux(_shin_T_7, _shin_T_66, shin_r)
node _shout_r_T = bits(io.fn, 3, 3)
node _shout_r_T_1 = bits(shin, 63, 63)
node _shout_r_T_2 = and(_shout_r_T, _shout_r_T_1)
node _shout_r_T_3 = cat(_shout_r_T_2, shin)
node _shout_r_T_4 = asSInt(_shout_r_T_3)
node _shout_r_T_5 = dshr(_shout_r_T_4, shamt)
node shout_r = bits(_shout_r_T_5, 63, 0)
node _shout_l_T = shl(UInt<32>(0hffffffff), 32)
node _shout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _shout_l_T)
node _shout_l_T_2 = shr(shout_r, 32)
node _shout_l_T_3 = and(_shout_l_T_2, _shout_l_T_1)
node _shout_l_T_4 = bits(shout_r, 31, 0)
node _shout_l_T_5 = shl(_shout_l_T_4, 32)
node _shout_l_T_6 = not(_shout_l_T_1)
node _shout_l_T_7 = and(_shout_l_T_5, _shout_l_T_6)
node _shout_l_T_8 = or(_shout_l_T_3, _shout_l_T_7)
node _shout_l_T_9 = bits(_shout_l_T_1, 47, 0)
node _shout_l_T_10 = shl(_shout_l_T_9, 16)
node _shout_l_T_11 = xor(_shout_l_T_1, _shout_l_T_10)
node _shout_l_T_12 = shr(_shout_l_T_8, 16)
node _shout_l_T_13 = and(_shout_l_T_12, _shout_l_T_11)
node _shout_l_T_14 = bits(_shout_l_T_8, 47, 0)
node _shout_l_T_15 = shl(_shout_l_T_14, 16)
node _shout_l_T_16 = not(_shout_l_T_11)
node _shout_l_T_17 = and(_shout_l_T_15, _shout_l_T_16)
node _shout_l_T_18 = or(_shout_l_T_13, _shout_l_T_17)
node _shout_l_T_19 = bits(_shout_l_T_11, 55, 0)
node _shout_l_T_20 = shl(_shout_l_T_19, 8)
node _shout_l_T_21 = xor(_shout_l_T_11, _shout_l_T_20)
node _shout_l_T_22 = shr(_shout_l_T_18, 8)
node _shout_l_T_23 = and(_shout_l_T_22, _shout_l_T_21)
node _shout_l_T_24 = bits(_shout_l_T_18, 55, 0)
node _shout_l_T_25 = shl(_shout_l_T_24, 8)
node _shout_l_T_26 = not(_shout_l_T_21)
node _shout_l_T_27 = and(_shout_l_T_25, _shout_l_T_26)
node _shout_l_T_28 = or(_shout_l_T_23, _shout_l_T_27)
node _shout_l_T_29 = bits(_shout_l_T_21, 59, 0)
node _shout_l_T_30 = shl(_shout_l_T_29, 4)
node _shout_l_T_31 = xor(_shout_l_T_21, _shout_l_T_30)
node _shout_l_T_32 = shr(_shout_l_T_28, 4)
node _shout_l_T_33 = and(_shout_l_T_32, _shout_l_T_31)
node _shout_l_T_34 = bits(_shout_l_T_28, 59, 0)
node _shout_l_T_35 = shl(_shout_l_T_34, 4)
node _shout_l_T_36 = not(_shout_l_T_31)
node _shout_l_T_37 = and(_shout_l_T_35, _shout_l_T_36)
node _shout_l_T_38 = or(_shout_l_T_33, _shout_l_T_37)
node _shout_l_T_39 = bits(_shout_l_T_31, 61, 0)
node _shout_l_T_40 = shl(_shout_l_T_39, 2)
node _shout_l_T_41 = xor(_shout_l_T_31, _shout_l_T_40)
node _shout_l_T_42 = shr(_shout_l_T_38, 2)
node _shout_l_T_43 = and(_shout_l_T_42, _shout_l_T_41)
node _shout_l_T_44 = bits(_shout_l_T_38, 61, 0)
node _shout_l_T_45 = shl(_shout_l_T_44, 2)
node _shout_l_T_46 = not(_shout_l_T_41)
node _shout_l_T_47 = and(_shout_l_T_45, _shout_l_T_46)
node _shout_l_T_48 = or(_shout_l_T_43, _shout_l_T_47)
node _shout_l_T_49 = bits(_shout_l_T_41, 62, 0)
node _shout_l_T_50 = shl(_shout_l_T_49, 1)
node _shout_l_T_51 = xor(_shout_l_T_41, _shout_l_T_50)
node _shout_l_T_52 = shr(_shout_l_T_48, 1)
node _shout_l_T_53 = and(_shout_l_T_52, _shout_l_T_51)
node _shout_l_T_54 = bits(_shout_l_T_48, 62, 0)
node _shout_l_T_55 = shl(_shout_l_T_54, 1)
node _shout_l_T_56 = not(_shout_l_T_51)
node _shout_l_T_57 = and(_shout_l_T_55, _shout_l_T_56)
node shout_l = or(_shout_l_T_53, _shout_l_T_57)
node _shout_T = eq(io.fn, UInt<3>(0h5))
node _shout_T_1 = eq(io.fn, UInt<4>(0hb))
node _shout_T_2 = or(_shout_T, _shout_T_1)
node _shout_T_3 = eq(io.fn, UInt<5>(0h13))
node _shout_T_4 = or(_shout_T_2, _shout_T_3)
node _shout_T_5 = mux(_shout_T_4, shout_r, UInt<1>(0h0))
node _shout_T_6 = eq(io.fn, UInt<1>(0h1))
node _shout_T_7 = mux(_shout_T_6, shout_l, UInt<1>(0h0))
node shout = or(_shout_T_5, _shout_T_7)
node in2_not_zero = orr(io.in2)
node _logic_T = eq(io.fn, UInt<3>(0h4))
node _logic_T_1 = eq(io.fn, UInt<3>(0h6))
node _logic_T_2 = or(_logic_T, _logic_T_1)
node _logic_T_3 = eq(io.fn, UInt<5>(0h19))
node _logic_T_4 = or(_logic_T_2, _logic_T_3)
node _logic_T_5 = eq(io.fn, UInt<5>(0h1a))
node _logic_T_6 = or(_logic_T_4, _logic_T_5)
node _logic_T_7 = mux(_logic_T_6, in1_xor_in2, UInt<1>(0h0))
node _logic_T_8 = eq(io.fn, UInt<3>(0h6))
node _logic_T_9 = eq(io.fn, UInt<3>(0h7))
node _logic_T_10 = or(_logic_T_8, _logic_T_9)
node _logic_T_11 = eq(io.fn, UInt<5>(0h19))
node _logic_T_12 = or(_logic_T_10, _logic_T_11)
node _logic_T_13 = eq(io.fn, UInt<5>(0h18))
node _logic_T_14 = or(_logic_T_12, _logic_T_13)
node _logic_T_15 = mux(_logic_T_14, in1_and_in2, UInt<1>(0h0))
node logic = or(_logic_T_7, _logic_T_15)
node _bext_mask_T = eq(io.fn, UInt<5>(0h13))
node _bext_mask_T_1 = and(UInt<1>(0h1), _bext_mask_T)
node _bext_mask_T_2 = not(UInt<64>(0h0))
node bext_mask = mux(_bext_mask_T_1, UInt<1>(0h1), _bext_mask_T_2)
node _shift_logic_T = geq(io.fn, UInt<4>(0hc))
node _shift_logic_T_1 = leq(io.fn, UInt<4>(0hf))
node _shift_logic_T_2 = and(_shift_logic_T, _shift_logic_T_1)
node _shift_logic_T_3 = and(_shift_logic_T_2, slt)
node _shift_logic_T_4 = or(_shift_logic_T_3, logic)
node _shift_logic_T_5 = and(shout, bext_mask)
node shift_logic = or(_shift_logic_T_4, _shift_logic_T_5)
node _tz_in_T = eq(io.dw, UInt<1>(0h0))
node _tz_in_T_1 = bits(io.in2, 0, 0)
node _tz_in_T_2 = eq(_tz_in_T_1, UInt<1>(0h0))
node _tz_in_T_3 = cat(_tz_in_T, _tz_in_T_2)
node _tz_in_T_4 = shl(UInt<32>(0hffffffff), 32)
node _tz_in_T_5 = xor(UInt<64>(0hffffffffffffffff), _tz_in_T_4)
node _tz_in_T_6 = shr(io.in1, 32)
node _tz_in_T_7 = and(_tz_in_T_6, _tz_in_T_5)
node _tz_in_T_8 = bits(io.in1, 31, 0)
node _tz_in_T_9 = shl(_tz_in_T_8, 32)
node _tz_in_T_10 = not(_tz_in_T_5)
node _tz_in_T_11 = and(_tz_in_T_9, _tz_in_T_10)
node _tz_in_T_12 = or(_tz_in_T_7, _tz_in_T_11)
node _tz_in_T_13 = bits(_tz_in_T_5, 47, 0)
node _tz_in_T_14 = shl(_tz_in_T_13, 16)
node _tz_in_T_15 = xor(_tz_in_T_5, _tz_in_T_14)
node _tz_in_T_16 = shr(_tz_in_T_12, 16)
node _tz_in_T_17 = and(_tz_in_T_16, _tz_in_T_15)
node _tz_in_T_18 = bits(_tz_in_T_12, 47, 0)
node _tz_in_T_19 = shl(_tz_in_T_18, 16)
node _tz_in_T_20 = not(_tz_in_T_15)
node _tz_in_T_21 = and(_tz_in_T_19, _tz_in_T_20)
node _tz_in_T_22 = or(_tz_in_T_17, _tz_in_T_21)
node _tz_in_T_23 = bits(_tz_in_T_15, 55, 0)
node _tz_in_T_24 = shl(_tz_in_T_23, 8)
node _tz_in_T_25 = xor(_tz_in_T_15, _tz_in_T_24)
node _tz_in_T_26 = shr(_tz_in_T_22, 8)
node _tz_in_T_27 = and(_tz_in_T_26, _tz_in_T_25)
node _tz_in_T_28 = bits(_tz_in_T_22, 55, 0)
node _tz_in_T_29 = shl(_tz_in_T_28, 8)
node _tz_in_T_30 = not(_tz_in_T_25)
node _tz_in_T_31 = and(_tz_in_T_29, _tz_in_T_30)
node _tz_in_T_32 = or(_tz_in_T_27, _tz_in_T_31)
node _tz_in_T_33 = bits(_tz_in_T_25, 59, 0)
node _tz_in_T_34 = shl(_tz_in_T_33, 4)
node _tz_in_T_35 = xor(_tz_in_T_25, _tz_in_T_34)
node _tz_in_T_36 = shr(_tz_in_T_32, 4)
node _tz_in_T_37 = and(_tz_in_T_36, _tz_in_T_35)
node _tz_in_T_38 = bits(_tz_in_T_32, 59, 0)
node _tz_in_T_39 = shl(_tz_in_T_38, 4)
node _tz_in_T_40 = not(_tz_in_T_35)
node _tz_in_T_41 = and(_tz_in_T_39, _tz_in_T_40)
node _tz_in_T_42 = or(_tz_in_T_37, _tz_in_T_41)
node _tz_in_T_43 = bits(_tz_in_T_35, 61, 0)
node _tz_in_T_44 = shl(_tz_in_T_43, 2)
node _tz_in_T_45 = xor(_tz_in_T_35, _tz_in_T_44)
node _tz_in_T_46 = shr(_tz_in_T_42, 2)
node _tz_in_T_47 = and(_tz_in_T_46, _tz_in_T_45)
node _tz_in_T_48 = bits(_tz_in_T_42, 61, 0)
node _tz_in_T_49 = shl(_tz_in_T_48, 2)
node _tz_in_T_50 = not(_tz_in_T_45)
node _tz_in_T_51 = and(_tz_in_T_49, _tz_in_T_50)
node _tz_in_T_52 = or(_tz_in_T_47, _tz_in_T_51)
node _tz_in_T_53 = bits(_tz_in_T_45, 62, 0)
node _tz_in_T_54 = shl(_tz_in_T_53, 1)
node _tz_in_T_55 = xor(_tz_in_T_45, _tz_in_T_54)
node _tz_in_T_56 = shr(_tz_in_T_52, 1)
node _tz_in_T_57 = and(_tz_in_T_56, _tz_in_T_55)
node _tz_in_T_58 = bits(_tz_in_T_52, 62, 0)
node _tz_in_T_59 = shl(_tz_in_T_58, 1)
node _tz_in_T_60 = not(_tz_in_T_55)
node _tz_in_T_61 = and(_tz_in_T_59, _tz_in_T_60)
node _tz_in_T_62 = or(_tz_in_T_57, _tz_in_T_61)
node _tz_in_T_63 = bits(io.in1, 31, 0)
node _tz_in_T_64 = cat(UInt<1>(0h1), _tz_in_T_63)
node _tz_in_T_65 = bits(io.in1, 31, 0)
node _tz_in_T_66 = shl(UInt<16>(0hffff), 16)
node _tz_in_T_67 = xor(UInt<32>(0hffffffff), _tz_in_T_66)
node _tz_in_T_68 = shr(_tz_in_T_65, 16)
node _tz_in_T_69 = and(_tz_in_T_68, _tz_in_T_67)
node _tz_in_T_70 = bits(_tz_in_T_65, 15, 0)
node _tz_in_T_71 = shl(_tz_in_T_70, 16)
node _tz_in_T_72 = not(_tz_in_T_67)
node _tz_in_T_73 = and(_tz_in_T_71, _tz_in_T_72)
node _tz_in_T_74 = or(_tz_in_T_69, _tz_in_T_73)
node _tz_in_T_75 = bits(_tz_in_T_67, 23, 0)
node _tz_in_T_76 = shl(_tz_in_T_75, 8)
node _tz_in_T_77 = xor(_tz_in_T_67, _tz_in_T_76)
node _tz_in_T_78 = shr(_tz_in_T_74, 8)
node _tz_in_T_79 = and(_tz_in_T_78, _tz_in_T_77)
node _tz_in_T_80 = bits(_tz_in_T_74, 23, 0)
node _tz_in_T_81 = shl(_tz_in_T_80, 8)
node _tz_in_T_82 = not(_tz_in_T_77)
node _tz_in_T_83 = and(_tz_in_T_81, _tz_in_T_82)
node _tz_in_T_84 = or(_tz_in_T_79, _tz_in_T_83)
node _tz_in_T_85 = bits(_tz_in_T_77, 27, 0)
node _tz_in_T_86 = shl(_tz_in_T_85, 4)
node _tz_in_T_87 = xor(_tz_in_T_77, _tz_in_T_86)
node _tz_in_T_88 = shr(_tz_in_T_84, 4)
node _tz_in_T_89 = and(_tz_in_T_88, _tz_in_T_87)
node _tz_in_T_90 = bits(_tz_in_T_84, 27, 0)
node _tz_in_T_91 = shl(_tz_in_T_90, 4)
node _tz_in_T_92 = not(_tz_in_T_87)
node _tz_in_T_93 = and(_tz_in_T_91, _tz_in_T_92)
node _tz_in_T_94 = or(_tz_in_T_89, _tz_in_T_93)
node _tz_in_T_95 = bits(_tz_in_T_87, 29, 0)
node _tz_in_T_96 = shl(_tz_in_T_95, 2)
node _tz_in_T_97 = xor(_tz_in_T_87, _tz_in_T_96)
node _tz_in_T_98 = shr(_tz_in_T_94, 2)
node _tz_in_T_99 = and(_tz_in_T_98, _tz_in_T_97)
node _tz_in_T_100 = bits(_tz_in_T_94, 29, 0)
node _tz_in_T_101 = shl(_tz_in_T_100, 2)
node _tz_in_T_102 = not(_tz_in_T_97)
node _tz_in_T_103 = and(_tz_in_T_101, _tz_in_T_102)
node _tz_in_T_104 = or(_tz_in_T_99, _tz_in_T_103)
node _tz_in_T_105 = bits(_tz_in_T_97, 30, 0)
node _tz_in_T_106 = shl(_tz_in_T_105, 1)
node _tz_in_T_107 = xor(_tz_in_T_97, _tz_in_T_106)
node _tz_in_T_108 = shr(_tz_in_T_104, 1)
node _tz_in_T_109 = and(_tz_in_T_108, _tz_in_T_107)
node _tz_in_T_110 = bits(_tz_in_T_104, 30, 0)
node _tz_in_T_111 = shl(_tz_in_T_110, 1)
node _tz_in_T_112 = not(_tz_in_T_107)
node _tz_in_T_113 = and(_tz_in_T_111, _tz_in_T_112)
node _tz_in_T_114 = or(_tz_in_T_109, _tz_in_T_113)
node _tz_in_T_115 = cat(UInt<1>(0h1), _tz_in_T_114)
node _tz_in_T_116 = eq(UInt<1>(0h1), _tz_in_T_3)
node _tz_in_T_117 = mux(_tz_in_T_116, _tz_in_T_62, io.in1)
node _tz_in_T_118 = eq(UInt<2>(0h2), _tz_in_T_3)
node _tz_in_T_119 = mux(_tz_in_T_118, _tz_in_T_64, _tz_in_T_117)
node _tz_in_T_120 = eq(UInt<2>(0h3), _tz_in_T_3)
node tz_in = mux(_tz_in_T_120, _tz_in_T_115, _tz_in_T_119)
node _popc_in_T = bits(io.in2, 1, 1)
node _popc_in_T_1 = eq(io.dw, UInt<1>(0h0))
node _popc_in_T_2 = bits(io.in1, 31, 0)
node _popc_in_T_3 = mux(_popc_in_T_1, _popc_in_T_2, io.in1)
node _popc_in_T_4 = cat(UInt<1>(0h1), tz_in)
node _popc_in_T_5 = bits(_popc_in_T_4, 0, 0)
node _popc_in_T_6 = bits(_popc_in_T_4, 1, 1)
node _popc_in_T_7 = bits(_popc_in_T_4, 2, 2)
node _popc_in_T_8 = bits(_popc_in_T_4, 3, 3)
node _popc_in_T_9 = bits(_popc_in_T_4, 4, 4)
node _popc_in_T_10 = bits(_popc_in_T_4, 5, 5)
node _popc_in_T_11 = bits(_popc_in_T_4, 6, 6)
node _popc_in_T_12 = bits(_popc_in_T_4, 7, 7)
node _popc_in_T_13 = bits(_popc_in_T_4, 8, 8)
node _popc_in_T_14 = bits(_popc_in_T_4, 9, 9)
node _popc_in_T_15 = bits(_popc_in_T_4, 10, 10)
node _popc_in_T_16 = bits(_popc_in_T_4, 11, 11)
node _popc_in_T_17 = bits(_popc_in_T_4, 12, 12)
node _popc_in_T_18 = bits(_popc_in_T_4, 13, 13)
node _popc_in_T_19 = bits(_popc_in_T_4, 14, 14)
node _popc_in_T_20 = bits(_popc_in_T_4, 15, 15)
node _popc_in_T_21 = bits(_popc_in_T_4, 16, 16)
node _popc_in_T_22 = bits(_popc_in_T_4, 17, 17)
node _popc_in_T_23 = bits(_popc_in_T_4, 18, 18)
node _popc_in_T_24 = bits(_popc_in_T_4, 19, 19)
node _popc_in_T_25 = bits(_popc_in_T_4, 20, 20)
node _popc_in_T_26 = bits(_popc_in_T_4, 21, 21)
node _popc_in_T_27 = bits(_popc_in_T_4, 22, 22)
node _popc_in_T_28 = bits(_popc_in_T_4, 23, 23)
node _popc_in_T_29 = bits(_popc_in_T_4, 24, 24)
node _popc_in_T_30 = bits(_popc_in_T_4, 25, 25)
node _popc_in_T_31 = bits(_popc_in_T_4, 26, 26)
node _popc_in_T_32 = bits(_popc_in_T_4, 27, 27)
node _popc_in_T_33 = bits(_popc_in_T_4, 28, 28)
node _popc_in_T_34 = bits(_popc_in_T_4, 29, 29)
node _popc_in_T_35 = bits(_popc_in_T_4, 30, 30)
node _popc_in_T_36 = bits(_popc_in_T_4, 31, 31)
node _popc_in_T_37 = bits(_popc_in_T_4, 32, 32)
node _popc_in_T_38 = bits(_popc_in_T_4, 33, 33)
node _popc_in_T_39 = bits(_popc_in_T_4, 34, 34)
node _popc_in_T_40 = bits(_popc_in_T_4, 35, 35)
node _popc_in_T_41 = bits(_popc_in_T_4, 36, 36)
node _popc_in_T_42 = bits(_popc_in_T_4, 37, 37)
node _popc_in_T_43 = bits(_popc_in_T_4, 38, 38)
node _popc_in_T_44 = bits(_popc_in_T_4, 39, 39)
node _popc_in_T_45 = bits(_popc_in_T_4, 40, 40)
node _popc_in_T_46 = bits(_popc_in_T_4, 41, 41)
node _popc_in_T_47 = bits(_popc_in_T_4, 42, 42)
node _popc_in_T_48 = bits(_popc_in_T_4, 43, 43)
node _popc_in_T_49 = bits(_popc_in_T_4, 44, 44)
node _popc_in_T_50 = bits(_popc_in_T_4, 45, 45)
node _popc_in_T_51 = bits(_popc_in_T_4, 46, 46)
node _popc_in_T_52 = bits(_popc_in_T_4, 47, 47)
node _popc_in_T_53 = bits(_popc_in_T_4, 48, 48)
node _popc_in_T_54 = bits(_popc_in_T_4, 49, 49)
node _popc_in_T_55 = bits(_popc_in_T_4, 50, 50)
node _popc_in_T_56 = bits(_popc_in_T_4, 51, 51)
node _popc_in_T_57 = bits(_popc_in_T_4, 52, 52)
node _popc_in_T_58 = bits(_popc_in_T_4, 53, 53)
node _popc_in_T_59 = bits(_popc_in_T_4, 54, 54)
node _popc_in_T_60 = bits(_popc_in_T_4, 55, 55)
node _popc_in_T_61 = bits(_popc_in_T_4, 56, 56)
node _popc_in_T_62 = bits(_popc_in_T_4, 57, 57)
node _popc_in_T_63 = bits(_popc_in_T_4, 58, 58)
node _popc_in_T_64 = bits(_popc_in_T_4, 59, 59)
node _popc_in_T_65 = bits(_popc_in_T_4, 60, 60)
node _popc_in_T_66 = bits(_popc_in_T_4, 61, 61)
node _popc_in_T_67 = bits(_popc_in_T_4, 62, 62)
node _popc_in_T_68 = bits(_popc_in_T_4, 63, 63)
node _popc_in_T_69 = bits(_popc_in_T_4, 64, 64)
node _popc_in_T_70 = mux(_popc_in_T_69, UInt<65>(0h10000000000000000), UInt<65>(0h0))
node _popc_in_T_71 = mux(_popc_in_T_68, UInt<65>(0h8000000000000000), _popc_in_T_70)
node _popc_in_T_72 = mux(_popc_in_T_67, UInt<65>(0h4000000000000000), _popc_in_T_71)
node _popc_in_T_73 = mux(_popc_in_T_66, UInt<65>(0h2000000000000000), _popc_in_T_72)
node _popc_in_T_74 = mux(_popc_in_T_65, UInt<65>(0h1000000000000000), _popc_in_T_73)
node _popc_in_T_75 = mux(_popc_in_T_64, UInt<65>(0h800000000000000), _popc_in_T_74)
node _popc_in_T_76 = mux(_popc_in_T_63, UInt<65>(0h400000000000000), _popc_in_T_75)
node _popc_in_T_77 = mux(_popc_in_T_62, UInt<65>(0h200000000000000), _popc_in_T_76)
node _popc_in_T_78 = mux(_popc_in_T_61, UInt<65>(0h100000000000000), _popc_in_T_77)
node _popc_in_T_79 = mux(_popc_in_T_60, UInt<65>(0h80000000000000), _popc_in_T_78)
node _popc_in_T_80 = mux(_popc_in_T_59, UInt<65>(0h40000000000000), _popc_in_T_79)
node _popc_in_T_81 = mux(_popc_in_T_58, UInt<65>(0h20000000000000), _popc_in_T_80)
node _popc_in_T_82 = mux(_popc_in_T_57, UInt<65>(0h10000000000000), _popc_in_T_81)
node _popc_in_T_83 = mux(_popc_in_T_56, UInt<65>(0h8000000000000), _popc_in_T_82)
node _popc_in_T_84 = mux(_popc_in_T_55, UInt<65>(0h4000000000000), _popc_in_T_83)
node _popc_in_T_85 = mux(_popc_in_T_54, UInt<65>(0h2000000000000), _popc_in_T_84)
node _popc_in_T_86 = mux(_popc_in_T_53, UInt<65>(0h1000000000000), _popc_in_T_85)
node _popc_in_T_87 = mux(_popc_in_T_52, UInt<65>(0h800000000000), _popc_in_T_86)
node _popc_in_T_88 = mux(_popc_in_T_51, UInt<65>(0h400000000000), _popc_in_T_87)
node _popc_in_T_89 = mux(_popc_in_T_50, UInt<65>(0h200000000000), _popc_in_T_88)
node _popc_in_T_90 = mux(_popc_in_T_49, UInt<65>(0h100000000000), _popc_in_T_89)
node _popc_in_T_91 = mux(_popc_in_T_48, UInt<65>(0h80000000000), _popc_in_T_90)
node _popc_in_T_92 = mux(_popc_in_T_47, UInt<65>(0h40000000000), _popc_in_T_91)
node _popc_in_T_93 = mux(_popc_in_T_46, UInt<65>(0h20000000000), _popc_in_T_92)
node _popc_in_T_94 = mux(_popc_in_T_45, UInt<65>(0h10000000000), _popc_in_T_93)
node _popc_in_T_95 = mux(_popc_in_T_44, UInt<65>(0h8000000000), _popc_in_T_94)
node _popc_in_T_96 = mux(_popc_in_T_43, UInt<65>(0h4000000000), _popc_in_T_95)
node _popc_in_T_97 = mux(_popc_in_T_42, UInt<65>(0h2000000000), _popc_in_T_96)
node _popc_in_T_98 = mux(_popc_in_T_41, UInt<65>(0h1000000000), _popc_in_T_97)
node _popc_in_T_99 = mux(_popc_in_T_40, UInt<65>(0h800000000), _popc_in_T_98)
node _popc_in_T_100 = mux(_popc_in_T_39, UInt<65>(0h400000000), _popc_in_T_99)
node _popc_in_T_101 = mux(_popc_in_T_38, UInt<65>(0h200000000), _popc_in_T_100)
node _popc_in_T_102 = mux(_popc_in_T_37, UInt<65>(0h100000000), _popc_in_T_101)
node _popc_in_T_103 = mux(_popc_in_T_36, UInt<65>(0h80000000), _popc_in_T_102)
node _popc_in_T_104 = mux(_popc_in_T_35, UInt<65>(0h40000000), _popc_in_T_103)
node _popc_in_T_105 = mux(_popc_in_T_34, UInt<65>(0h20000000), _popc_in_T_104)
node _popc_in_T_106 = mux(_popc_in_T_33, UInt<65>(0h10000000), _popc_in_T_105)
node _popc_in_T_107 = mux(_popc_in_T_32, UInt<65>(0h8000000), _popc_in_T_106)
node _popc_in_T_108 = mux(_popc_in_T_31, UInt<65>(0h4000000), _popc_in_T_107)
node _popc_in_T_109 = mux(_popc_in_T_30, UInt<65>(0h2000000), _popc_in_T_108)
node _popc_in_T_110 = mux(_popc_in_T_29, UInt<65>(0h1000000), _popc_in_T_109)
node _popc_in_T_111 = mux(_popc_in_T_28, UInt<65>(0h800000), _popc_in_T_110)
node _popc_in_T_112 = mux(_popc_in_T_27, UInt<65>(0h400000), _popc_in_T_111)
node _popc_in_T_113 = mux(_popc_in_T_26, UInt<65>(0h200000), _popc_in_T_112)
node _popc_in_T_114 = mux(_popc_in_T_25, UInt<65>(0h100000), _popc_in_T_113)
node _popc_in_T_115 = mux(_popc_in_T_24, UInt<65>(0h80000), _popc_in_T_114)
node _popc_in_T_116 = mux(_popc_in_T_23, UInt<65>(0h40000), _popc_in_T_115)
node _popc_in_T_117 = mux(_popc_in_T_22, UInt<65>(0h20000), _popc_in_T_116)
node _popc_in_T_118 = mux(_popc_in_T_21, UInt<65>(0h10000), _popc_in_T_117)
node _popc_in_T_119 = mux(_popc_in_T_20, UInt<65>(0h8000), _popc_in_T_118)
node _popc_in_T_120 = mux(_popc_in_T_19, UInt<65>(0h4000), _popc_in_T_119)
node _popc_in_T_121 = mux(_popc_in_T_18, UInt<65>(0h2000), _popc_in_T_120)
node _popc_in_T_122 = mux(_popc_in_T_17, UInt<65>(0h1000), _popc_in_T_121)
node _popc_in_T_123 = mux(_popc_in_T_16, UInt<65>(0h800), _popc_in_T_122)
node _popc_in_T_124 = mux(_popc_in_T_15, UInt<65>(0h400), _popc_in_T_123)
node _popc_in_T_125 = mux(_popc_in_T_14, UInt<65>(0h200), _popc_in_T_124)
node _popc_in_T_126 = mux(_popc_in_T_13, UInt<65>(0h100), _popc_in_T_125)
node _popc_in_T_127 = mux(_popc_in_T_12, UInt<65>(0h80), _popc_in_T_126)
node _popc_in_T_128 = mux(_popc_in_T_11, UInt<65>(0h40), _popc_in_T_127)
node _popc_in_T_129 = mux(_popc_in_T_10, UInt<65>(0h20), _popc_in_T_128)
node _popc_in_T_130 = mux(_popc_in_T_9, UInt<65>(0h10), _popc_in_T_129)
node _popc_in_T_131 = mux(_popc_in_T_8, UInt<65>(0h8), _popc_in_T_130)
node _popc_in_T_132 = mux(_popc_in_T_7, UInt<65>(0h4), _popc_in_T_131)
node _popc_in_T_133 = mux(_popc_in_T_6, UInt<65>(0h2), _popc_in_T_132)
node _popc_in_T_134 = mux(_popc_in_T_5, UInt<65>(0h1), _popc_in_T_133)
node _popc_in_T_135 = sub(_popc_in_T_134, UInt<1>(0h1))
node _popc_in_T_136 = tail(_popc_in_T_135, 1)
node _popc_in_T_137 = mux(_popc_in_T, _popc_in_T_3, _popc_in_T_136)
node popc_in = bits(_popc_in_T_137, 63, 0)
node _count_T = bits(popc_in, 0, 0)
node _count_T_1 = bits(popc_in, 1, 1)
node _count_T_2 = bits(popc_in, 2, 2)
node _count_T_3 = bits(popc_in, 3, 3)
node _count_T_4 = bits(popc_in, 4, 4)
node _count_T_5 = bits(popc_in, 5, 5)
node _count_T_6 = bits(popc_in, 6, 6)
node _count_T_7 = bits(popc_in, 7, 7)
node _count_T_8 = bits(popc_in, 8, 8)
node _count_T_9 = bits(popc_in, 9, 9)
node _count_T_10 = bits(popc_in, 10, 10)
node _count_T_11 = bits(popc_in, 11, 11)
node _count_T_12 = bits(popc_in, 12, 12)
node _count_T_13 = bits(popc_in, 13, 13)
node _count_T_14 = bits(popc_in, 14, 14)
node _count_T_15 = bits(popc_in, 15, 15)
node _count_T_16 = bits(popc_in, 16, 16)
node _count_T_17 = bits(popc_in, 17, 17)
node _count_T_18 = bits(popc_in, 18, 18)
node _count_T_19 = bits(popc_in, 19, 19)
node _count_T_20 = bits(popc_in, 20, 20)
node _count_T_21 = bits(popc_in, 21, 21)
node _count_T_22 = bits(popc_in, 22, 22)
node _count_T_23 = bits(popc_in, 23, 23)
node _count_T_24 = bits(popc_in, 24, 24)
node _count_T_25 = bits(popc_in, 25, 25)
node _count_T_26 = bits(popc_in, 26, 26)
node _count_T_27 = bits(popc_in, 27, 27)
node _count_T_28 = bits(popc_in, 28, 28)
node _count_T_29 = bits(popc_in, 29, 29)
node _count_T_30 = bits(popc_in, 30, 30)
node _count_T_31 = bits(popc_in, 31, 31)
node _count_T_32 = bits(popc_in, 32, 32)
node _count_T_33 = bits(popc_in, 33, 33)
node _count_T_34 = bits(popc_in, 34, 34)
node _count_T_35 = bits(popc_in, 35, 35)
node _count_T_36 = bits(popc_in, 36, 36)
node _count_T_37 = bits(popc_in, 37, 37)
node _count_T_38 = bits(popc_in, 38, 38)
node _count_T_39 = bits(popc_in, 39, 39)
node _count_T_40 = bits(popc_in, 40, 40)
node _count_T_41 = bits(popc_in, 41, 41)
node _count_T_42 = bits(popc_in, 42, 42)
node _count_T_43 = bits(popc_in, 43, 43)
node _count_T_44 = bits(popc_in, 44, 44)
node _count_T_45 = bits(popc_in, 45, 45)
node _count_T_46 = bits(popc_in, 46, 46)
node _count_T_47 = bits(popc_in, 47, 47)
node _count_T_48 = bits(popc_in, 48, 48)
node _count_T_49 = bits(popc_in, 49, 49)
node _count_T_50 = bits(popc_in, 50, 50)
node _count_T_51 = bits(popc_in, 51, 51)
node _count_T_52 = bits(popc_in, 52, 52)
node _count_T_53 = bits(popc_in, 53, 53)
node _count_T_54 = bits(popc_in, 54, 54)
node _count_T_55 = bits(popc_in, 55, 55)
node _count_T_56 = bits(popc_in, 56, 56)
node _count_T_57 = bits(popc_in, 57, 57)
node _count_T_58 = bits(popc_in, 58, 58)
node _count_T_59 = bits(popc_in, 59, 59)
node _count_T_60 = bits(popc_in, 60, 60)
node _count_T_61 = bits(popc_in, 61, 61)
node _count_T_62 = bits(popc_in, 62, 62)
node _count_T_63 = bits(popc_in, 63, 63)
node _count_T_64 = add(_count_T, _count_T_1)
node _count_T_65 = bits(_count_T_64, 1, 0)
node _count_T_66 = add(_count_T_2, _count_T_3)
node _count_T_67 = bits(_count_T_66, 1, 0)
node _count_T_68 = add(_count_T_65, _count_T_67)
node _count_T_69 = bits(_count_T_68, 2, 0)
node _count_T_70 = add(_count_T_4, _count_T_5)
node _count_T_71 = bits(_count_T_70, 1, 0)
node _count_T_72 = add(_count_T_6, _count_T_7)
node _count_T_73 = bits(_count_T_72, 1, 0)
node _count_T_74 = add(_count_T_71, _count_T_73)
node _count_T_75 = bits(_count_T_74, 2, 0)
node _count_T_76 = add(_count_T_69, _count_T_75)
node _count_T_77 = bits(_count_T_76, 3, 0)
node _count_T_78 = add(_count_T_8, _count_T_9)
node _count_T_79 = bits(_count_T_78, 1, 0)
node _count_T_80 = add(_count_T_10, _count_T_11)
node _count_T_81 = bits(_count_T_80, 1, 0)
node _count_T_82 = add(_count_T_79, _count_T_81)
node _count_T_83 = bits(_count_T_82, 2, 0)
node _count_T_84 = add(_count_T_12, _count_T_13)
node _count_T_85 = bits(_count_T_84, 1, 0)
node _count_T_86 = add(_count_T_14, _count_T_15)
node _count_T_87 = bits(_count_T_86, 1, 0)
node _count_T_88 = add(_count_T_85, _count_T_87)
node _count_T_89 = bits(_count_T_88, 2, 0)
node _count_T_90 = add(_count_T_83, _count_T_89)
node _count_T_91 = bits(_count_T_90, 3, 0)
node _count_T_92 = add(_count_T_77, _count_T_91)
node _count_T_93 = bits(_count_T_92, 4, 0)
node _count_T_94 = add(_count_T_16, _count_T_17)
node _count_T_95 = bits(_count_T_94, 1, 0)
node _count_T_96 = add(_count_T_18, _count_T_19)
node _count_T_97 = bits(_count_T_96, 1, 0)
node _count_T_98 = add(_count_T_95, _count_T_97)
node _count_T_99 = bits(_count_T_98, 2, 0)
node _count_T_100 = add(_count_T_20, _count_T_21)
node _count_T_101 = bits(_count_T_100, 1, 0)
node _count_T_102 = add(_count_T_22, _count_T_23)
node _count_T_103 = bits(_count_T_102, 1, 0)
node _count_T_104 = add(_count_T_101, _count_T_103)
node _count_T_105 = bits(_count_T_104, 2, 0)
node _count_T_106 = add(_count_T_99, _count_T_105)
node _count_T_107 = bits(_count_T_106, 3, 0)
node _count_T_108 = add(_count_T_24, _count_T_25)
node _count_T_109 = bits(_count_T_108, 1, 0)
node _count_T_110 = add(_count_T_26, _count_T_27)
node _count_T_111 = bits(_count_T_110, 1, 0)
node _count_T_112 = add(_count_T_109, _count_T_111)
node _count_T_113 = bits(_count_T_112, 2, 0)
node _count_T_114 = add(_count_T_28, _count_T_29)
node _count_T_115 = bits(_count_T_114, 1, 0)
node _count_T_116 = add(_count_T_30, _count_T_31)
node _count_T_117 = bits(_count_T_116, 1, 0)
node _count_T_118 = add(_count_T_115, _count_T_117)
node _count_T_119 = bits(_count_T_118, 2, 0)
node _count_T_120 = add(_count_T_113, _count_T_119)
node _count_T_121 = bits(_count_T_120, 3, 0)
node _count_T_122 = add(_count_T_107, _count_T_121)
node _count_T_123 = bits(_count_T_122, 4, 0)
node _count_T_124 = add(_count_T_93, _count_T_123)
node _count_T_125 = bits(_count_T_124, 5, 0)
node _count_T_126 = add(_count_T_32, _count_T_33)
node _count_T_127 = bits(_count_T_126, 1, 0)
node _count_T_128 = add(_count_T_34, _count_T_35)
node _count_T_129 = bits(_count_T_128, 1, 0)
node _count_T_130 = add(_count_T_127, _count_T_129)
node _count_T_131 = bits(_count_T_130, 2, 0)
node _count_T_132 = add(_count_T_36, _count_T_37)
node _count_T_133 = bits(_count_T_132, 1, 0)
node _count_T_134 = add(_count_T_38, _count_T_39)
node _count_T_135 = bits(_count_T_134, 1, 0)
node _count_T_136 = add(_count_T_133, _count_T_135)
node _count_T_137 = bits(_count_T_136, 2, 0)
node _count_T_138 = add(_count_T_131, _count_T_137)
node _count_T_139 = bits(_count_T_138, 3, 0)
node _count_T_140 = add(_count_T_40, _count_T_41)
node _count_T_141 = bits(_count_T_140, 1, 0)
node _count_T_142 = add(_count_T_42, _count_T_43)
node _count_T_143 = bits(_count_T_142, 1, 0)
node _count_T_144 = add(_count_T_141, _count_T_143)
node _count_T_145 = bits(_count_T_144, 2, 0)
node _count_T_146 = add(_count_T_44, _count_T_45)
node _count_T_147 = bits(_count_T_146, 1, 0)
node _count_T_148 = add(_count_T_46, _count_T_47)
node _count_T_149 = bits(_count_T_148, 1, 0)
node _count_T_150 = add(_count_T_147, _count_T_149)
node _count_T_151 = bits(_count_T_150, 2, 0)
node _count_T_152 = add(_count_T_145, _count_T_151)
node _count_T_153 = bits(_count_T_152, 3, 0)
node _count_T_154 = add(_count_T_139, _count_T_153)
node _count_T_155 = bits(_count_T_154, 4, 0)
node _count_T_156 = add(_count_T_48, _count_T_49)
node _count_T_157 = bits(_count_T_156, 1, 0)
node _count_T_158 = add(_count_T_50, _count_T_51)
node _count_T_159 = bits(_count_T_158, 1, 0)
node _count_T_160 = add(_count_T_157, _count_T_159)
node _count_T_161 = bits(_count_T_160, 2, 0)
node _count_T_162 = add(_count_T_52, _count_T_53)
node _count_T_163 = bits(_count_T_162, 1, 0)
node _count_T_164 = add(_count_T_54, _count_T_55)
node _count_T_165 = bits(_count_T_164, 1, 0)
node _count_T_166 = add(_count_T_163, _count_T_165)
node _count_T_167 = bits(_count_T_166, 2, 0)
node _count_T_168 = add(_count_T_161, _count_T_167)
node _count_T_169 = bits(_count_T_168, 3, 0)
node _count_T_170 = add(_count_T_56, _count_T_57)
node _count_T_171 = bits(_count_T_170, 1, 0)
node _count_T_172 = add(_count_T_58, _count_T_59)
node _count_T_173 = bits(_count_T_172, 1, 0)
node _count_T_174 = add(_count_T_171, _count_T_173)
node _count_T_175 = bits(_count_T_174, 2, 0)
node _count_T_176 = add(_count_T_60, _count_T_61)
node _count_T_177 = bits(_count_T_176, 1, 0)
node _count_T_178 = add(_count_T_62, _count_T_63)
node _count_T_179 = bits(_count_T_178, 1, 0)
node _count_T_180 = add(_count_T_177, _count_T_179)
node _count_T_181 = bits(_count_T_180, 2, 0)
node _count_T_182 = add(_count_T_175, _count_T_181)
node _count_T_183 = bits(_count_T_182, 3, 0)
node _count_T_184 = add(_count_T_169, _count_T_183)
node _count_T_185 = bits(_count_T_184, 4, 0)
node _count_T_186 = add(_count_T_155, _count_T_185)
node _count_T_187 = bits(_count_T_186, 5, 0)
node _count_T_188 = add(_count_T_125, _count_T_187)
node count = bits(_count_T_188, 6, 0)
wire in1_bytes : UInt<8>[8]
wire _in1_bytes_WIRE : UInt<64>
connect _in1_bytes_WIRE, io.in1
node _in1_bytes_T = bits(_in1_bytes_WIRE, 7, 0)
connect in1_bytes[0], _in1_bytes_T
node _in1_bytes_T_1 = bits(_in1_bytes_WIRE, 15, 8)
connect in1_bytes[1], _in1_bytes_T_1
node _in1_bytes_T_2 = bits(_in1_bytes_WIRE, 23, 16)
connect in1_bytes[2], _in1_bytes_T_2
node _in1_bytes_T_3 = bits(_in1_bytes_WIRE, 31, 24)
connect in1_bytes[3], _in1_bytes_T_3
node _in1_bytes_T_4 = bits(_in1_bytes_WIRE, 39, 32)
connect in1_bytes[4], _in1_bytes_T_4
node _in1_bytes_T_5 = bits(_in1_bytes_WIRE, 47, 40)
connect in1_bytes[5], _in1_bytes_T_5
node _in1_bytes_T_6 = bits(_in1_bytes_WIRE, 55, 48)
connect in1_bytes[6], _in1_bytes_T_6
node _in1_bytes_T_7 = bits(_in1_bytes_WIRE, 63, 56)
connect in1_bytes[7], _in1_bytes_T_7
node _orcb_T = neq(in1_bytes[0], UInt<1>(0h0))
node _orcb_T_1 = mux(_orcb_T, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_2 = neq(in1_bytes[1], UInt<1>(0h0))
node _orcb_T_3 = mux(_orcb_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_4 = neq(in1_bytes[2], UInt<1>(0h0))
node _orcb_T_5 = mux(_orcb_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_6 = neq(in1_bytes[3], UInt<1>(0h0))
node _orcb_T_7 = mux(_orcb_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_8 = neq(in1_bytes[4], UInt<1>(0h0))
node _orcb_T_9 = mux(_orcb_T_8, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_10 = neq(in1_bytes[5], UInt<1>(0h0))
node _orcb_T_11 = mux(_orcb_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_12 = neq(in1_bytes[6], UInt<1>(0h0))
node _orcb_T_13 = mux(_orcb_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_14 = neq(in1_bytes[7], UInt<1>(0h0))
node _orcb_T_15 = mux(_orcb_T_14, UInt<8>(0hff), UInt<8>(0h0))
wire _orcb_WIRE : UInt<8>[8]
connect _orcb_WIRE[0], _orcb_T_1
connect _orcb_WIRE[1], _orcb_T_3
connect _orcb_WIRE[2], _orcb_T_5
connect _orcb_WIRE[3], _orcb_T_7
connect _orcb_WIRE[4], _orcb_T_9
connect _orcb_WIRE[5], _orcb_T_11
connect _orcb_WIRE[6], _orcb_T_13
connect _orcb_WIRE[7], _orcb_T_15
node orcb_lo_lo = cat(_orcb_WIRE[1], _orcb_WIRE[0])
node orcb_lo_hi = cat(_orcb_WIRE[3], _orcb_WIRE[2])
node orcb_lo = cat(orcb_lo_hi, orcb_lo_lo)
node orcb_hi_lo = cat(_orcb_WIRE[5], _orcb_WIRE[4])
node orcb_hi_hi = cat(_orcb_WIRE[7], _orcb_WIRE[6])
node orcb_hi = cat(orcb_hi_hi, orcb_hi_lo)
node orcb = cat(orcb_hi, orcb_lo)
wire _rev8_WIRE : UInt<8>[8]
connect _rev8_WIRE[0], in1_bytes[7]
connect _rev8_WIRE[1], in1_bytes[6]
connect _rev8_WIRE[2], in1_bytes[5]
connect _rev8_WIRE[3], in1_bytes[4]
connect _rev8_WIRE[4], in1_bytes[3]
connect _rev8_WIRE[5], in1_bytes[2]
connect _rev8_WIRE[6], in1_bytes[1]
connect _rev8_WIRE[7], in1_bytes[0]
node rev8_lo_lo = cat(_rev8_WIRE[1], _rev8_WIRE[0])
node rev8_lo_hi = cat(_rev8_WIRE[3], _rev8_WIRE[2])
node rev8_lo = cat(rev8_lo_hi, rev8_lo_lo)
node rev8_hi_lo = cat(_rev8_WIRE[5], _rev8_WIRE[4])
node rev8_hi_hi = cat(_rev8_WIRE[7], _rev8_WIRE[6])
node rev8_hi = cat(rev8_hi_hi, rev8_hi_lo)
node rev8 = cat(rev8_hi, rev8_lo)
node _unary_T = bits(io.in2, 11, 0)
node _unary_T_1 = bits(io.in1, 15, 0)
node _unary_T_2 = bits(io.in1, 7, 7)
node _unary_T_3 = mux(_unary_T_2, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _unary_T_4 = bits(io.in1, 7, 0)
node _unary_T_5 = cat(_unary_T_3, _unary_T_4)
node _unary_T_6 = bits(io.in1, 15, 15)
node _unary_T_7 = mux(_unary_T_6, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _unary_T_8 = bits(io.in1, 15, 0)
node _unary_T_9 = cat(_unary_T_7, _unary_T_8)
node _unary_T_10 = eq(UInt<10>(0h287), _unary_T)
node _unary_T_11 = mux(_unary_T_10, orcb, count)
node _unary_T_12 = eq(UInt<11>(0h6b8), _unary_T)
node _unary_T_13 = mux(_unary_T_12, rev8, _unary_T_11)
node _unary_T_14 = eq(UInt<8>(0h80), _unary_T)
node _unary_T_15 = mux(_unary_T_14, _unary_T_1, _unary_T_13)
node _unary_T_16 = eq(UInt<11>(0h604), _unary_T)
node _unary_T_17 = mux(_unary_T_16, _unary_T_5, _unary_T_15)
node _unary_T_18 = eq(UInt<11>(0h605), _unary_T)
node unary = mux(_unary_T_18, _unary_T_9, _unary_T_17)
node maxmin_out = mux(io.cmp_out, io.in2, io.in1)
node _rot_shamt_T = eq(io.dw, UInt<1>(0h0))
node _rot_shamt_T_1 = mux(_rot_shamt_T, UInt<6>(0h20), UInt<7>(0h40))
node _rot_shamt_T_2 = sub(_rot_shamt_T_1, shamt)
node rot_shamt = tail(_rot_shamt_T_2, 1)
node _rotin_T = bits(io.fn, 0, 0)
node _rotin_T_1 = shl(UInt<32>(0hffffffff), 32)
node _rotin_T_2 = xor(UInt<64>(0hffffffffffffffff), _rotin_T_1)
node _rotin_T_3 = shr(shin_r, 32)
node _rotin_T_4 = and(_rotin_T_3, _rotin_T_2)
node _rotin_T_5 = bits(shin_r, 31, 0)
node _rotin_T_6 = shl(_rotin_T_5, 32)
node _rotin_T_7 = not(_rotin_T_2)
node _rotin_T_8 = and(_rotin_T_6, _rotin_T_7)
node _rotin_T_9 = or(_rotin_T_4, _rotin_T_8)
node _rotin_T_10 = bits(_rotin_T_2, 47, 0)
node _rotin_T_11 = shl(_rotin_T_10, 16)
node _rotin_T_12 = xor(_rotin_T_2, _rotin_T_11)
node _rotin_T_13 = shr(_rotin_T_9, 16)
node _rotin_T_14 = and(_rotin_T_13, _rotin_T_12)
node _rotin_T_15 = bits(_rotin_T_9, 47, 0)
node _rotin_T_16 = shl(_rotin_T_15, 16)
node _rotin_T_17 = not(_rotin_T_12)
node _rotin_T_18 = and(_rotin_T_16, _rotin_T_17)
node _rotin_T_19 = or(_rotin_T_14, _rotin_T_18)
node _rotin_T_20 = bits(_rotin_T_12, 55, 0)
node _rotin_T_21 = shl(_rotin_T_20, 8)
node _rotin_T_22 = xor(_rotin_T_12, _rotin_T_21)
node _rotin_T_23 = shr(_rotin_T_19, 8)
node _rotin_T_24 = and(_rotin_T_23, _rotin_T_22)
node _rotin_T_25 = bits(_rotin_T_19, 55, 0)
node _rotin_T_26 = shl(_rotin_T_25, 8)
node _rotin_T_27 = not(_rotin_T_22)
node _rotin_T_28 = and(_rotin_T_26, _rotin_T_27)
node _rotin_T_29 = or(_rotin_T_24, _rotin_T_28)
node _rotin_T_30 = bits(_rotin_T_22, 59, 0)
node _rotin_T_31 = shl(_rotin_T_30, 4)
node _rotin_T_32 = xor(_rotin_T_22, _rotin_T_31)
node _rotin_T_33 = shr(_rotin_T_29, 4)
node _rotin_T_34 = and(_rotin_T_33, _rotin_T_32)
node _rotin_T_35 = bits(_rotin_T_29, 59, 0)
node _rotin_T_36 = shl(_rotin_T_35, 4)
node _rotin_T_37 = not(_rotin_T_32)
node _rotin_T_38 = and(_rotin_T_36, _rotin_T_37)
node _rotin_T_39 = or(_rotin_T_34, _rotin_T_38)
node _rotin_T_40 = bits(_rotin_T_32, 61, 0)
node _rotin_T_41 = shl(_rotin_T_40, 2)
node _rotin_T_42 = xor(_rotin_T_32, _rotin_T_41)
node _rotin_T_43 = shr(_rotin_T_39, 2)
node _rotin_T_44 = and(_rotin_T_43, _rotin_T_42)
node _rotin_T_45 = bits(_rotin_T_39, 61, 0)
node _rotin_T_46 = shl(_rotin_T_45, 2)
node _rotin_T_47 = not(_rotin_T_42)
node _rotin_T_48 = and(_rotin_T_46, _rotin_T_47)
node _rotin_T_49 = or(_rotin_T_44, _rotin_T_48)
node _rotin_T_50 = bits(_rotin_T_42, 62, 0)
node _rotin_T_51 = shl(_rotin_T_50, 1)
node _rotin_T_52 = xor(_rotin_T_42, _rotin_T_51)
node _rotin_T_53 = shr(_rotin_T_49, 1)
node _rotin_T_54 = and(_rotin_T_53, _rotin_T_52)
node _rotin_T_55 = bits(_rotin_T_49, 62, 0)
node _rotin_T_56 = shl(_rotin_T_55, 1)
node _rotin_T_57 = not(_rotin_T_52)
node _rotin_T_58 = and(_rotin_T_56, _rotin_T_57)
node _rotin_T_59 = or(_rotin_T_54, _rotin_T_58)
node rotin = mux(_rotin_T, shin_r, _rotin_T_59)
node _rotout_r_T = dshr(rotin, rot_shamt)
node rotout_r = bits(_rotout_r_T, 63, 0)
node _rotout_l_T = shl(UInt<32>(0hffffffff), 32)
node _rotout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _rotout_l_T)
node _rotout_l_T_2 = shr(rotout_r, 32)
node _rotout_l_T_3 = and(_rotout_l_T_2, _rotout_l_T_1)
node _rotout_l_T_4 = bits(rotout_r, 31, 0)
node _rotout_l_T_5 = shl(_rotout_l_T_4, 32)
node _rotout_l_T_6 = not(_rotout_l_T_1)
node _rotout_l_T_7 = and(_rotout_l_T_5, _rotout_l_T_6)
node _rotout_l_T_8 = or(_rotout_l_T_3, _rotout_l_T_7)
node _rotout_l_T_9 = bits(_rotout_l_T_1, 47, 0)
node _rotout_l_T_10 = shl(_rotout_l_T_9, 16)
node _rotout_l_T_11 = xor(_rotout_l_T_1, _rotout_l_T_10)
node _rotout_l_T_12 = shr(_rotout_l_T_8, 16)
node _rotout_l_T_13 = and(_rotout_l_T_12, _rotout_l_T_11)
node _rotout_l_T_14 = bits(_rotout_l_T_8, 47, 0)
node _rotout_l_T_15 = shl(_rotout_l_T_14, 16)
node _rotout_l_T_16 = not(_rotout_l_T_11)
node _rotout_l_T_17 = and(_rotout_l_T_15, _rotout_l_T_16)
node _rotout_l_T_18 = or(_rotout_l_T_13, _rotout_l_T_17)
node _rotout_l_T_19 = bits(_rotout_l_T_11, 55, 0)
node _rotout_l_T_20 = shl(_rotout_l_T_19, 8)
node _rotout_l_T_21 = xor(_rotout_l_T_11, _rotout_l_T_20)
node _rotout_l_T_22 = shr(_rotout_l_T_18, 8)
node _rotout_l_T_23 = and(_rotout_l_T_22, _rotout_l_T_21)
node _rotout_l_T_24 = bits(_rotout_l_T_18, 55, 0)
node _rotout_l_T_25 = shl(_rotout_l_T_24, 8)
node _rotout_l_T_26 = not(_rotout_l_T_21)
node _rotout_l_T_27 = and(_rotout_l_T_25, _rotout_l_T_26)
node _rotout_l_T_28 = or(_rotout_l_T_23, _rotout_l_T_27)
node _rotout_l_T_29 = bits(_rotout_l_T_21, 59, 0)
node _rotout_l_T_30 = shl(_rotout_l_T_29, 4)
node _rotout_l_T_31 = xor(_rotout_l_T_21, _rotout_l_T_30)
node _rotout_l_T_32 = shr(_rotout_l_T_28, 4)
node _rotout_l_T_33 = and(_rotout_l_T_32, _rotout_l_T_31)
node _rotout_l_T_34 = bits(_rotout_l_T_28, 59, 0)
node _rotout_l_T_35 = shl(_rotout_l_T_34, 4)
node _rotout_l_T_36 = not(_rotout_l_T_31)
node _rotout_l_T_37 = and(_rotout_l_T_35, _rotout_l_T_36)
node _rotout_l_T_38 = or(_rotout_l_T_33, _rotout_l_T_37)
node _rotout_l_T_39 = bits(_rotout_l_T_31, 61, 0)
node _rotout_l_T_40 = shl(_rotout_l_T_39, 2)
node _rotout_l_T_41 = xor(_rotout_l_T_31, _rotout_l_T_40)
node _rotout_l_T_42 = shr(_rotout_l_T_38, 2)
node _rotout_l_T_43 = and(_rotout_l_T_42, _rotout_l_T_41)
node _rotout_l_T_44 = bits(_rotout_l_T_38, 61, 0)
node _rotout_l_T_45 = shl(_rotout_l_T_44, 2)
node _rotout_l_T_46 = not(_rotout_l_T_41)
node _rotout_l_T_47 = and(_rotout_l_T_45, _rotout_l_T_46)
node _rotout_l_T_48 = or(_rotout_l_T_43, _rotout_l_T_47)
node _rotout_l_T_49 = bits(_rotout_l_T_41, 62, 0)
node _rotout_l_T_50 = shl(_rotout_l_T_49, 1)
node _rotout_l_T_51 = xor(_rotout_l_T_41, _rotout_l_T_50)
node _rotout_l_T_52 = shr(_rotout_l_T_48, 1)
node _rotout_l_T_53 = and(_rotout_l_T_52, _rotout_l_T_51)
node _rotout_l_T_54 = bits(_rotout_l_T_48, 62, 0)
node _rotout_l_T_55 = shl(_rotout_l_T_54, 1)
node _rotout_l_T_56 = not(_rotout_l_T_51)
node _rotout_l_T_57 = and(_rotout_l_T_55, _rotout_l_T_56)
node rotout_l = or(_rotout_l_T_53, _rotout_l_T_57)
node _rotout_T = bits(io.fn, 0, 0)
node _rotout_T_1 = mux(_rotout_T, rotout_r, rotout_l)
node _rotout_T_2 = bits(io.fn, 0, 0)
node _rotout_T_3 = mux(_rotout_T_2, shout_l, shout_r)
node rotout = or(_rotout_T_1, _rotout_T_3)
node _out_T = eq(UInt<1>(0h0), io.fn)
node _out_T_1 = mux(_out_T, io.adder_out, shift_logic)
node _out_T_2 = eq(UInt<4>(0ha), io.fn)
node _out_T_3 = mux(_out_T_2, io.adder_out, _out_T_1)
node _out_T_4 = eq(UInt<5>(0h10), io.fn)
node _out_T_5 = mux(_out_T_4, unary, _out_T_3)
node _out_T_6 = eq(UInt<5>(0h1c), io.fn)
node _out_T_7 = mux(_out_T_6, maxmin_out, _out_T_5)
node _out_T_8 = eq(UInt<5>(0h1d), io.fn)
node _out_T_9 = mux(_out_T_8, maxmin_out, _out_T_7)
node _out_T_10 = eq(UInt<5>(0h1e), io.fn)
node _out_T_11 = mux(_out_T_10, maxmin_out, _out_T_9)
node _out_T_12 = eq(UInt<5>(0h1f), io.fn)
node _out_T_13 = mux(_out_T_12, maxmin_out, _out_T_11)
node _out_T_14 = eq(UInt<5>(0h11), io.fn)
node _out_T_15 = mux(_out_T_14, rotout, _out_T_13)
node _out_T_16 = eq(UInt<5>(0h12), io.fn)
node out = mux(_out_T_16, rotout, _out_T_15)
connect io.out, out
node _T_1 = eq(io.dw, UInt<1>(0h0))
when _T_1 :
node _io_out_T = bits(out, 31, 31)
node _io_out_T_1 = mux(_io_out_T, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_out_T_2 = bits(out, 31, 0)
node _io_out_T_3 = cat(_io_out_T_1, _io_out_T_2)
connect io.out, _io_out_T_3 | module ALU( // @[ALU.scala:83:7]
input io_dw, // @[ALU.scala:72:14]
input [4:0] io_fn, // @[ALU.scala:72:14]
input [63:0] io_in2, // @[ALU.scala:72:14]
input [63:0] io_in1, // @[ALU.scala:72:14]
output [63:0] io_out, // @[ALU.scala:72:14]
output [63:0] io_adder_out, // @[ALU.scala:72:14]
output io_cmp_out // @[ALU.scala:72:14]
);
wire [63:0] in2_inv = {64{io_fn[3]}} ^ io_in2; // @[ALU.scala:58:29, :85:20]
wire [63:0] in1_xor_in2 = io_in1 ^ in2_inv; // @[ALU.scala:85:20, :86:28]
wire [63:0] _io_adder_out_T_3 = io_in1 + in2_inv + {63'h0, io_fn[3]}; // @[ALU.scala:58:29, :85:20, :88:{26,36}]
wire slt = io_in1[63] == io_in2[63] ? _io_adder_out_T_3[63] : io_fn[1] ? io_in2[63] : io_in1[63]; // @[ALU.scala:61:35, :88:{26,36}, :92:{8,15,24,34,56}, :93:8]
wire io_cmp_out_0 = io_fn[0] ^ (io_fn[3] ? slt : in1_xor_in2 == 64'h0); // @[ALU.scala:58:29, :62:35, :86:28, :92:8, :94:{36,41,68}]
wire [31:0] shin_hi = io_dw ? io_in1[63:32] : {32{io_fn[3] & io_in1[31]}}; // @[ALU.scala:58:29, :101:{28,46,55}, :102:{24,48}]
wire _shamt_T_2 = io_in2[5] & io_dw; // @[ALU.scala:103:{29,33}]
wire [63:0] shin_r = {shin_hi, io_in1[31:0]}; // @[ALU.scala:102:24, :104:{18,34}]
wire _shout_T = io_fn == 5'h5; // @[package.scala:16:47]
wire _shout_T_1 = io_fn == 5'hB; // @[package.scala:16:47]
wire _out_T_16 = io_fn == 5'h12; // @[package.scala:16:47]
wire _bext_mask_T_1 = io_fn == 5'h13; // @[package.scala:16:47]
wire [31:0] _GEN = {io_in1[31:16], 16'h0} | shin_hi & 32'hFFFF; // @[ALU.scala:102:24, :106:46]
wire [31:0] _GEN_0 = {{io_in1[15:0], _GEN[31:24]} & 24'hFF00FF, 8'h0} | _GEN & 32'hFF00FF; // @[ALU.scala:106:46]
wire [31:0] _GEN_1 = {{io_in1[7:0], _GEN_0[31:12]} & 28'hF0F0F0F, 4'h0} | _GEN_0 & 32'hF0F0F0F; // @[ALU.scala:106:46]
wire [45:0] _GEN_2 = {io_in1[3:0], _GEN_1, _GEN_0[7:4], _GEN[11:8], _GEN[15:14]} & 46'h333333333333; // @[ALU.scala:106:46]
wire [31:0] _GEN_3 = _GEN_2[45:14] | _GEN_1 & 32'h33333333; // @[ALU.scala:106:46]
wire [1:0] _GEN_4 = _GEN_2[11:10] | _GEN_0[5:4]; // @[ALU.scala:106:46]
wire [7:0] _GEN_5 = {_GEN_2[5:0], 2'h0} | {_GEN[15:12], shin_hi[19:16]} & 8'h33; // @[ALU.scala:102:24, :106:46]
wire [54:0] _GEN_6 = {io_in1[1:0], _GEN_3, _GEN_1[3:2], _GEN_4, _GEN_0[7:6], _GEN[9:8], _GEN_5, shin_hi[19:18], shin_hi[21:20], shin_hi[23]} & 55'h55555555555555; // @[ALU.scala:102:24, :106:46]
wire [63:0] _GEN_7 = {io_in1[0], _GEN_6[54:23] | _GEN_3 & 32'h55555555, _GEN_3[1], _GEN_6[21] | _GEN_1[2], {_GEN_1[3], 1'h0} | _GEN_4 & 2'h1, _GEN_6[18:15] | {_GEN_0[7:6], _GEN[9:8]} & 4'h5, _GEN_6[14:7] | _GEN_5 & 8'h55, _GEN_5[1], _GEN_6[5] | shin_hi[18], shin_hi[19], shin_hi[20], {_GEN_6[2:0], 1'h0} | {shin_hi[23:22], shin_hi[25:24]} & 4'h5, shin_hi[25], shin_hi[26], shin_hi[27], shin_hi[28], shin_hi[29], shin_hi[30], shin_hi[31]}; // @[ALU.scala:102:24, :106:46]
wire [63:0] shin = _shout_T | _shout_T_1 | _out_T_16 | _bext_mask_T_1 ? shin_r : _GEN_7; // @[package.scala:16:47, :81:59]
wire [64:0] _shout_r_T_5 = $signed($signed({io_fn[3] & shin[63], shin}) >>> {59'h0, _shamt_T_2, io_in2[4:0]}); // @[ALU.scala:58:29, :103:{33,60}, :106:17, :107:{21,35,41,64}]
wire [37:0] _GEN_8 = {_shout_r_T_5[11:8], _shout_r_T_5[15:12], _shout_r_T_5[19:16], _shout_r_T_5[23:20], _shout_r_T_5[27:24], _shout_r_T_5[31:28], _shout_r_T_5[35:32], _shout_r_T_5[39:36], _shout_r_T_5[43:40], _shout_r_T_5[47:46]} & 38'h3333333333; // @[ALU.scala:107:{64,73}, :108:24]
wire [7:0] _GEN_9 = _GEN_8[37:30] | {_shout_r_T_5[15:12], _shout_r_T_5[19:16]} & 8'h33; // @[ALU.scala:107:64, :108:24]
wire [1:0] _GEN_10 = _GEN_8[27:26] | _shout_r_T_5[21:20]; // @[ALU.scala:107:64, :108:24]
wire [7:0] _GEN_11 = _GEN_8[21:14] | {_shout_r_T_5[31:28], _shout_r_T_5[35:32]} & 8'h33; // @[ALU.scala:107:{64,73}, :108:24]
wire [1:0] _GEN_12 = _GEN_8[11:10] | _shout_r_T_5[37:36]; // @[ALU.scala:107:64, :108:24]
wire [7:0] _GEN_13 = {_GEN_8[5:0], 2'h0} | {_shout_r_T_5[47:44], _shout_r_T_5[51:48]} & 8'h33; // @[ALU.scala:107:64, :108:24]
wire [50:0] _GEN_14 = {_shout_r_T_5[5:4], _shout_r_T_5[7:6], _shout_r_T_5[9:8], _GEN_9, _shout_r_T_5[19:18], _GEN_10, _shout_r_T_5[23:22], _shout_r_T_5[25:24], _GEN_11, _shout_r_T_5[35:34], _GEN_12, _shout_r_T_5[39:38], _shout_r_T_5[41:40], _GEN_13, _shout_r_T_5[51:50], _shout_r_T_5[53:52], _shout_r_T_5[55]} & 51'h5555555555555; // @[ALU.scala:107:64, :108:24]
wire [63:0] _GEN_15 = {_shout_r_T_5[0], _shout_r_T_5[1], _shout_r_T_5[2], _shout_r_T_5[3], _shout_r_T_5[4], _GEN_14[50:47] | {_shout_r_T_5[7:6], _shout_r_T_5[9:8]} & 4'h5, _GEN_14[46:39] | _GEN_9 & 8'h55, _GEN_9[1], _GEN_14[37] | _shout_r_T_5[18], {_shout_r_T_5[19], 1'h0} | _GEN_10 & 2'h1, _GEN_14[34:31] | {_shout_r_T_5[23:22], _shout_r_T_5[25:24]} & 4'h5, _GEN_14[30:23] | _GEN_11 & 8'h55, _GEN_11[1], _GEN_14[21] | _shout_r_T_5[34], {_shout_r_T_5[35], 1'h0} | _GEN_12 & 2'h1, _GEN_14[18:15] | {_shout_r_T_5[39:38], _shout_r_T_5[41:40]} & 4'h5, _GEN_14[14:7] | _GEN_13 & 8'h55, _GEN_13[1], _GEN_14[5] | _shout_r_T_5[50], _shout_r_T_5[51], _shout_r_T_5[52], {_GEN_14[2:0], 1'h0} | {_shout_r_T_5[55:54], _shout_r_T_5[57:56]} & 4'h5, _shout_r_T_5[57], _shout_r_T_5[58], _shout_r_T_5[59], _shout_r_T_5[60], _shout_r_T_5[61], _shout_r_T_5[62], _shout_r_T_5[63]}; // @[ALU.scala:107:64, :108:24]
wire _logic_T_8 = io_fn == 5'h6; // @[ALU.scala:119:45]
wire _logic_T_11 = io_fn == 5'h19; // @[ALU.scala:119:64]
wire [37:0] _GEN_16 = {io_in1[11:8], io_in1[15:12], io_in1[19:16], io_in1[23:20], io_in1[27:24], io_in1[31:28], io_in1[35:32], io_in1[39:36], io_in1[43:40], io_in1[47:46]} & 38'h3333333333; // @[ALU.scala:132:19]
wire [7:0] _GEN_17 = _GEN_16[37:30] | {io_in1[15:12], io_in1[19:16]} & 8'h33; // @[ALU.scala:132:19]
wire [1:0] _GEN_18 = _GEN_16[27:26] | io_in1[21:20]; // @[ALU.scala:132:19]
wire [7:0] _GEN_19 = _GEN_16[21:14] | {io_in1[31:28], io_in1[35:32]} & 8'h33; // @[ALU.scala:132:19]
wire [1:0] _GEN_20 = _GEN_16[11:10] | io_in1[37:36]; // @[ALU.scala:132:19]
wire [7:0] _GEN_21 = {_GEN_16[5:0], 2'h0} | {io_in1[47:44], io_in1[51:48]} & 8'h33; // @[ALU.scala:132:19]
wire [50:0] _GEN_22 = {io_in1[5:4], io_in1[7:6], io_in1[9:8], _GEN_17, io_in1[19:18], _GEN_18, io_in1[23:22], io_in1[25:24], _GEN_19, io_in1[35:34], _GEN_20, io_in1[39:38], io_in1[41:40], _GEN_21, io_in1[51:50], io_in1[53:52], io_in1[55]} & 51'h5555555555555; // @[ALU.scala:132:19]
wire [3:0] _GEN_23 = {io_in1[7:6], io_in1[9:8]} & 4'h5; // @[ALU.scala:132:19]
wire [3:0] _GEN_24 = {io_in1[23:22], io_in1[25:24]} & 4'h5; // @[ALU.scala:132:19]
wire [18:0] _GEN_25 = {io_in1[5:4], io_in1[7:6], io_in1[9:8], io_in1[11:10], io_in1[13:12], io_in1[15:14], io_in1[17:16], io_in1[19:18], io_in1[21:20], io_in1[23]} & 19'h55555; // @[ALU.scala:104:34, :132:19, :134:26]
wire [3:0][63:0] _GEN_26 = {{{32'h1, io_in1[0], io_in1[1], io_in1[2], io_in1[3], io_in1[4], _GEN_25[18:15] | _GEN_23, io_in1[9], _GEN_25[13] | io_in1[10], io_in1[11], io_in1[12], _GEN_25[10:7] | {io_in1[15:14], io_in1[17:16]} & 4'h5, io_in1[17], _GEN_25[5] | io_in1[18], io_in1[19], io_in1[20], {_GEN_25[2:0], 1'h0} | _GEN_24, io_in1[25], io_in1[26], io_in1[27], io_in1[28], io_in1[29], io_in1[30], io_in1[31]}}, {{32'h1, io_in1[31:0]}}, {{io_in1[0], io_in1[1], io_in1[2], io_in1[3], io_in1[4], _GEN_22[50:47] | _GEN_23, _GEN_22[46:39] | _GEN_17 & 8'h55, _GEN_17[1], _GEN_22[37] | io_in1[18], {io_in1[19], 1'h0} | _GEN_18 & 2'h1, _GEN_22[34:31] | _GEN_24, _GEN_22[30:23] | _GEN_19 & 8'h55, _GEN_19[1], _GEN_22[21] | io_in1[34], {io_in1[35], 1'h0} | _GEN_20 & 2'h1, _GEN_22[18:15] | {io_in1[39:38], io_in1[41:40]} & 4'h5, _GEN_22[14:7] | _GEN_21 & 8'h55, _GEN_21[1], _GEN_22[5] | io_in1[50], io_in1[51], io_in1[52], {_GEN_22[2:0], 1'h0} | {io_in1[55:54], io_in1[57:56]} & 4'h5, io_in1[57], io_in1[58], io_in1[59], io_in1[60], io_in1[61], io_in1[62], io_in1[63]}}, {io_in1}}; // @[ALU.scala:104:34, :106:46, :130:62, :132:19, :134:26]
wire [63:0] tz_in = _GEN_26[{~io_dw, ~(io_in2[0])}]; // @[ALU.scala:130:{32,43,46,53,62}]
wire [63:0] _popc_in_T_137 = io_in2[1] ? (io_dw ? io_in1 : {32'h0, io_in1[31:0]}) : (tz_in[0] ? 64'h1 : tz_in[1] ? 64'h2 : tz_in[2] ? 64'h4 : tz_in[3] ? 64'h8 : tz_in[4] ? 64'h10 : tz_in[5] ? 64'h20 : tz_in[6] ? 64'h40 : tz_in[7] ? 64'h80 : tz_in[8] ? 64'h100 : tz_in[9] ? 64'h200 : tz_in[10] ? 64'h400 : tz_in[11] ? 64'h800 : tz_in[12] ? 64'h1000 : tz_in[13] ? 64'h2000 : tz_in[14] ? 64'h4000 : tz_in[15] ? 64'h8000 : tz_in[16] ? 64'h10000 : tz_in[17] ? 64'h20000 : tz_in[18] ? 64'h40000 : tz_in[19] ? 64'h80000 : tz_in[20] ? 64'h100000 : tz_in[21] ? 64'h200000 : tz_in[22] ? 64'h400000 : tz_in[23] ? 64'h800000 : tz_in[24] ? 64'h1000000 : tz_in[25] ? 64'h2000000 : tz_in[26] ? 64'h4000000 : tz_in[27] ? 64'h8000000 : tz_in[28] ? 64'h10000000 : tz_in[29] ? 64'h20000000 : tz_in[30] ? 64'h40000000 : tz_in[31] ? 64'h80000000 : tz_in[32] ? 64'h100000000 : tz_in[33] ? 64'h200000000 : tz_in[34] ? 64'h400000000 : tz_in[35] ? 64'h800000000 : tz_in[36] ? 64'h1000000000 : tz_in[37] ? 64'h2000000000 : tz_in[38] ? 64'h4000000000 : tz_in[39] ? 64'h8000000000 : tz_in[40] ? 64'h10000000000 : tz_in[41] ? 64'h20000000000 : tz_in[42] ? 64'h40000000000 : tz_in[43] ? 64'h80000000000 : tz_in[44] ? 64'h100000000000 : tz_in[45] ? 64'h200000000000 : tz_in[46] ? 64'h400000000000 : tz_in[47] ? 64'h800000000000 : tz_in[48] ? 64'h1000000000000 : tz_in[49] ? 64'h2000000000000 : tz_in[50] ? 64'h4000000000000 : tz_in[51] ? 64'h8000000000000 : tz_in[52] ? 64'h10000000000000 : tz_in[53] ? 64'h20000000000000 : tz_in[54] ? 64'h40000000000000 : tz_in[55] ? 64'h80000000000000 : tz_in[56] ? 64'h100000000000000 : tz_in[57] ? 64'h200000000000000 : tz_in[58] ? 64'h400000000000000 : tz_in[59] ? 64'h800000000000000 : tz_in[60] ? 64'h1000000000000000 : tz_in[61] ? 64'h2000000000000000 : tz_in[62] ? 64'h4000000000000000 : {tz_in[63], 63'h0}) - 64'h1; // @[OneHot.scala:85:71]
wire [63:0] rotout_r = (io_fn[0] ? shin_r : _GEN_7) >> (io_dw ? 7'h40 : 7'h20) - {1'h0, _shamt_T_2, io_in2[4:0]}; // @[ALU.scala:62:35, :103:{33,60}, :104:18, :106:46, :155:{22,54}, :156:18, :157:25]
wire [37:0] _GEN_27 = {rotout_r[11:8], rotout_r[15:12], rotout_r[19:16], rotout_r[23:20], rotout_r[27:24], rotout_r[31:28], rotout_r[35:32], rotout_r[39:36], rotout_r[43:40], rotout_r[47:46]} & 38'h3333333333; // @[ALU.scala:157:25, :158:25]
wire [7:0] _GEN_28 = _GEN_27[37:30] | {rotout_r[15:12], rotout_r[19:16]} & 8'h33; // @[ALU.scala:157:25, :158:25]
wire [1:0] _GEN_29 = _GEN_27[27:26] | rotout_r[21:20]; // @[ALU.scala:157:25, :158:25]
wire [7:0] _GEN_30 = _GEN_27[21:14] | {rotout_r[31:28], rotout_r[35:32]} & 8'h33; // @[ALU.scala:157:25, :158:25]
wire [1:0] _GEN_31 = _GEN_27[11:10] | rotout_r[37:36]; // @[ALU.scala:157:25, :158:25]
wire [7:0] _GEN_32 = {_GEN_27[5:0], 2'h0} | {rotout_r[47:44], rotout_r[51:48]} & 8'h33; // @[ALU.scala:157:25, :158:25]
wire [50:0] _GEN_33 = {rotout_r[5:4], rotout_r[7:6], rotout_r[9:8], _GEN_28, rotout_r[19:18], _GEN_29, rotout_r[23:22], rotout_r[25:24], _GEN_30, rotout_r[35:34], _GEN_31, rotout_r[39:38], rotout_r[41:40], _GEN_32, rotout_r[51:50], rotout_r[53:52], rotout_r[55]} & 51'h5555555555555; // @[ALU.scala:157:25, :158:25]
wire [63:0] _out_T_5 =
io_fn == 5'h10
? (io_in2[11:0] == 12'h605
? {{48{io_in1[15]}}, io_in1[15:0]}
: io_in2[11:0] == 12'h604
? {{56{io_in1[7]}}, io_in1[7:0]}
: io_in2[11:0] == 12'h80
? {48'h0, io_in1[15:0]}
: io_in2[11:0] == 12'h6B8
? {io_in1[7:0], io_in1[15:8], io_in1[23:16], io_in1[31:24], io_in1[39:32], io_in1[47:40], io_in1[55:48], io_in1[63:56]}
: io_in2[11:0] == 12'h287
? {{8{|(io_in1[63:56])}}, {8{|(io_in1[55:48])}}, {8{|(io_in1[47:40])}}, {8{|(io_in1[39:32])}}, {8{|(io_in1[31:24])}}, {8{|(io_in1[23:16])}}, {8{|(io_in1[15:8])}}, {8{|(io_in1[7:0])}}}
: {57'h0,
{1'h0, {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[0]} + {1'h0, _popc_in_T_137[1]}} + {1'h0, {1'h0, _popc_in_T_137[2]} + {1'h0, _popc_in_T_137[3]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[4]} + {1'h0, _popc_in_T_137[5]}} + {1'h0, {1'h0, _popc_in_T_137[6]} + {1'h0, _popc_in_T_137[7]}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[8]} + {1'h0, _popc_in_T_137[9]}} + {1'h0, {1'h0, _popc_in_T_137[10]} + {1'h0, _popc_in_T_137[11]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[12]} + {1'h0, _popc_in_T_137[13]}} + {1'h0, {1'h0, _popc_in_T_137[14]} + {1'h0, _popc_in_T_137[15]}}}}} + {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[16]} + {1'h0, _popc_in_T_137[17]}} + {1'h0, {1'h0, _popc_in_T_137[18]} + {1'h0, _popc_in_T_137[19]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[20]} + {1'h0, _popc_in_T_137[21]}} + {1'h0, {1'h0, _popc_in_T_137[22]} + {1'h0, _popc_in_T_137[23]}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[24]} + {1'h0, _popc_in_T_137[25]}} + {1'h0, {1'h0, _popc_in_T_137[26]} + {1'h0, _popc_in_T_137[27]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[28]} + {1'h0, _popc_in_T_137[29]}} + {1'h0, {1'h0, _popc_in_T_137[30]} + {1'h0, _popc_in_T_137[31]}}}}}}
+ {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[32]} + {1'h0, _popc_in_T_137[33]}} + {1'h0, {1'h0, _popc_in_T_137[34]} + {1'h0, _popc_in_T_137[35]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[36]} + {1'h0, _popc_in_T_137[37]}} + {1'h0, {1'h0, _popc_in_T_137[38]} + {1'h0, _popc_in_T_137[39]}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[40]} + {1'h0, _popc_in_T_137[41]}} + {1'h0, {1'h0, _popc_in_T_137[42]} + {1'h0, _popc_in_T_137[43]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[44]} + {1'h0, _popc_in_T_137[45]}} + {1'h0, {1'h0, _popc_in_T_137[46]} + {1'h0, _popc_in_T_137[47]}}}}} + {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[48]} + {1'h0, _popc_in_T_137[49]}} + {1'h0, {1'h0, _popc_in_T_137[50]} + {1'h0, _popc_in_T_137[51]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[52]} + {1'h0, _popc_in_T_137[53]}} + {1'h0, {1'h0, _popc_in_T_137[54]} + {1'h0, _popc_in_T_137[55]}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _popc_in_T_137[56]} + {1'h0, _popc_in_T_137[57]}} + {1'h0, {1'h0, _popc_in_T_137[58]} + {1'h0, _popc_in_T_137[59]}}} + {1'h0, {1'h0, {1'h0, _popc_in_T_137[60]} + {1'h0, _popc_in_T_137[61]}} + {1'h0, {1'h0, _popc_in_T_137[62]} + {1'h0, _popc_in_T_137[63]}}}}}}})
: io_fn == 5'hA | io_fn == 5'h0 ? _io_adder_out_T_3 : {63'h0, io_fn > 5'hB & ~(io_fn[4]) & slt} | (io_fn == 5'h4 | _logic_T_8 | _logic_T_11 | io_fn == 5'h1A ? in1_xor_in2 : 64'h0) | (_logic_T_8 | io_fn == 5'h7 | _logic_T_11 | io_fn == 5'h18 ? io_in1 & in2_inv : 64'h0) | ((_shout_T | _shout_T_1 | _bext_mask_T_1 ? _shout_r_T_5[63:0] : 64'h0) | (io_fn == 5'h1 ? _GEN_15 : 64'h0)) & (_bext_mask_T_1 ? 64'h1 : 64'hFFFFFFFFFFFFFFFF); // @[package.scala:16:47]
wire [63:0] out = _out_T_16 | io_fn == 5'h11 ? (io_fn[0] ? rotout_r : {rotout_r[0], rotout_r[1], rotout_r[2], rotout_r[3], rotout_r[4], _GEN_33[50:47] | {rotout_r[7:6], rotout_r[9:8]} & 4'h5, _GEN_33[46:39] | _GEN_28 & 8'h55, _GEN_28[1], _GEN_33[37] | rotout_r[18], {rotout_r[19], 1'h0} | _GEN_29 & 2'h1, _GEN_33[34:31] | {rotout_r[23:22], rotout_r[25:24]} & 4'h5, _GEN_33[30:23] | _GEN_30 & 8'h55, _GEN_30[1], _GEN_33[21] | rotout_r[34], {rotout_r[35], 1'h0} | _GEN_31 & 2'h1, _GEN_33[18:15] | {rotout_r[39:38], rotout_r[41:40]} & 4'h5, _GEN_33[14:7] | _GEN_32 & 8'h55, _GEN_32[1], _GEN_33[5] | rotout_r[50], rotout_r[51], rotout_r[52], {_GEN_33[2:0], 1'h0} | {rotout_r[55:54], rotout_r[57:56]} & 4'h5, rotout_r[57], rotout_r[58], rotout_r[59], rotout_r[60], rotout_r[61], rotout_r[62], rotout_r[63]}) | (io_fn[0] ? _GEN_15 : _shout_r_T_5[63:0]) : (&io_fn) | io_fn == 5'h1E | io_fn == 5'h1D | io_fn == 5'h1C ? (io_cmp_out_0 ? io_in2 : io_in1) : _out_T_5; // @[package.scala:16:47]
assign io_out = io_dw ? out : {{32{out[31]}}, out[31:0]}; // @[ALU.scala:83:7, :161:47, :175:10, :178:{28,37,43,48,56,66}]
assign io_adder_out = _io_adder_out_T_3; // @[ALU.scala:83:7, :88:{26,36}]
assign io_cmp_out = io_cmp_out_0; // @[ALU.scala:83:7, :94:36]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_2_router_15ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_62
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0
connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1
connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2
connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free
connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return
connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit
connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free
connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return
connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit
connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free
connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return
connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_2_router_15ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_62 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),
.auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),
.auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),
.auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),
.auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),
.auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),
.auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),
.auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),
.auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),
.auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),
.auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h2))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE : UInt<1>[3]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_7
node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h2))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _T_25 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_28 = cvt(_T_27)
node _T_29 = and(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = asSInt(_T_29)
node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0)))
node _T_32 = or(_T_26, _T_31)
node _T_33 = and(_T_16, _T_24)
node _T_34 = and(_T_33, _T_32)
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
node _T_37 = eq(_T_34, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_34, UInt<1>(0h1), "") : assert_1
node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_38 :
node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_41 = and(_T_39, _T_40)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_42 = shr(io.in.a.bits.source, 2)
node _T_43 = eq(_T_42, UInt<1>(0h0))
node _T_44 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_45 = and(_T_43, _T_44)
node _T_46 = leq(uncommonBits_1, UInt<2>(0h2))
node _T_47 = and(_T_45, _T_46)
node _T_48 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_49 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_50 = or(_T_47, _T_48)
node _T_51 = or(_T_50, _T_49)
node _T_52 = and(_T_41, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_56 = cvt(_T_55)
node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000)))
node _T_58 = asSInt(_T_57)
node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0)))
node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_61 = cvt(_T_60)
node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000)))
node _T_63 = asSInt(_T_62)
node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0)))
node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_59, _T_64)
node _T_96 = or(_T_95, _T_69)
node _T_97 = or(_T_96, _T_74)
node _T_98 = or(_T_97, _T_79)
node _T_99 = or(_T_98, _T_84)
node _T_100 = or(_T_99, _T_89)
node _T_101 = or(_T_100, _T_94)
node _T_102 = and(_T_54, _T_101)
node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = or(_T_109, _T_114)
node _T_116 = and(_T_104, _T_115)
node _T_117 = or(UInt<1>(0h0), _T_102)
node _T_118 = or(_T_117, _T_116)
node _T_119 = and(_T_53, _T_118)
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_119, UInt<1>(0h1), "") : assert_2
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_123 = shr(io.in.a.bits.source, 2)
node _T_124 = eq(_T_123, UInt<1>(0h0))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_2, UInt<2>(0h2))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_130 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _WIRE : UInt<1>[3]
connect _WIRE[0], _T_128
connect _WIRE[1], _T_129
connect _WIRE[2], _T_130
node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0))
node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_135 = or(_T_132, _T_133)
node _T_136 = or(_T_135, _T_134)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_136
node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_139 = and(_T_137, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_145, _T_150)
node _T_192 = or(_T_191, _T_155)
node _T_193 = or(_T_192, _T_160)
node _T_194 = or(_T_193, _T_165)
node _T_195 = or(_T_194, _T_170)
node _T_196 = or(_T_195, _T_175)
node _T_197 = or(_T_196, _T_180)
node _T_198 = or(_T_197, _T_185)
node _T_199 = or(_T_198, _T_190)
node _T_200 = and(_T_140, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = and(_WIRE_1, _T_201)
node _T_203 = asUInt(reset)
node _T_204 = eq(_T_203, UInt<1>(0h0))
when _T_204 :
node _T_205 = eq(_T_202, UInt<1>(0h0))
when _T_205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_202, UInt<1>(0h1), "") : assert_3
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(source_ok, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(_T_209, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_209, UInt<1>(0h1), "") : assert_5
node _T_213 = asUInt(reset)
node _T_214 = eq(_T_213, UInt<1>(0h0))
when _T_214 :
node _T_215 = eq(is_aligned, UInt<1>(0h0))
when _T_215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_216, UInt<1>(0h1), "") : assert_7
node _T_220 = not(io.in.a.bits.mask)
node _T_221 = eq(_T_220, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_221, UInt<1>(0h1), "") : assert_8
node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_225, UInt<1>(0h1), "") : assert_9
node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_229 :
node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_232 = and(_T_230, _T_231)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_233 = shr(io.in.a.bits.source, 2)
node _T_234 = eq(_T_233, UInt<1>(0h0))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_3, UInt<2>(0h2))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_240 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_241 = or(_T_238, _T_239)
node _T_242 = or(_T_241, _T_240)
node _T_243 = and(_T_232, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_252 = cvt(_T_251)
node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000)))
node _T_254 = asSInt(_T_253)
node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_267 = cvt(_T_266)
node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000)))
node _T_269 = asSInt(_T_268)
node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0)))
node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_277 = cvt(_T_276)
node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000)))
node _T_279 = asSInt(_T_278)
node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0)))
node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = or(_T_250, _T_255)
node _T_287 = or(_T_286, _T_260)
node _T_288 = or(_T_287, _T_265)
node _T_289 = or(_T_288, _T_270)
node _T_290 = or(_T_289, _T_275)
node _T_291 = or(_T_290, _T_280)
node _T_292 = or(_T_291, _T_285)
node _T_293 = and(_T_245, _T_292)
node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_293)
node _T_309 = or(_T_308, _T_307)
node _T_310 = and(_T_244, _T_309)
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_310, UInt<1>(0h1), "") : assert_10
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_314 = shr(io.in.a.bits.source, 2)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_317 = and(_T_315, _T_316)
node _T_318 = leq(uncommonBits_4, UInt<2>(0h2))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_321 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _WIRE_2 : UInt<1>[3]
connect _WIRE_2[0], _T_319
connect _WIRE_2[1], _T_320
connect _WIRE_2[2], _T_321
node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0))
node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_326 = or(_T_323, _T_324)
node _T_327 = or(_T_326, _T_325)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_327
node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_330 = and(_T_328, _T_329)
node _T_331 = or(UInt<1>(0h0), _T_330)
node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_353 = cvt(_T_352)
node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000)))
node _T_355 = asSInt(_T_354)
node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0)))
node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_358 = cvt(_T_357)
node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000)))
node _T_360 = asSInt(_T_359)
node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0)))
node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_368 = cvt(_T_367)
node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000)))
node _T_370 = asSInt(_T_369)
node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0)))
node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = or(_T_336, _T_341)
node _T_383 = or(_T_382, _T_346)
node _T_384 = or(_T_383, _T_351)
node _T_385 = or(_T_384, _T_356)
node _T_386 = or(_T_385, _T_361)
node _T_387 = or(_T_386, _T_366)
node _T_388 = or(_T_387, _T_371)
node _T_389 = or(_T_388, _T_376)
node _T_390 = or(_T_389, _T_381)
node _T_391 = and(_T_331, _T_390)
node _T_392 = or(UInt<1>(0h0), _T_391)
node _T_393 = and(_WIRE_3, _T_392)
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_393, UInt<1>(0h1), "") : assert_11
node _T_397 = asUInt(reset)
node _T_398 = eq(_T_397, UInt<1>(0h0))
when _T_398 :
node _T_399 = eq(source_ok, UInt<1>(0h0))
when _T_399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_401 = asUInt(reset)
node _T_402 = eq(_T_401, UInt<1>(0h0))
when _T_402 :
node _T_403 = eq(_T_400, UInt<1>(0h0))
when _T_403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_400, UInt<1>(0h1), "") : assert_13
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(is_aligned, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_407, UInt<1>(0h1), "") : assert_15
node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_411, UInt<1>(0h1), "") : assert_16
node _T_415 = not(io.in.a.bits.mask)
node _T_416 = eq(_T_415, UInt<1>(0h0))
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_416, UInt<1>(0h1), "") : assert_17
node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_T_420, UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_420, UInt<1>(0h1), "") : assert_18
node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_424 :
node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_427 = and(_T_425, _T_426)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_428 = shr(io.in.a.bits.source, 2)
node _T_429 = eq(_T_428, UInt<1>(0h0))
node _T_430 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_431 = and(_T_429, _T_430)
node _T_432 = leq(uncommonBits_5, UInt<2>(0h2))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_435 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_436 = or(_T_433, _T_434)
node _T_437 = or(_T_436, _T_435)
node _T_438 = and(_T_427, _T_437)
node _T_439 = or(UInt<1>(0h0), _T_438)
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_439, UInt<1>(0h1), "") : assert_19
node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_445 = and(_T_443, _T_444)
node _T_446 = or(UInt<1>(0h0), _T_445)
node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = and(_T_446, _T_451)
node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_455 = and(_T_453, _T_454)
node _T_456 = or(UInt<1>(0h0), _T_455)
node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = or(_T_461, _T_466)
node _T_503 = or(_T_502, _T_471)
node _T_504 = or(_T_503, _T_476)
node _T_505 = or(_T_504, _T_481)
node _T_506 = or(_T_505, _T_486)
node _T_507 = or(_T_506, _T_491)
node _T_508 = or(_T_507, _T_496)
node _T_509 = or(_T_508, _T_501)
node _T_510 = and(_T_456, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_452)
node _T_512 = or(_T_511, _T_510)
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(_T_512, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_512, UInt<1>(0h1), "") : assert_20
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(source_ok, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(is_aligned, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_522, UInt<1>(0h1), "") : assert_23
node _T_526 = eq(io.in.a.bits.mask, mask)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_526, UInt<1>(0h1), "") : assert_24
node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_530, UInt<1>(0h1), "") : assert_25
node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_534 :
node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_537 = and(_T_535, _T_536)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_538 = shr(io.in.a.bits.source, 2)
node _T_539 = eq(_T_538, UInt<1>(0h0))
node _T_540 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_541 = and(_T_539, _T_540)
node _T_542 = leq(uncommonBits_6, UInt<2>(0h2))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_545 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_546 = or(_T_543, _T_544)
node _T_547 = or(_T_546, _T_545)
node _T_548 = and(_T_537, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_552 = and(_T_550, _T_551)
node _T_553 = or(UInt<1>(0h0), _T_552)
node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = and(_T_553, _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = or(_T_568, _T_573)
node _T_605 = or(_T_604, _T_578)
node _T_606 = or(_T_605, _T_583)
node _T_607 = or(_T_606, _T_588)
node _T_608 = or(_T_607, _T_593)
node _T_609 = or(_T_608, _T_598)
node _T_610 = or(_T_609, _T_603)
node _T_611 = and(_T_563, _T_610)
node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = and(_T_612, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_559)
node _T_620 = or(_T_619, _T_611)
node _T_621 = or(_T_620, _T_618)
node _T_622 = and(_T_549, _T_621)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_622, UInt<1>(0h1), "") : assert_26
node _T_626 = asUInt(reset)
node _T_627 = eq(_T_626, UInt<1>(0h0))
when _T_627 :
node _T_628 = eq(source_ok, UInt<1>(0h0))
when _T_628 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(is_aligned, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_632, UInt<1>(0h1), "") : assert_29
node _T_636 = eq(io.in.a.bits.mask, mask)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_636, UInt<1>(0h1), "") : assert_30
node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_640 :
node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_643 = and(_T_641, _T_642)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_644 = shr(io.in.a.bits.source, 2)
node _T_645 = eq(_T_644, UInt<1>(0h0))
node _T_646 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_647 = and(_T_645, _T_646)
node _T_648 = leq(uncommonBits_7, UInt<2>(0h2))
node _T_649 = and(_T_647, _T_648)
node _T_650 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_651 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_652 = or(_T_649, _T_650)
node _T_653 = or(_T_652, _T_651)
node _T_654 = and(_T_643, _T_653)
node _T_655 = or(UInt<1>(0h0), _T_654)
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_658)
node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = and(_T_659, _T_664)
node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_668 = and(_T_666, _T_667)
node _T_669 = or(UInt<1>(0h0), _T_668)
node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_671 = cvt(_T_670)
node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000)))
node _T_673 = asSInt(_T_672)
node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0)))
node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_676 = cvt(_T_675)
node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000)))
node _T_678 = asSInt(_T_677)
node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0)))
node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_681 = cvt(_T_680)
node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000)))
node _T_683 = asSInt(_T_682)
node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0)))
node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_686 = cvt(_T_685)
node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000)))
node _T_688 = asSInt(_T_687)
node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0)))
node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_691 = cvt(_T_690)
node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000)))
node _T_693 = asSInt(_T_692)
node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0)))
node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_696 = cvt(_T_695)
node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000)))
node _T_698 = asSInt(_T_697)
node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0)))
node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_701 = cvt(_T_700)
node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000)))
node _T_703 = asSInt(_T_702)
node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0)))
node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = or(_T_674, _T_679)
node _T_711 = or(_T_710, _T_684)
node _T_712 = or(_T_711, _T_689)
node _T_713 = or(_T_712, _T_694)
node _T_714 = or(_T_713, _T_699)
node _T_715 = or(_T_714, _T_704)
node _T_716 = or(_T_715, _T_709)
node _T_717 = and(_T_669, _T_716)
node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_720 = cvt(_T_719)
node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000)))
node _T_722 = asSInt(_T_721)
node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0)))
node _T_724 = and(_T_718, _T_723)
node _T_725 = or(UInt<1>(0h0), _T_665)
node _T_726 = or(_T_725, _T_717)
node _T_727 = or(_T_726, _T_724)
node _T_728 = and(_T_655, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_728, UInt<1>(0h1), "") : assert_31
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(source_ok, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(is_aligned, UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(_T_738, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_738, UInt<1>(0h1), "") : assert_34
node _T_742 = not(mask)
node _T_743 = and(io.in.a.bits.mask, _T_742)
node _T_744 = eq(_T_743, UInt<1>(0h0))
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(_T_744, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_744, UInt<1>(0h1), "") : assert_35
node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_748 :
node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<1>(0h0))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_8, UInt<2>(0h2))
node _T_757 = and(_T_755, _T_756)
node _T_758 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_759 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_760 = or(_T_757, _T_758)
node _T_761 = or(_T_760, _T_759)
node _T_762 = and(_T_751, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_762)
node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_766 = and(_T_764, _T_765)
node _T_767 = or(UInt<1>(0h0), _T_766)
node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_769 = cvt(_T_768)
node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000)))
node _T_771 = asSInt(_T_770)
node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0)))
node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_774 = cvt(_T_773)
node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000)))
node _T_776 = asSInt(_T_775)
node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0)))
node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_784 = cvt(_T_783)
node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000)))
node _T_786 = asSInt(_T_785)
node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0)))
node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_789 = cvt(_T_788)
node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000)))
node _T_791 = asSInt(_T_790)
node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0)))
node _T_793 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_794 = cvt(_T_793)
node _T_795 = and(_T_794, asSInt(UInt<17>(0h10000)))
node _T_796 = asSInt(_T_795)
node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0)))
node _T_798 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_799 = cvt(_T_798)
node _T_800 = and(_T_799, asSInt(UInt<27>(0h4000000)))
node _T_801 = asSInt(_T_800)
node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0)))
node _T_803 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_809 = cvt(_T_808)
node _T_810 = and(_T_809, asSInt(UInt<29>(0h10000000)))
node _T_811 = asSInt(_T_810)
node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0)))
node _T_813 = or(_T_772, _T_777)
node _T_814 = or(_T_813, _T_782)
node _T_815 = or(_T_814, _T_787)
node _T_816 = or(_T_815, _T_792)
node _T_817 = or(_T_816, _T_797)
node _T_818 = or(_T_817, _T_802)
node _T_819 = or(_T_818, _T_807)
node _T_820 = or(_T_819, _T_812)
node _T_821 = and(_T_767, _T_820)
node _T_822 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_823 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_824 = cvt(_T_823)
node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000)))
node _T_826 = asSInt(_T_825)
node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0)))
node _T_828 = and(_T_822, _T_827)
node _T_829 = or(UInt<1>(0h0), _T_821)
node _T_830 = or(_T_829, _T_828)
node _T_831 = and(_T_763, _T_830)
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_T_831, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_831, UInt<1>(0h1), "") : assert_36
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(source_ok, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_838 = asUInt(reset)
node _T_839 = eq(_T_838, UInt<1>(0h0))
when _T_839 :
node _T_840 = eq(is_aligned, UInt<1>(0h0))
when _T_840 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_841 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_841, UInt<1>(0h1), "") : assert_39
node _T_845 = eq(io.in.a.bits.mask, mask)
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_845, UInt<1>(0h1), "") : assert_40
node _T_849 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_849 :
node _T_850 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_851 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_852 = and(_T_850, _T_851)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_853 = shr(io.in.a.bits.source, 2)
node _T_854 = eq(_T_853, UInt<1>(0h0))
node _T_855 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_856 = and(_T_854, _T_855)
node _T_857 = leq(uncommonBits_9, UInt<2>(0h2))
node _T_858 = and(_T_856, _T_857)
node _T_859 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_860 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_861 = or(_T_858, _T_859)
node _T_862 = or(_T_861, _T_860)
node _T_863 = and(_T_852, _T_862)
node _T_864 = or(UInt<1>(0h0), _T_863)
node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_866 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_867 = and(_T_865, _T_866)
node _T_868 = or(UInt<1>(0h0), _T_867)
node _T_869 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<14>(0h2000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<18>(0h2f000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = or(_T_873, _T_878)
node _T_915 = or(_T_914, _T_883)
node _T_916 = or(_T_915, _T_888)
node _T_917 = or(_T_916, _T_893)
node _T_918 = or(_T_917, _T_898)
node _T_919 = or(_T_918, _T_903)
node _T_920 = or(_T_919, _T_908)
node _T_921 = or(_T_920, _T_913)
node _T_922 = and(_T_868, _T_921)
node _T_923 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = and(_T_923, _T_928)
node _T_930 = or(UInt<1>(0h0), _T_922)
node _T_931 = or(_T_930, _T_929)
node _T_932 = and(_T_864, _T_931)
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(_T_932, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_932, UInt<1>(0h1), "") : assert_41
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(source_ok, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(is_aligned, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_942, UInt<1>(0h1), "") : assert_44
node _T_946 = eq(io.in.a.bits.mask, mask)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_946, UInt<1>(0h1), "") : assert_45
node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_950 :
node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_953 = and(_T_951, _T_952)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_954 = shr(io.in.a.bits.source, 2)
node _T_955 = eq(_T_954, UInt<1>(0h0))
node _T_956 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_957 = and(_T_955, _T_956)
node _T_958 = leq(uncommonBits_10, UInt<2>(0h2))
node _T_959 = and(_T_957, _T_958)
node _T_960 = eq(io.in.a.bits.source, UInt<2>(0h3))
node _T_961 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_962 = or(_T_959, _T_960)
node _T_963 = or(_T_962, _T_961)
node _T_964 = and(_T_953, _T_963)
node _T_965 = or(UInt<1>(0h0), _T_964)
node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_968 = and(_T_966, _T_967)
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_971 = cvt(_T_970)
node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000)))
node _T_973 = asSInt(_T_972)
node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0)))
node _T_975 = and(_T_969, _T_974)
node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_977 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_978 = cvt(_T_977)
node _T_979 = and(_T_978, asSInt(UInt<14>(0h2000)))
node _T_980 = asSInt(_T_979)
node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0)))
node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_988 = cvt(_T_987)
node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000)))
node _T_990 = asSInt(_T_989)
node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0)))
node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = or(_T_981, _T_986)
node _T_1013 = or(_T_1012, _T_991)
node _T_1014 = or(_T_1013, _T_996)
node _T_1015 = or(_T_1014, _T_1001)
node _T_1016 = or(_T_1015, _T_1006)
node _T_1017 = or(_T_1016, _T_1011)
node _T_1018 = and(_T_976, _T_1017)
node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1020 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1021 = and(_T_1019, _T_1020)
node _T_1022 = or(UInt<1>(0h0), _T_1021)
node _T_1023 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1024 = cvt(_T_1023)
node _T_1025 = and(_T_1024, asSInt(UInt<17>(0h10000)))
node _T_1026 = asSInt(_T_1025)
node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0)))
node _T_1028 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1029 = cvt(_T_1028)
node _T_1030 = and(_T_1029, asSInt(UInt<29>(0h10000000)))
node _T_1031 = asSInt(_T_1030)
node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0)))
node _T_1033 = or(_T_1027, _T_1032)
node _T_1034 = and(_T_1022, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_975)
node _T_1036 = or(_T_1035, _T_1018)
node _T_1037 = or(_T_1036, _T_1034)
node _T_1038 = and(_T_965, _T_1037)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_46
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(source_ok, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(is_aligned, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1048 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_49
node _T_1052 = eq(io.in.a.bits.mask, mask)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_50
node _T_1056 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1060 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_9 = shr(io.in.d.bits.source, 2)
node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0))
node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<2>(0h2))
node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13)
node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<2>(0h3))
node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE_1 : UInt<1>[3]
connect _source_ok_WIRE_1[0], _source_ok_T_14
connect _source_ok_WIRE_1[1], _source_ok_T_15
connect _source_ok_WIRE_1[2], _source_ok_T_16
node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1064 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1064 :
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(source_ok_1, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1068 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_54
node _T_1072 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_55
node _T_1076 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_56
node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_57
node _T_1084 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1084 :
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(source_ok_1, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(sink_ok, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1091 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1092 = asUInt(reset)
node _T_1093 = eq(_T_1092, UInt<1>(0h0))
when _T_1093 :
node _T_1094 = eq(_T_1091, UInt<1>(0h0))
when _T_1094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1091, UInt<1>(0h1), "") : assert_60
node _T_1095 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1096 = asUInt(reset)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(_T_1095, UInt<1>(0h0))
when _T_1098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1095, UInt<1>(0h1), "") : assert_61
node _T_1099 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_62
node _T_1103 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_63
node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1108 = or(UInt<1>(0h1), _T_1107)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_64
node _T_1112 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1112 :
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok_1, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(sink_ok, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_67
node _T_1123 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_68
node _T_1127 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_69
node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1132 = or(_T_1131, io.in.d.bits.corrupt)
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_70
node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1137 = or(UInt<1>(0h1), _T_1136)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_71
node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(source_ok_1, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_73
node _T_1149 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_74
node _T_1153 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1154 = or(UInt<1>(0h1), _T_1153)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_75
node _T_1158 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1158 :
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(source_ok_1, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1162 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_77
node _T_1166 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1167 = or(_T_1166, io.in.d.bits.corrupt)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_78
node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1172 = or(UInt<1>(0h1), _T_1171)
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_79
node _T_1176 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1176 :
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(source_ok_1, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1180 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_81
node _T_1184 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_82
node _T_1188 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1189 = or(UInt<1>(0h1), _T_1188)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1193 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1194 = asUInt(reset)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
when _T_1195 :
node _T_1196 = eq(_T_1193, UInt<1>(0h0))
when _T_1196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1193, UInt<1>(0h1), "") : assert_84
node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_1197 = shr(io.in.b.bits.source, 2)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_1200 = and(_T_1198, _T_1199)
node _T_1201 = leq(uncommonBits_11, UInt<2>(0h2))
node _T_1202 = and(_T_1200, _T_1201)
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
node _T_1204 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1205 = cvt(_T_1204)
node _T_1206 = and(_T_1205, asSInt(UInt<1>(0h0)))
node _T_1207 = asSInt(_T_1206)
node _T_1208 = eq(_T_1207, asSInt(UInt<1>(0h0)))
node _T_1209 = or(_T_1203, _T_1208)
node _T_1210 = eq(io.in.b.bits.source, UInt<2>(0h3))
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
node _T_1212 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1213 = cvt(_T_1212)
node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = asSInt(_T_1214)
node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0)))
node _T_1217 = or(_T_1211, _T_1216)
node _T_1218 = eq(io.in.b.bits.source, UInt<3>(0h4))
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
node _T_1220 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1221 = cvt(_T_1220)
node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0)))
node _T_1223 = asSInt(_T_1222)
node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0)))
node _T_1225 = or(_T_1219, _T_1224)
node _T_1226 = and(_T_1209, _T_1217)
node _T_1227 = and(_T_1226, _T_1225)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T = shr(io.in.b.bits.source, 2)
node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0))
node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2)
node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<2>(0h2))
node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4)
node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h3))
node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<3>(0h4))
wire _legal_source_WIRE : UInt<1>[3]
connect _legal_source_WIRE[0], _legal_source_T_5
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_7
node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<2>(0h3), UInt<1>(0h0))
node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10)
wire _legal_source_WIRE_1 : UInt<3>
connect _legal_source_WIRE_1, _legal_source_T_12
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1231 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1231 :
node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_1232 = shr(io.in.b.bits.source, 2)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
node _T_1234 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_1235 = and(_T_1233, _T_1234)
node _T_1236 = leq(uncommonBits_12, UInt<2>(0h2))
node _T_1237 = and(_T_1235, _T_1236)
node _T_1238 = eq(io.in.b.bits.source, UInt<2>(0h3))
node _T_1239 = eq(io.in.b.bits.source, UInt<3>(0h4))
wire _WIRE_4 : UInt<1>[3]
connect _WIRE_4[0], _T_1237
connect _WIRE_4[1], _T_1238
connect _WIRE_4[2], _T_1239
node _T_1240 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1241 = mux(_WIRE_4[0], _T_1240, UInt<1>(0h0))
node _T_1242 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1243 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1244 = or(_T_1241, _T_1242)
node _T_1245 = or(_T_1244, _T_1243)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1245
node _T_1246 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1247 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1248 = and(_T_1246, _T_1247)
node _T_1249 = or(UInt<1>(0h0), _T_1248)
node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1251 = cvt(_T_1250)
node _T_1252 = and(_T_1251, asSInt(UInt<14>(0h2000)))
node _T_1253 = asSInt(_T_1252)
node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0)))
node _T_1255 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1256 = cvt(_T_1255)
node _T_1257 = and(_T_1256, asSInt(UInt<13>(0h1000)))
node _T_1258 = asSInt(_T_1257)
node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0)))
node _T_1260 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1261 = cvt(_T_1260)
node _T_1262 = and(_T_1261, asSInt(UInt<17>(0h10000)))
node _T_1263 = asSInt(_T_1262)
node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0)))
node _T_1265 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1266 = cvt(_T_1265)
node _T_1267 = and(_T_1266, asSInt(UInt<18>(0h2f000)))
node _T_1268 = asSInt(_T_1267)
node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0)))
node _T_1270 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1271 = cvt(_T_1270)
node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000)))
node _T_1273 = asSInt(_T_1272)
node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0)))
node _T_1275 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1276 = cvt(_T_1275)
node _T_1277 = and(_T_1276, asSInt(UInt<13>(0h1000)))
node _T_1278 = asSInt(_T_1277)
node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0)))
node _T_1280 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1281 = cvt(_T_1280)
node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000)))
node _T_1283 = asSInt(_T_1282)
node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0)))
node _T_1285 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1286 = cvt(_T_1285)
node _T_1287 = and(_T_1286, asSInt(UInt<27>(0h4000000)))
node _T_1288 = asSInt(_T_1287)
node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0)))
node _T_1290 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1291 = cvt(_T_1290)
node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000)))
node _T_1293 = asSInt(_T_1292)
node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0)))
node _T_1295 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1296 = cvt(_T_1295)
node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000)))
node _T_1298 = asSInt(_T_1297)
node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0)))
node _T_1300 = or(_T_1254, _T_1259)
node _T_1301 = or(_T_1300, _T_1264)
node _T_1302 = or(_T_1301, _T_1269)
node _T_1303 = or(_T_1302, _T_1274)
node _T_1304 = or(_T_1303, _T_1279)
node _T_1305 = or(_T_1304, _T_1284)
node _T_1306 = or(_T_1305, _T_1289)
node _T_1307 = or(_T_1306, _T_1294)
node _T_1308 = or(_T_1307, _T_1299)
node _T_1309 = and(_T_1249, _T_1308)
node _T_1310 = or(UInt<1>(0h0), _T_1309)
node _T_1311 = and(_WIRE_5, _T_1310)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_86
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(address_ok, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1318 = asUInt(reset)
node _T_1319 = eq(_T_1318, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = eq(legal_source, UInt<1>(0h0))
when _T_1320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1324 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_90
node _T_1328 = eq(io.in.b.bits.mask, mask_1)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_91
node _T_1332 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92
node _T_1336 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1336 :
node _T_1337 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1338 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1339 = and(_T_1337, _T_1338)
node _T_1340 = or(UInt<1>(0h0), _T_1339)
node _T_1341 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1342 = cvt(_T_1341)
node _T_1343 = and(_T_1342, asSInt(UInt<14>(0h2000)))
node _T_1344 = asSInt(_T_1343)
node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0)))
node _T_1346 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1347 = cvt(_T_1346)
node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000)))
node _T_1349 = asSInt(_T_1348)
node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0)))
node _T_1351 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1352 = cvt(_T_1351)
node _T_1353 = and(_T_1352, asSInt(UInt<17>(0h10000)))
node _T_1354 = asSInt(_T_1353)
node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0)))
node _T_1356 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1357 = cvt(_T_1356)
node _T_1358 = and(_T_1357, asSInt(UInt<18>(0h2f000)))
node _T_1359 = asSInt(_T_1358)
node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0)))
node _T_1361 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1362 = cvt(_T_1361)
node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000)))
node _T_1364 = asSInt(_T_1363)
node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0)))
node _T_1366 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1367 = cvt(_T_1366)
node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000)))
node _T_1369 = asSInt(_T_1368)
node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0)))
node _T_1371 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1372 = cvt(_T_1371)
node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000)))
node _T_1374 = asSInt(_T_1373)
node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0)))
node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1377 = cvt(_T_1376)
node _T_1378 = and(_T_1377, asSInt(UInt<27>(0h4000000)))
node _T_1379 = asSInt(_T_1378)
node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0)))
node _T_1381 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1382 = cvt(_T_1381)
node _T_1383 = and(_T_1382, asSInt(UInt<13>(0h1000)))
node _T_1384 = asSInt(_T_1383)
node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0)))
node _T_1386 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<29>(0h10000000)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = or(_T_1345, _T_1350)
node _T_1392 = or(_T_1391, _T_1355)
node _T_1393 = or(_T_1392, _T_1360)
node _T_1394 = or(_T_1393, _T_1365)
node _T_1395 = or(_T_1394, _T_1370)
node _T_1396 = or(_T_1395, _T_1375)
node _T_1397 = or(_T_1396, _T_1380)
node _T_1398 = or(_T_1397, _T_1385)
node _T_1399 = or(_T_1398, _T_1390)
node _T_1400 = and(_T_1340, _T_1399)
node _T_1401 = or(UInt<1>(0h0), _T_1400)
node _T_1402 = and(UInt<1>(0h0), _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93
node _T_1406 = asUInt(reset)
node _T_1407 = eq(_T_1406, UInt<1>(0h0))
when _T_1407 :
node _T_1408 = eq(address_ok, UInt<1>(0h0))
when _T_1408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(legal_source, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1412 = asUInt(reset)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
when _T_1413 :
node _T_1414 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1415 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1416 = asUInt(reset)
node _T_1417 = eq(_T_1416, UInt<1>(0h0))
when _T_1417 :
node _T_1418 = eq(_T_1415, UInt<1>(0h0))
when _T_1418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1415, UInt<1>(0h1), "") : assert_97
node _T_1419 = eq(io.in.b.bits.mask, mask_1)
node _T_1420 = asUInt(reset)
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
when _T_1421 :
node _T_1422 = eq(_T_1419, UInt<1>(0h0))
when _T_1422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1419, UInt<1>(0h1), "") : assert_98
node _T_1423 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1424 = asUInt(reset)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
when _T_1425 :
node _T_1426 = eq(_T_1423, UInt<1>(0h0))
when _T_1426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1423, UInt<1>(0h1), "") : assert_99
node _T_1427 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1429 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1430 = and(_T_1428, _T_1429)
node _T_1431 = or(UInt<1>(0h0), _T_1430)
node _T_1432 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1433 = cvt(_T_1432)
node _T_1434 = and(_T_1433, asSInt(UInt<14>(0h2000)))
node _T_1435 = asSInt(_T_1434)
node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0)))
node _T_1437 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1438 = cvt(_T_1437)
node _T_1439 = and(_T_1438, asSInt(UInt<13>(0h1000)))
node _T_1440 = asSInt(_T_1439)
node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0)))
node _T_1442 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1443 = cvt(_T_1442)
node _T_1444 = and(_T_1443, asSInt(UInt<17>(0h10000)))
node _T_1445 = asSInt(_T_1444)
node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0)))
node _T_1447 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1448 = cvt(_T_1447)
node _T_1449 = and(_T_1448, asSInt(UInt<18>(0h2f000)))
node _T_1450 = asSInt(_T_1449)
node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0)))
node _T_1452 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1453 = cvt(_T_1452)
node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000)))
node _T_1455 = asSInt(_T_1454)
node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0)))
node _T_1457 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1458 = cvt(_T_1457)
node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000)))
node _T_1460 = asSInt(_T_1459)
node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0)))
node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1463 = cvt(_T_1462)
node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000)))
node _T_1465 = asSInt(_T_1464)
node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0)))
node _T_1467 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1468 = cvt(_T_1467)
node _T_1469 = and(_T_1468, asSInt(UInt<27>(0h4000000)))
node _T_1470 = asSInt(_T_1469)
node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0)))
node _T_1472 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1473 = cvt(_T_1472)
node _T_1474 = and(_T_1473, asSInt(UInt<13>(0h1000)))
node _T_1475 = asSInt(_T_1474)
node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0)))
node _T_1477 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1478 = cvt(_T_1477)
node _T_1479 = and(_T_1478, asSInt(UInt<29>(0h10000000)))
node _T_1480 = asSInt(_T_1479)
node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0)))
node _T_1482 = or(_T_1436, _T_1441)
node _T_1483 = or(_T_1482, _T_1446)
node _T_1484 = or(_T_1483, _T_1451)
node _T_1485 = or(_T_1484, _T_1456)
node _T_1486 = or(_T_1485, _T_1461)
node _T_1487 = or(_T_1486, _T_1466)
node _T_1488 = or(_T_1487, _T_1471)
node _T_1489 = or(_T_1488, _T_1476)
node _T_1490 = or(_T_1489, _T_1481)
node _T_1491 = and(_T_1431, _T_1490)
node _T_1492 = or(UInt<1>(0h0), _T_1491)
node _T_1493 = and(UInt<1>(0h0), _T_1492)
node _T_1494 = asUInt(reset)
node _T_1495 = eq(_T_1494, UInt<1>(0h0))
when _T_1495 :
node _T_1496 = eq(_T_1493, UInt<1>(0h0))
when _T_1496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1493, UInt<1>(0h1), "") : assert_100
node _T_1497 = asUInt(reset)
node _T_1498 = eq(_T_1497, UInt<1>(0h0))
when _T_1498 :
node _T_1499 = eq(address_ok, UInt<1>(0h0))
when _T_1499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(legal_source, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1503 = asUInt(reset)
node _T_1504 = eq(_T_1503, UInt<1>(0h0))
when _T_1504 :
node _T_1505 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1506 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1507 = asUInt(reset)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
when _T_1508 :
node _T_1509 = eq(_T_1506, UInt<1>(0h0))
when _T_1509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1506, UInt<1>(0h1), "") : assert_104
node _T_1510 = eq(io.in.b.bits.mask, mask_1)
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_105
node _T_1514 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1514 :
node _T_1515 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1516 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1517 = and(_T_1515, _T_1516)
node _T_1518 = or(UInt<1>(0h0), _T_1517)
node _T_1519 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1520 = cvt(_T_1519)
node _T_1521 = and(_T_1520, asSInt(UInt<14>(0h2000)))
node _T_1522 = asSInt(_T_1521)
node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0)))
node _T_1524 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1525 = cvt(_T_1524)
node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000)))
node _T_1527 = asSInt(_T_1526)
node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0)))
node _T_1529 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1530 = cvt(_T_1529)
node _T_1531 = and(_T_1530, asSInt(UInt<17>(0h10000)))
node _T_1532 = asSInt(_T_1531)
node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0)))
node _T_1534 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1535 = cvt(_T_1534)
node _T_1536 = and(_T_1535, asSInt(UInt<18>(0h2f000)))
node _T_1537 = asSInt(_T_1536)
node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0)))
node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1540 = cvt(_T_1539)
node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000)))
node _T_1542 = asSInt(_T_1541)
node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0)))
node _T_1544 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1545 = cvt(_T_1544)
node _T_1546 = and(_T_1545, asSInt(UInt<13>(0h1000)))
node _T_1547 = asSInt(_T_1546)
node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0)))
node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1550 = cvt(_T_1549)
node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000)))
node _T_1552 = asSInt(_T_1551)
node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0)))
node _T_1554 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1555 = cvt(_T_1554)
node _T_1556 = and(_T_1555, asSInt(UInt<27>(0h4000000)))
node _T_1557 = asSInt(_T_1556)
node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0)))
node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1560 = cvt(_T_1559)
node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000)))
node _T_1562 = asSInt(_T_1561)
node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0)))
node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1565 = cvt(_T_1564)
node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000)))
node _T_1567 = asSInt(_T_1566)
node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0)))
node _T_1569 = or(_T_1523, _T_1528)
node _T_1570 = or(_T_1569, _T_1533)
node _T_1571 = or(_T_1570, _T_1538)
node _T_1572 = or(_T_1571, _T_1543)
node _T_1573 = or(_T_1572, _T_1548)
node _T_1574 = or(_T_1573, _T_1553)
node _T_1575 = or(_T_1574, _T_1558)
node _T_1576 = or(_T_1575, _T_1563)
node _T_1577 = or(_T_1576, _T_1568)
node _T_1578 = and(_T_1518, _T_1577)
node _T_1579 = or(UInt<1>(0h0), _T_1578)
node _T_1580 = and(UInt<1>(0h0), _T_1579)
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_106
node _T_1584 = asUInt(reset)
node _T_1585 = eq(_T_1584, UInt<1>(0h0))
when _T_1585 :
node _T_1586 = eq(address_ok, UInt<1>(0h0))
when _T_1586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1587 = asUInt(reset)
node _T_1588 = eq(_T_1587, UInt<1>(0h0))
when _T_1588 :
node _T_1589 = eq(legal_source, UInt<1>(0h0))
when _T_1589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1593 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_110
node _T_1597 = not(mask_1)
node _T_1598 = and(io.in.b.bits.mask, _T_1597)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_111
node _T_1603 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1603 :
node _T_1604 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1605 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1606 = and(_T_1604, _T_1605)
node _T_1607 = or(UInt<1>(0h0), _T_1606)
node _T_1608 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1609 = cvt(_T_1608)
node _T_1610 = and(_T_1609, asSInt(UInt<14>(0h2000)))
node _T_1611 = asSInt(_T_1610)
node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0)))
node _T_1613 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1614 = cvt(_T_1613)
node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000)))
node _T_1616 = asSInt(_T_1615)
node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0)))
node _T_1618 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1619 = cvt(_T_1618)
node _T_1620 = and(_T_1619, asSInt(UInt<17>(0h10000)))
node _T_1621 = asSInt(_T_1620)
node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0)))
node _T_1623 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1624 = cvt(_T_1623)
node _T_1625 = and(_T_1624, asSInt(UInt<18>(0h2f000)))
node _T_1626 = asSInt(_T_1625)
node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0)))
node _T_1628 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1629 = cvt(_T_1628)
node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000)))
node _T_1631 = asSInt(_T_1630)
node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0)))
node _T_1633 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1634 = cvt(_T_1633)
node _T_1635 = and(_T_1634, asSInt(UInt<13>(0h1000)))
node _T_1636 = asSInt(_T_1635)
node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0)))
node _T_1638 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1639 = cvt(_T_1638)
node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000)))
node _T_1641 = asSInt(_T_1640)
node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0)))
node _T_1643 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1644 = cvt(_T_1643)
node _T_1645 = and(_T_1644, asSInt(UInt<27>(0h4000000)))
node _T_1646 = asSInt(_T_1645)
node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0)))
node _T_1648 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1649 = cvt(_T_1648)
node _T_1650 = and(_T_1649, asSInt(UInt<13>(0h1000)))
node _T_1651 = asSInt(_T_1650)
node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0)))
node _T_1653 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1654 = cvt(_T_1653)
node _T_1655 = and(_T_1654, asSInt(UInt<29>(0h10000000)))
node _T_1656 = asSInt(_T_1655)
node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0)))
node _T_1658 = or(_T_1612, _T_1617)
node _T_1659 = or(_T_1658, _T_1622)
node _T_1660 = or(_T_1659, _T_1627)
node _T_1661 = or(_T_1660, _T_1632)
node _T_1662 = or(_T_1661, _T_1637)
node _T_1663 = or(_T_1662, _T_1642)
node _T_1664 = or(_T_1663, _T_1647)
node _T_1665 = or(_T_1664, _T_1652)
node _T_1666 = or(_T_1665, _T_1657)
node _T_1667 = and(_T_1607, _T_1666)
node _T_1668 = or(UInt<1>(0h0), _T_1667)
node _T_1669 = and(UInt<1>(0h0), _T_1668)
node _T_1670 = asUInt(reset)
node _T_1671 = eq(_T_1670, UInt<1>(0h0))
when _T_1671 :
node _T_1672 = eq(_T_1669, UInt<1>(0h0))
when _T_1672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1669, UInt<1>(0h1), "") : assert_112
node _T_1673 = asUInt(reset)
node _T_1674 = eq(_T_1673, UInt<1>(0h0))
when _T_1674 :
node _T_1675 = eq(address_ok, UInt<1>(0h0))
when _T_1675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(legal_source, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1679 = asUInt(reset)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
when _T_1680 :
node _T_1681 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1682 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1683 = asUInt(reset)
node _T_1684 = eq(_T_1683, UInt<1>(0h0))
when _T_1684 :
node _T_1685 = eq(_T_1682, UInt<1>(0h0))
when _T_1685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1682, UInt<1>(0h1), "") : assert_116
node _T_1686 = eq(io.in.b.bits.mask, mask_1)
node _T_1687 = asUInt(reset)
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
when _T_1688 :
node _T_1689 = eq(_T_1686, UInt<1>(0h0))
when _T_1689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1686, UInt<1>(0h1), "") : assert_117
node _T_1690 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1690 :
node _T_1691 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1692 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1693 = and(_T_1691, _T_1692)
node _T_1694 = or(UInt<1>(0h0), _T_1693)
node _T_1695 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1696 = cvt(_T_1695)
node _T_1697 = and(_T_1696, asSInt(UInt<14>(0h2000)))
node _T_1698 = asSInt(_T_1697)
node _T_1699 = eq(_T_1698, asSInt(UInt<1>(0h0)))
node _T_1700 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1701 = cvt(_T_1700)
node _T_1702 = and(_T_1701, asSInt(UInt<13>(0h1000)))
node _T_1703 = asSInt(_T_1702)
node _T_1704 = eq(_T_1703, asSInt(UInt<1>(0h0)))
node _T_1705 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1706 = cvt(_T_1705)
node _T_1707 = and(_T_1706, asSInt(UInt<17>(0h10000)))
node _T_1708 = asSInt(_T_1707)
node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0)))
node _T_1710 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1711 = cvt(_T_1710)
node _T_1712 = and(_T_1711, asSInt(UInt<18>(0h2f000)))
node _T_1713 = asSInt(_T_1712)
node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0)))
node _T_1715 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1716 = cvt(_T_1715)
node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000)))
node _T_1718 = asSInt(_T_1717)
node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0)))
node _T_1720 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1721 = cvt(_T_1720)
node _T_1722 = and(_T_1721, asSInt(UInt<13>(0h1000)))
node _T_1723 = asSInt(_T_1722)
node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0)))
node _T_1725 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1726 = cvt(_T_1725)
node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000)))
node _T_1728 = asSInt(_T_1727)
node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0)))
node _T_1730 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1731 = cvt(_T_1730)
node _T_1732 = and(_T_1731, asSInt(UInt<27>(0h4000000)))
node _T_1733 = asSInt(_T_1732)
node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0)))
node _T_1735 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1736 = cvt(_T_1735)
node _T_1737 = and(_T_1736, asSInt(UInt<13>(0h1000)))
node _T_1738 = asSInt(_T_1737)
node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0)))
node _T_1740 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1741 = cvt(_T_1740)
node _T_1742 = and(_T_1741, asSInt(UInt<29>(0h10000000)))
node _T_1743 = asSInt(_T_1742)
node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0)))
node _T_1745 = or(_T_1699, _T_1704)
node _T_1746 = or(_T_1745, _T_1709)
node _T_1747 = or(_T_1746, _T_1714)
node _T_1748 = or(_T_1747, _T_1719)
node _T_1749 = or(_T_1748, _T_1724)
node _T_1750 = or(_T_1749, _T_1729)
node _T_1751 = or(_T_1750, _T_1734)
node _T_1752 = or(_T_1751, _T_1739)
node _T_1753 = or(_T_1752, _T_1744)
node _T_1754 = and(_T_1694, _T_1753)
node _T_1755 = or(UInt<1>(0h0), _T_1754)
node _T_1756 = and(UInt<1>(0h0), _T_1755)
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_118
node _T_1760 = asUInt(reset)
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
when _T_1761 :
node _T_1762 = eq(address_ok, UInt<1>(0h0))
when _T_1762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1763 = asUInt(reset)
node _T_1764 = eq(_T_1763, UInt<1>(0h0))
when _T_1764 :
node _T_1765 = eq(legal_source, UInt<1>(0h0))
when _T_1765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1766 = asUInt(reset)
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1770 = asUInt(reset)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
when _T_1771 :
node _T_1772 = eq(_T_1769, UInt<1>(0h0))
when _T_1772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1769, UInt<1>(0h1), "") : assert_122
node _T_1773 = eq(io.in.b.bits.mask, mask_1)
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(_T_1773, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1773, UInt<1>(0h1), "") : assert_123
node _T_1777 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1777 :
node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1780 = and(_T_1778, _T_1779)
node _T_1781 = or(UInt<1>(0h0), _T_1780)
node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1783 = cvt(_T_1782)
node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000)))
node _T_1785 = asSInt(_T_1784)
node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0)))
node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1788 = cvt(_T_1787)
node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000)))
node _T_1790 = asSInt(_T_1789)
node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0)))
node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1793 = cvt(_T_1792)
node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000)))
node _T_1795 = asSInt(_T_1794)
node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0)))
node _T_1797 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1798 = cvt(_T_1797)
node _T_1799 = and(_T_1798, asSInt(UInt<18>(0h2f000)))
node _T_1800 = asSInt(_T_1799)
node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0)))
node _T_1802 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1803 = cvt(_T_1802)
node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000)))
node _T_1805 = asSInt(_T_1804)
node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0)))
node _T_1807 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1808 = cvt(_T_1807)
node _T_1809 = and(_T_1808, asSInt(UInt<13>(0h1000)))
node _T_1810 = asSInt(_T_1809)
node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0)))
node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1813 = cvt(_T_1812)
node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000)))
node _T_1815 = asSInt(_T_1814)
node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0)))
node _T_1817 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1818 = cvt(_T_1817)
node _T_1819 = and(_T_1818, asSInt(UInt<27>(0h4000000)))
node _T_1820 = asSInt(_T_1819)
node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0)))
node _T_1822 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1823 = cvt(_T_1822)
node _T_1824 = and(_T_1823, asSInt(UInt<13>(0h1000)))
node _T_1825 = asSInt(_T_1824)
node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0)))
node _T_1827 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1828 = cvt(_T_1827)
node _T_1829 = and(_T_1828, asSInt(UInt<29>(0h10000000)))
node _T_1830 = asSInt(_T_1829)
node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0)))
node _T_1832 = or(_T_1786, _T_1791)
node _T_1833 = or(_T_1832, _T_1796)
node _T_1834 = or(_T_1833, _T_1801)
node _T_1835 = or(_T_1834, _T_1806)
node _T_1836 = or(_T_1835, _T_1811)
node _T_1837 = or(_T_1836, _T_1816)
node _T_1838 = or(_T_1837, _T_1821)
node _T_1839 = or(_T_1838, _T_1826)
node _T_1840 = or(_T_1839, _T_1831)
node _T_1841 = and(_T_1781, _T_1840)
node _T_1842 = or(UInt<1>(0h0), _T_1841)
node _T_1843 = and(UInt<1>(0h0), _T_1842)
node _T_1844 = asUInt(reset)
node _T_1845 = eq(_T_1844, UInt<1>(0h0))
when _T_1845 :
node _T_1846 = eq(_T_1843, UInt<1>(0h0))
when _T_1846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1843, UInt<1>(0h1), "") : assert_124
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(address_ok, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1850 = asUInt(reset)
node _T_1851 = eq(_T_1850, UInt<1>(0h0))
when _T_1851 :
node _T_1852 = eq(legal_source, UInt<1>(0h0))
when _T_1852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1853 = asUInt(reset)
node _T_1854 = eq(_T_1853, UInt<1>(0h0))
when _T_1854 :
node _T_1855 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1855 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1856 = eq(io.in.b.bits.mask, mask_1)
node _T_1857 = asUInt(reset)
node _T_1858 = eq(_T_1857, UInt<1>(0h0))
when _T_1858 :
node _T_1859 = eq(_T_1856, UInt<1>(0h0))
when _T_1859 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1856, UInt<1>(0h1), "") : assert_128
node _T_1860 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1861 = asUInt(reset)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
node _T_1863 = eq(_T_1860, UInt<1>(0h0))
when _T_1863 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1860, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1864 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(_T_1864, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1864, UInt<1>(0h1), "") : assert_130
node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_18 = shr(io.in.c.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<2>(0h2))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<2>(0h3))
node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE_2 : UInt<1>[3]
connect _source_ok_WIRE_2[0], _source_ok_T_23
connect _source_ok_WIRE_2[1], _source_ok_T_24
connect _source_ok_WIRE_2[2], _source_ok_T_25
node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_1868 = shr(io.in.c.bits.source, 2)
node _T_1869 = eq(_T_1868, UInt<1>(0h0))
node _T_1870 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_1871 = and(_T_1869, _T_1870)
node _T_1872 = leq(uncommonBits_13, UInt<2>(0h2))
node _T_1873 = and(_T_1871, _T_1872)
node _T_1874 = eq(_T_1873, UInt<1>(0h0))
node _T_1875 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1876 = cvt(_T_1875)
node _T_1877 = and(_T_1876, asSInt(UInt<1>(0h0)))
node _T_1878 = asSInt(_T_1877)
node _T_1879 = eq(_T_1878, asSInt(UInt<1>(0h0)))
node _T_1880 = or(_T_1874, _T_1879)
node _T_1881 = eq(io.in.c.bits.source, UInt<2>(0h3))
node _T_1882 = eq(_T_1881, UInt<1>(0h0))
node _T_1883 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1884 = cvt(_T_1883)
node _T_1885 = and(_T_1884, asSInt(UInt<1>(0h0)))
node _T_1886 = asSInt(_T_1885)
node _T_1887 = eq(_T_1886, asSInt(UInt<1>(0h0)))
node _T_1888 = or(_T_1882, _T_1887)
node _T_1889 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_1890 = eq(_T_1889, UInt<1>(0h0))
node _T_1891 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1892 = cvt(_T_1891)
node _T_1893 = and(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = asSInt(_T_1893)
node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0)))
node _T_1896 = or(_T_1890, _T_1895)
node _T_1897 = and(_T_1880, _T_1888)
node _T_1898 = and(_T_1897, _T_1896)
node _T_1899 = asUInt(reset)
node _T_1900 = eq(_T_1899, UInt<1>(0h0))
when _T_1900 :
node _T_1901 = eq(_T_1898, UInt<1>(0h0))
when _T_1901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1898, UInt<1>(0h1), "") : assert_131
node _T_1902 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1902 :
node _T_1903 = asUInt(reset)
node _T_1904 = eq(_T_1903, UInt<1>(0h0))
when _T_1904 :
node _T_1905 = eq(address_ok_1, UInt<1>(0h0))
when _T_1905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1906 = asUInt(reset)
node _T_1907 = eq(_T_1906, UInt<1>(0h0))
when _T_1907 :
node _T_1908 = eq(source_ok_2, UInt<1>(0h0))
when _T_1908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1909 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1910 = asUInt(reset)
node _T_1911 = eq(_T_1910, UInt<1>(0h0))
when _T_1911 :
node _T_1912 = eq(_T_1909, UInt<1>(0h0))
when _T_1912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1909, UInt<1>(0h1), "") : assert_134
node _T_1913 = asUInt(reset)
node _T_1914 = eq(_T_1913, UInt<1>(0h0))
when _T_1914 :
node _T_1915 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1916 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1917 = asUInt(reset)
node _T_1918 = eq(_T_1917, UInt<1>(0h0))
when _T_1918 :
node _T_1919 = eq(_T_1916, UInt<1>(0h0))
when _T_1919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1916, UInt<1>(0h1), "") : assert_136
node _T_1920 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1921 = asUInt(reset)
node _T_1922 = eq(_T_1921, UInt<1>(0h0))
when _T_1922 :
node _T_1923 = eq(_T_1920, UInt<1>(0h0))
when _T_1923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1920, UInt<1>(0h1), "") : assert_137
node _T_1924 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1924 :
node _T_1925 = asUInt(reset)
node _T_1926 = eq(_T_1925, UInt<1>(0h0))
when _T_1926 :
node _T_1927 = eq(address_ok_1, UInt<1>(0h0))
when _T_1927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1928 = asUInt(reset)
node _T_1929 = eq(_T_1928, UInt<1>(0h0))
when _T_1929 :
node _T_1930 = eq(source_ok_2, UInt<1>(0h0))
when _T_1930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1931 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1932 = asUInt(reset)
node _T_1933 = eq(_T_1932, UInt<1>(0h0))
when _T_1933 :
node _T_1934 = eq(_T_1931, UInt<1>(0h0))
when _T_1934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1931, UInt<1>(0h1), "") : assert_140
node _T_1935 = asUInt(reset)
node _T_1936 = eq(_T_1935, UInt<1>(0h0))
when _T_1936 :
node _T_1937 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1938 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1939 = asUInt(reset)
node _T_1940 = eq(_T_1939, UInt<1>(0h0))
when _T_1940 :
node _T_1941 = eq(_T_1938, UInt<1>(0h0))
when _T_1941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1938, UInt<1>(0h1), "") : assert_142
node _T_1942 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1942 :
node _T_1943 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1944 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1945 = and(_T_1943, _T_1944)
node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_1946 = shr(io.in.c.bits.source, 2)
node _T_1947 = eq(_T_1946, UInt<1>(0h0))
node _T_1948 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_1949 = and(_T_1947, _T_1948)
node _T_1950 = leq(uncommonBits_14, UInt<2>(0h2))
node _T_1951 = and(_T_1949, _T_1950)
node _T_1952 = eq(io.in.c.bits.source, UInt<2>(0h3))
node _T_1953 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_1954 = or(_T_1951, _T_1952)
node _T_1955 = or(_T_1954, _T_1953)
node _T_1956 = and(_T_1945, _T_1955)
node _T_1957 = or(UInt<1>(0h0), _T_1956)
node _T_1958 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1959 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1960 = cvt(_T_1959)
node _T_1961 = and(_T_1960, asSInt(UInt<14>(0h2000)))
node _T_1962 = asSInt(_T_1961)
node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0)))
node _T_1964 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1965 = cvt(_T_1964)
node _T_1966 = and(_T_1965, asSInt(UInt<13>(0h1000)))
node _T_1967 = asSInt(_T_1966)
node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0)))
node _T_1969 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1970 = cvt(_T_1969)
node _T_1971 = and(_T_1970, asSInt(UInt<17>(0h10000)))
node _T_1972 = asSInt(_T_1971)
node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0)))
node _T_1974 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1975 = cvt(_T_1974)
node _T_1976 = and(_T_1975, asSInt(UInt<18>(0h2f000)))
node _T_1977 = asSInt(_T_1976)
node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0)))
node _T_1979 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1980 = cvt(_T_1979)
node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000)))
node _T_1982 = asSInt(_T_1981)
node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0)))
node _T_1984 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1985 = cvt(_T_1984)
node _T_1986 = and(_T_1985, asSInt(UInt<13>(0h1000)))
node _T_1987 = asSInt(_T_1986)
node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0)))
node _T_1989 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1990 = cvt(_T_1989)
node _T_1991 = and(_T_1990, asSInt(UInt<27>(0h4000000)))
node _T_1992 = asSInt(_T_1991)
node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0)))
node _T_1994 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1995 = cvt(_T_1994)
node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000)))
node _T_1997 = asSInt(_T_1996)
node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0)))
node _T_1999 = or(_T_1963, _T_1968)
node _T_2000 = or(_T_1999, _T_1973)
node _T_2001 = or(_T_2000, _T_1978)
node _T_2002 = or(_T_2001, _T_1983)
node _T_2003 = or(_T_2002, _T_1988)
node _T_2004 = or(_T_2003, _T_1993)
node _T_2005 = or(_T_2004, _T_1998)
node _T_2006 = and(_T_1958, _T_2005)
node _T_2007 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2008 = or(UInt<1>(0h0), _T_2007)
node _T_2009 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2010 = cvt(_T_2009)
node _T_2011 = and(_T_2010, asSInt(UInt<17>(0h10000)))
node _T_2012 = asSInt(_T_2011)
node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0)))
node _T_2014 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2015 = cvt(_T_2014)
node _T_2016 = and(_T_2015, asSInt(UInt<29>(0h10000000)))
node _T_2017 = asSInt(_T_2016)
node _T_2018 = eq(_T_2017, asSInt(UInt<1>(0h0)))
node _T_2019 = or(_T_2013, _T_2018)
node _T_2020 = and(_T_2008, _T_2019)
node _T_2021 = or(UInt<1>(0h0), _T_2006)
node _T_2022 = or(_T_2021, _T_2020)
node _T_2023 = and(_T_1957, _T_2022)
node _T_2024 = asUInt(reset)
node _T_2025 = eq(_T_2024, UInt<1>(0h0))
when _T_2025 :
node _T_2026 = eq(_T_2023, UInt<1>(0h0))
when _T_2026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_2023, UInt<1>(0h1), "") : assert_143
node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_2027 = shr(io.in.c.bits.source, 2)
node _T_2028 = eq(_T_2027, UInt<1>(0h0))
node _T_2029 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_2030 = and(_T_2028, _T_2029)
node _T_2031 = leq(uncommonBits_15, UInt<2>(0h2))
node _T_2032 = and(_T_2030, _T_2031)
node _T_2033 = eq(io.in.c.bits.source, UInt<2>(0h3))
node _T_2034 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _WIRE_6 : UInt<1>[3]
connect _WIRE_6[0], _T_2032
connect _WIRE_6[1], _T_2033
connect _WIRE_6[2], _T_2034
node _T_2035 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2036 = mux(_WIRE_6[0], _T_2035, UInt<1>(0h0))
node _T_2037 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2038 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2039 = or(_T_2036, _T_2037)
node _T_2040 = or(_T_2039, _T_2038)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_2040
node _T_2041 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2042 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2043 = and(_T_2041, _T_2042)
node _T_2044 = or(UInt<1>(0h0), _T_2043)
node _T_2045 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2046 = cvt(_T_2045)
node _T_2047 = and(_T_2046, asSInt(UInt<14>(0h2000)))
node _T_2048 = asSInt(_T_2047)
node _T_2049 = eq(_T_2048, asSInt(UInt<1>(0h0)))
node _T_2050 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2051 = cvt(_T_2050)
node _T_2052 = and(_T_2051, asSInt(UInt<13>(0h1000)))
node _T_2053 = asSInt(_T_2052)
node _T_2054 = eq(_T_2053, asSInt(UInt<1>(0h0)))
node _T_2055 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2056 = cvt(_T_2055)
node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000)))
node _T_2058 = asSInt(_T_2057)
node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0)))
node _T_2060 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<18>(0h2f000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2066 = cvt(_T_2065)
node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000)))
node _T_2068 = asSInt(_T_2067)
node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0)))
node _T_2070 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<13>(0h1000)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2076 = cvt(_T_2075)
node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000)))
node _T_2078 = asSInt(_T_2077)
node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0)))
node _T_2080 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2081 = cvt(_T_2080)
node _T_2082 = and(_T_2081, asSInt(UInt<27>(0h4000000)))
node _T_2083 = asSInt(_T_2082)
node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0)))
node _T_2085 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2086 = cvt(_T_2085)
node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000)))
node _T_2088 = asSInt(_T_2087)
node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0)))
node _T_2090 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2091 = cvt(_T_2090)
node _T_2092 = and(_T_2091, asSInt(UInt<29>(0h10000000)))
node _T_2093 = asSInt(_T_2092)
node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0)))
node _T_2095 = or(_T_2049, _T_2054)
node _T_2096 = or(_T_2095, _T_2059)
node _T_2097 = or(_T_2096, _T_2064)
node _T_2098 = or(_T_2097, _T_2069)
node _T_2099 = or(_T_2098, _T_2074)
node _T_2100 = or(_T_2099, _T_2079)
node _T_2101 = or(_T_2100, _T_2084)
node _T_2102 = or(_T_2101, _T_2089)
node _T_2103 = or(_T_2102, _T_2094)
node _T_2104 = and(_T_2044, _T_2103)
node _T_2105 = or(UInt<1>(0h0), _T_2104)
node _T_2106 = and(_WIRE_7, _T_2105)
node _T_2107 = asUInt(reset)
node _T_2108 = eq(_T_2107, UInt<1>(0h0))
when _T_2108 :
node _T_2109 = eq(_T_2106, UInt<1>(0h0))
when _T_2109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2106, UInt<1>(0h1), "") : assert_144
node _T_2110 = asUInt(reset)
node _T_2111 = eq(_T_2110, UInt<1>(0h0))
when _T_2111 :
node _T_2112 = eq(source_ok_2, UInt<1>(0h0))
when _T_2112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2113 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2114 = asUInt(reset)
node _T_2115 = eq(_T_2114, UInt<1>(0h0))
when _T_2115 :
node _T_2116 = eq(_T_2113, UInt<1>(0h0))
when _T_2116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2113, UInt<1>(0h1), "") : assert_146
node _T_2117 = asUInt(reset)
node _T_2118 = eq(_T_2117, UInt<1>(0h0))
when _T_2118 :
node _T_2119 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2120 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2121 = asUInt(reset)
node _T_2122 = eq(_T_2121, UInt<1>(0h0))
when _T_2122 :
node _T_2123 = eq(_T_2120, UInt<1>(0h0))
when _T_2123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2120, UInt<1>(0h1), "") : assert_148
node _T_2124 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(_T_2124, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2124, UInt<1>(0h1), "") : assert_149
node _T_2128 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2128 :
node _T_2129 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2130 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2131 = and(_T_2129, _T_2130)
node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_2132 = shr(io.in.c.bits.source, 2)
node _T_2133 = eq(_T_2132, UInt<1>(0h0))
node _T_2134 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_2135 = and(_T_2133, _T_2134)
node _T_2136 = leq(uncommonBits_16, UInt<2>(0h2))
node _T_2137 = and(_T_2135, _T_2136)
node _T_2138 = eq(io.in.c.bits.source, UInt<2>(0h3))
node _T_2139 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_2140 = or(_T_2137, _T_2138)
node _T_2141 = or(_T_2140, _T_2139)
node _T_2142 = and(_T_2131, _T_2141)
node _T_2143 = or(UInt<1>(0h0), _T_2142)
node _T_2144 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2145 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2146 = cvt(_T_2145)
node _T_2147 = and(_T_2146, asSInt(UInt<14>(0h2000)))
node _T_2148 = asSInt(_T_2147)
node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0)))
node _T_2150 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2151 = cvt(_T_2150)
node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000)))
node _T_2153 = asSInt(_T_2152)
node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0)))
node _T_2155 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2156 = cvt(_T_2155)
node _T_2157 = and(_T_2156, asSInt(UInt<17>(0h10000)))
node _T_2158 = asSInt(_T_2157)
node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0)))
node _T_2160 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2161 = cvt(_T_2160)
node _T_2162 = and(_T_2161, asSInt(UInt<18>(0h2f000)))
node _T_2163 = asSInt(_T_2162)
node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0)))
node _T_2165 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2166 = cvt(_T_2165)
node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000)))
node _T_2168 = asSInt(_T_2167)
node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0)))
node _T_2170 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2171 = cvt(_T_2170)
node _T_2172 = and(_T_2171, asSInt(UInt<13>(0h1000)))
node _T_2173 = asSInt(_T_2172)
node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0)))
node _T_2175 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2176 = cvt(_T_2175)
node _T_2177 = and(_T_2176, asSInt(UInt<27>(0h4000000)))
node _T_2178 = asSInt(_T_2177)
node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0)))
node _T_2180 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2181 = cvt(_T_2180)
node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000)))
node _T_2183 = asSInt(_T_2182)
node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0)))
node _T_2185 = or(_T_2149, _T_2154)
node _T_2186 = or(_T_2185, _T_2159)
node _T_2187 = or(_T_2186, _T_2164)
node _T_2188 = or(_T_2187, _T_2169)
node _T_2189 = or(_T_2188, _T_2174)
node _T_2190 = or(_T_2189, _T_2179)
node _T_2191 = or(_T_2190, _T_2184)
node _T_2192 = and(_T_2144, _T_2191)
node _T_2193 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2194 = or(UInt<1>(0h0), _T_2193)
node _T_2195 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2196 = cvt(_T_2195)
node _T_2197 = and(_T_2196, asSInt(UInt<17>(0h10000)))
node _T_2198 = asSInt(_T_2197)
node _T_2199 = eq(_T_2198, asSInt(UInt<1>(0h0)))
node _T_2200 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2201 = cvt(_T_2200)
node _T_2202 = and(_T_2201, asSInt(UInt<29>(0h10000000)))
node _T_2203 = asSInt(_T_2202)
node _T_2204 = eq(_T_2203, asSInt(UInt<1>(0h0)))
node _T_2205 = or(_T_2199, _T_2204)
node _T_2206 = and(_T_2194, _T_2205)
node _T_2207 = or(UInt<1>(0h0), _T_2192)
node _T_2208 = or(_T_2207, _T_2206)
node _T_2209 = and(_T_2143, _T_2208)
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_150
node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_2213 = shr(io.in.c.bits.source, 2)
node _T_2214 = eq(_T_2213, UInt<1>(0h0))
node _T_2215 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_2216 = and(_T_2214, _T_2215)
node _T_2217 = leq(uncommonBits_17, UInt<2>(0h2))
node _T_2218 = and(_T_2216, _T_2217)
node _T_2219 = eq(io.in.c.bits.source, UInt<2>(0h3))
node _T_2220 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _WIRE_8 : UInt<1>[3]
connect _WIRE_8[0], _T_2218
connect _WIRE_8[1], _T_2219
connect _WIRE_8[2], _T_2220
node _T_2221 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2222 = mux(_WIRE_8[0], _T_2221, UInt<1>(0h0))
node _T_2223 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2224 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2225 = or(_T_2222, _T_2223)
node _T_2226 = or(_T_2225, _T_2224)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2226
node _T_2227 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2228 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2229 = and(_T_2227, _T_2228)
node _T_2230 = or(UInt<1>(0h0), _T_2229)
node _T_2231 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2232 = cvt(_T_2231)
node _T_2233 = and(_T_2232, asSInt(UInt<14>(0h2000)))
node _T_2234 = asSInt(_T_2233)
node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0)))
node _T_2236 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2237 = cvt(_T_2236)
node _T_2238 = and(_T_2237, asSInt(UInt<13>(0h1000)))
node _T_2239 = asSInt(_T_2238)
node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0)))
node _T_2241 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2242 = cvt(_T_2241)
node _T_2243 = and(_T_2242, asSInt(UInt<17>(0h10000)))
node _T_2244 = asSInt(_T_2243)
node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0)))
node _T_2246 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2247 = cvt(_T_2246)
node _T_2248 = and(_T_2247, asSInt(UInt<18>(0h2f000)))
node _T_2249 = asSInt(_T_2248)
node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0)))
node _T_2251 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2252 = cvt(_T_2251)
node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000)))
node _T_2254 = asSInt(_T_2253)
node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0)))
node _T_2256 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2257 = cvt(_T_2256)
node _T_2258 = and(_T_2257, asSInt(UInt<13>(0h1000)))
node _T_2259 = asSInt(_T_2258)
node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0)))
node _T_2261 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2262 = cvt(_T_2261)
node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000)))
node _T_2264 = asSInt(_T_2263)
node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0)))
node _T_2266 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2267 = cvt(_T_2266)
node _T_2268 = and(_T_2267, asSInt(UInt<27>(0h4000000)))
node _T_2269 = asSInt(_T_2268)
node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0)))
node _T_2271 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2272 = cvt(_T_2271)
node _T_2273 = and(_T_2272, asSInt(UInt<13>(0h1000)))
node _T_2274 = asSInt(_T_2273)
node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0)))
node _T_2276 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2277 = cvt(_T_2276)
node _T_2278 = and(_T_2277, asSInt(UInt<29>(0h10000000)))
node _T_2279 = asSInt(_T_2278)
node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0)))
node _T_2281 = or(_T_2235, _T_2240)
node _T_2282 = or(_T_2281, _T_2245)
node _T_2283 = or(_T_2282, _T_2250)
node _T_2284 = or(_T_2283, _T_2255)
node _T_2285 = or(_T_2284, _T_2260)
node _T_2286 = or(_T_2285, _T_2265)
node _T_2287 = or(_T_2286, _T_2270)
node _T_2288 = or(_T_2287, _T_2275)
node _T_2289 = or(_T_2288, _T_2280)
node _T_2290 = and(_T_2230, _T_2289)
node _T_2291 = or(UInt<1>(0h0), _T_2290)
node _T_2292 = and(_WIRE_9, _T_2291)
node _T_2293 = asUInt(reset)
node _T_2294 = eq(_T_2293, UInt<1>(0h0))
when _T_2294 :
node _T_2295 = eq(_T_2292, UInt<1>(0h0))
when _T_2295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2292, UInt<1>(0h1), "") : assert_151
node _T_2296 = asUInt(reset)
node _T_2297 = eq(_T_2296, UInt<1>(0h0))
when _T_2297 :
node _T_2298 = eq(source_ok_2, UInt<1>(0h0))
when _T_2298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2299 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_153
node _T_2303 = asUInt(reset)
node _T_2304 = eq(_T_2303, UInt<1>(0h0))
when _T_2304 :
node _T_2305 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2306 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2307 = asUInt(reset)
node _T_2308 = eq(_T_2307, UInt<1>(0h0))
when _T_2308 :
node _T_2309 = eq(_T_2306, UInt<1>(0h0))
when _T_2309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2306, UInt<1>(0h1), "") : assert_155
node _T_2310 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2310 :
node _T_2311 = asUInt(reset)
node _T_2312 = eq(_T_2311, UInt<1>(0h0))
when _T_2312 :
node _T_2313 = eq(address_ok_1, UInt<1>(0h0))
when _T_2313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
node _T_2316 = eq(source_ok_2, UInt<1>(0h0))
when _T_2316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2317 = asUInt(reset)
node _T_2318 = eq(_T_2317, UInt<1>(0h0))
when _T_2318 :
node _T_2319 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2320 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2321 = asUInt(reset)
node _T_2322 = eq(_T_2321, UInt<1>(0h0))
when _T_2322 :
node _T_2323 = eq(_T_2320, UInt<1>(0h0))
when _T_2323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2320, UInt<1>(0h1), "") : assert_159
node _T_2324 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2325 = asUInt(reset)
node _T_2326 = eq(_T_2325, UInt<1>(0h0))
when _T_2326 :
node _T_2327 = eq(_T_2324, UInt<1>(0h0))
when _T_2327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2324, UInt<1>(0h1), "") : assert_160
node _T_2328 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2328 :
node _T_2329 = asUInt(reset)
node _T_2330 = eq(_T_2329, UInt<1>(0h0))
when _T_2330 :
node _T_2331 = eq(address_ok_1, UInt<1>(0h0))
when _T_2331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2332 = asUInt(reset)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
when _T_2333 :
node _T_2334 = eq(source_ok_2, UInt<1>(0h0))
when _T_2334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2335 = asUInt(reset)
node _T_2336 = eq(_T_2335, UInt<1>(0h0))
when _T_2336 :
node _T_2337 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2338 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2339 = asUInt(reset)
node _T_2340 = eq(_T_2339, UInt<1>(0h0))
when _T_2340 :
node _T_2341 = eq(_T_2338, UInt<1>(0h0))
when _T_2341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2338, UInt<1>(0h1), "") : assert_164
node _T_2342 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2342 :
node _T_2343 = asUInt(reset)
node _T_2344 = eq(_T_2343, UInt<1>(0h0))
when _T_2344 :
node _T_2345 = eq(address_ok_1, UInt<1>(0h0))
when _T_2345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2346 = asUInt(reset)
node _T_2347 = eq(_T_2346, UInt<1>(0h0))
when _T_2347 :
node _T_2348 = eq(source_ok_2, UInt<1>(0h0))
when _T_2348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2349 = asUInt(reset)
node _T_2350 = eq(_T_2349, UInt<1>(0h0))
when _T_2350 :
node _T_2351 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2352 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2353 = asUInt(reset)
node _T_2354 = eq(_T_2353, UInt<1>(0h0))
when _T_2354 :
node _T_2355 = eq(_T_2352, UInt<1>(0h0))
when _T_2355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2352, UInt<1>(0h1), "") : assert_168
node _T_2356 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2357 = asUInt(reset)
node _T_2358 = eq(_T_2357, UInt<1>(0h0))
when _T_2358 :
node _T_2359 = eq(_T_2356, UInt<1>(0h0))
when _T_2359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2356, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2360 = asUInt(reset)
node _T_2361 = eq(_T_2360, UInt<1>(0h0))
when _T_2361 :
node _T_2362 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2363 = eq(a_first, UInt<1>(0h0))
node _T_2364 = and(io.in.a.valid, _T_2363)
when _T_2364 :
node _T_2365 = eq(io.in.a.bits.opcode, opcode)
node _T_2366 = asUInt(reset)
node _T_2367 = eq(_T_2366, UInt<1>(0h0))
when _T_2367 :
node _T_2368 = eq(_T_2365, UInt<1>(0h0))
when _T_2368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2365, UInt<1>(0h1), "") : assert_171
node _T_2369 = eq(io.in.a.bits.param, param)
node _T_2370 = asUInt(reset)
node _T_2371 = eq(_T_2370, UInt<1>(0h0))
when _T_2371 :
node _T_2372 = eq(_T_2369, UInt<1>(0h0))
when _T_2372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2369, UInt<1>(0h1), "") : assert_172
node _T_2373 = eq(io.in.a.bits.size, size)
node _T_2374 = asUInt(reset)
node _T_2375 = eq(_T_2374, UInt<1>(0h0))
when _T_2375 :
node _T_2376 = eq(_T_2373, UInt<1>(0h0))
when _T_2376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2373, UInt<1>(0h1), "") : assert_173
node _T_2377 = eq(io.in.a.bits.source, source)
node _T_2378 = asUInt(reset)
node _T_2379 = eq(_T_2378, UInt<1>(0h0))
when _T_2379 :
node _T_2380 = eq(_T_2377, UInt<1>(0h0))
when _T_2380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2377, UInt<1>(0h1), "") : assert_174
node _T_2381 = eq(io.in.a.bits.address, address)
node _T_2382 = asUInt(reset)
node _T_2383 = eq(_T_2382, UInt<1>(0h0))
when _T_2383 :
node _T_2384 = eq(_T_2381, UInt<1>(0h0))
when _T_2384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2381, UInt<1>(0h1), "") : assert_175
node _T_2385 = and(io.in.a.ready, io.in.a.valid)
node _T_2386 = and(_T_2385, a_first)
when _T_2386 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2387 = eq(d_first, UInt<1>(0h0))
node _T_2388 = and(io.in.d.valid, _T_2387)
when _T_2388 :
node _T_2389 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2390 = asUInt(reset)
node _T_2391 = eq(_T_2390, UInt<1>(0h0))
when _T_2391 :
node _T_2392 = eq(_T_2389, UInt<1>(0h0))
when _T_2392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2389, UInt<1>(0h1), "") : assert_176
node _T_2393 = eq(io.in.d.bits.param, param_1)
node _T_2394 = asUInt(reset)
node _T_2395 = eq(_T_2394, UInt<1>(0h0))
when _T_2395 :
node _T_2396 = eq(_T_2393, UInt<1>(0h0))
when _T_2396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2393, UInt<1>(0h1), "") : assert_177
node _T_2397 = eq(io.in.d.bits.size, size_1)
node _T_2398 = asUInt(reset)
node _T_2399 = eq(_T_2398, UInt<1>(0h0))
when _T_2399 :
node _T_2400 = eq(_T_2397, UInt<1>(0h0))
when _T_2400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2397, UInt<1>(0h1), "") : assert_178
node _T_2401 = eq(io.in.d.bits.source, source_1)
node _T_2402 = asUInt(reset)
node _T_2403 = eq(_T_2402, UInt<1>(0h0))
when _T_2403 :
node _T_2404 = eq(_T_2401, UInt<1>(0h0))
when _T_2404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2401, UInt<1>(0h1), "") : assert_179
node _T_2405 = eq(io.in.d.bits.sink, sink)
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_180
node _T_2409 = eq(io.in.d.bits.denied, denied)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_181
node _T_2413 = and(io.in.d.ready, io.in.d.valid)
node _T_2414 = and(_T_2413, d_first)
when _T_2414 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2415 = eq(b_first, UInt<1>(0h0))
node _T_2416 = and(io.in.b.valid, _T_2415)
when _T_2416 :
node _T_2417 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2418 = asUInt(reset)
node _T_2419 = eq(_T_2418, UInt<1>(0h0))
when _T_2419 :
node _T_2420 = eq(_T_2417, UInt<1>(0h0))
when _T_2420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2417, UInt<1>(0h1), "") : assert_182
node _T_2421 = eq(io.in.b.bits.param, param_2)
node _T_2422 = asUInt(reset)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
when _T_2423 :
node _T_2424 = eq(_T_2421, UInt<1>(0h0))
when _T_2424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2421, UInt<1>(0h1), "") : assert_183
node _T_2425 = eq(io.in.b.bits.size, size_2)
node _T_2426 = asUInt(reset)
node _T_2427 = eq(_T_2426, UInt<1>(0h0))
when _T_2427 :
node _T_2428 = eq(_T_2425, UInt<1>(0h0))
when _T_2428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2425, UInt<1>(0h1), "") : assert_184
node _T_2429 = eq(io.in.b.bits.source, source_2)
node _T_2430 = asUInt(reset)
node _T_2431 = eq(_T_2430, UInt<1>(0h0))
when _T_2431 :
node _T_2432 = eq(_T_2429, UInt<1>(0h0))
when _T_2432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2429, UInt<1>(0h1), "") : assert_185
node _T_2433 = eq(io.in.b.bits.address, address_1)
node _T_2434 = asUInt(reset)
node _T_2435 = eq(_T_2434, UInt<1>(0h0))
when _T_2435 :
node _T_2436 = eq(_T_2433, UInt<1>(0h0))
when _T_2436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2433, UInt<1>(0h1), "") : assert_186
node _T_2437 = and(io.in.b.ready, io.in.b.valid)
node _T_2438 = and(_T_2437, b_first)
when _T_2438 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2439 = eq(c_first, UInt<1>(0h0))
node _T_2440 = and(io.in.c.valid, _T_2439)
when _T_2440 :
node _T_2441 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2442 = asUInt(reset)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
when _T_2443 :
node _T_2444 = eq(_T_2441, UInt<1>(0h0))
when _T_2444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2441, UInt<1>(0h1), "") : assert_187
node _T_2445 = eq(io.in.c.bits.param, param_3)
node _T_2446 = asUInt(reset)
node _T_2447 = eq(_T_2446, UInt<1>(0h0))
when _T_2447 :
node _T_2448 = eq(_T_2445, UInt<1>(0h0))
when _T_2448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2445, UInt<1>(0h1), "") : assert_188
node _T_2449 = eq(io.in.c.bits.size, size_3)
node _T_2450 = asUInt(reset)
node _T_2451 = eq(_T_2450, UInt<1>(0h0))
when _T_2451 :
node _T_2452 = eq(_T_2449, UInt<1>(0h0))
when _T_2452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2449, UInt<1>(0h1), "") : assert_189
node _T_2453 = eq(io.in.c.bits.source, source_3)
node _T_2454 = asUInt(reset)
node _T_2455 = eq(_T_2454, UInt<1>(0h0))
when _T_2455 :
node _T_2456 = eq(_T_2453, UInt<1>(0h0))
when _T_2456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2453, UInt<1>(0h1), "") : assert_190
node _T_2457 = eq(io.in.c.bits.address, address_2)
node _T_2458 = asUInt(reset)
node _T_2459 = eq(_T_2458, UInt<1>(0h0))
when _T_2459 :
node _T_2460 = eq(_T_2457, UInt<1>(0h0))
when _T_2460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2457, UInt<1>(0h1), "") : assert_191
node _T_2461 = and(io.in.c.ready, io.in.c.valid)
node _T_2462 = and(_T_2461, c_first)
when _T_2462 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<5>
connect a_set, UInt<5>(0h0)
wire a_set_wo_ready : UInt<5>
connect a_set_wo_ready, UInt<5>(0h0)
wire a_opcodes_set : UInt<20>
connect a_opcodes_set, UInt<20>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2463 = and(io.in.a.valid, a_first_1)
node _T_2464 = and(_T_2463, UInt<1>(0h1))
when _T_2464 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2465 = and(io.in.a.ready, io.in.a.valid)
node _T_2466 = and(_T_2465, a_first_1)
node _T_2467 = and(_T_2466, UInt<1>(0h1))
when _T_2467 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2468 = dshr(inflight, io.in.a.bits.source)
node _T_2469 = bits(_T_2468, 0, 0)
node _T_2470 = eq(_T_2469, UInt<1>(0h0))
node _T_2471 = asUInt(reset)
node _T_2472 = eq(_T_2471, UInt<1>(0h0))
when _T_2472 :
node _T_2473 = eq(_T_2470, UInt<1>(0h0))
when _T_2473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2470, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<5>
connect d_clr, UInt<5>(0h0)
wire d_clr_wo_ready : UInt<5>
connect d_clr_wo_ready, UInt<5>(0h0)
wire d_opcodes_clr : UInt<20>
connect d_opcodes_clr, UInt<20>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2474 = and(io.in.d.valid, d_first_1)
node _T_2475 = and(_T_2474, UInt<1>(0h1))
node _T_2476 = eq(d_release_ack, UInt<1>(0h0))
node _T_2477 = and(_T_2475, _T_2476)
when _T_2477 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2478 = and(io.in.d.ready, io.in.d.valid)
node _T_2479 = and(_T_2478, d_first_1)
node _T_2480 = and(_T_2479, UInt<1>(0h1))
node _T_2481 = eq(d_release_ack, UInt<1>(0h0))
node _T_2482 = and(_T_2480, _T_2481)
when _T_2482 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2483 = and(io.in.d.valid, d_first_1)
node _T_2484 = and(_T_2483, UInt<1>(0h1))
node _T_2485 = eq(d_release_ack, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2487 = dshr(inflight, io.in.d.bits.source)
node _T_2488 = bits(_T_2487, 0, 0)
node _T_2489 = or(_T_2488, same_cycle_resp)
node _T_2490 = asUInt(reset)
node _T_2491 = eq(_T_2490, UInt<1>(0h0))
when _T_2491 :
node _T_2492 = eq(_T_2489, UInt<1>(0h0))
when _T_2492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2489, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2493 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2494 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2495 = or(_T_2493, _T_2494)
node _T_2496 = asUInt(reset)
node _T_2497 = eq(_T_2496, UInt<1>(0h0))
when _T_2497 :
node _T_2498 = eq(_T_2495, UInt<1>(0h0))
when _T_2498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2495, UInt<1>(0h1), "") : assert_194
node _T_2499 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2500 = asUInt(reset)
node _T_2501 = eq(_T_2500, UInt<1>(0h0))
when _T_2501 :
node _T_2502 = eq(_T_2499, UInt<1>(0h0))
when _T_2502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2499, UInt<1>(0h1), "") : assert_195
else :
node _T_2503 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2505 = or(_T_2503, _T_2504)
node _T_2506 = asUInt(reset)
node _T_2507 = eq(_T_2506, UInt<1>(0h0))
when _T_2507 :
node _T_2508 = eq(_T_2505, UInt<1>(0h0))
when _T_2508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2505, UInt<1>(0h1), "") : assert_196
node _T_2509 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2510 = asUInt(reset)
node _T_2511 = eq(_T_2510, UInt<1>(0h0))
when _T_2511 :
node _T_2512 = eq(_T_2509, UInt<1>(0h0))
when _T_2512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2509, UInt<1>(0h1), "") : assert_197
node _T_2513 = and(io.in.d.valid, d_first_1)
node _T_2514 = and(_T_2513, a_first_1)
node _T_2515 = and(_T_2514, io.in.a.valid)
node _T_2516 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2517 = and(_T_2515, _T_2516)
node _T_2518 = eq(d_release_ack, UInt<1>(0h0))
node _T_2519 = and(_T_2517, _T_2518)
when _T_2519 :
node _T_2520 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2521 = or(_T_2520, io.in.a.ready)
node _T_2522 = asUInt(reset)
node _T_2523 = eq(_T_2522, UInt<1>(0h0))
when _T_2523 :
node _T_2524 = eq(_T_2521, UInt<1>(0h0))
when _T_2524 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2521, UInt<1>(0h1), "") : assert_198
node _T_2525 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2526 = orr(a_set_wo_ready)
node _T_2527 = eq(_T_2526, UInt<1>(0h0))
node _T_2528 = or(_T_2525, _T_2527)
node _T_2529 = asUInt(reset)
node _T_2530 = eq(_T_2529, UInt<1>(0h0))
when _T_2530 :
node _T_2531 = eq(_T_2528, UInt<1>(0h0))
when _T_2531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2528, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_4
node _T_2532 = orr(inflight)
node _T_2533 = eq(_T_2532, UInt<1>(0h0))
node _T_2534 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2535 = or(_T_2533, _T_2534)
node _T_2536 = lt(watchdog, plusarg_reader.out)
node _T_2537 = or(_T_2535, _T_2536)
node _T_2538 = asUInt(reset)
node _T_2539 = eq(_T_2538, UInt<1>(0h0))
when _T_2539 :
node _T_2540 = eq(_T_2537, UInt<1>(0h0))
when _T_2540 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2537, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2541 = and(io.in.a.ready, io.in.a.valid)
node _T_2542 = and(io.in.d.ready, io.in.d.valid)
node _T_2543 = or(_T_2541, _T_2542)
when _T_2543 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<5>
connect c_set, UInt<5>(0h0)
wire c_set_wo_ready : UInt<5>
connect c_set_wo_ready, UInt<5>(0h0)
wire c_opcodes_set : UInt<20>
connect c_opcodes_set, UInt<20>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2544 = and(io.in.c.valid, c_first_1)
node _T_2545 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2546 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2547 = and(_T_2545, _T_2546)
node _T_2548 = and(_T_2544, _T_2547)
when _T_2548 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2549 = and(io.in.c.ready, io.in.c.valid)
node _T_2550 = and(_T_2549, c_first_1)
node _T_2551 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2552 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2553 = and(_T_2551, _T_2552)
node _T_2554 = and(_T_2550, _T_2553)
when _T_2554 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2555 = dshr(inflight_1, io.in.c.bits.source)
node _T_2556 = bits(_T_2555, 0, 0)
node _T_2557 = eq(_T_2556, UInt<1>(0h0))
node _T_2558 = asUInt(reset)
node _T_2559 = eq(_T_2558, UInt<1>(0h0))
when _T_2559 :
node _T_2560 = eq(_T_2557, UInt<1>(0h0))
when _T_2560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2557, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<5>
connect d_clr_1, UInt<5>(0h0)
wire d_clr_wo_ready_1 : UInt<5>
connect d_clr_wo_ready_1, UInt<5>(0h0)
wire d_opcodes_clr_1 : UInt<20>
connect d_opcodes_clr_1, UInt<20>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2561 = and(io.in.d.valid, d_first_2)
node _T_2562 = and(_T_2561, UInt<1>(0h1))
node _T_2563 = and(_T_2562, d_release_ack_1)
when _T_2563 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2564 = and(io.in.d.ready, io.in.d.valid)
node _T_2565 = and(_T_2564, d_first_2)
node _T_2566 = and(_T_2565, UInt<1>(0h1))
node _T_2567 = and(_T_2566, d_release_ack_1)
when _T_2567 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2568 = and(io.in.d.valid, d_first_2)
node _T_2569 = and(_T_2568, UInt<1>(0h1))
node _T_2570 = and(_T_2569, d_release_ack_1)
when _T_2570 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2571 = dshr(inflight_1, io.in.d.bits.source)
node _T_2572 = bits(_T_2571, 0, 0)
node _T_2573 = or(_T_2572, same_cycle_resp_1)
node _T_2574 = asUInt(reset)
node _T_2575 = eq(_T_2574, UInt<1>(0h0))
when _T_2575 :
node _T_2576 = eq(_T_2573, UInt<1>(0h0))
when _T_2576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2573, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2577 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2578 = asUInt(reset)
node _T_2579 = eq(_T_2578, UInt<1>(0h0))
when _T_2579 :
node _T_2580 = eq(_T_2577, UInt<1>(0h0))
when _T_2580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2577, UInt<1>(0h1), "") : assert_203
else :
node _T_2581 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2582 = asUInt(reset)
node _T_2583 = eq(_T_2582, UInt<1>(0h0))
when _T_2583 :
node _T_2584 = eq(_T_2581, UInt<1>(0h0))
when _T_2584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2581, UInt<1>(0h1), "") : assert_204
node _T_2585 = and(io.in.d.valid, d_first_2)
node _T_2586 = and(_T_2585, c_first_1)
node _T_2587 = and(_T_2586, io.in.c.valid)
node _T_2588 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2589 = and(_T_2587, _T_2588)
node _T_2590 = and(_T_2589, d_release_ack_1)
node _T_2591 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2592 = and(_T_2590, _T_2591)
when _T_2592 :
node _T_2593 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2594 = or(_T_2593, io.in.c.ready)
node _T_2595 = asUInt(reset)
node _T_2596 = eq(_T_2595, UInt<1>(0h0))
when _T_2596 :
node _T_2597 = eq(_T_2594, UInt<1>(0h0))
when _T_2597 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2594, UInt<1>(0h1), "") : assert_205
node _T_2598 = orr(c_set_wo_ready)
when _T_2598 :
node _T_2599 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2600 = asUInt(reset)
node _T_2601 = eq(_T_2600, UInt<1>(0h0))
when _T_2601 :
node _T_2602 = eq(_T_2599, UInt<1>(0h0))
when _T_2602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2599, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_5
node _T_2603 = orr(inflight_1)
node _T_2604 = eq(_T_2603, UInt<1>(0h0))
node _T_2605 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2606 = or(_T_2604, _T_2605)
node _T_2607 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2608 = or(_T_2606, _T_2607)
node _T_2609 = asUInt(reset)
node _T_2610 = eq(_T_2609, UInt<1>(0h0))
when _T_2610 :
node _T_2611 = eq(_T_2608, UInt<1>(0h0))
when _T_2611 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2608, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2612 = and(io.in.c.ready, io.in.c.valid)
node _T_2613 = and(io.in.d.ready, io.in.d.valid)
node _T_2614 = or(_T_2612, _T_2613)
when _T_2614 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2615 = and(io.in.d.ready, io.in.d.valid)
node _T_2616 = and(_T_2615, d_first_3)
node _T_2617 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2618 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2619 = eq(_T_2618, UInt<1>(0h0))
node _T_2620 = and(_T_2617, _T_2619)
node _T_2621 = and(_T_2616, _T_2620)
when _T_2621 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2622 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2623 = bits(_T_2622, 0, 0)
node _T_2624 = eq(_T_2623, UInt<1>(0h0))
node _T_2625 = asUInt(reset)
node _T_2626 = eq(_T_2625, UInt<1>(0h0))
when _T_2626 :
node _T_2627 = eq(_T_2624, UInt<1>(0h0))
when _T_2627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2624, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2628 = and(io.in.e.ready, io.in.e.valid)
node _T_2629 = and(_T_2628, UInt<1>(0h1))
node _T_2630 = and(_T_2629, UInt<1>(0h1))
when _T_2630 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2631 = or(d_set, inflight_2)
node _T_2632 = dshr(_T_2631, io.in.e.bits.sink)
node _T_2633 = bits(_T_2632, 0, 0)
node _T_2634 = asUInt(reset)
node _T_2635 = eq(_T_2634, UInt<1>(0h0))
when _T_2635 :
node _T_2636 = eq(_T_2633, UInt<1>(0h0))
when _T_2636 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2633, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_2( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7]
wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[2]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_4 = source_ok_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h3; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = io_in_a_bits_source_0 == 3'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31]
wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_9 = io_in_d_bits_source_0[2]; // @[Monitor.scala:36:7]
wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_13 = source_ok_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31]
wire _source_ok_T_15 = io_in_d_bits_source_0 == 3'h3; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31]
wire _source_ok_T_16 = io_in_d_bits_source_0 == 3'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31]
wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T = io_in_b_bits_source_0[2]; // @[Monitor.scala:36:7]
wire _legal_source_T_6 = io_in_b_bits_source_0 == 3'h3; // @[Monitor.scala:36:7]
wire _legal_source_T_7 = io_in_b_bits_source_0 == 3'h4; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_4 = legal_source_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31]
wire [1:0] _legal_source_T_9 = {2{_legal_source_WIRE_1}}; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73]
wire [2:0] _legal_source_T_10 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} | _legal_source_T_10; // @[Mux.scala:30:73]
wire [2:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_18 = io_in_c_bits_source_0[2]; // @[Monitor.scala:36:7]
wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_22 = source_ok_uncommonBits_2 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = io_in_c_bits_source_0 == 3'h3; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_c_bits_source_0 == 3'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire _T_2541 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2541; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2541; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [2:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2615 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2615; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [2:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2612 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2612; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2612; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [2:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [4:0] inflight; // @[Monitor.scala:614:27]
reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [4:0] a_set; // @[Monitor.scala:626:34]
wire [4:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [19:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [5:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69]
wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101]
wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69]
wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101]
wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [19:0] _a_opcode_lookup_T_6 = {16'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [19:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [5:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65]
wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99]
wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67]
wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {32'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [7:0] _GEN_20 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35]
wire [7:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2467 = _T_2541 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2467 ? _a_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2467 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2467 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2467 ? _a_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2467 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [4:0] d_clr; // @[Monitor.scala:664:34]
wire [4:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [19:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46]
wire _T_2513 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [7:0] _GEN_22 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2513 & ~d_release_ack ? _d_clr_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2482 = _T_2615 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2482 ? _d_clr_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2482 ? _d_opcodes_clr_T_5[19:0] : 20'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2482 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [4:0] inflight_1; // @[Monitor.scala:726:35]
reg [19:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [4:0] c_set; // @[Monitor.scala:738:34]
wire [4:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [19:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [19:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [19:0] _c_opcode_lookup_T_6 = {16'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [19:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {32'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [7:0] _GEN_23 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35]
wire [7:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2554 = _T_2612 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2554 ? _c_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2554 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2554 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2554 ? _c_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2554 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [4:0] d_clr_1; // @[Monitor.scala:774:34]
wire [4:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [19:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2585 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2585 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2567 = _T_2615 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2567 ? _d_clr_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2567 ? _d_opcodes_clr_T_11[19:0] : 20'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2567 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [4:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [4:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [19:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [19:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2621 = _T_2615 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35]
assign d_set = _T_2621 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2630 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35]
assign e_clr = _T_2630 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_5 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_5( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29]
wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_145 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_145( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_16 :
input clock : Clock
input reset : Reset
output auto : { }
skip | module TLBuffer_16( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset // @[Buffer.scala:40:9]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_143 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_157
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_143( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_157 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_68 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_68( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_250 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_250( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DCacheDataArray :
input clock : Clock
input reset : Reset
output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<14>, write : UInt<1>, wdata : UInt<64>, wordMask : UInt<1>, eccMask : UInt<8>, way_en : UInt<1>}}, resp : UInt<64>[1]}
node eccMask_0 = bits(io.req.bits.eccMask, 0, 0)
node eccMask_1 = bits(io.req.bits.eccMask, 1, 1)
node eccMask_2 = bits(io.req.bits.eccMask, 2, 2)
node eccMask_3 = bits(io.req.bits.eccMask, 3, 3)
node eccMask_4 = bits(io.req.bits.eccMask, 4, 4)
node eccMask_5 = bits(io.req.bits.eccMask, 5, 5)
node eccMask_6 = bits(io.req.bits.eccMask, 6, 6)
node eccMask_7 = bits(io.req.bits.eccMask, 7, 7)
node wWords_0 = bits(io.req.bits.wdata, 63, 0)
node addr = shr(io.req.bits.addr, 3)
smem rockettile_dcache_data_arrays_0 : UInt<8>[8] [2048]
node _rdata_valid_T = bits(io.req.bits.wordMask, 0, 0)
node _rdata_valid_T_1 = or(UInt<1>(0h1), _rdata_valid_T)
node rdata_valid = and(io.req.valid, _rdata_valid_T_1)
node _rdata_T = and(rdata_valid, io.req.bits.write)
when _rdata_T :
node rdata_wData_0 = bits(wWords_0, 7, 0)
node rdata_wData_1 = bits(wWords_0, 15, 8)
node rdata_wData_2 = bits(wWords_0, 23, 16)
node rdata_wData_3 = bits(wWords_0, 31, 24)
node rdata_wData_4 = bits(wWords_0, 39, 32)
node rdata_wData_5 = bits(wWords_0, 47, 40)
node rdata_wData_6 = bits(wWords_0, 55, 48)
node rdata_wData_7 = bits(wWords_0, 63, 56)
wire _rdata_WIRE : UInt<8>[8]
connect _rdata_WIRE[0], rdata_wData_0
connect _rdata_WIRE[1], rdata_wData_1
connect _rdata_WIRE[2], rdata_wData_2
connect _rdata_WIRE[3], rdata_wData_3
connect _rdata_WIRE[4], rdata_wData_4
connect _rdata_WIRE[5], rdata_wData_5
connect _rdata_WIRE[6], rdata_wData_6
connect _rdata_WIRE[7], rdata_wData_7
write mport rdata_MPORT = rockettile_dcache_data_arrays_0[addr], clock
when eccMask_0 :
connect rdata_MPORT[0], _rdata_WIRE[0]
when eccMask_1 :
connect rdata_MPORT[1], _rdata_WIRE[1]
when eccMask_2 :
connect rdata_MPORT[2], _rdata_WIRE[2]
when eccMask_3 :
connect rdata_MPORT[3], _rdata_WIRE[3]
when eccMask_4 :
connect rdata_MPORT[4], _rdata_WIRE[4]
when eccMask_5 :
connect rdata_MPORT[5], _rdata_WIRE[5]
when eccMask_6 :
connect rdata_MPORT[6], _rdata_WIRE[6]
when eccMask_7 :
connect rdata_MPORT[7], _rdata_WIRE[7]
node _rdata_data_T = eq(io.req.bits.write, UInt<1>(0h0))
node _rdata_data_T_1 = and(rdata_valid, _rdata_data_T)
wire _rdata_data_WIRE : UInt<11>
invalidate _rdata_data_WIRE
when _rdata_data_T_1 :
connect _rdata_data_WIRE, addr
read mport rdata_data = rockettile_dcache_data_arrays_0[_rdata_data_WIRE], clock
node rdata_lo_lo = cat(rdata_data[1], rdata_data[0])
node rdata_lo_hi = cat(rdata_data[3], rdata_data[2])
node rdata_lo = cat(rdata_lo_hi, rdata_lo_lo)
node rdata_hi_lo = cat(rdata_data[5], rdata_data[4])
node rdata_hi_hi = cat(rdata_data[7], rdata_data[6])
node rdata_hi = cat(rdata_hi_hi, rdata_hi_lo)
node rdata_0_0 = cat(rdata_hi, rdata_lo)
connect io.resp[0], rdata_0_0 | module DCacheDataArray( // @[DCache.scala:49:7]
input clock, // @[DCache.scala:49:7]
input reset, // @[DCache.scala:49:7]
input io_req_valid, // @[DCache.scala:50:14]
input [13:0] io_req_bits_addr, // @[DCache.scala:50:14]
input io_req_bits_write, // @[DCache.scala:50:14]
input [63:0] io_req_bits_wdata, // @[DCache.scala:50:14]
input io_req_bits_wordMask, // @[DCache.scala:50:14]
input [7:0] io_req_bits_eccMask, // @[DCache.scala:50:14]
input io_req_bits_way_en, // @[DCache.scala:50:14]
output [63:0] io_resp_0 // @[DCache.scala:50:14]
);
wire [63:0] _rockettile_dcache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire io_req_valid_0 = io_req_valid; // @[DCache.scala:49:7]
wire [13:0] io_req_bits_addr_0 = io_req_bits_addr; // @[DCache.scala:49:7]
wire io_req_bits_write_0 = io_req_bits_write; // @[DCache.scala:49:7]
wire [63:0] io_req_bits_wdata_0 = io_req_bits_wdata; // @[DCache.scala:49:7]
wire io_req_bits_wordMask_0 = io_req_bits_wordMask; // @[DCache.scala:49:7]
wire [7:0] io_req_bits_eccMask_0 = io_req_bits_eccMask; // @[DCache.scala:49:7]
wire io_req_bits_way_en_0 = io_req_bits_way_en; // @[DCache.scala:49:7]
wire _rdata_valid_T_1 = 1'h1; // @[DCache.scala:71:60]
wire rdata_valid = io_req_valid_0; // @[DCache.scala:49:7, :71:30]
wire [63:0] wWords_0 = io_req_bits_wdata_0; // @[package.scala:211:50]
wire _rdata_valid_T = io_req_bits_wordMask_0; // @[DCache.scala:49:7, :71:83]
wire [63:0] rdata_0_0; // @[package.scala:45:27]
wire [63:0] io_resp_0_0; // @[DCache.scala:49:7]
wire eccMask_0 = io_req_bits_eccMask_0[0]; // @[DCache.scala:49:7, :56:82]
wire eccMask_1 = io_req_bits_eccMask_0[1]; // @[DCache.scala:49:7, :56:82]
wire eccMask_2 = io_req_bits_eccMask_0[2]; // @[DCache.scala:49:7, :56:82]
wire eccMask_3 = io_req_bits_eccMask_0[3]; // @[DCache.scala:49:7, :56:82]
wire eccMask_4 = io_req_bits_eccMask_0[4]; // @[DCache.scala:49:7, :56:82]
wire eccMask_5 = io_req_bits_eccMask_0[5]; // @[DCache.scala:49:7, :56:82]
wire eccMask_6 = io_req_bits_eccMask_0[6]; // @[DCache.scala:49:7, :56:82]
wire eccMask_7 = io_req_bits_eccMask_0[7]; // @[DCache.scala:49:7, :56:82]
wire [10:0] addr = io_req_bits_addr_0[13:3]; // @[DCache.scala:49:7, :59:31]
wire [10:0] _rdata_data_WIRE = addr; // @[DCache.scala:59:31, :77:26]
wire _rdata_T; // @[DCache.scala:72:17]
wire _rdata_data_T_1; // @[DCache.scala:77:39]
wire [7:0] _rdata_WIRE_0; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_1; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_2; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_3; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_4; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_5; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_6; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_7; // @[DCache.scala:75:32]
assign _rdata_T = rdata_valid & io_req_bits_write_0; // @[DCache.scala:49:7, :71:30, :72:17]
wire [7:0] rdata_wData_0 = wWords_0[7:0]; // @[package.scala:211:50]
assign _rdata_WIRE_0 = rdata_wData_0; // @[package.scala:211:50]
wire [7:0] rdata_wData_1 = wWords_0[15:8]; // @[package.scala:211:50]
assign _rdata_WIRE_1 = rdata_wData_1; // @[package.scala:211:50]
wire [7:0] rdata_wData_2 = wWords_0[23:16]; // @[package.scala:211:50]
assign _rdata_WIRE_2 = rdata_wData_2; // @[package.scala:211:50]
wire [7:0] rdata_wData_3 = wWords_0[31:24]; // @[package.scala:211:50]
assign _rdata_WIRE_3 = rdata_wData_3; // @[package.scala:211:50]
wire [7:0] rdata_wData_4 = wWords_0[39:32]; // @[package.scala:211:50]
assign _rdata_WIRE_4 = rdata_wData_4; // @[package.scala:211:50]
wire [7:0] rdata_wData_5 = wWords_0[47:40]; // @[package.scala:211:50]
assign _rdata_WIRE_5 = rdata_wData_5; // @[package.scala:211:50]
wire [7:0] rdata_wData_6 = wWords_0[55:48]; // @[package.scala:211:50]
assign _rdata_WIRE_6 = rdata_wData_6; // @[package.scala:211:50]
wire [7:0] rdata_wData_7 = wWords_0[63:56]; // @[package.scala:211:50]
assign _rdata_WIRE_7 = rdata_wData_7; // @[package.scala:211:50]
wire _rdata_data_T = ~io_req_bits_write_0; // @[DCache.scala:49:7, :77:42]
assign _rdata_data_T_1 = rdata_valid & _rdata_data_T; // @[DCache.scala:71:30, :77:{39,42}]
wire [15:0] rdata_lo_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[15:0]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[31:16]; // @[package.scala:45:27]
wire [31:0] rdata_lo = {rdata_lo_hi, rdata_lo_lo}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[47:32]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[63:48]; // @[package.scala:45:27]
wire [31:0] rdata_hi = {rdata_hi_hi, rdata_hi_lo}; // @[package.scala:45:27]
assign rdata_0_0 = {rdata_hi, rdata_lo}; // @[package.scala:45:27]
assign io_resp_0_0 = rdata_0_0; // @[package.scala:45:27]
rockettile_dcache_data_arrays_0 rockettile_dcache_data_arrays_0 ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (_rdata_T ? addr : _rdata_data_WIRE), // @[DescribedSRAM.scala:17:26]
.RW0_en (_rdata_data_T_1 | _rdata_T), // @[DescribedSRAM.scala:17:26]
.RW0_clk (clock),
.RW0_wmode (io_req_bits_write_0), // @[DCache.scala:49:7]
.RW0_wdata ({_rdata_WIRE_7, _rdata_WIRE_6, _rdata_WIRE_5, _rdata_WIRE_4, _rdata_WIRE_3, _rdata_WIRE_2, _rdata_WIRE_1, _rdata_WIRE_0}), // @[DescribedSRAM.scala:17:26]
.RW0_rdata (_rockettile_dcache_data_arrays_0_RW0_rdata),
.RW0_wmask ({eccMask_7, eccMask_6, eccMask_5, eccMask_4, eccMask_3, eccMask_2, eccMask_1, eccMask_0}) // @[DescribedSRAM.scala:17:26]
); // @[DescribedSRAM.scala:17:26]
assign io_resp_0 = io_resp_0_0; // @[DCache.scala:49:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_2 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 13, 13)
wire common_expOut : UInt<6>
wire common_fractOut : UInt<10>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 5, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _roundMask_T_1)
node _roundMask_T_2 = bits(roundMask_shift, 18, 7)
node _roundMask_T_3 = bits(_roundMask_T_2, 7, 0)
node _roundMask_T_4 = shl(UInt<4>(0hf), 4)
node _roundMask_T_5 = xor(UInt<8>(0hff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 4)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 3, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 4)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 5, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 2)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 2)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 5, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 2)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 6, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 1)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 1)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 6, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 1)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_2, 11, 8)
node _roundMask_T_34 = bits(_roundMask_T_33, 1, 0)
node _roundMask_T_35 = bits(_roundMask_T_34, 0, 0)
node _roundMask_T_36 = bits(_roundMask_T_34, 1, 1)
node _roundMask_T_37 = cat(_roundMask_T_35, _roundMask_T_36)
node _roundMask_T_38 = bits(_roundMask_T_33, 3, 2)
node _roundMask_T_39 = bits(_roundMask_T_38, 0, 0)
node _roundMask_T_40 = bits(_roundMask_T_38, 1, 1)
node _roundMask_T_41 = cat(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = cat(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = cat(_roundMask_T_32, _roundMask_T_42)
node _roundMask_T_44 = or(_roundMask_T_43, doShiftSigDown1)
node roundMask = cat(_roundMask_T_44, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<13>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 11)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 5, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 10, 1)
node _common_fractOut_T_1 = bits(roundedSig, 9, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 4)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<5>(0h8)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 12, 12)
node _roundCarry_T_1 = bits(roundedSig, 11, 11)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 5)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<6>(0h38), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<6>(0h8))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<6>(0h10), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<6>(0h8), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<6>(0h8), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<6>(0h2f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<6>(0h30), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<6>(0h38), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<10>(0h200), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<10>(0h3ff), UInt<10>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_2( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [7:0] _roundMask_T_5 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_4 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_10 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_13 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_14 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_15 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_20 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_23 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_24 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_25 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_30 = 8'hAA; // @[primitives.scala:77:20]
wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [13:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49]
wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[13]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [5:0] _roundMask_T = io_in_sExp_0[5:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [5:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1); // @[primitives.scala:52:21, :76:56]
wire [11:0] _roundMask_T_2 = roundMask_shift[18:7]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _roundMask_T_3 = _roundMask_T_2[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_6 = _roundMask_T_3[7:4]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_7 = {4'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_8 = _roundMask_T_3[3:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_9 = {_roundMask_T_8, 4'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_11 = _roundMask_T_9 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_16 = _roundMask_T_12[7:2]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_17 = {2'h0, _roundMask_T_16 & 6'h33}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_18 = _roundMask_T_12[5:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_19 = {_roundMask_T_18, 2'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_21 = _roundMask_T_19 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_26 = _roundMask_T_22[7:1]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_27 = {1'h0, _roundMask_T_26 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_28 = _roundMask_T_22[6:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_29 = {_roundMask_T_28, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_31 = _roundMask_T_29 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_33 = _roundMask_T_2[11:8]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _roundMask_T_34 = _roundMask_T_33[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_35 = _roundMask_T_34[0]; // @[primitives.scala:77:20]
wire _roundMask_T_36 = _roundMask_T_34[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_37 = {_roundMask_T_35, _roundMask_T_36}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_38 = _roundMask_T_33[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_39 = _roundMask_T_38[0]; // @[primitives.scala:77:20]
wire _roundMask_T_40 = _roundMask_T_38[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_41 = {_roundMask_T_39, _roundMask_T_40}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_42 = {_roundMask_T_37, _roundMask_T_41}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_43 = {_roundMask_T_32, _roundMask_T_42}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_44 = {_roundMask_T_43[11:1], _roundMask_T_43[0] | doShiftSigDown1}; // @[primitives.scala:77:20]
wire [13:0] roundMask = {_roundMask_T_44, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [14:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [13:0] shiftedRoundMask = _shiftedRoundMask_T[14:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [13:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [13:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [13:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [13:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [13:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [12:0] _roundedSig_T_6 = roundMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [12:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [13:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [13:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [12:0] _roundedSig_T_14 = roundPosMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [12:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [7:0] sRoundedExp = {io_in_sExp_0[6], io_in_sExp_0} + {{5{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[7:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 8'sh8; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[6:5]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [5:0] _expOut_T_5 = pegMinNonzeroMagOut ? 6'h37 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [5:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [5:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [5:0] _expOut_T_14 = {2'h0, pegMinNonzeroMagOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [5:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [5:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [5:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [5:0] _expOut_T_20 = isNaNOut ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [5:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [9:0] _fractOut_T_2 = {isNaNOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [9:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_3 :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 9, 6)
node req_tag = shr(req.addr, 10)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 3)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue_3
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal
connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr
connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br
connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned
connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned
connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state
connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std
connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta
connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load
connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd
connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw
connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn
connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel
connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel
connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel
connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type
connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code
connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock
reg refill_ctr : UInt<3>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
invalidate io.meta_write.bits.data.tag
invalidate io.meta_write.bits.data.coh.state
invalidate io.meta_write.bits.tag
invalidate io.meta_write.bits.way_en
invalidate io.meta_write.bits.idx
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
invalidate io.mem_acquire.bits.corrupt
invalidate io.mem_acquire.bits.data
invalidate io.mem_acquire.bits.mask
invalidate io.mem_acquire.bits.address
invalidate io.mem_acquire.bits.source
invalidate io.mem_acquire.bits.size
invalidate io.mem_acquire.bits.param
invalidate io.mem_acquire.bits.opcode
connect io.refill.valid, UInt<1>(0h0)
invalidate io.refill.bits.data
invalidate io.refill.bits.wmask
invalidate io.refill.bits.addr
invalidate io.refill.bits.way_en
connect io.replay.valid, UInt<1>(0h0)
invalidate io.replay.bits.sdq_id
invalidate io.replay.bits.way_en
invalidate io.replay.bits.old_meta.tag
invalidate io.replay.bits.old_meta.coh.state
invalidate io.replay.bits.tag_match
invalidate io.replay.bits.is_hella
invalidate io.replay.bits.data
invalidate io.replay.bits.addr
invalidate io.replay.bits.uop.debug_tsrc
invalidate io.replay.bits.uop.debug_fsrc
invalidate io.replay.bits.uop.bp_xcpt_if
invalidate io.replay.bits.uop.bp_debug_if
invalidate io.replay.bits.uop.xcpt_ma_if
invalidate io.replay.bits.uop.xcpt_ae_if
invalidate io.replay.bits.uop.xcpt_pf_if
invalidate io.replay.bits.uop.fp_single
invalidate io.replay.bits.uop.fp_val
invalidate io.replay.bits.uop.frs3_en
invalidate io.replay.bits.uop.lrs2_rtype
invalidate io.replay.bits.uop.lrs1_rtype
invalidate io.replay.bits.uop.dst_rtype
invalidate io.replay.bits.uop.ldst_val
invalidate io.replay.bits.uop.lrs3
invalidate io.replay.bits.uop.lrs2
invalidate io.replay.bits.uop.lrs1
invalidate io.replay.bits.uop.ldst
invalidate io.replay.bits.uop.ldst_is_rs1
invalidate io.replay.bits.uop.flush_on_commit
invalidate io.replay.bits.uop.is_unique
invalidate io.replay.bits.uop.is_sys_pc2epc
invalidate io.replay.bits.uop.uses_stq
invalidate io.replay.bits.uop.uses_ldq
invalidate io.replay.bits.uop.is_amo
invalidate io.replay.bits.uop.is_fencei
invalidate io.replay.bits.uop.is_fence
invalidate io.replay.bits.uop.mem_signed
invalidate io.replay.bits.uop.mem_size
invalidate io.replay.bits.uop.mem_cmd
invalidate io.replay.bits.uop.bypassable
invalidate io.replay.bits.uop.exc_cause
invalidate io.replay.bits.uop.exception
invalidate io.replay.bits.uop.stale_pdst
invalidate io.replay.bits.uop.ppred_busy
invalidate io.replay.bits.uop.prs3_busy
invalidate io.replay.bits.uop.prs2_busy
invalidate io.replay.bits.uop.prs1_busy
invalidate io.replay.bits.uop.ppred
invalidate io.replay.bits.uop.prs3
invalidate io.replay.bits.uop.prs2
invalidate io.replay.bits.uop.prs1
invalidate io.replay.bits.uop.pdst
invalidate io.replay.bits.uop.rxq_idx
invalidate io.replay.bits.uop.stq_idx
invalidate io.replay.bits.uop.ldq_idx
invalidate io.replay.bits.uop.rob_idx
invalidate io.replay.bits.uop.csr_addr
invalidate io.replay.bits.uop.imm_packed
invalidate io.replay.bits.uop.taken
invalidate io.replay.bits.uop.pc_lob
invalidate io.replay.bits.uop.edge_inst
invalidate io.replay.bits.uop.ftq_idx
invalidate io.replay.bits.uop.br_tag
invalidate io.replay.bits.uop.br_mask
invalidate io.replay.bits.uop.is_sfb
invalidate io.replay.bits.uop.is_jal
invalidate io.replay.bits.uop.is_jalr
invalidate io.replay.bits.uop.is_br
invalidate io.replay.bits.uop.iw_p2_poisoned
invalidate io.replay.bits.uop.iw_p1_poisoned
invalidate io.replay.bits.uop.iw_state
invalidate io.replay.bits.uop.ctrl.is_std
invalidate io.replay.bits.uop.ctrl.is_sta
invalidate io.replay.bits.uop.ctrl.is_load
invalidate io.replay.bits.uop.ctrl.csr_cmd
invalidate io.replay.bits.uop.ctrl.fcn_dw
invalidate io.replay.bits.uop.ctrl.op_fcn
invalidate io.replay.bits.uop.ctrl.imm_sel
invalidate io.replay.bits.uop.ctrl.op2_sel
invalidate io.replay.bits.uop.ctrl.op1_sel
invalidate io.replay.bits.uop.ctrl.br_type
invalidate io.replay.bits.uop.fu_code
invalidate io.replay.bits.uop.iq_type
invalidate io.replay.bits.uop.debug_pc
invalidate io.replay.bits.uop.is_rvc
invalidate io.replay.bits.uop.debug_inst
invalidate io.replay.bits.uop.inst
invalidate io.replay.bits.uop.uopc
connect io.wb_req.valid, UInt<1>(0h0)
invalidate io.wb_req.bits.voluntary
invalidate io.wb_req.bits.way_en
invalidate io.wb_req.bits.param
invalidate io.wb_req.bits.source
invalidate io.wb_req.bits.idx
invalidate io.wb_req.bits.tag
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.is_hella
invalidate io.resp.bits.data
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
invalidate io.meta_read.bits.tag
invalidate io.meta_read.bits.way_en
invalidate io.meta_read.bits.idx
connect io.mem_finish.valid, UInt<1>(0h0)
invalidate io.mem_finish.bits.sink
connect io.lb_write.valid, UInt<1>(0h0)
invalidate io.lb_write.bits.data
invalidate io.lb_write.bits.offset
invalidate io.lb_write.bits.id
connect io.lb_read.valid, UInt<1>(0h0)
invalidate io.lb_read.bits.offset
invalidate io.lb_read.bits.id
connect io.mem_grant.ready, UInt<1>(0h0)
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5)
node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7)
node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9)
node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.mem_grant.ready, io.lb_write.ready
connect io.lb_write.valid, io.mem_grant.valid
connect io.lb_write.bits.id, io.id
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<3>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready)
node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1
node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.lb_read.valid, _io_lb_read_valid_T
connect io.lb_read.bits.id, io.id
node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3)
connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T
node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid)
node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T)
node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load)
connect io.resp.valid, _io_resp_valid_T_2
connect io.resp.bits.uop, rpq.io.deq.bits.uop
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.valid, UInt<1>(0h1)
connect io.lb_read.bits.id, io.id
connect io.lb_read.bits.offset, refill_ctr
node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid)
connect io.refill.valid, _io_refill_valid_T
node _io_refill_bits_addr_T = shl(refill_ctr, 3)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<1>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<3>(0h7))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
connect io.mem_finish.bits, grantack.bits
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR_3( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [33:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [1:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [3:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [1:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [23:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [33:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
input io_lb_write_ready, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire [2:0] io_id = 3'h3; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_id = 3'h3; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_id = 3'h3; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_source = 4'h3; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_source = 4'h3; // @[mshrs.scala:36:7]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] io_mem_acquire_bits_a_source = 4'h3; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [3:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [23:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26]
wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [33:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [1:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34]
wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [27:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59]
wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_119 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_207
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_119( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_207 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x2 :
output auto : { flip in : { sync : UInt<1>[2]}, out : UInt<1>[2]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { sync : UInt<1>[2]}
invalidate nodeIn.sync[0]
invalidate nodeIn.sync[1]
wire nodeOut : UInt<1>[2]
invalidate nodeOut[0]
invalidate nodeOut[1]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn.sync | module IntSyncSyncCrossingSink_n1x2(); // @[Crossing.scala:96:9]
wire auto_in_sync_0 = 1'h0; // @[Crossing.scala:96:9]
wire auto_in_sync_1 = 1'h0; // @[Crossing.scala:96:9]
wire auto_out_0 = 1'h0; // @[Crossing.scala:96:9]
wire auto_out_1 = 1'h0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_sync_1 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_1 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_163 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_163( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_4 :
input clock : Clock
input reset : Reset
output io : { req : { flip `5` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}}, resp : { `5` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `4` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `3` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `2` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `1` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `0` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, channel_status : { flip `5` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `4` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `3` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10]}, out_allocs : { `5` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `4` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `3` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10]}}
regreset mask : UInt<6>, clock, reset, UInt<6>(0h0)
wire in_arb_reqs : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}[6]
wire in_arb_vals : UInt<1>[6]
node in_arb_filter_lo_hi = cat(in_arb_vals[2], in_arb_vals[1])
node in_arb_filter_lo = cat(in_arb_filter_lo_hi, in_arb_vals[0])
node in_arb_filter_hi_hi = cat(in_arb_vals[5], in_arb_vals[4])
node in_arb_filter_hi = cat(in_arb_filter_hi_hi, in_arb_vals[3])
node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo)
node in_arb_filter_lo_hi_1 = cat(in_arb_vals[2], in_arb_vals[1])
node in_arb_filter_lo_1 = cat(in_arb_filter_lo_hi_1, in_arb_vals[0])
node in_arb_filter_hi_hi_1 = cat(in_arb_vals[5], in_arb_vals[4])
node in_arb_filter_hi_1 = cat(in_arb_filter_hi_hi_1, in_arb_vals[3])
node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1)
node _in_arb_filter_T_2 = not(mask)
node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2)
node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3)
node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0)
node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1)
node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2)
node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3)
node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4)
node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5)
node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6)
node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7)
node _in_arb_filter_T_13 = bits(_in_arb_filter_T_4, 8, 8)
node _in_arb_filter_T_14 = bits(_in_arb_filter_T_4, 9, 9)
node _in_arb_filter_T_15 = bits(_in_arb_filter_T_4, 10, 10)
node _in_arb_filter_T_16 = bits(_in_arb_filter_T_4, 11, 11)
node _in_arb_filter_T_17 = mux(_in_arb_filter_T_16, UInt<12>(0h800), UInt<12>(0h0))
node _in_arb_filter_T_18 = mux(_in_arb_filter_T_15, UInt<12>(0h400), _in_arb_filter_T_17)
node _in_arb_filter_T_19 = mux(_in_arb_filter_T_14, UInt<12>(0h200), _in_arb_filter_T_18)
node _in_arb_filter_T_20 = mux(_in_arb_filter_T_13, UInt<12>(0h100), _in_arb_filter_T_19)
node _in_arb_filter_T_21 = mux(_in_arb_filter_T_12, UInt<12>(0h80), _in_arb_filter_T_20)
node _in_arb_filter_T_22 = mux(_in_arb_filter_T_11, UInt<12>(0h40), _in_arb_filter_T_21)
node _in_arb_filter_T_23 = mux(_in_arb_filter_T_10, UInt<12>(0h20), _in_arb_filter_T_22)
node _in_arb_filter_T_24 = mux(_in_arb_filter_T_9, UInt<12>(0h10), _in_arb_filter_T_23)
node _in_arb_filter_T_25 = mux(_in_arb_filter_T_8, UInt<12>(0h8), _in_arb_filter_T_24)
node _in_arb_filter_T_26 = mux(_in_arb_filter_T_7, UInt<12>(0h4), _in_arb_filter_T_25)
node _in_arb_filter_T_27 = mux(_in_arb_filter_T_6, UInt<12>(0h2), _in_arb_filter_T_26)
node in_arb_filter = mux(_in_arb_filter_T_5, UInt<12>(0h1), _in_arb_filter_T_27)
node _in_arb_sel_T = bits(in_arb_filter, 5, 0)
node _in_arb_sel_T_1 = shr(in_arb_filter, 6)
node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1)
node _T = or(in_arb_vals[0], in_arb_vals[1])
node _T_1 = or(_T, in_arb_vals[2])
node _T_2 = or(_T_1, in_arb_vals[3])
node _T_3 = or(_T_2, in_arb_vals[4])
node _T_4 = or(_T_3, in_arb_vals[5])
when _T_4 :
node _mask_T = not(UInt<1>(0h0))
node _mask_T_1 = not(UInt<2>(0h0))
node _mask_T_2 = not(UInt<3>(0h0))
node _mask_T_3 = not(UInt<4>(0h0))
node _mask_T_4 = not(UInt<5>(0h0))
node _mask_T_5 = not(UInt<6>(0h0))
node _mask_T_6 = bits(in_arb_sel, 0, 0)
node _mask_T_7 = bits(in_arb_sel, 1, 1)
node _mask_T_8 = bits(in_arb_sel, 2, 2)
node _mask_T_9 = bits(in_arb_sel, 3, 3)
node _mask_T_10 = bits(in_arb_sel, 4, 4)
node _mask_T_11 = bits(in_arb_sel, 5, 5)
node _mask_T_12 = mux(_mask_T_6, _mask_T, UInt<1>(0h0))
node _mask_T_13 = mux(_mask_T_7, _mask_T_1, UInt<1>(0h0))
node _mask_T_14 = mux(_mask_T_8, _mask_T_2, UInt<1>(0h0))
node _mask_T_15 = mux(_mask_T_9, _mask_T_3, UInt<1>(0h0))
node _mask_T_16 = mux(_mask_T_10, _mask_T_4, UInt<1>(0h0))
node _mask_T_17 = mux(_mask_T_11, _mask_T_5, UInt<1>(0h0))
node _mask_T_18 = or(_mask_T_12, _mask_T_13)
node _mask_T_19 = or(_mask_T_18, _mask_T_14)
node _mask_T_20 = or(_mask_T_19, _mask_T_15)
node _mask_T_21 = or(_mask_T_20, _mask_T_16)
node _mask_T_22 = or(_mask_T_21, _mask_T_17)
wire _mask_WIRE : UInt<6>
connect _mask_WIRE, _mask_T_22
connect mask, _mask_WIRE
node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T)
connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1
node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T)
connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1
node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T)
connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1
node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T)
connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1
node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T)
connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1
node _in_arb_reqs_0_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_5_T_1 = and(io.req.`0`.bits.vc_sel.`0`[5], _in_arb_reqs_0_0_5_T)
connect in_arb_reqs[0].`0`[5], _in_arb_reqs_0_0_5_T_1
node _in_arb_reqs_0_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_6_T_1 = and(io.req.`0`.bits.vc_sel.`0`[6], _in_arb_reqs_0_0_6_T)
connect in_arb_reqs[0].`0`[6], _in_arb_reqs_0_0_6_T_1
node _in_arb_reqs_0_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_7_T_1 = and(io.req.`0`.bits.vc_sel.`0`[7], _in_arb_reqs_0_0_7_T)
connect in_arb_reqs[0].`0`[7], _in_arb_reqs_0_0_7_T_1
node _in_arb_reqs_0_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_8_T_1 = and(io.req.`0`.bits.vc_sel.`0`[8], _in_arb_reqs_0_0_8_T)
connect in_arb_reqs[0].`0`[8], _in_arb_reqs_0_0_8_T_1
node _in_arb_reqs_0_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_9_T_1 = and(io.req.`0`.bits.vc_sel.`0`[9], _in_arb_reqs_0_0_9_T)
connect in_arb_reqs[0].`0`[9], _in_arb_reqs_0_0_9_T_1
node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T)
connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1
node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T)
connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1
node _in_arb_reqs_0_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_3_0_T_1 = and(io.req.`0`.bits.vc_sel.`3`[0], _in_arb_reqs_0_3_0_T)
connect in_arb_reqs[0].`3`[0], _in_arb_reqs_0_3_0_T_1
node _in_arb_reqs_0_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_4_0_T_1 = and(io.req.`0`.bits.vc_sel.`4`[0], _in_arb_reqs_0_4_0_T)
connect in_arb_reqs[0].`4`[0], _in_arb_reqs_0_4_0_T_1
node _in_arb_reqs_0_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_5_0_T_1 = and(io.req.`0`.bits.vc_sel.`5`[0], _in_arb_reqs_0_5_0_T)
connect in_arb_reqs[0].`5`[0], _in_arb_reqs_0_5_0_T_1
node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1])
node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2])
node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3])
node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4])
node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`0`[5])
node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`0`[6])
node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`0`[7])
node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`0`[8])
node _in_arb_vals_0_T_8 = or(_in_arb_vals_0_T_7, in_arb_reqs[0].`0`[9])
node _in_arb_vals_0_T_9 = or(_in_arb_vals_0_T_8, in_arb_reqs[0].`1`[0])
node _in_arb_vals_0_T_10 = or(_in_arb_vals_0_T_9, in_arb_reqs[0].`2`[0])
node _in_arb_vals_0_T_11 = or(_in_arb_vals_0_T_10, in_arb_reqs[0].`3`[0])
node _in_arb_vals_0_T_12 = or(_in_arb_vals_0_T_11, in_arb_reqs[0].`4`[0])
node _in_arb_vals_0_T_13 = or(_in_arb_vals_0_T_12, in_arb_reqs[0].`5`[0])
node _in_arb_vals_0_T_14 = and(io.req.`0`.valid, _in_arb_vals_0_T_13)
connect in_arb_vals[0], _in_arb_vals_0_T_14
node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T)
connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1
node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T)
connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1
node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T)
connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1
node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T)
connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1
node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T)
connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1
node _in_arb_reqs_1_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_5_T_1 = and(io.req.`1`.bits.vc_sel.`0`[5], _in_arb_reqs_1_0_5_T)
connect in_arb_reqs[1].`0`[5], _in_arb_reqs_1_0_5_T_1
node _in_arb_reqs_1_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_6_T_1 = and(io.req.`1`.bits.vc_sel.`0`[6], _in_arb_reqs_1_0_6_T)
connect in_arb_reqs[1].`0`[6], _in_arb_reqs_1_0_6_T_1
node _in_arb_reqs_1_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_7_T_1 = and(io.req.`1`.bits.vc_sel.`0`[7], _in_arb_reqs_1_0_7_T)
connect in_arb_reqs[1].`0`[7], _in_arb_reqs_1_0_7_T_1
node _in_arb_reqs_1_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_8_T_1 = and(io.req.`1`.bits.vc_sel.`0`[8], _in_arb_reqs_1_0_8_T)
connect in_arb_reqs[1].`0`[8], _in_arb_reqs_1_0_8_T_1
node _in_arb_reqs_1_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_9_T_1 = and(io.req.`1`.bits.vc_sel.`0`[9], _in_arb_reqs_1_0_9_T)
connect in_arb_reqs[1].`0`[9], _in_arb_reqs_1_0_9_T_1
node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T)
connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1
node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T)
connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1
node _in_arb_reqs_1_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_3_0_T_1 = and(io.req.`1`.bits.vc_sel.`3`[0], _in_arb_reqs_1_3_0_T)
connect in_arb_reqs[1].`3`[0], _in_arb_reqs_1_3_0_T_1
node _in_arb_reqs_1_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_4_0_T_1 = and(io.req.`1`.bits.vc_sel.`4`[0], _in_arb_reqs_1_4_0_T)
connect in_arb_reqs[1].`4`[0], _in_arb_reqs_1_4_0_T_1
node _in_arb_reqs_1_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_5_0_T_1 = and(io.req.`1`.bits.vc_sel.`5`[0], _in_arb_reqs_1_5_0_T)
connect in_arb_reqs[1].`5`[0], _in_arb_reqs_1_5_0_T_1
node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1])
node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2])
node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3])
node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4])
node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`0`[5])
node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`0`[6])
node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`0`[7])
node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`0`[8])
node _in_arb_vals_1_T_8 = or(_in_arb_vals_1_T_7, in_arb_reqs[1].`0`[9])
node _in_arb_vals_1_T_9 = or(_in_arb_vals_1_T_8, in_arb_reqs[1].`1`[0])
node _in_arb_vals_1_T_10 = or(_in_arb_vals_1_T_9, in_arb_reqs[1].`2`[0])
node _in_arb_vals_1_T_11 = or(_in_arb_vals_1_T_10, in_arb_reqs[1].`3`[0])
node _in_arb_vals_1_T_12 = or(_in_arb_vals_1_T_11, in_arb_reqs[1].`4`[0])
node _in_arb_vals_1_T_13 = or(_in_arb_vals_1_T_12, in_arb_reqs[1].`5`[0])
node _in_arb_vals_1_T_14 = and(io.req.`1`.valid, _in_arb_vals_1_T_13)
connect in_arb_vals[1], _in_arb_vals_1_T_14
node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T)
connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1
node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T)
connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1
node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T)
connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1
node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T)
connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1
node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T)
connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1
node _in_arb_reqs_2_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_5_T_1 = and(io.req.`2`.bits.vc_sel.`0`[5], _in_arb_reqs_2_0_5_T)
connect in_arb_reqs[2].`0`[5], _in_arb_reqs_2_0_5_T_1
node _in_arb_reqs_2_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_6_T_1 = and(io.req.`2`.bits.vc_sel.`0`[6], _in_arb_reqs_2_0_6_T)
connect in_arb_reqs[2].`0`[6], _in_arb_reqs_2_0_6_T_1
node _in_arb_reqs_2_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_7_T_1 = and(io.req.`2`.bits.vc_sel.`0`[7], _in_arb_reqs_2_0_7_T)
connect in_arb_reqs[2].`0`[7], _in_arb_reqs_2_0_7_T_1
node _in_arb_reqs_2_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_8_T_1 = and(io.req.`2`.bits.vc_sel.`0`[8], _in_arb_reqs_2_0_8_T)
connect in_arb_reqs[2].`0`[8], _in_arb_reqs_2_0_8_T_1
node _in_arb_reqs_2_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_9_T_1 = and(io.req.`2`.bits.vc_sel.`0`[9], _in_arb_reqs_2_0_9_T)
connect in_arb_reqs[2].`0`[9], _in_arb_reqs_2_0_9_T_1
node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T)
connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1
node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T)
connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1
node _in_arb_reqs_2_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_3_0_T_1 = and(io.req.`2`.bits.vc_sel.`3`[0], _in_arb_reqs_2_3_0_T)
connect in_arb_reqs[2].`3`[0], _in_arb_reqs_2_3_0_T_1
node _in_arb_reqs_2_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_4_0_T_1 = and(io.req.`2`.bits.vc_sel.`4`[0], _in_arb_reqs_2_4_0_T)
connect in_arb_reqs[2].`4`[0], _in_arb_reqs_2_4_0_T_1
node _in_arb_reqs_2_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_5_0_T_1 = and(io.req.`2`.bits.vc_sel.`5`[0], _in_arb_reqs_2_5_0_T)
connect in_arb_reqs[2].`5`[0], _in_arb_reqs_2_5_0_T_1
node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1])
node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2])
node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3])
node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4])
node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`0`[5])
node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`0`[6])
node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`0`[7])
node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`0`[8])
node _in_arb_vals_2_T_8 = or(_in_arb_vals_2_T_7, in_arb_reqs[2].`0`[9])
node _in_arb_vals_2_T_9 = or(_in_arb_vals_2_T_8, in_arb_reqs[2].`1`[0])
node _in_arb_vals_2_T_10 = or(_in_arb_vals_2_T_9, in_arb_reqs[2].`2`[0])
node _in_arb_vals_2_T_11 = or(_in_arb_vals_2_T_10, in_arb_reqs[2].`3`[0])
node _in_arb_vals_2_T_12 = or(_in_arb_vals_2_T_11, in_arb_reqs[2].`4`[0])
node _in_arb_vals_2_T_13 = or(_in_arb_vals_2_T_12, in_arb_reqs[2].`5`[0])
node _in_arb_vals_2_T_14 = and(io.req.`2`.valid, _in_arb_vals_2_T_13)
connect in_arb_vals[2], _in_arb_vals_2_T_14
node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T)
connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1
node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T)
connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1
node _in_arb_reqs_3_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_2_T_1 = and(io.req.`3`.bits.vc_sel.`0`[2], _in_arb_reqs_3_0_2_T)
connect in_arb_reqs[3].`0`[2], _in_arb_reqs_3_0_2_T_1
node _in_arb_reqs_3_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_3_T_1 = and(io.req.`3`.bits.vc_sel.`0`[3], _in_arb_reqs_3_0_3_T)
connect in_arb_reqs[3].`0`[3], _in_arb_reqs_3_0_3_T_1
node _in_arb_reqs_3_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_4_T_1 = and(io.req.`3`.bits.vc_sel.`0`[4], _in_arb_reqs_3_0_4_T)
connect in_arb_reqs[3].`0`[4], _in_arb_reqs_3_0_4_T_1
node _in_arb_reqs_3_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_5_T_1 = and(io.req.`3`.bits.vc_sel.`0`[5], _in_arb_reqs_3_0_5_T)
connect in_arb_reqs[3].`0`[5], _in_arb_reqs_3_0_5_T_1
node _in_arb_reqs_3_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_6_T_1 = and(io.req.`3`.bits.vc_sel.`0`[6], _in_arb_reqs_3_0_6_T)
connect in_arb_reqs[3].`0`[6], _in_arb_reqs_3_0_6_T_1
node _in_arb_reqs_3_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_7_T_1 = and(io.req.`3`.bits.vc_sel.`0`[7], _in_arb_reqs_3_0_7_T)
connect in_arb_reqs[3].`0`[7], _in_arb_reqs_3_0_7_T_1
node _in_arb_reqs_3_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_8_T_1 = and(io.req.`3`.bits.vc_sel.`0`[8], _in_arb_reqs_3_0_8_T)
connect in_arb_reqs[3].`0`[8], _in_arb_reqs_3_0_8_T_1
node _in_arb_reqs_3_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_9_T_1 = and(io.req.`3`.bits.vc_sel.`0`[9], _in_arb_reqs_3_0_9_T)
connect in_arb_reqs[3].`0`[9], _in_arb_reqs_3_0_9_T_1
node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T)
connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1
node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T)
connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1
node _in_arb_reqs_3_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_3_0_T_1 = and(io.req.`3`.bits.vc_sel.`3`[0], _in_arb_reqs_3_3_0_T)
connect in_arb_reqs[3].`3`[0], _in_arb_reqs_3_3_0_T_1
node _in_arb_reqs_3_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_4_0_T_1 = and(io.req.`3`.bits.vc_sel.`4`[0], _in_arb_reqs_3_4_0_T)
connect in_arb_reqs[3].`4`[0], _in_arb_reqs_3_4_0_T_1
node _in_arb_reqs_3_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_5_0_T_1 = and(io.req.`3`.bits.vc_sel.`5`[0], _in_arb_reqs_3_5_0_T)
connect in_arb_reqs[3].`5`[0], _in_arb_reqs_3_5_0_T_1
node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1])
node _in_arb_vals_3_T_1 = or(_in_arb_vals_3_T, in_arb_reqs[3].`0`[2])
node _in_arb_vals_3_T_2 = or(_in_arb_vals_3_T_1, in_arb_reqs[3].`0`[3])
node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`0`[4])
node _in_arb_vals_3_T_4 = or(_in_arb_vals_3_T_3, in_arb_reqs[3].`0`[5])
node _in_arb_vals_3_T_5 = or(_in_arb_vals_3_T_4, in_arb_reqs[3].`0`[6])
node _in_arb_vals_3_T_6 = or(_in_arb_vals_3_T_5, in_arb_reqs[3].`0`[7])
node _in_arb_vals_3_T_7 = or(_in_arb_vals_3_T_6, in_arb_reqs[3].`0`[8])
node _in_arb_vals_3_T_8 = or(_in_arb_vals_3_T_7, in_arb_reqs[3].`0`[9])
node _in_arb_vals_3_T_9 = or(_in_arb_vals_3_T_8, in_arb_reqs[3].`1`[0])
node _in_arb_vals_3_T_10 = or(_in_arb_vals_3_T_9, in_arb_reqs[3].`2`[0])
node _in_arb_vals_3_T_11 = or(_in_arb_vals_3_T_10, in_arb_reqs[3].`3`[0])
node _in_arb_vals_3_T_12 = or(_in_arb_vals_3_T_11, in_arb_reqs[3].`4`[0])
node _in_arb_vals_3_T_13 = or(_in_arb_vals_3_T_12, in_arb_reqs[3].`5`[0])
node _in_arb_vals_3_T_14 = and(io.req.`3`.valid, _in_arb_vals_3_T_13)
connect in_arb_vals[3], _in_arb_vals_3_T_14
node _in_arb_reqs_4_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_0_T_1 = and(io.req.`4`.bits.vc_sel.`0`[0], _in_arb_reqs_4_0_0_T)
connect in_arb_reqs[4].`0`[0], _in_arb_reqs_4_0_0_T_1
node _in_arb_reqs_4_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_1_T_1 = and(io.req.`4`.bits.vc_sel.`0`[1], _in_arb_reqs_4_0_1_T)
connect in_arb_reqs[4].`0`[1], _in_arb_reqs_4_0_1_T_1
node _in_arb_reqs_4_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_2_T_1 = and(io.req.`4`.bits.vc_sel.`0`[2], _in_arb_reqs_4_0_2_T)
connect in_arb_reqs[4].`0`[2], _in_arb_reqs_4_0_2_T_1
node _in_arb_reqs_4_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_3_T_1 = and(io.req.`4`.bits.vc_sel.`0`[3], _in_arb_reqs_4_0_3_T)
connect in_arb_reqs[4].`0`[3], _in_arb_reqs_4_0_3_T_1
node _in_arb_reqs_4_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_4_T_1 = and(io.req.`4`.bits.vc_sel.`0`[4], _in_arb_reqs_4_0_4_T)
connect in_arb_reqs[4].`0`[4], _in_arb_reqs_4_0_4_T_1
node _in_arb_reqs_4_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_5_T_1 = and(io.req.`4`.bits.vc_sel.`0`[5], _in_arb_reqs_4_0_5_T)
connect in_arb_reqs[4].`0`[5], _in_arb_reqs_4_0_5_T_1
node _in_arb_reqs_4_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_6_T_1 = and(io.req.`4`.bits.vc_sel.`0`[6], _in_arb_reqs_4_0_6_T)
connect in_arb_reqs[4].`0`[6], _in_arb_reqs_4_0_6_T_1
node _in_arb_reqs_4_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_7_T_1 = and(io.req.`4`.bits.vc_sel.`0`[7], _in_arb_reqs_4_0_7_T)
connect in_arb_reqs[4].`0`[7], _in_arb_reqs_4_0_7_T_1
node _in_arb_reqs_4_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_8_T_1 = and(io.req.`4`.bits.vc_sel.`0`[8], _in_arb_reqs_4_0_8_T)
connect in_arb_reqs[4].`0`[8], _in_arb_reqs_4_0_8_T_1
node _in_arb_reqs_4_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_9_T_1 = and(io.req.`4`.bits.vc_sel.`0`[9], _in_arb_reqs_4_0_9_T)
connect in_arb_reqs[4].`0`[9], _in_arb_reqs_4_0_9_T_1
node _in_arb_reqs_4_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_1_0_T_1 = and(io.req.`4`.bits.vc_sel.`1`[0], _in_arb_reqs_4_1_0_T)
connect in_arb_reqs[4].`1`[0], _in_arb_reqs_4_1_0_T_1
node _in_arb_reqs_4_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_2_0_T_1 = and(io.req.`4`.bits.vc_sel.`2`[0], _in_arb_reqs_4_2_0_T)
connect in_arb_reqs[4].`2`[0], _in_arb_reqs_4_2_0_T_1
node _in_arb_reqs_4_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_3_0_T_1 = and(io.req.`4`.bits.vc_sel.`3`[0], _in_arb_reqs_4_3_0_T)
connect in_arb_reqs[4].`3`[0], _in_arb_reqs_4_3_0_T_1
node _in_arb_reqs_4_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_4_0_T_1 = and(io.req.`4`.bits.vc_sel.`4`[0], _in_arb_reqs_4_4_0_T)
connect in_arb_reqs[4].`4`[0], _in_arb_reqs_4_4_0_T_1
node _in_arb_reqs_4_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_5_0_T_1 = and(io.req.`4`.bits.vc_sel.`5`[0], _in_arb_reqs_4_5_0_T)
connect in_arb_reqs[4].`5`[0], _in_arb_reqs_4_5_0_T_1
node _in_arb_vals_4_T = or(in_arb_reqs[4].`0`[0], in_arb_reqs[4].`0`[1])
node _in_arb_vals_4_T_1 = or(_in_arb_vals_4_T, in_arb_reqs[4].`0`[2])
node _in_arb_vals_4_T_2 = or(_in_arb_vals_4_T_1, in_arb_reqs[4].`0`[3])
node _in_arb_vals_4_T_3 = or(_in_arb_vals_4_T_2, in_arb_reqs[4].`0`[4])
node _in_arb_vals_4_T_4 = or(_in_arb_vals_4_T_3, in_arb_reqs[4].`0`[5])
node _in_arb_vals_4_T_5 = or(_in_arb_vals_4_T_4, in_arb_reqs[4].`0`[6])
node _in_arb_vals_4_T_6 = or(_in_arb_vals_4_T_5, in_arb_reqs[4].`0`[7])
node _in_arb_vals_4_T_7 = or(_in_arb_vals_4_T_6, in_arb_reqs[4].`0`[8])
node _in_arb_vals_4_T_8 = or(_in_arb_vals_4_T_7, in_arb_reqs[4].`0`[9])
node _in_arb_vals_4_T_9 = or(_in_arb_vals_4_T_8, in_arb_reqs[4].`1`[0])
node _in_arb_vals_4_T_10 = or(_in_arb_vals_4_T_9, in_arb_reqs[4].`2`[0])
node _in_arb_vals_4_T_11 = or(_in_arb_vals_4_T_10, in_arb_reqs[4].`3`[0])
node _in_arb_vals_4_T_12 = or(_in_arb_vals_4_T_11, in_arb_reqs[4].`4`[0])
node _in_arb_vals_4_T_13 = or(_in_arb_vals_4_T_12, in_arb_reqs[4].`5`[0])
node _in_arb_vals_4_T_14 = and(io.req.`4`.valid, _in_arb_vals_4_T_13)
connect in_arb_vals[4], _in_arb_vals_4_T_14
node _in_arb_reqs_5_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_0_T_1 = and(io.req.`5`.bits.vc_sel.`0`[0], _in_arb_reqs_5_0_0_T)
connect in_arb_reqs[5].`0`[0], _in_arb_reqs_5_0_0_T_1
node _in_arb_reqs_5_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_1_T_1 = and(io.req.`5`.bits.vc_sel.`0`[1], _in_arb_reqs_5_0_1_T)
connect in_arb_reqs[5].`0`[1], _in_arb_reqs_5_0_1_T_1
node _in_arb_reqs_5_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_2_T_1 = and(io.req.`5`.bits.vc_sel.`0`[2], _in_arb_reqs_5_0_2_T)
connect in_arb_reqs[5].`0`[2], _in_arb_reqs_5_0_2_T_1
node _in_arb_reqs_5_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_3_T_1 = and(io.req.`5`.bits.vc_sel.`0`[3], _in_arb_reqs_5_0_3_T)
connect in_arb_reqs[5].`0`[3], _in_arb_reqs_5_0_3_T_1
node _in_arb_reqs_5_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_4_T_1 = and(io.req.`5`.bits.vc_sel.`0`[4], _in_arb_reqs_5_0_4_T)
connect in_arb_reqs[5].`0`[4], _in_arb_reqs_5_0_4_T_1
node _in_arb_reqs_5_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_5_T_1 = and(io.req.`5`.bits.vc_sel.`0`[5], _in_arb_reqs_5_0_5_T)
connect in_arb_reqs[5].`0`[5], _in_arb_reqs_5_0_5_T_1
node _in_arb_reqs_5_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_6_T_1 = and(io.req.`5`.bits.vc_sel.`0`[6], _in_arb_reqs_5_0_6_T)
connect in_arb_reqs[5].`0`[6], _in_arb_reqs_5_0_6_T_1
node _in_arb_reqs_5_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_7_T_1 = and(io.req.`5`.bits.vc_sel.`0`[7], _in_arb_reqs_5_0_7_T)
connect in_arb_reqs[5].`0`[7], _in_arb_reqs_5_0_7_T_1
node _in_arb_reqs_5_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_8_T_1 = and(io.req.`5`.bits.vc_sel.`0`[8], _in_arb_reqs_5_0_8_T)
connect in_arb_reqs[5].`0`[8], _in_arb_reqs_5_0_8_T_1
node _in_arb_reqs_5_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_9_T_1 = and(io.req.`5`.bits.vc_sel.`0`[9], _in_arb_reqs_5_0_9_T)
connect in_arb_reqs[5].`0`[9], _in_arb_reqs_5_0_9_T_1
node _in_arb_reqs_5_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_1_0_T_1 = and(io.req.`5`.bits.vc_sel.`1`[0], _in_arb_reqs_5_1_0_T)
connect in_arb_reqs[5].`1`[0], _in_arb_reqs_5_1_0_T_1
node _in_arb_reqs_5_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_2_0_T_1 = and(io.req.`5`.bits.vc_sel.`2`[0], _in_arb_reqs_5_2_0_T)
connect in_arb_reqs[5].`2`[0], _in_arb_reqs_5_2_0_T_1
node _in_arb_reqs_5_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_3_0_T_1 = and(io.req.`5`.bits.vc_sel.`3`[0], _in_arb_reqs_5_3_0_T)
connect in_arb_reqs[5].`3`[0], _in_arb_reqs_5_3_0_T_1
node _in_arb_reqs_5_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_4_0_T_1 = and(io.req.`5`.bits.vc_sel.`4`[0], _in_arb_reqs_5_4_0_T)
connect in_arb_reqs[5].`4`[0], _in_arb_reqs_5_4_0_T_1
node _in_arb_reqs_5_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_5_0_T_1 = and(io.req.`5`.bits.vc_sel.`5`[0], _in_arb_reqs_5_5_0_T)
connect in_arb_reqs[5].`5`[0], _in_arb_reqs_5_5_0_T_1
node _in_arb_vals_5_T = or(in_arb_reqs[5].`0`[0], in_arb_reqs[5].`0`[1])
node _in_arb_vals_5_T_1 = or(_in_arb_vals_5_T, in_arb_reqs[5].`0`[2])
node _in_arb_vals_5_T_2 = or(_in_arb_vals_5_T_1, in_arb_reqs[5].`0`[3])
node _in_arb_vals_5_T_3 = or(_in_arb_vals_5_T_2, in_arb_reqs[5].`0`[4])
node _in_arb_vals_5_T_4 = or(_in_arb_vals_5_T_3, in_arb_reqs[5].`0`[5])
node _in_arb_vals_5_T_5 = or(_in_arb_vals_5_T_4, in_arb_reqs[5].`0`[6])
node _in_arb_vals_5_T_6 = or(_in_arb_vals_5_T_5, in_arb_reqs[5].`0`[7])
node _in_arb_vals_5_T_7 = or(_in_arb_vals_5_T_6, in_arb_reqs[5].`0`[8])
node _in_arb_vals_5_T_8 = or(_in_arb_vals_5_T_7, in_arb_reqs[5].`0`[9])
node _in_arb_vals_5_T_9 = or(_in_arb_vals_5_T_8, in_arb_reqs[5].`1`[0])
node _in_arb_vals_5_T_10 = or(_in_arb_vals_5_T_9, in_arb_reqs[5].`2`[0])
node _in_arb_vals_5_T_11 = or(_in_arb_vals_5_T_10, in_arb_reqs[5].`3`[0])
node _in_arb_vals_5_T_12 = or(_in_arb_vals_5_T_11, in_arb_reqs[5].`4`[0])
node _in_arb_vals_5_T_13 = or(_in_arb_vals_5_T_12, in_arb_reqs[5].`5`[0])
node _in_arb_vals_5_T_14 = and(io.req.`5`.valid, _in_arb_vals_5_T_13)
connect in_arb_vals[5], _in_arb_vals_5_T_14
connect io.req.`0`.ready, UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h0)
connect io.req.`2`.ready, UInt<1>(0h0)
connect io.req.`3`.ready, UInt<1>(0h0)
connect io.req.`4`.ready, UInt<1>(0h0)
connect io.req.`5`.ready, UInt<1>(0h0)
wire in_alloc : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}
node _in_flow_T = bits(in_arb_sel, 0, 0)
node _in_flow_T_1 = bits(in_arb_sel, 1, 1)
node _in_flow_T_2 = bits(in_arb_sel, 2, 2)
node _in_flow_T_3 = bits(in_arb_sel, 3, 3)
node _in_flow_T_4 = bits(in_arb_sel, 4, 4)
node _in_flow_T_5 = bits(in_arb_sel, 5, 5)
wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}
node _in_flow_T_6 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_7 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_8 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_9 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_10 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_11 = mux(_in_flow_T_5, io.req.`5`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_12 = or(_in_flow_T_6, _in_flow_T_7)
node _in_flow_T_13 = or(_in_flow_T_12, _in_flow_T_8)
node _in_flow_T_14 = or(_in_flow_T_13, _in_flow_T_9)
node _in_flow_T_15 = or(_in_flow_T_14, _in_flow_T_10)
node _in_flow_T_16 = or(_in_flow_T_15, _in_flow_T_11)
wire _in_flow_WIRE : UInt<3>
connect _in_flow_WIRE, _in_flow_T_16
connect in_flow.egress_node_id, _in_flow_WIRE
node _in_flow_T_17 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_18 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_19 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_20 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_21 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_22 = mux(_in_flow_T_5, io.req.`5`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_23 = or(_in_flow_T_17, _in_flow_T_18)
node _in_flow_T_24 = or(_in_flow_T_23, _in_flow_T_19)
node _in_flow_T_25 = or(_in_flow_T_24, _in_flow_T_20)
node _in_flow_T_26 = or(_in_flow_T_25, _in_flow_T_21)
node _in_flow_T_27 = or(_in_flow_T_26, _in_flow_T_22)
wire _in_flow_WIRE_1 : UInt<4>
connect _in_flow_WIRE_1, _in_flow_T_27
connect in_flow.egress_node, _in_flow_WIRE_1
node _in_flow_T_28 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_29 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_30 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_31 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_32 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_33 = mux(_in_flow_T_5, io.req.`5`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_34 = or(_in_flow_T_28, _in_flow_T_29)
node _in_flow_T_35 = or(_in_flow_T_34, _in_flow_T_30)
node _in_flow_T_36 = or(_in_flow_T_35, _in_flow_T_31)
node _in_flow_T_37 = or(_in_flow_T_36, _in_flow_T_32)
node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_33)
wire _in_flow_WIRE_2 : UInt<3>
connect _in_flow_WIRE_2, _in_flow_T_38
connect in_flow.ingress_node_id, _in_flow_WIRE_2
node _in_flow_T_39 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_40 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_41 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_42 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_43 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_44 = mux(_in_flow_T_5, io.req.`5`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_45 = or(_in_flow_T_39, _in_flow_T_40)
node _in_flow_T_46 = or(_in_flow_T_45, _in_flow_T_41)
node _in_flow_T_47 = or(_in_flow_T_46, _in_flow_T_42)
node _in_flow_T_48 = or(_in_flow_T_47, _in_flow_T_43)
node _in_flow_T_49 = or(_in_flow_T_48, _in_flow_T_44)
wire _in_flow_WIRE_3 : UInt<4>
connect _in_flow_WIRE_3, _in_flow_T_49
connect in_flow.ingress_node, _in_flow_WIRE_3
node _in_flow_T_50 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_51 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_52 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_53 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_54 = mux(_in_flow_T_4, io.req.`4`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_55 = mux(_in_flow_T_5, io.req.`5`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_56 = or(_in_flow_T_50, _in_flow_T_51)
node _in_flow_T_57 = or(_in_flow_T_56, _in_flow_T_52)
node _in_flow_T_58 = or(_in_flow_T_57, _in_flow_T_53)
node _in_flow_T_59 = or(_in_flow_T_58, _in_flow_T_54)
node _in_flow_T_60 = or(_in_flow_T_59, _in_flow_T_55)
wire _in_flow_WIRE_4 : UInt<3>
connect _in_flow_WIRE_4, _in_flow_T_60
connect in_flow.vnet_id, _in_flow_WIRE_4
node _in_vc_T = bits(in_arb_sel, 0, 0)
node _in_vc_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_T_3 = bits(in_arb_sel, 3, 3)
node _in_vc_T_4 = bits(in_arb_sel, 4, 4)
node _in_vc_T_5 = bits(in_arb_sel, 5, 5)
node _in_vc_T_6 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_7 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_8 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_9 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_10 = mux(_in_vc_T_4, io.req.`4`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_11 = mux(_in_vc_T_5, io.req.`5`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_12 = or(_in_vc_T_6, _in_vc_T_7)
node _in_vc_T_13 = or(_in_vc_T_12, _in_vc_T_8)
node _in_vc_T_14 = or(_in_vc_T_13, _in_vc_T_9)
node _in_vc_T_15 = or(_in_vc_T_14, _in_vc_T_10)
node _in_vc_T_16 = or(_in_vc_T_15, _in_vc_T_11)
wire in_vc : UInt<4>
connect in_vc, _in_vc_T_16
node _in_vc_sel_T = bits(in_arb_sel, 0, 0)
node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3)
node _in_vc_sel_T_4 = bits(in_arb_sel, 4, 4)
node _in_vc_sel_T_5 = bits(in_arb_sel, 5, 5)
wire in_vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}
wire _in_vc_sel_WIRE : UInt<1>[10]
node _in_vc_sel_T_6 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_7 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_8 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_9 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_10 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_11 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_12 = or(_in_vc_sel_T_6, _in_vc_sel_T_7)
node _in_vc_sel_T_13 = or(_in_vc_sel_T_12, _in_vc_sel_T_8)
node _in_vc_sel_T_14 = or(_in_vc_sel_T_13, _in_vc_sel_T_9)
node _in_vc_sel_T_15 = or(_in_vc_sel_T_14, _in_vc_sel_T_10)
node _in_vc_sel_T_16 = or(_in_vc_sel_T_15, _in_vc_sel_T_11)
wire _in_vc_sel_WIRE_1 : UInt<1>
connect _in_vc_sel_WIRE_1, _in_vc_sel_T_16
connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1
node _in_vc_sel_T_17 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_18 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_19 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_20 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_21 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_22 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_23 = or(_in_vc_sel_T_17, _in_vc_sel_T_18)
node _in_vc_sel_T_24 = or(_in_vc_sel_T_23, _in_vc_sel_T_19)
node _in_vc_sel_T_25 = or(_in_vc_sel_T_24, _in_vc_sel_T_20)
node _in_vc_sel_T_26 = or(_in_vc_sel_T_25, _in_vc_sel_T_21)
node _in_vc_sel_T_27 = or(_in_vc_sel_T_26, _in_vc_sel_T_22)
wire _in_vc_sel_WIRE_2 : UInt<1>
connect _in_vc_sel_WIRE_2, _in_vc_sel_T_27
connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2
node _in_vc_sel_T_28 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_29 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_30 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_31 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_32 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_33 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_34 = or(_in_vc_sel_T_28, _in_vc_sel_T_29)
node _in_vc_sel_T_35 = or(_in_vc_sel_T_34, _in_vc_sel_T_30)
node _in_vc_sel_T_36 = or(_in_vc_sel_T_35, _in_vc_sel_T_31)
node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_32)
node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_33)
wire _in_vc_sel_WIRE_3 : UInt<1>
connect _in_vc_sel_WIRE_3, _in_vc_sel_T_38
connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3
node _in_vc_sel_T_39 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_40 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_41 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_42 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_43 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_44 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_45 = or(_in_vc_sel_T_39, _in_vc_sel_T_40)
node _in_vc_sel_T_46 = or(_in_vc_sel_T_45, _in_vc_sel_T_41)
node _in_vc_sel_T_47 = or(_in_vc_sel_T_46, _in_vc_sel_T_42)
node _in_vc_sel_T_48 = or(_in_vc_sel_T_47, _in_vc_sel_T_43)
node _in_vc_sel_T_49 = or(_in_vc_sel_T_48, _in_vc_sel_T_44)
wire _in_vc_sel_WIRE_4 : UInt<1>
connect _in_vc_sel_WIRE_4, _in_vc_sel_T_49
connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4
node _in_vc_sel_T_50 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_51 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_52 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_53 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_54 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_55 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_56 = or(_in_vc_sel_T_50, _in_vc_sel_T_51)
node _in_vc_sel_T_57 = or(_in_vc_sel_T_56, _in_vc_sel_T_52)
node _in_vc_sel_T_58 = or(_in_vc_sel_T_57, _in_vc_sel_T_53)
node _in_vc_sel_T_59 = or(_in_vc_sel_T_58, _in_vc_sel_T_54)
node _in_vc_sel_T_60 = or(_in_vc_sel_T_59, _in_vc_sel_T_55)
wire _in_vc_sel_WIRE_5 : UInt<1>
connect _in_vc_sel_WIRE_5, _in_vc_sel_T_60
connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5
node _in_vc_sel_T_61 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_62 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_63 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_64 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_65 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_66 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_67 = or(_in_vc_sel_T_61, _in_vc_sel_T_62)
node _in_vc_sel_T_68 = or(_in_vc_sel_T_67, _in_vc_sel_T_63)
node _in_vc_sel_T_69 = or(_in_vc_sel_T_68, _in_vc_sel_T_64)
node _in_vc_sel_T_70 = or(_in_vc_sel_T_69, _in_vc_sel_T_65)
node _in_vc_sel_T_71 = or(_in_vc_sel_T_70, _in_vc_sel_T_66)
wire _in_vc_sel_WIRE_6 : UInt<1>
connect _in_vc_sel_WIRE_6, _in_vc_sel_T_71
connect _in_vc_sel_WIRE[5], _in_vc_sel_WIRE_6
node _in_vc_sel_T_72 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[6], UInt<1>(0h0))
node _in_vc_sel_T_73 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[6], UInt<1>(0h0))
node _in_vc_sel_T_74 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[6], UInt<1>(0h0))
node _in_vc_sel_T_75 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[6], UInt<1>(0h0))
node _in_vc_sel_T_76 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[6], UInt<1>(0h0))
node _in_vc_sel_T_77 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[6], UInt<1>(0h0))
node _in_vc_sel_T_78 = or(_in_vc_sel_T_72, _in_vc_sel_T_73)
node _in_vc_sel_T_79 = or(_in_vc_sel_T_78, _in_vc_sel_T_74)
node _in_vc_sel_T_80 = or(_in_vc_sel_T_79, _in_vc_sel_T_75)
node _in_vc_sel_T_81 = or(_in_vc_sel_T_80, _in_vc_sel_T_76)
node _in_vc_sel_T_82 = or(_in_vc_sel_T_81, _in_vc_sel_T_77)
wire _in_vc_sel_WIRE_7 : UInt<1>
connect _in_vc_sel_WIRE_7, _in_vc_sel_T_82
connect _in_vc_sel_WIRE[6], _in_vc_sel_WIRE_7
node _in_vc_sel_T_83 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[7], UInt<1>(0h0))
node _in_vc_sel_T_84 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[7], UInt<1>(0h0))
node _in_vc_sel_T_85 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[7], UInt<1>(0h0))
node _in_vc_sel_T_86 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[7], UInt<1>(0h0))
node _in_vc_sel_T_87 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[7], UInt<1>(0h0))
node _in_vc_sel_T_88 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[7], UInt<1>(0h0))
node _in_vc_sel_T_89 = or(_in_vc_sel_T_83, _in_vc_sel_T_84)
node _in_vc_sel_T_90 = or(_in_vc_sel_T_89, _in_vc_sel_T_85)
node _in_vc_sel_T_91 = or(_in_vc_sel_T_90, _in_vc_sel_T_86)
node _in_vc_sel_T_92 = or(_in_vc_sel_T_91, _in_vc_sel_T_87)
node _in_vc_sel_T_93 = or(_in_vc_sel_T_92, _in_vc_sel_T_88)
wire _in_vc_sel_WIRE_8 : UInt<1>
connect _in_vc_sel_WIRE_8, _in_vc_sel_T_93
connect _in_vc_sel_WIRE[7], _in_vc_sel_WIRE_8
node _in_vc_sel_T_94 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[8], UInt<1>(0h0))
node _in_vc_sel_T_95 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[8], UInt<1>(0h0))
node _in_vc_sel_T_96 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[8], UInt<1>(0h0))
node _in_vc_sel_T_97 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[8], UInt<1>(0h0))
node _in_vc_sel_T_98 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[8], UInt<1>(0h0))
node _in_vc_sel_T_99 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[8], UInt<1>(0h0))
node _in_vc_sel_T_100 = or(_in_vc_sel_T_94, _in_vc_sel_T_95)
node _in_vc_sel_T_101 = or(_in_vc_sel_T_100, _in_vc_sel_T_96)
node _in_vc_sel_T_102 = or(_in_vc_sel_T_101, _in_vc_sel_T_97)
node _in_vc_sel_T_103 = or(_in_vc_sel_T_102, _in_vc_sel_T_98)
node _in_vc_sel_T_104 = or(_in_vc_sel_T_103, _in_vc_sel_T_99)
wire _in_vc_sel_WIRE_9 : UInt<1>
connect _in_vc_sel_WIRE_9, _in_vc_sel_T_104
connect _in_vc_sel_WIRE[8], _in_vc_sel_WIRE_9
node _in_vc_sel_T_105 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[9], UInt<1>(0h0))
node _in_vc_sel_T_106 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[9], UInt<1>(0h0))
node _in_vc_sel_T_107 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[9], UInt<1>(0h0))
node _in_vc_sel_T_108 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[9], UInt<1>(0h0))
node _in_vc_sel_T_109 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[9], UInt<1>(0h0))
node _in_vc_sel_T_110 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[9], UInt<1>(0h0))
node _in_vc_sel_T_111 = or(_in_vc_sel_T_105, _in_vc_sel_T_106)
node _in_vc_sel_T_112 = or(_in_vc_sel_T_111, _in_vc_sel_T_107)
node _in_vc_sel_T_113 = or(_in_vc_sel_T_112, _in_vc_sel_T_108)
node _in_vc_sel_T_114 = or(_in_vc_sel_T_113, _in_vc_sel_T_109)
node _in_vc_sel_T_115 = or(_in_vc_sel_T_114, _in_vc_sel_T_110)
wire _in_vc_sel_WIRE_10 : UInt<1>
connect _in_vc_sel_WIRE_10, _in_vc_sel_T_115
connect _in_vc_sel_WIRE[9], _in_vc_sel_WIRE_10
connect in_vc_sel.`0`, _in_vc_sel_WIRE
wire _in_vc_sel_WIRE_11 : UInt<1>[1]
node _in_vc_sel_T_116 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_117 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_118 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_119 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_120 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_121 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_122 = or(_in_vc_sel_T_116, _in_vc_sel_T_117)
node _in_vc_sel_T_123 = or(_in_vc_sel_T_122, _in_vc_sel_T_118)
node _in_vc_sel_T_124 = or(_in_vc_sel_T_123, _in_vc_sel_T_119)
node _in_vc_sel_T_125 = or(_in_vc_sel_T_124, _in_vc_sel_T_120)
node _in_vc_sel_T_126 = or(_in_vc_sel_T_125, _in_vc_sel_T_121)
wire _in_vc_sel_WIRE_12 : UInt<1>
connect _in_vc_sel_WIRE_12, _in_vc_sel_T_126
connect _in_vc_sel_WIRE_11[0], _in_vc_sel_WIRE_12
connect in_vc_sel.`1`, _in_vc_sel_WIRE_11
wire _in_vc_sel_WIRE_13 : UInt<1>[1]
node _in_vc_sel_T_127 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_128 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_129 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_130 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_131 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_132 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_133 = or(_in_vc_sel_T_127, _in_vc_sel_T_128)
node _in_vc_sel_T_134 = or(_in_vc_sel_T_133, _in_vc_sel_T_129)
node _in_vc_sel_T_135 = or(_in_vc_sel_T_134, _in_vc_sel_T_130)
node _in_vc_sel_T_136 = or(_in_vc_sel_T_135, _in_vc_sel_T_131)
node _in_vc_sel_T_137 = or(_in_vc_sel_T_136, _in_vc_sel_T_132)
wire _in_vc_sel_WIRE_14 : UInt<1>
connect _in_vc_sel_WIRE_14, _in_vc_sel_T_137
connect _in_vc_sel_WIRE_13[0], _in_vc_sel_WIRE_14
connect in_vc_sel.`2`, _in_vc_sel_WIRE_13
wire _in_vc_sel_WIRE_15 : UInt<1>[1]
node _in_vc_sel_T_138 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_139 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_140 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_141 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_142 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_143 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_144 = or(_in_vc_sel_T_138, _in_vc_sel_T_139)
node _in_vc_sel_T_145 = or(_in_vc_sel_T_144, _in_vc_sel_T_140)
node _in_vc_sel_T_146 = or(_in_vc_sel_T_145, _in_vc_sel_T_141)
node _in_vc_sel_T_147 = or(_in_vc_sel_T_146, _in_vc_sel_T_142)
node _in_vc_sel_T_148 = or(_in_vc_sel_T_147, _in_vc_sel_T_143)
wire _in_vc_sel_WIRE_16 : UInt<1>
connect _in_vc_sel_WIRE_16, _in_vc_sel_T_148
connect _in_vc_sel_WIRE_15[0], _in_vc_sel_WIRE_16
connect in_vc_sel.`3`, _in_vc_sel_WIRE_15
wire _in_vc_sel_WIRE_17 : UInt<1>[1]
node _in_vc_sel_T_149 = mux(_in_vc_sel_T, in_arb_reqs[0].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_150 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_151 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_152 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_153 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_154 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_155 = or(_in_vc_sel_T_149, _in_vc_sel_T_150)
node _in_vc_sel_T_156 = or(_in_vc_sel_T_155, _in_vc_sel_T_151)
node _in_vc_sel_T_157 = or(_in_vc_sel_T_156, _in_vc_sel_T_152)
node _in_vc_sel_T_158 = or(_in_vc_sel_T_157, _in_vc_sel_T_153)
node _in_vc_sel_T_159 = or(_in_vc_sel_T_158, _in_vc_sel_T_154)
wire _in_vc_sel_WIRE_18 : UInt<1>
connect _in_vc_sel_WIRE_18, _in_vc_sel_T_159
connect _in_vc_sel_WIRE_17[0], _in_vc_sel_WIRE_18
connect in_vc_sel.`4`, _in_vc_sel_WIRE_17
wire _in_vc_sel_WIRE_19 : UInt<1>[1]
node _in_vc_sel_T_160 = mux(_in_vc_sel_T, in_arb_reqs[0].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_161 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_162 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_163 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_164 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_165 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_166 = or(_in_vc_sel_T_160, _in_vc_sel_T_161)
node _in_vc_sel_T_167 = or(_in_vc_sel_T_166, _in_vc_sel_T_162)
node _in_vc_sel_T_168 = or(_in_vc_sel_T_167, _in_vc_sel_T_163)
node _in_vc_sel_T_169 = or(_in_vc_sel_T_168, _in_vc_sel_T_164)
node _in_vc_sel_T_170 = or(_in_vc_sel_T_169, _in_vc_sel_T_165)
wire _in_vc_sel_WIRE_20 : UInt<1>
connect _in_vc_sel_WIRE_20, _in_vc_sel_T_170
connect _in_vc_sel_WIRE_19[0], _in_vc_sel_WIRE_20
connect in_vc_sel.`5`, _in_vc_sel_WIRE_19
node _T_5 = or(in_arb_vals[0], in_arb_vals[1])
node _T_6 = or(_T_5, in_arb_vals[2])
node _T_7 = or(_T_6, in_arb_vals[3])
node _T_8 = or(_T_7, in_arb_vals[4])
node _T_9 = or(_T_8, in_arb_vals[5])
node hi = bits(in_arb_sel, 5, 4)
node lo = bits(in_arb_sel, 3, 0)
node _T_10 = orr(hi)
node _T_11 = or(hi, lo)
node hi_1 = bits(_T_11, 3, 2)
node lo_1 = bits(_T_11, 1, 0)
node _T_12 = orr(hi_1)
node _T_13 = or(hi_1, lo_1)
node _T_14 = bits(_T_13, 1, 1)
node _T_15 = cat(_T_12, _T_14)
node _T_16 = cat(_T_10, _T_15)
node _T_17 = and(io.req.`0`.ready, io.req.`0`.valid)
node _T_18 = and(io.req.`1`.ready, io.req.`1`.valid)
node _T_19 = and(io.req.`2`.ready, io.req.`2`.valid)
node _T_20 = and(io.req.`3`.ready, io.req.`3`.valid)
node _T_21 = and(io.req.`4`.ready, io.req.`4`.valid)
node _T_22 = and(io.req.`5`.ready, io.req.`5`.valid)
node _T_23 = or(_T_17, _T_18)
node _T_24 = or(_T_23, _T_19)
node _T_25 = or(_T_24, _T_20)
node _T_26 = or(_T_25, _T_21)
node _T_27 = or(_T_26, _T_22)
node lo_lo = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0])
node lo_hi_hi = cat(in_vc_sel.`0`[4], in_vc_sel.`0`[3])
node lo_hi = cat(lo_hi_hi, in_vc_sel.`0`[2])
node lo_2 = cat(lo_hi, lo_lo)
node hi_lo = cat(in_vc_sel.`0`[6], in_vc_sel.`0`[5])
node hi_hi_hi = cat(in_vc_sel.`0`[9], in_vc_sel.`0`[8])
node hi_hi = cat(hi_hi_hi, in_vc_sel.`0`[7])
node hi_2 = cat(hi_hi, hi_lo)
node _T_28 = cat(hi_2, lo_2)
node lo_hi_1 = cat(in_vc_sel.`2`[0], in_vc_sel.`1`[0])
node lo_3 = cat(lo_hi_1, _T_28)
node hi_hi_1 = cat(in_vc_sel.`5`[0], in_vc_sel.`4`[0])
node hi_3 = cat(hi_hi_1, in_vc_sel.`3`[0])
node _T_29 = cat(hi_3, lo_3)
regreset mask_1 : UInt<15>, clock, reset, UInt<15>(0h0)
node _full_T = not(mask_1)
node _full_T_1 = and(_T_29, _full_T)
node full = cat(_T_29, _full_T_1)
node _oh_T = bits(full, 0, 0)
node _oh_T_1 = bits(full, 1, 1)
node _oh_T_2 = bits(full, 2, 2)
node _oh_T_3 = bits(full, 3, 3)
node _oh_T_4 = bits(full, 4, 4)
node _oh_T_5 = bits(full, 5, 5)
node _oh_T_6 = bits(full, 6, 6)
node _oh_T_7 = bits(full, 7, 7)
node _oh_T_8 = bits(full, 8, 8)
node _oh_T_9 = bits(full, 9, 9)
node _oh_T_10 = bits(full, 10, 10)
node _oh_T_11 = bits(full, 11, 11)
node _oh_T_12 = bits(full, 12, 12)
node _oh_T_13 = bits(full, 13, 13)
node _oh_T_14 = bits(full, 14, 14)
node _oh_T_15 = bits(full, 15, 15)
node _oh_T_16 = bits(full, 16, 16)
node _oh_T_17 = bits(full, 17, 17)
node _oh_T_18 = bits(full, 18, 18)
node _oh_T_19 = bits(full, 19, 19)
node _oh_T_20 = bits(full, 20, 20)
node _oh_T_21 = bits(full, 21, 21)
node _oh_T_22 = bits(full, 22, 22)
node _oh_T_23 = bits(full, 23, 23)
node _oh_T_24 = bits(full, 24, 24)
node _oh_T_25 = bits(full, 25, 25)
node _oh_T_26 = bits(full, 26, 26)
node _oh_T_27 = bits(full, 27, 27)
node _oh_T_28 = bits(full, 28, 28)
node _oh_T_29 = bits(full, 29, 29)
node _oh_T_30 = mux(_oh_T_29, UInt<30>(0h20000000), UInt<30>(0h0))
node _oh_T_31 = mux(_oh_T_28, UInt<30>(0h10000000), _oh_T_30)
node _oh_T_32 = mux(_oh_T_27, UInt<30>(0h8000000), _oh_T_31)
node _oh_T_33 = mux(_oh_T_26, UInt<30>(0h4000000), _oh_T_32)
node _oh_T_34 = mux(_oh_T_25, UInt<30>(0h2000000), _oh_T_33)
node _oh_T_35 = mux(_oh_T_24, UInt<30>(0h1000000), _oh_T_34)
node _oh_T_36 = mux(_oh_T_23, UInt<30>(0h800000), _oh_T_35)
node _oh_T_37 = mux(_oh_T_22, UInt<30>(0h400000), _oh_T_36)
node _oh_T_38 = mux(_oh_T_21, UInt<30>(0h200000), _oh_T_37)
node _oh_T_39 = mux(_oh_T_20, UInt<30>(0h100000), _oh_T_38)
node _oh_T_40 = mux(_oh_T_19, UInt<30>(0h80000), _oh_T_39)
node _oh_T_41 = mux(_oh_T_18, UInt<30>(0h40000), _oh_T_40)
node _oh_T_42 = mux(_oh_T_17, UInt<30>(0h20000), _oh_T_41)
node _oh_T_43 = mux(_oh_T_16, UInt<30>(0h10000), _oh_T_42)
node _oh_T_44 = mux(_oh_T_15, UInt<30>(0h8000), _oh_T_43)
node _oh_T_45 = mux(_oh_T_14, UInt<30>(0h4000), _oh_T_44)
node _oh_T_46 = mux(_oh_T_13, UInt<30>(0h2000), _oh_T_45)
node _oh_T_47 = mux(_oh_T_12, UInt<30>(0h1000), _oh_T_46)
node _oh_T_48 = mux(_oh_T_11, UInt<30>(0h800), _oh_T_47)
node _oh_T_49 = mux(_oh_T_10, UInt<30>(0h400), _oh_T_48)
node _oh_T_50 = mux(_oh_T_9, UInt<30>(0h200), _oh_T_49)
node _oh_T_51 = mux(_oh_T_8, UInt<30>(0h100), _oh_T_50)
node _oh_T_52 = mux(_oh_T_7, UInt<30>(0h80), _oh_T_51)
node _oh_T_53 = mux(_oh_T_6, UInt<30>(0h40), _oh_T_52)
node _oh_T_54 = mux(_oh_T_5, UInt<30>(0h20), _oh_T_53)
node _oh_T_55 = mux(_oh_T_4, UInt<30>(0h10), _oh_T_54)
node _oh_T_56 = mux(_oh_T_3, UInt<30>(0h8), _oh_T_55)
node _oh_T_57 = mux(_oh_T_2, UInt<30>(0h4), _oh_T_56)
node _oh_T_58 = mux(_oh_T_1, UInt<30>(0h2), _oh_T_57)
node oh = mux(_oh_T, UInt<30>(0h1), _oh_T_58)
node _sel_T = bits(oh, 14, 0)
node _sel_T_1 = shr(oh, 15)
node sel = or(_sel_T, _sel_T_1)
when _T_27 :
node _mask_T_23 = bits(sel, 0, 0)
node _mask_T_24 = not(UInt<1>(0h0))
node _mask_T_25 = bits(sel, 1, 1)
node _mask_T_26 = not(UInt<2>(0h0))
node _mask_T_27 = bits(sel, 2, 2)
node _mask_T_28 = not(UInt<3>(0h0))
node _mask_T_29 = bits(sel, 3, 3)
node _mask_T_30 = not(UInt<4>(0h0))
node _mask_T_31 = bits(sel, 4, 4)
node _mask_T_32 = not(UInt<5>(0h0))
node _mask_T_33 = bits(sel, 5, 5)
node _mask_T_34 = not(UInt<6>(0h0))
node _mask_T_35 = bits(sel, 6, 6)
node _mask_T_36 = not(UInt<7>(0h0))
node _mask_T_37 = bits(sel, 7, 7)
node _mask_T_38 = not(UInt<8>(0h0))
node _mask_T_39 = bits(sel, 8, 8)
node _mask_T_40 = not(UInt<9>(0h0))
node _mask_T_41 = bits(sel, 9, 9)
node _mask_T_42 = not(UInt<10>(0h0))
node _mask_T_43 = bits(sel, 10, 10)
node _mask_T_44 = not(UInt<11>(0h0))
node _mask_T_45 = bits(sel, 11, 11)
node _mask_T_46 = not(UInt<12>(0h0))
node _mask_T_47 = bits(sel, 12, 12)
node _mask_T_48 = not(UInt<13>(0h0))
node _mask_T_49 = bits(sel, 13, 13)
node _mask_T_50 = not(UInt<14>(0h0))
node _mask_T_51 = bits(sel, 14, 14)
node _mask_T_52 = not(UInt<15>(0h0))
node _mask_T_53 = mux(_mask_T_51, _mask_T_52, UInt<1>(0h0))
node _mask_T_54 = mux(_mask_T_49, _mask_T_50, _mask_T_53)
node _mask_T_55 = mux(_mask_T_47, _mask_T_48, _mask_T_54)
node _mask_T_56 = mux(_mask_T_45, _mask_T_46, _mask_T_55)
node _mask_T_57 = mux(_mask_T_43, _mask_T_44, _mask_T_56)
node _mask_T_58 = mux(_mask_T_41, _mask_T_42, _mask_T_57)
node _mask_T_59 = mux(_mask_T_39, _mask_T_40, _mask_T_58)
node _mask_T_60 = mux(_mask_T_37, _mask_T_38, _mask_T_59)
node _mask_T_61 = mux(_mask_T_35, _mask_T_36, _mask_T_60)
node _mask_T_62 = mux(_mask_T_33, _mask_T_34, _mask_T_61)
node _mask_T_63 = mux(_mask_T_31, _mask_T_32, _mask_T_62)
node _mask_T_64 = mux(_mask_T_29, _mask_T_30, _mask_T_63)
node _mask_T_65 = mux(_mask_T_27, _mask_T_28, _mask_T_64)
node _mask_T_66 = mux(_mask_T_25, _mask_T_26, _mask_T_65)
node _mask_T_67 = mux(_mask_T_23, _mask_T_24, _mask_T_66)
connect mask_1, _mask_T_67
wire _WIRE : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}
wire _WIRE_1 : UInt<15>
connect _WIRE_1, sel
node _T_30 = bits(_WIRE_1, 0, 0)
connect _WIRE.`0`[0], _T_30
node _T_31 = bits(_WIRE_1, 1, 1)
connect _WIRE.`0`[1], _T_31
node _T_32 = bits(_WIRE_1, 2, 2)
connect _WIRE.`0`[2], _T_32
node _T_33 = bits(_WIRE_1, 3, 3)
connect _WIRE.`0`[3], _T_33
node _T_34 = bits(_WIRE_1, 4, 4)
connect _WIRE.`0`[4], _T_34
node _T_35 = bits(_WIRE_1, 5, 5)
connect _WIRE.`0`[5], _T_35
node _T_36 = bits(_WIRE_1, 6, 6)
connect _WIRE.`0`[6], _T_36
node _T_37 = bits(_WIRE_1, 7, 7)
connect _WIRE.`0`[7], _T_37
node _T_38 = bits(_WIRE_1, 8, 8)
connect _WIRE.`0`[8], _T_38
node _T_39 = bits(_WIRE_1, 9, 9)
connect _WIRE.`0`[9], _T_39
node _T_40 = bits(_WIRE_1, 10, 10)
connect _WIRE.`1`[0], _T_40
node _T_41 = bits(_WIRE_1, 11, 11)
connect _WIRE.`2`[0], _T_41
node _T_42 = bits(_WIRE_1, 12, 12)
connect _WIRE.`3`[0], _T_42
node _T_43 = bits(_WIRE_1, 13, 13)
connect _WIRE.`4`[0], _T_43
node _T_44 = bits(_WIRE_1, 14, 14)
connect _WIRE.`5`[0], _T_44
wire _WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}
connect _WIRE_2.`0`[0], UInt<1>(0h0)
connect _WIRE_2.`0`[1], UInt<1>(0h0)
connect _WIRE_2.`0`[2], UInt<1>(0h0)
connect _WIRE_2.`0`[3], UInt<1>(0h0)
connect _WIRE_2.`0`[4], UInt<1>(0h0)
connect _WIRE_2.`0`[5], UInt<1>(0h0)
connect _WIRE_2.`0`[6], UInt<1>(0h0)
connect _WIRE_2.`0`[7], UInt<1>(0h0)
connect _WIRE_2.`0`[8], UInt<1>(0h0)
connect _WIRE_2.`0`[9], UInt<1>(0h0)
connect _WIRE_2.`1`[0], UInt<1>(0h0)
connect _WIRE_2.`2`[0], UInt<1>(0h0)
connect _WIRE_2.`3`[0], UInt<1>(0h0)
connect _WIRE_2.`4`[0], UInt<1>(0h0)
connect _WIRE_2.`5`[0], UInt<1>(0h0)
node _T_45 = mux(_T_9, _WIRE, _WIRE_2)
connect in_alloc.`0`, _T_45.`0`
connect in_alloc.`1`, _T_45.`1`
connect in_alloc.`2`, _T_45.`2`
connect in_alloc.`3`, _T_45.`3`
connect in_alloc.`4`, _T_45.`4`
connect in_alloc.`5`, _T_45.`5`
node _io_req_0_ready_T = bits(in_arb_sel, 0, 0)
connect io.req.`0`.ready, _io_req_0_ready_T
connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`0`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`0`.vc_sel.`0`[6], in_alloc.`0`[6]
connect io.resp.`0`.vc_sel.`0`[7], in_alloc.`0`[7]
connect io.resp.`0`.vc_sel.`0`[8], in_alloc.`0`[8]
connect io.resp.`0`.vc_sel.`0`[9], in_alloc.`0`[9]
connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`0`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`0`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`0`.vc_sel.`5`[0], in_alloc.`5`[0]
node lo_lo_1 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0])
node lo_hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[4], io.resp.`0`.vc_sel.`0`[3])
node lo_hi_2 = cat(lo_hi_hi_1, io.resp.`0`.vc_sel.`0`[2])
node lo_4 = cat(lo_hi_2, lo_lo_1)
node hi_lo_1 = cat(io.resp.`0`.vc_sel.`0`[6], io.resp.`0`.vc_sel.`0`[5])
node hi_hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[9], io.resp.`0`.vc_sel.`0`[8])
node hi_hi_2 = cat(hi_hi_hi_1, io.resp.`0`.vc_sel.`0`[7])
node hi_4 = cat(hi_hi_2, hi_lo_1)
node _T_46 = cat(hi_4, lo_4)
node lo_hi_3 = cat(io.resp.`0`.vc_sel.`2`[0], io.resp.`0`.vc_sel.`1`[0])
node lo_5 = cat(lo_hi_3, _T_46)
node hi_hi_3 = cat(io.resp.`0`.vc_sel.`5`[0], io.resp.`0`.vc_sel.`4`[0])
node hi_5 = cat(hi_hi_3, io.resp.`0`.vc_sel.`3`[0])
node _T_47 = cat(hi_5, lo_5)
node _T_48 = bits(_T_47, 0, 0)
node _T_49 = bits(_T_47, 1, 1)
node _T_50 = bits(_T_47, 2, 2)
node _T_51 = bits(_T_47, 3, 3)
node _T_52 = bits(_T_47, 4, 4)
node _T_53 = bits(_T_47, 5, 5)
node _T_54 = bits(_T_47, 6, 6)
node _T_55 = bits(_T_47, 7, 7)
node _T_56 = bits(_T_47, 8, 8)
node _T_57 = bits(_T_47, 9, 9)
node _T_58 = bits(_T_47, 10, 10)
node _T_59 = bits(_T_47, 11, 11)
node _T_60 = bits(_T_47, 12, 12)
node _T_61 = bits(_T_47, 13, 13)
node _T_62 = bits(_T_47, 14, 14)
node _T_63 = add(_T_49, _T_50)
node _T_64 = bits(_T_63, 1, 0)
node _T_65 = add(_T_48, _T_64)
node _T_66 = bits(_T_65, 1, 0)
node _T_67 = add(_T_51, _T_52)
node _T_68 = bits(_T_67, 1, 0)
node _T_69 = add(_T_53, _T_54)
node _T_70 = bits(_T_69, 1, 0)
node _T_71 = add(_T_68, _T_70)
node _T_72 = bits(_T_71, 2, 0)
node _T_73 = add(_T_66, _T_72)
node _T_74 = bits(_T_73, 2, 0)
node _T_75 = add(_T_55, _T_56)
node _T_76 = bits(_T_75, 1, 0)
node _T_77 = add(_T_57, _T_58)
node _T_78 = bits(_T_77, 1, 0)
node _T_79 = add(_T_76, _T_78)
node _T_80 = bits(_T_79, 2, 0)
node _T_81 = add(_T_59, _T_60)
node _T_82 = bits(_T_81, 1, 0)
node _T_83 = add(_T_61, _T_62)
node _T_84 = bits(_T_83, 1, 0)
node _T_85 = add(_T_82, _T_84)
node _T_86 = bits(_T_85, 2, 0)
node _T_87 = add(_T_80, _T_86)
node _T_88 = bits(_T_87, 3, 0)
node _T_89 = add(_T_74, _T_88)
node _T_90 = bits(_T_89, 3, 0)
node _T_91 = leq(_T_90, UInt<1>(0h1))
node _T_92 = asUInt(reset)
node _T_93 = eq(_T_92, UInt<1>(0h0))
when _T_93 :
node _T_94 = eq(_T_91, UInt<1>(0h0))
when _T_94 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf
assert(clock, _T_91, UInt<1>(0h1), "") : assert
node _io_req_1_ready_T = bits(in_arb_sel, 1, 1)
connect io.req.`1`.ready, _io_req_1_ready_T
connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`1`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`1`.vc_sel.`0`[6], in_alloc.`0`[6]
connect io.resp.`1`.vc_sel.`0`[7], in_alloc.`0`[7]
connect io.resp.`1`.vc_sel.`0`[8], in_alloc.`0`[8]
connect io.resp.`1`.vc_sel.`0`[9], in_alloc.`0`[9]
connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`1`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`1`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`1`.vc_sel.`5`[0], in_alloc.`5`[0]
node lo_lo_2 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0])
node lo_hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[4], io.resp.`1`.vc_sel.`0`[3])
node lo_hi_4 = cat(lo_hi_hi_2, io.resp.`1`.vc_sel.`0`[2])
node lo_6 = cat(lo_hi_4, lo_lo_2)
node hi_lo_2 = cat(io.resp.`1`.vc_sel.`0`[6], io.resp.`1`.vc_sel.`0`[5])
node hi_hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[9], io.resp.`1`.vc_sel.`0`[8])
node hi_hi_4 = cat(hi_hi_hi_2, io.resp.`1`.vc_sel.`0`[7])
node hi_6 = cat(hi_hi_4, hi_lo_2)
node _T_95 = cat(hi_6, lo_6)
node lo_hi_5 = cat(io.resp.`1`.vc_sel.`2`[0], io.resp.`1`.vc_sel.`1`[0])
node lo_7 = cat(lo_hi_5, _T_95)
node hi_hi_5 = cat(io.resp.`1`.vc_sel.`5`[0], io.resp.`1`.vc_sel.`4`[0])
node hi_7 = cat(hi_hi_5, io.resp.`1`.vc_sel.`3`[0])
node _T_96 = cat(hi_7, lo_7)
node _T_97 = bits(_T_96, 0, 0)
node _T_98 = bits(_T_96, 1, 1)
node _T_99 = bits(_T_96, 2, 2)
node _T_100 = bits(_T_96, 3, 3)
node _T_101 = bits(_T_96, 4, 4)
node _T_102 = bits(_T_96, 5, 5)
node _T_103 = bits(_T_96, 6, 6)
node _T_104 = bits(_T_96, 7, 7)
node _T_105 = bits(_T_96, 8, 8)
node _T_106 = bits(_T_96, 9, 9)
node _T_107 = bits(_T_96, 10, 10)
node _T_108 = bits(_T_96, 11, 11)
node _T_109 = bits(_T_96, 12, 12)
node _T_110 = bits(_T_96, 13, 13)
node _T_111 = bits(_T_96, 14, 14)
node _T_112 = add(_T_98, _T_99)
node _T_113 = bits(_T_112, 1, 0)
node _T_114 = add(_T_97, _T_113)
node _T_115 = bits(_T_114, 1, 0)
node _T_116 = add(_T_100, _T_101)
node _T_117 = bits(_T_116, 1, 0)
node _T_118 = add(_T_102, _T_103)
node _T_119 = bits(_T_118, 1, 0)
node _T_120 = add(_T_117, _T_119)
node _T_121 = bits(_T_120, 2, 0)
node _T_122 = add(_T_115, _T_121)
node _T_123 = bits(_T_122, 2, 0)
node _T_124 = add(_T_104, _T_105)
node _T_125 = bits(_T_124, 1, 0)
node _T_126 = add(_T_106, _T_107)
node _T_127 = bits(_T_126, 1, 0)
node _T_128 = add(_T_125, _T_127)
node _T_129 = bits(_T_128, 2, 0)
node _T_130 = add(_T_108, _T_109)
node _T_131 = bits(_T_130, 1, 0)
node _T_132 = add(_T_110, _T_111)
node _T_133 = bits(_T_132, 1, 0)
node _T_134 = add(_T_131, _T_133)
node _T_135 = bits(_T_134, 2, 0)
node _T_136 = add(_T_129, _T_135)
node _T_137 = bits(_T_136, 3, 0)
node _T_138 = add(_T_123, _T_137)
node _T_139 = bits(_T_138, 3, 0)
node _T_140 = leq(_T_139, UInt<1>(0h1))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1
assert(clock, _T_140, UInt<1>(0h1), "") : assert_1
node _io_req_2_ready_T = bits(in_arb_sel, 2, 2)
connect io.req.`2`.ready, _io_req_2_ready_T
connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`2`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`2`.vc_sel.`0`[6], in_alloc.`0`[6]
connect io.resp.`2`.vc_sel.`0`[7], in_alloc.`0`[7]
connect io.resp.`2`.vc_sel.`0`[8], in_alloc.`0`[8]
connect io.resp.`2`.vc_sel.`0`[9], in_alloc.`0`[9]
connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`2`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`2`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`2`.vc_sel.`5`[0], in_alloc.`5`[0]
node lo_lo_3 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0])
node lo_hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[4], io.resp.`2`.vc_sel.`0`[3])
node lo_hi_6 = cat(lo_hi_hi_3, io.resp.`2`.vc_sel.`0`[2])
node lo_8 = cat(lo_hi_6, lo_lo_3)
node hi_lo_3 = cat(io.resp.`2`.vc_sel.`0`[6], io.resp.`2`.vc_sel.`0`[5])
node hi_hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[9], io.resp.`2`.vc_sel.`0`[8])
node hi_hi_6 = cat(hi_hi_hi_3, io.resp.`2`.vc_sel.`0`[7])
node hi_8 = cat(hi_hi_6, hi_lo_3)
node _T_144 = cat(hi_8, lo_8)
node lo_hi_7 = cat(io.resp.`2`.vc_sel.`2`[0], io.resp.`2`.vc_sel.`1`[0])
node lo_9 = cat(lo_hi_7, _T_144)
node hi_hi_7 = cat(io.resp.`2`.vc_sel.`5`[0], io.resp.`2`.vc_sel.`4`[0])
node hi_9 = cat(hi_hi_7, io.resp.`2`.vc_sel.`3`[0])
node _T_145 = cat(hi_9, lo_9)
node _T_146 = bits(_T_145, 0, 0)
node _T_147 = bits(_T_145, 1, 1)
node _T_148 = bits(_T_145, 2, 2)
node _T_149 = bits(_T_145, 3, 3)
node _T_150 = bits(_T_145, 4, 4)
node _T_151 = bits(_T_145, 5, 5)
node _T_152 = bits(_T_145, 6, 6)
node _T_153 = bits(_T_145, 7, 7)
node _T_154 = bits(_T_145, 8, 8)
node _T_155 = bits(_T_145, 9, 9)
node _T_156 = bits(_T_145, 10, 10)
node _T_157 = bits(_T_145, 11, 11)
node _T_158 = bits(_T_145, 12, 12)
node _T_159 = bits(_T_145, 13, 13)
node _T_160 = bits(_T_145, 14, 14)
node _T_161 = add(_T_147, _T_148)
node _T_162 = bits(_T_161, 1, 0)
node _T_163 = add(_T_146, _T_162)
node _T_164 = bits(_T_163, 1, 0)
node _T_165 = add(_T_149, _T_150)
node _T_166 = bits(_T_165, 1, 0)
node _T_167 = add(_T_151, _T_152)
node _T_168 = bits(_T_167, 1, 0)
node _T_169 = add(_T_166, _T_168)
node _T_170 = bits(_T_169, 2, 0)
node _T_171 = add(_T_164, _T_170)
node _T_172 = bits(_T_171, 2, 0)
node _T_173 = add(_T_153, _T_154)
node _T_174 = bits(_T_173, 1, 0)
node _T_175 = add(_T_155, _T_156)
node _T_176 = bits(_T_175, 1, 0)
node _T_177 = add(_T_174, _T_176)
node _T_178 = bits(_T_177, 2, 0)
node _T_179 = add(_T_157, _T_158)
node _T_180 = bits(_T_179, 1, 0)
node _T_181 = add(_T_159, _T_160)
node _T_182 = bits(_T_181, 1, 0)
node _T_183 = add(_T_180, _T_182)
node _T_184 = bits(_T_183, 2, 0)
node _T_185 = add(_T_178, _T_184)
node _T_186 = bits(_T_185, 3, 0)
node _T_187 = add(_T_172, _T_186)
node _T_188 = bits(_T_187, 3, 0)
node _T_189 = leq(_T_188, UInt<1>(0h1))
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2
assert(clock, _T_189, UInt<1>(0h1), "") : assert_2
node _io_req_3_ready_T = bits(in_arb_sel, 3, 3)
connect io.req.`3`.ready, _io_req_3_ready_T
connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`3`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`3`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`3`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`3`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`3`.vc_sel.`0`[6], in_alloc.`0`[6]
connect io.resp.`3`.vc_sel.`0`[7], in_alloc.`0`[7]
connect io.resp.`3`.vc_sel.`0`[8], in_alloc.`0`[8]
connect io.resp.`3`.vc_sel.`0`[9], in_alloc.`0`[9]
connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`3`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`3`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`3`.vc_sel.`5`[0], in_alloc.`5`[0]
node lo_lo_4 = cat(io.resp.`3`.vc_sel.`0`[1], io.resp.`3`.vc_sel.`0`[0])
node lo_hi_hi_4 = cat(io.resp.`3`.vc_sel.`0`[4], io.resp.`3`.vc_sel.`0`[3])
node lo_hi_8 = cat(lo_hi_hi_4, io.resp.`3`.vc_sel.`0`[2])
node lo_10 = cat(lo_hi_8, lo_lo_4)
node hi_lo_4 = cat(io.resp.`3`.vc_sel.`0`[6], io.resp.`3`.vc_sel.`0`[5])
node hi_hi_hi_4 = cat(io.resp.`3`.vc_sel.`0`[9], io.resp.`3`.vc_sel.`0`[8])
node hi_hi_8 = cat(hi_hi_hi_4, io.resp.`3`.vc_sel.`0`[7])
node hi_10 = cat(hi_hi_8, hi_lo_4)
node _T_193 = cat(hi_10, lo_10)
node lo_hi_9 = cat(io.resp.`3`.vc_sel.`2`[0], io.resp.`3`.vc_sel.`1`[0])
node lo_11 = cat(lo_hi_9, _T_193)
node hi_hi_9 = cat(io.resp.`3`.vc_sel.`5`[0], io.resp.`3`.vc_sel.`4`[0])
node hi_11 = cat(hi_hi_9, io.resp.`3`.vc_sel.`3`[0])
node _T_194 = cat(hi_11, lo_11)
node _T_195 = bits(_T_194, 0, 0)
node _T_196 = bits(_T_194, 1, 1)
node _T_197 = bits(_T_194, 2, 2)
node _T_198 = bits(_T_194, 3, 3)
node _T_199 = bits(_T_194, 4, 4)
node _T_200 = bits(_T_194, 5, 5)
node _T_201 = bits(_T_194, 6, 6)
node _T_202 = bits(_T_194, 7, 7)
node _T_203 = bits(_T_194, 8, 8)
node _T_204 = bits(_T_194, 9, 9)
node _T_205 = bits(_T_194, 10, 10)
node _T_206 = bits(_T_194, 11, 11)
node _T_207 = bits(_T_194, 12, 12)
node _T_208 = bits(_T_194, 13, 13)
node _T_209 = bits(_T_194, 14, 14)
node _T_210 = add(_T_196, _T_197)
node _T_211 = bits(_T_210, 1, 0)
node _T_212 = add(_T_195, _T_211)
node _T_213 = bits(_T_212, 1, 0)
node _T_214 = add(_T_198, _T_199)
node _T_215 = bits(_T_214, 1, 0)
node _T_216 = add(_T_200, _T_201)
node _T_217 = bits(_T_216, 1, 0)
node _T_218 = add(_T_215, _T_217)
node _T_219 = bits(_T_218, 2, 0)
node _T_220 = add(_T_213, _T_219)
node _T_221 = bits(_T_220, 2, 0)
node _T_222 = add(_T_202, _T_203)
node _T_223 = bits(_T_222, 1, 0)
node _T_224 = add(_T_204, _T_205)
node _T_225 = bits(_T_224, 1, 0)
node _T_226 = add(_T_223, _T_225)
node _T_227 = bits(_T_226, 2, 0)
node _T_228 = add(_T_206, _T_207)
node _T_229 = bits(_T_228, 1, 0)
node _T_230 = add(_T_208, _T_209)
node _T_231 = bits(_T_230, 1, 0)
node _T_232 = add(_T_229, _T_231)
node _T_233 = bits(_T_232, 2, 0)
node _T_234 = add(_T_227, _T_233)
node _T_235 = bits(_T_234, 3, 0)
node _T_236 = add(_T_221, _T_235)
node _T_237 = bits(_T_236, 3, 0)
node _T_238 = leq(_T_237, UInt<1>(0h1))
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(_T_238, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3
assert(clock, _T_238, UInt<1>(0h1), "") : assert_3
node _io_req_4_ready_T = bits(in_arb_sel, 4, 4)
connect io.req.`4`.ready, _io_req_4_ready_T
connect io.resp.`4`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`4`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`4`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`4`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`4`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`4`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`4`.vc_sel.`0`[6], in_alloc.`0`[6]
connect io.resp.`4`.vc_sel.`0`[7], in_alloc.`0`[7]
connect io.resp.`4`.vc_sel.`0`[8], in_alloc.`0`[8]
connect io.resp.`4`.vc_sel.`0`[9], in_alloc.`0`[9]
connect io.resp.`4`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`4`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`4`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`4`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`4`.vc_sel.`5`[0], in_alloc.`5`[0]
node lo_lo_5 = cat(io.resp.`4`.vc_sel.`0`[1], io.resp.`4`.vc_sel.`0`[0])
node lo_hi_hi_5 = cat(io.resp.`4`.vc_sel.`0`[4], io.resp.`4`.vc_sel.`0`[3])
node lo_hi_10 = cat(lo_hi_hi_5, io.resp.`4`.vc_sel.`0`[2])
node lo_12 = cat(lo_hi_10, lo_lo_5)
node hi_lo_5 = cat(io.resp.`4`.vc_sel.`0`[6], io.resp.`4`.vc_sel.`0`[5])
node hi_hi_hi_5 = cat(io.resp.`4`.vc_sel.`0`[9], io.resp.`4`.vc_sel.`0`[8])
node hi_hi_10 = cat(hi_hi_hi_5, io.resp.`4`.vc_sel.`0`[7])
node hi_12 = cat(hi_hi_10, hi_lo_5)
node _T_242 = cat(hi_12, lo_12)
node lo_hi_11 = cat(io.resp.`4`.vc_sel.`2`[0], io.resp.`4`.vc_sel.`1`[0])
node lo_13 = cat(lo_hi_11, _T_242)
node hi_hi_11 = cat(io.resp.`4`.vc_sel.`5`[0], io.resp.`4`.vc_sel.`4`[0])
node hi_13 = cat(hi_hi_11, io.resp.`4`.vc_sel.`3`[0])
node _T_243 = cat(hi_13, lo_13)
node _T_244 = bits(_T_243, 0, 0)
node _T_245 = bits(_T_243, 1, 1)
node _T_246 = bits(_T_243, 2, 2)
node _T_247 = bits(_T_243, 3, 3)
node _T_248 = bits(_T_243, 4, 4)
node _T_249 = bits(_T_243, 5, 5)
node _T_250 = bits(_T_243, 6, 6)
node _T_251 = bits(_T_243, 7, 7)
node _T_252 = bits(_T_243, 8, 8)
node _T_253 = bits(_T_243, 9, 9)
node _T_254 = bits(_T_243, 10, 10)
node _T_255 = bits(_T_243, 11, 11)
node _T_256 = bits(_T_243, 12, 12)
node _T_257 = bits(_T_243, 13, 13)
node _T_258 = bits(_T_243, 14, 14)
node _T_259 = add(_T_245, _T_246)
node _T_260 = bits(_T_259, 1, 0)
node _T_261 = add(_T_244, _T_260)
node _T_262 = bits(_T_261, 1, 0)
node _T_263 = add(_T_247, _T_248)
node _T_264 = bits(_T_263, 1, 0)
node _T_265 = add(_T_249, _T_250)
node _T_266 = bits(_T_265, 1, 0)
node _T_267 = add(_T_264, _T_266)
node _T_268 = bits(_T_267, 2, 0)
node _T_269 = add(_T_262, _T_268)
node _T_270 = bits(_T_269, 2, 0)
node _T_271 = add(_T_251, _T_252)
node _T_272 = bits(_T_271, 1, 0)
node _T_273 = add(_T_253, _T_254)
node _T_274 = bits(_T_273, 1, 0)
node _T_275 = add(_T_272, _T_274)
node _T_276 = bits(_T_275, 2, 0)
node _T_277 = add(_T_255, _T_256)
node _T_278 = bits(_T_277, 1, 0)
node _T_279 = add(_T_257, _T_258)
node _T_280 = bits(_T_279, 1, 0)
node _T_281 = add(_T_278, _T_280)
node _T_282 = bits(_T_281, 2, 0)
node _T_283 = add(_T_276, _T_282)
node _T_284 = bits(_T_283, 3, 0)
node _T_285 = add(_T_270, _T_284)
node _T_286 = bits(_T_285, 3, 0)
node _T_287 = leq(_T_286, UInt<1>(0h1))
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(_T_287, UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_4
assert(clock, _T_287, UInt<1>(0h1), "") : assert_4
node _io_req_5_ready_T = bits(in_arb_sel, 5, 5)
connect io.req.`5`.ready, _io_req_5_ready_T
connect io.resp.`5`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`5`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`5`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`5`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`5`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`5`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`5`.vc_sel.`0`[6], in_alloc.`0`[6]
connect io.resp.`5`.vc_sel.`0`[7], in_alloc.`0`[7]
connect io.resp.`5`.vc_sel.`0`[8], in_alloc.`0`[8]
connect io.resp.`5`.vc_sel.`0`[9], in_alloc.`0`[9]
connect io.resp.`5`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`5`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`5`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`5`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`5`.vc_sel.`5`[0], in_alloc.`5`[0]
node lo_lo_6 = cat(io.resp.`5`.vc_sel.`0`[1], io.resp.`5`.vc_sel.`0`[0])
node lo_hi_hi_6 = cat(io.resp.`5`.vc_sel.`0`[4], io.resp.`5`.vc_sel.`0`[3])
node lo_hi_12 = cat(lo_hi_hi_6, io.resp.`5`.vc_sel.`0`[2])
node lo_14 = cat(lo_hi_12, lo_lo_6)
node hi_lo_6 = cat(io.resp.`5`.vc_sel.`0`[6], io.resp.`5`.vc_sel.`0`[5])
node hi_hi_hi_6 = cat(io.resp.`5`.vc_sel.`0`[9], io.resp.`5`.vc_sel.`0`[8])
node hi_hi_12 = cat(hi_hi_hi_6, io.resp.`5`.vc_sel.`0`[7])
node hi_14 = cat(hi_hi_12, hi_lo_6)
node _T_291 = cat(hi_14, lo_14)
node lo_hi_13 = cat(io.resp.`5`.vc_sel.`2`[0], io.resp.`5`.vc_sel.`1`[0])
node lo_15 = cat(lo_hi_13, _T_291)
node hi_hi_13 = cat(io.resp.`5`.vc_sel.`5`[0], io.resp.`5`.vc_sel.`4`[0])
node hi_15 = cat(hi_hi_13, io.resp.`5`.vc_sel.`3`[0])
node _T_292 = cat(hi_15, lo_15)
node _T_293 = bits(_T_292, 0, 0)
node _T_294 = bits(_T_292, 1, 1)
node _T_295 = bits(_T_292, 2, 2)
node _T_296 = bits(_T_292, 3, 3)
node _T_297 = bits(_T_292, 4, 4)
node _T_298 = bits(_T_292, 5, 5)
node _T_299 = bits(_T_292, 6, 6)
node _T_300 = bits(_T_292, 7, 7)
node _T_301 = bits(_T_292, 8, 8)
node _T_302 = bits(_T_292, 9, 9)
node _T_303 = bits(_T_292, 10, 10)
node _T_304 = bits(_T_292, 11, 11)
node _T_305 = bits(_T_292, 12, 12)
node _T_306 = bits(_T_292, 13, 13)
node _T_307 = bits(_T_292, 14, 14)
node _T_308 = add(_T_294, _T_295)
node _T_309 = bits(_T_308, 1, 0)
node _T_310 = add(_T_293, _T_309)
node _T_311 = bits(_T_310, 1, 0)
node _T_312 = add(_T_296, _T_297)
node _T_313 = bits(_T_312, 1, 0)
node _T_314 = add(_T_298, _T_299)
node _T_315 = bits(_T_314, 1, 0)
node _T_316 = add(_T_313, _T_315)
node _T_317 = bits(_T_316, 2, 0)
node _T_318 = add(_T_311, _T_317)
node _T_319 = bits(_T_318, 2, 0)
node _T_320 = add(_T_300, _T_301)
node _T_321 = bits(_T_320, 1, 0)
node _T_322 = add(_T_302, _T_303)
node _T_323 = bits(_T_322, 1, 0)
node _T_324 = add(_T_321, _T_323)
node _T_325 = bits(_T_324, 2, 0)
node _T_326 = add(_T_304, _T_305)
node _T_327 = bits(_T_326, 1, 0)
node _T_328 = add(_T_306, _T_307)
node _T_329 = bits(_T_328, 1, 0)
node _T_330 = add(_T_327, _T_329)
node _T_331 = bits(_T_330, 2, 0)
node _T_332 = add(_T_325, _T_331)
node _T_333 = bits(_T_332, 3, 0)
node _T_334 = add(_T_319, _T_333)
node _T_335 = bits(_T_334, 3, 0)
node _T_336 = leq(_T_335, UInt<1>(0h1))
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(_T_336, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_5
assert(clock, _T_336, UInt<1>(0h1), "") : assert_5
connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0]
connect io.out_allocs.`0`[0].flow, in_flow
connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1]
connect io.out_allocs.`0`[1].flow, in_flow
connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2]
connect io.out_allocs.`0`[2].flow, in_flow
connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3]
connect io.out_allocs.`0`[3].flow, in_flow
connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4]
connect io.out_allocs.`0`[4].flow, in_flow
connect io.out_allocs.`0`[5].alloc, in_alloc.`0`[5]
connect io.out_allocs.`0`[5].flow, in_flow
connect io.out_allocs.`0`[6].alloc, in_alloc.`0`[6]
connect io.out_allocs.`0`[6].flow, in_flow
connect io.out_allocs.`0`[7].alloc, in_alloc.`0`[7]
connect io.out_allocs.`0`[7].flow, in_flow
connect io.out_allocs.`0`[8].alloc, in_alloc.`0`[8]
connect io.out_allocs.`0`[8].flow, in_flow
connect io.out_allocs.`0`[9].alloc, in_alloc.`0`[9]
connect io.out_allocs.`0`[9].flow, in_flow
connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0]
connect io.out_allocs.`1`[0].flow, in_flow
connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0]
connect io.out_allocs.`2`[0].flow, in_flow
connect io.out_allocs.`3`[0].alloc, in_alloc.`3`[0]
connect io.out_allocs.`3`[0].flow, in_flow
connect io.out_allocs.`4`[0].alloc, in_alloc.`4`[0]
connect io.out_allocs.`4`[0].flow, in_flow
connect io.out_allocs.`5`[0].alloc, in_alloc.`5`[0]
connect io.out_allocs.`5`[0].flow, in_flow | module RotatingSingleVCAllocator_4( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_5_ready, // @[VCAllocator.scala:49:14]
input io_req_5_valid, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_6, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_7, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_8, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_6, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_7, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_8, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_9, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_8, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_9, // @[VCAllocator.scala:49:14]
input io_channel_status_5_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_4_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_8_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_9_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_5_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_4_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_5_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_8_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_9_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_5; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [5:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [5:0] _in_arb_filter_T_3 = {in_arb_vals_5, 3'h0, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39]
wire [11:0] in_arb_filter = _in_arb_filter_T_3[0] ? 12'h1 : _in_arb_filter_T_3[1] ? 12'h2 : _in_arb_filter_T_3[2] ? 12'h4 : _in_arb_filter_T_3[3] ? 12'h8 : _in_arb_filter_T_3[4] ? 12'h10 : _in_arb_filter_T_3[5] ? 12'h20 : in_arb_vals_0 ? 12'h40 : in_arb_vals_1 ? 12'h80 : {in_arb_vals_5, 11'h0}; // @[OneHot.scala:85:71]
wire [5:0] in_arb_sel = in_arb_filter[5:0] | in_arb_filter[11:6]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_5; // @[package.scala:81:59]
wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_3 = io_req_0_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_4 = io_req_0_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_5 = io_req_0_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_8 = io_req_0_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_9 = io_req_0_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_4_0 = io_req_0_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_5_0 = io_req_0_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | in_arb_reqs_0_0_1 | io_req_0_bits_vc_sel_0_2 | in_arb_reqs_0_0_3 | in_arb_reqs_0_0_4 | in_arb_reqs_0_0_5 | in_arb_reqs_0_0_8 | in_arb_reqs_0_0_9 | in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0 | in_arb_reqs_0_3_0 | in_arb_reqs_0_4_0 | in_arb_reqs_0_5_0); // @[package.scala:81:59]
wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_8 = io_req_1_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_9 = io_req_1_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_4_0 = io_req_1_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_5_0 = io_req_1_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | in_arb_reqs_1_0_1 | io_req_1_bits_vc_sel_0_2 | in_arb_reqs_1_0_3 | in_arb_reqs_1_0_4 | in_arb_reqs_1_0_5 | io_req_1_bits_vc_sel_0_6 | io_req_1_bits_vc_sel_0_7 | in_arb_reqs_1_0_8 | in_arb_reqs_1_0_9 | in_arb_reqs_1_1_0 | in_arb_reqs_1_2_0 | in_arb_reqs_1_3_0 | in_arb_reqs_1_4_0 | in_arb_reqs_1_5_0); // @[package.scala:81:59]
wire in_arb_reqs_5_0_0 = io_req_5_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_1 = io_req_5_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_3 = io_req_5_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_4 = io_req_5_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_5 = io_req_5_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_8 = io_req_5_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_9 = io_req_5_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_1_0 = io_req_5_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_2_0 = io_req_5_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_3_0 = io_req_5_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_4_0 = io_req_5_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_5_0 = io_req_5_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_5 = io_req_5_valid & (in_arb_reqs_5_0_0 | in_arb_reqs_5_0_1 | io_req_5_bits_vc_sel_0_2 | in_arb_reqs_5_0_3 | in_arb_reqs_5_0_4 | in_arb_reqs_5_0_5 | io_req_5_bits_vc_sel_0_6 | io_req_5_bits_vc_sel_0_7 | in_arb_reqs_5_0_8 | in_arb_reqs_5_0_9 | in_arb_reqs_5_1_0 | in_arb_reqs_5_2_0 | in_arb_reqs_5_3_0 | in_arb_reqs_5_4_0 | in_arb_reqs_5_5_0); // @[package.scala:81:59]
wire _in_vc_sel_T_16 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0 | in_arb_sel[5] & in_arb_reqs_5_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_27 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[5] & in_arb_reqs_5_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_38 = in_arb_sel[0] & io_req_0_bits_vc_sel_0_2 | in_arb_sel[1] & io_req_1_bits_vc_sel_0_2 | in_arb_sel[5] & io_req_5_bits_vc_sel_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_49 = in_arb_sel[0] & in_arb_reqs_0_0_3 | in_arb_sel[1] & in_arb_reqs_1_0_3 | in_arb_sel[5] & in_arb_reqs_5_0_3; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_60 = in_arb_sel[0] & in_arb_reqs_0_0_4 | in_arb_sel[1] & in_arb_reqs_1_0_4 | in_arb_sel[5] & in_arb_reqs_5_0_4; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_71 = in_arb_sel[0] & in_arb_reqs_0_0_5 | in_arb_sel[1] & in_arb_reqs_1_0_5 | in_arb_sel[5] & in_arb_reqs_5_0_5; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_82 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_6 | in_arb_sel[5] & io_req_5_bits_vc_sel_0_6; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_93 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_7 | in_arb_sel[5] & io_req_5_bits_vc_sel_0_7; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_104 = in_arb_sel[0] & in_arb_reqs_0_0_8 | in_arb_sel[1] & in_arb_reqs_1_0_8 | in_arb_sel[5] & in_arb_reqs_5_0_8; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_115 = in_arb_sel[0] & in_arb_reqs_0_0_9 | in_arb_sel[1] & in_arb_reqs_1_0_9 | in_arb_sel[5] & in_arb_reqs_5_0_9; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_126 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[5] & in_arb_reqs_5_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_137 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[5] & in_arb_reqs_5_2_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_148 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[1] & in_arb_reqs_1_3_0 | in_arb_sel[5] & in_arb_reqs_5_3_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_159 = in_arb_sel[0] & in_arb_reqs_0_4_0 | in_arb_sel[1] & in_arb_reqs_1_4_0 | in_arb_sel[5] & in_arb_reqs_5_4_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_170 = in_arb_sel[0] & in_arb_reqs_0_5_0 | in_arb_sel[1] & in_arb_reqs_1_5_0 | in_arb_sel[5] & in_arb_reqs_5_5_0; // @[Mux.scala:30:73, :32:36]
reg [14:0] mask_1; // @[ISLIP.scala:17:25]
wire [14:0] _full_T_1 = {_in_vc_sel_T_170, _in_vc_sel_T_159, _in_vc_sel_T_148, _in_vc_sel_T_137, _in_vc_sel_T_126, _in_vc_sel_T_115, _in_vc_sel_T_104, _in_vc_sel_T_93, _in_vc_sel_T_82, _in_vc_sel_T_71, _in_vc_sel_T_60, _in_vc_sel_T_49, _in_vc_sel_T_38, _in_vc_sel_T_27, _in_vc_sel_T_16} & ~mask_1; // @[Mux.scala:30:73]
wire [29:0] oh = _full_T_1[0] ? 30'h1 : _full_T_1[1] ? 30'h2 : _full_T_1[2] ? 30'h4 : _full_T_1[3] ? 30'h8 : _full_T_1[4] ? 30'h10 : _full_T_1[5] ? 30'h20 : _full_T_1[6] ? 30'h40 : _full_T_1[7] ? 30'h80 : _full_T_1[8] ? 30'h100 : _full_T_1[9] ? 30'h200 : _full_T_1[10] ? 30'h400 : _full_T_1[11] ? 30'h800 : _full_T_1[12] ? 30'h1000 : _full_T_1[13] ? 30'h2000 : _full_T_1[14] ? 30'h4000 : _in_vc_sel_T_16 ? 30'h8000 : _in_vc_sel_T_27 ? 30'h10000 : _in_vc_sel_T_38 ? 30'h20000 : _in_vc_sel_T_49 ? 30'h40000 : _in_vc_sel_T_60 ? 30'h80000 : _in_vc_sel_T_71 ? 30'h100000 : _in_vc_sel_T_82 ? 30'h200000 : _in_vc_sel_T_93 ? 30'h400000 : _in_vc_sel_T_104 ? 30'h800000 : _in_vc_sel_T_115 ? 30'h1000000 : _in_vc_sel_T_126 ? 30'h2000000 : _in_vc_sel_T_137 ? 30'h4000000 : _in_vc_sel_T_148 ? 30'h8000000 : _in_vc_sel_T_159 ? 30'h10000000 : {_in_vc_sel_T_170, 29'h0}; // @[OneHot.scala:85:71]
wire [14:0] sel = oh[14:0] | oh[29:15]; // @[Mux.scala:50:70]
wire in_alloc_5_0 = _GEN & sel[14]; // @[package.scala:81:59]
wire in_alloc_4_0 = _GEN & sel[13]; // @[package.scala:81:59]
wire in_alloc_3_0 = _GEN & sel[12]; // @[package.scala:81:59]
wire in_alloc_2_0 = _GEN & sel[11]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[10]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]
wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59]
wire in_alloc_0_6 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_0_7 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_0_8 = _GEN & sel[8]; // @[package.scala:81:59]
wire in_alloc_0_9 = _GEN & sel[9]; // @[package.scala:81:59] |
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_1 :
input clock : Clock
input reset : Reset
output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>}
node default = gt(io.prv, UInt<1>(0h1))
wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmp0_WIRE.mask, UInt<32>(0h0)
connect _pmp0_WIRE.addr, UInt<30>(0h0)
connect _pmp0_WIRE.cfg.r, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.w, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.x, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.a, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.res, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.l, UInt<1>(0h0)
wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp0, _pmp0_WIRE
connect pmp0.cfg.r, default
connect pmp0.cfg.w, default
connect pmp0.cfg.x, default
node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1)
node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0)
node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1)
node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2)
node _res_hit_msbMatch_T = shr(io.addr, 3)
node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1)
node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3))
node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3)
node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3)
node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3)
node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5)
node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6)
node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8)
node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0))
node _res_hit_lsbMatch_T = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1)
node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3))
node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3)
node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0)
node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0)
node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5)
node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6)
node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8)
node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0))
node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch)
node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0)
node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0)
node _res_hit_T_5 = not(_res_hit_T_4)
node _res_hit_msbsLess_T = shr(io.addr, 3)
node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1)
node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3))
node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3)
node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3)
node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5)
node _res_hit_msbsEqual_T = shr(io.addr, 3)
node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1)
node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3))
node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3)
node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3)
node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5)
node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0))
node _res_hit_lsbsLess_T = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5)
node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2)
node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3))
node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4)
node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0)
node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6)
node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess)
node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6)
node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0))
node _res_hit_msbsLess_T_6 = shr(io.addr, 3)
node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7)
node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3))
node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9)
node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3)
node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11)
node _res_hit_msbsEqual_T_7 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8)
node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3))
node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10)
node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3)
node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12)
node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0))
node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0))
node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9)
node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3))
node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11)
node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0)
node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13)
node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1)
node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9)
node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10)
node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11)
node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12)
node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0))
node res_ignore = and(default, _res_ignore_T)
node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0)
node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1)
node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1)
node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3)
node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3)
node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5)
node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8)
node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10)
node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0)
node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13)
node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14)
node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16)
node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1)
node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3)
node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3)
node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5)
node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8)
node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10)
node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0)
node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask)
node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14)
node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16)
node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound)
node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0)
node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T)
node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1)
node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0))
node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1)
node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned)
node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0))
node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1))
node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r)
node _res_T_6 = eq(_res_T_5, UInt<1>(0h0))
node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r)
node _res_T_8 = eq(_res_T_7, UInt<1>(0h1))
node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r)
node _res_T_10 = eq(_res_T_9, UInt<2>(0h3))
node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r)
node _res_T_12 = eq(_res_T_11, UInt<3>(0h4))
node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r)
node _res_T_14 = eq(_res_T_13, UInt<3>(0h5))
node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r)
node _res_T_16 = eq(_res_T_15, UInt<3>(0h7))
node _res_T_17 = eq(res_ignore, UInt<1>(0h0))
node _res_T_18 = and(_res_T_17, res_hit)
node _res_T_19 = and(_res_T_18, res_aligned)
node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_21 = and(_res_T_19, _res_T_20)
node _res_T_22 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_23 = and(_res_T_22, res_aligned)
node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_25 = and(_res_T_23, _res_T_24)
node _res_T_26 = eq(res_ignore, UInt<1>(0h0))
node _res_T_27 = and(_res_T_26, res_hit)
node _res_T_28 = and(_res_T_27, res_aligned)
node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_30 = and(_res_T_28, _res_T_29)
node _res_T_31 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_32 = and(_res_T_31, res_aligned)
node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_34 = and(_res_T_32, _res_T_33)
node _res_T_35 = eq(res_ignore, UInt<1>(0h0))
node _res_T_36 = and(_res_T_35, res_hit)
node _res_T_37 = and(_res_T_36, res_aligned)
node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_39 = and(_res_T_37, _res_T_38)
node _res_T_40 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_41 = and(_res_T_40, res_aligned)
node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_43 = and(_res_T_41, _res_T_42)
wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur, io.pmp[7]
node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore)
node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T)
connect res_cur.cfg.r, _res_cur_cfg_r_T_1
node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore)
node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T)
connect res_cur.cfg.w, _res_cur_cfg_w_T_1
node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore)
node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T)
connect res_cur.cfg.x, _res_cur_cfg_x_T_1
node _res_T_44 = mux(res_hit, res_cur, pmp0)
node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1)
node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0)
node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4)
node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5)
node _res_hit_msbMatch_T_10 = shr(io.addr, 3)
node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11)
node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3))
node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13)
node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3)
node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3)
node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15)
node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16)
node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18)
node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0))
node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11)
node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3))
node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13)
node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0)
node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0)
node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15)
node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16)
node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18)
node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0))
node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1)
node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0)
node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0)
node _res_hit_T_18 = not(_res_hit_T_17)
node _res_hit_msbsLess_T_12 = shr(io.addr, 3)
node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13)
node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3))
node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15)
node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3)
node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17)
node _res_hit_msbsEqual_T_14 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15)
node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3))
node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17)
node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3)
node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19)
node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0))
node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18)
node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16)
node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3))
node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18)
node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0)
node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20)
node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2)
node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19)
node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0))
node _res_hit_msbsLess_T_18 = shr(io.addr, 3)
node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19)
node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3))
node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21)
node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3)
node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23)
node _res_hit_msbsEqual_T_21 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22)
node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3))
node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24)
node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3)
node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26)
node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0))
node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0))
node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23)
node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3))
node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25)
node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0)
node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27)
node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3)
node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22)
node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23)
node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24)
node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25)
node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0))
node res_ignore_1 = and(default, _res_ignore_T_1)
node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0)
node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3)
node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18)
node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20)
node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3)
node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22)
node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25)
node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27)
node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0)
node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30)
node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31)
node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33)
node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18)
node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20)
node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3)
node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22)
node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25)
node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27)
node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0)
node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1)
node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31)
node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33)
node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1)
node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0)
node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3)
node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4)
node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0))
node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1)
node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1)
node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0))
node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1))
node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r)
node _res_T_51 = eq(_res_T_50, UInt<1>(0h0))
node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r)
node _res_T_53 = eq(_res_T_52, UInt<1>(0h1))
node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r)
node _res_T_55 = eq(_res_T_54, UInt<2>(0h3))
node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r)
node _res_T_57 = eq(_res_T_56, UInt<3>(0h4))
node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r)
node _res_T_59 = eq(_res_T_58, UInt<3>(0h5))
node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r)
node _res_T_61 = eq(_res_T_60, UInt<3>(0h7))
node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_63 = and(_res_T_62, res_hit_1)
node _res_T_64 = and(_res_T_63, res_aligned_1)
node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_66 = and(_res_T_64, _res_T_65)
node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_68 = and(_res_T_67, res_aligned_1)
node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_70 = and(_res_T_68, _res_T_69)
node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_72 = and(_res_T_71, res_hit_1)
node _res_T_73 = and(_res_T_72, res_aligned_1)
node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_75 = and(_res_T_73, _res_T_74)
node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_77 = and(_res_T_76, res_aligned_1)
node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_79 = and(_res_T_77, _res_T_78)
node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_81 = and(_res_T_80, res_hit_1)
node _res_T_82 = and(_res_T_81, res_aligned_1)
node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_84 = and(_res_T_82, _res_T_83)
node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_86 = and(_res_T_85, res_aligned_1)
node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_88 = and(_res_T_86, _res_T_87)
wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_1, io.pmp[6]
node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1)
node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2)
connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3
node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1)
node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2)
connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3
node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1)
node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2)
connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3
node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44)
node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1)
node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0)
node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7)
node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8)
node _res_hit_msbMatch_T_20 = shr(io.addr, 3)
node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21)
node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3))
node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23)
node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3)
node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3)
node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25)
node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26)
node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28)
node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0))
node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21)
node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3))
node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23)
node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0)
node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0)
node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25)
node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26)
node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28)
node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0))
node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2)
node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0)
node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0)
node _res_hit_T_31 = not(_res_hit_T_30)
node _res_hit_msbsLess_T_24 = shr(io.addr, 3)
node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25)
node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3))
node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27)
node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3)
node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29)
node _res_hit_msbsEqual_T_28 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29)
node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3))
node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31)
node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3)
node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33)
node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0))
node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31)
node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30)
node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3))
node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32)
node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0)
node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34)
node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4)
node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32)
node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0))
node _res_hit_msbsLess_T_30 = shr(io.addr, 3)
node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31)
node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3))
node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33)
node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3)
node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35)
node _res_hit_msbsEqual_T_35 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36)
node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3))
node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38)
node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3)
node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40)
node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0))
node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0))
node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37)
node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3))
node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39)
node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0)
node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41)
node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5)
node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35)
node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36)
node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37)
node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38)
node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0))
node res_ignore_2 = and(default, _res_ignore_T_2)
node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0)
node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5)
node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35)
node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37)
node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3)
node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39)
node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42)
node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44)
node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0)
node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47)
node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48)
node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50)
node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35)
node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37)
node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3)
node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39)
node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42)
node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44)
node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0)
node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2)
node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48)
node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50)
node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2)
node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0)
node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6)
node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7)
node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0))
node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1)
node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2)
node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0))
node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1))
node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r)
node _res_T_96 = eq(_res_T_95, UInt<1>(0h0))
node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r)
node _res_T_98 = eq(_res_T_97, UInt<1>(0h1))
node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r)
node _res_T_100 = eq(_res_T_99, UInt<2>(0h3))
node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r)
node _res_T_102 = eq(_res_T_101, UInt<3>(0h4))
node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r)
node _res_T_104 = eq(_res_T_103, UInt<3>(0h5))
node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r)
node _res_T_106 = eq(_res_T_105, UInt<3>(0h7))
node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_108 = and(_res_T_107, res_hit_2)
node _res_T_109 = and(_res_T_108, res_aligned_2)
node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_111 = and(_res_T_109, _res_T_110)
node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_113 = and(_res_T_112, res_aligned_2)
node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_115 = and(_res_T_113, _res_T_114)
node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_117 = and(_res_T_116, res_hit_2)
node _res_T_118 = and(_res_T_117, res_aligned_2)
node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_120 = and(_res_T_118, _res_T_119)
node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_122 = and(_res_T_121, res_aligned_2)
node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_124 = and(_res_T_122, _res_T_123)
node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_126 = and(_res_T_125, res_hit_2)
node _res_T_127 = and(_res_T_126, res_aligned_2)
node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_129 = and(_res_T_127, _res_T_128)
node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_131 = and(_res_T_130, res_aligned_2)
node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_133 = and(_res_T_131, _res_T_132)
wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_2, io.pmp[5]
node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2)
node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4)
connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5
node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2)
node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4)
connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5
node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2)
node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4)
connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5
node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89)
node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1)
node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0)
node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10)
node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11)
node _res_hit_msbMatch_T_30 = shr(io.addr, 3)
node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31)
node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3))
node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33)
node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3)
node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3)
node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35)
node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36)
node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38)
node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0))
node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31)
node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3))
node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33)
node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0)
node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0)
node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35)
node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36)
node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38)
node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0))
node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3)
node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0)
node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0)
node _res_hit_T_44 = not(_res_hit_T_43)
node _res_hit_msbsLess_T_36 = shr(io.addr, 3)
node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37)
node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3))
node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39)
node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3)
node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41)
node _res_hit_msbsEqual_T_42 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43)
node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3))
node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45)
node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3)
node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47)
node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0))
node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44)
node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44)
node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3))
node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46)
node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0)
node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48)
node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6)
node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45)
node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0))
node _res_hit_msbsLess_T_42 = shr(io.addr, 3)
node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43)
node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3))
node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45)
node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3)
node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47)
node _res_hit_msbsEqual_T_49 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50)
node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3))
node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52)
node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3)
node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54)
node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0))
node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0))
node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51)
node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3))
node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53)
node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0)
node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55)
node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7)
node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48)
node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49)
node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50)
node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51)
node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0))
node res_ignore_3 = and(default, _res_ignore_T_3)
node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0)
node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7)
node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52)
node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54)
node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3)
node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56)
node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59)
node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61)
node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0)
node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64)
node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65)
node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67)
node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52)
node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54)
node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3)
node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56)
node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59)
node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61)
node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0)
node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3)
node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65)
node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67)
node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3)
node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0)
node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9)
node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10)
node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0))
node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1)
node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3)
node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0))
node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1))
node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r)
node _res_T_141 = eq(_res_T_140, UInt<1>(0h0))
node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r)
node _res_T_143 = eq(_res_T_142, UInt<1>(0h1))
node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r)
node _res_T_145 = eq(_res_T_144, UInt<2>(0h3))
node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r)
node _res_T_147 = eq(_res_T_146, UInt<3>(0h4))
node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r)
node _res_T_149 = eq(_res_T_148, UInt<3>(0h5))
node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r)
node _res_T_151 = eq(_res_T_150, UInt<3>(0h7))
node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_153 = and(_res_T_152, res_hit_3)
node _res_T_154 = and(_res_T_153, res_aligned_3)
node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_156 = and(_res_T_154, _res_T_155)
node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_158 = and(_res_T_157, res_aligned_3)
node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_160 = and(_res_T_158, _res_T_159)
node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_162 = and(_res_T_161, res_hit_3)
node _res_T_163 = and(_res_T_162, res_aligned_3)
node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_165 = and(_res_T_163, _res_T_164)
node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_167 = and(_res_T_166, res_aligned_3)
node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_169 = and(_res_T_167, _res_T_168)
node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_171 = and(_res_T_170, res_hit_3)
node _res_T_172 = and(_res_T_171, res_aligned_3)
node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_174 = and(_res_T_172, _res_T_173)
node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_176 = and(_res_T_175, res_aligned_3)
node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_178 = and(_res_T_176, _res_T_177)
wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_3, io.pmp[4]
node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3)
node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6)
connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7
node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3)
node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6)
connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7
node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3)
node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6)
connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7
node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134)
node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1)
node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0)
node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13)
node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14)
node _res_hit_msbMatch_T_40 = shr(io.addr, 3)
node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41)
node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3))
node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43)
node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3)
node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3)
node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45)
node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46)
node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48)
node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0))
node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41)
node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3))
node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43)
node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0)
node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0)
node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45)
node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46)
node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48)
node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0))
node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4)
node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0)
node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0)
node _res_hit_T_57 = not(_res_hit_T_56)
node _res_hit_msbsLess_T_48 = shr(io.addr, 3)
node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49)
node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3))
node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51)
node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3)
node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53)
node _res_hit_msbsEqual_T_56 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57)
node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3))
node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59)
node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3)
node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61)
node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0))
node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57)
node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58)
node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3))
node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60)
node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0)
node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62)
node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8)
node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58)
node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0))
node _res_hit_msbsLess_T_54 = shr(io.addr, 3)
node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55)
node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3))
node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57)
node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3)
node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59)
node _res_hit_msbsEqual_T_63 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64)
node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3))
node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66)
node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3)
node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68)
node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0))
node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0))
node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65)
node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3))
node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67)
node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0)
node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69)
node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9)
node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61)
node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62)
node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63)
node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64)
node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0))
node res_ignore_4 = and(default, _res_ignore_T_4)
node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0)
node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9)
node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69)
node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71)
node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3)
node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73)
node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76)
node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78)
node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0)
node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81)
node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82)
node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84)
node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69)
node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71)
node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3)
node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73)
node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76)
node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78)
node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0)
node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4)
node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82)
node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84)
node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4)
node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0)
node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12)
node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13)
node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0))
node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1)
node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4)
node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0))
node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1))
node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r)
node _res_T_186 = eq(_res_T_185, UInt<1>(0h0))
node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r)
node _res_T_188 = eq(_res_T_187, UInt<1>(0h1))
node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r)
node _res_T_190 = eq(_res_T_189, UInt<2>(0h3))
node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r)
node _res_T_192 = eq(_res_T_191, UInt<3>(0h4))
node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r)
node _res_T_194 = eq(_res_T_193, UInt<3>(0h5))
node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r)
node _res_T_196 = eq(_res_T_195, UInt<3>(0h7))
node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_198 = and(_res_T_197, res_hit_4)
node _res_T_199 = and(_res_T_198, res_aligned_4)
node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_201 = and(_res_T_199, _res_T_200)
node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_203 = and(_res_T_202, res_aligned_4)
node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_205 = and(_res_T_203, _res_T_204)
node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_207 = and(_res_T_206, res_hit_4)
node _res_T_208 = and(_res_T_207, res_aligned_4)
node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_210 = and(_res_T_208, _res_T_209)
node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_212 = and(_res_T_211, res_aligned_4)
node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_214 = and(_res_T_212, _res_T_213)
node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_216 = and(_res_T_215, res_hit_4)
node _res_T_217 = and(_res_T_216, res_aligned_4)
node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_219 = and(_res_T_217, _res_T_218)
node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_221 = and(_res_T_220, res_aligned_4)
node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_223 = and(_res_T_221, _res_T_222)
wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_4, io.pmp[3]
node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4)
node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8)
connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9
node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4)
node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8)
connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9
node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4)
node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8)
connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9
node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179)
node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1)
node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0)
node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16)
node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17)
node _res_hit_msbMatch_T_50 = shr(io.addr, 3)
node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51)
node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3))
node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53)
node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3)
node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3)
node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55)
node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56)
node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58)
node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0))
node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51)
node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3))
node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53)
node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0)
node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0)
node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55)
node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56)
node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58)
node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0))
node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5)
node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0)
node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0)
node _res_hit_T_70 = not(_res_hit_T_69)
node _res_hit_msbsLess_T_60 = shr(io.addr, 3)
node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61)
node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3))
node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63)
node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3)
node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65)
node _res_hit_msbsEqual_T_70 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71)
node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3))
node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73)
node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3)
node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75)
node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0))
node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70)
node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72)
node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3))
node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74)
node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0)
node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76)
node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10)
node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71)
node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0))
node _res_hit_msbsLess_T_66 = shr(io.addr, 3)
node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67)
node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3))
node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69)
node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3)
node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71)
node _res_hit_msbsEqual_T_77 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78)
node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3))
node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80)
node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3)
node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82)
node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0))
node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0))
node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79)
node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3))
node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81)
node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0)
node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83)
node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11)
node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74)
node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75)
node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76)
node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77)
node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0))
node res_ignore_5 = and(default, _res_ignore_T_5)
node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0)
node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11)
node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86)
node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88)
node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3)
node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90)
node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93)
node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95)
node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0)
node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98)
node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99)
node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101)
node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86)
node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88)
node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3)
node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90)
node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93)
node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95)
node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0)
node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5)
node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99)
node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101)
node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5)
node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0)
node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15)
node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16)
node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0))
node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1)
node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5)
node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0))
node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1))
node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r)
node _res_T_231 = eq(_res_T_230, UInt<1>(0h0))
node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r)
node _res_T_233 = eq(_res_T_232, UInt<1>(0h1))
node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r)
node _res_T_235 = eq(_res_T_234, UInt<2>(0h3))
node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r)
node _res_T_237 = eq(_res_T_236, UInt<3>(0h4))
node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r)
node _res_T_239 = eq(_res_T_238, UInt<3>(0h5))
node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r)
node _res_T_241 = eq(_res_T_240, UInt<3>(0h7))
node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_243 = and(_res_T_242, res_hit_5)
node _res_T_244 = and(_res_T_243, res_aligned_5)
node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_246 = and(_res_T_244, _res_T_245)
node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_248 = and(_res_T_247, res_aligned_5)
node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_250 = and(_res_T_248, _res_T_249)
node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_252 = and(_res_T_251, res_hit_5)
node _res_T_253 = and(_res_T_252, res_aligned_5)
node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_255 = and(_res_T_253, _res_T_254)
node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_257 = and(_res_T_256, res_aligned_5)
node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_259 = and(_res_T_257, _res_T_258)
node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_261 = and(_res_T_260, res_hit_5)
node _res_T_262 = and(_res_T_261, res_aligned_5)
node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_264 = and(_res_T_262, _res_T_263)
node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_266 = and(_res_T_265, res_aligned_5)
node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_268 = and(_res_T_266, _res_T_267)
wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_5, io.pmp[2]
node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5)
node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10)
connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11
node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5)
node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10)
connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11
node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5)
node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10)
connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11
node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224)
node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1)
node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0)
node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19)
node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20)
node _res_hit_msbMatch_T_60 = shr(io.addr, 3)
node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61)
node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3))
node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63)
node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3)
node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3)
node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65)
node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66)
node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68)
node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0))
node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61)
node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3))
node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63)
node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0)
node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0)
node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65)
node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66)
node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68)
node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0))
node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6)
node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0)
node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0)
node _res_hit_T_83 = not(_res_hit_T_82)
node _res_hit_msbsLess_T_72 = shr(io.addr, 3)
node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73)
node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3))
node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75)
node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3)
node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77)
node _res_hit_msbsEqual_T_84 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85)
node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3))
node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87)
node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3)
node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89)
node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0))
node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83)
node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86)
node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3))
node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88)
node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0)
node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90)
node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12)
node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84)
node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0))
node _res_hit_msbsLess_T_78 = shr(io.addr, 3)
node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79)
node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3))
node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81)
node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3)
node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83)
node _res_hit_msbsEqual_T_91 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92)
node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3))
node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94)
node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3)
node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96)
node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0))
node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0))
node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93)
node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3))
node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95)
node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0)
node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97)
node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13)
node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87)
node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88)
node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89)
node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90)
node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0))
node res_ignore_6 = and(default, _res_ignore_T_6)
node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0)
node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13)
node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103)
node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105)
node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3)
node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107)
node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110)
node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112)
node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0)
node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115)
node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116)
node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118)
node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103)
node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105)
node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3)
node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107)
node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110)
node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112)
node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0)
node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6)
node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116)
node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118)
node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6)
node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0)
node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18)
node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19)
node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0))
node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1)
node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6)
node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0))
node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1))
node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r)
node _res_T_276 = eq(_res_T_275, UInt<1>(0h0))
node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r)
node _res_T_278 = eq(_res_T_277, UInt<1>(0h1))
node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r)
node _res_T_280 = eq(_res_T_279, UInt<2>(0h3))
node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r)
node _res_T_282 = eq(_res_T_281, UInt<3>(0h4))
node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r)
node _res_T_284 = eq(_res_T_283, UInt<3>(0h5))
node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r)
node _res_T_286 = eq(_res_T_285, UInt<3>(0h7))
node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_288 = and(_res_T_287, res_hit_6)
node _res_T_289 = and(_res_T_288, res_aligned_6)
node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_291 = and(_res_T_289, _res_T_290)
node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_293 = and(_res_T_292, res_aligned_6)
node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_295 = and(_res_T_293, _res_T_294)
node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_297 = and(_res_T_296, res_hit_6)
node _res_T_298 = and(_res_T_297, res_aligned_6)
node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_300 = and(_res_T_298, _res_T_299)
node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_302 = and(_res_T_301, res_aligned_6)
node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_304 = and(_res_T_302, _res_T_303)
node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_306 = and(_res_T_305, res_hit_6)
node _res_T_307 = and(_res_T_306, res_aligned_6)
node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_309 = and(_res_T_307, _res_T_308)
node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_311 = and(_res_T_310, res_aligned_6)
node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_313 = and(_res_T_311, _res_T_312)
wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_6, io.pmp[1]
node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6)
node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12)
connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13
node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6)
node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12)
connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13
node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6)
node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12)
connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13
node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269)
node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1)
node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0)
node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22)
node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23)
node _res_hit_msbMatch_T_70 = shr(io.addr, 3)
node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71)
node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3))
node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73)
node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3)
node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3)
node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75)
node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76)
node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78)
node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0))
node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71)
node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3))
node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73)
node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0)
node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0)
node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75)
node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76)
node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78)
node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0))
node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7)
node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0)
node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0)
node _res_hit_T_96 = not(_res_hit_T_95)
node _res_hit_msbsLess_T_84 = shr(io.addr, 3)
node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2)
node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85)
node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3))
node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87)
node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3)
node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89)
node _res_hit_msbsEqual_T_98 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2)
node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99)
node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3))
node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101)
node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3)
node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103)
node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0))
node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96)
node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2)
node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100)
node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3))
node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102)
node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0)
node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104)
node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14)
node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97)
node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0))
node _res_hit_msbsLess_T_90 = shr(io.addr, 3)
node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91)
node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3))
node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93)
node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3)
node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95)
node _res_hit_msbsEqual_T_105 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106)
node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3))
node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108)
node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3)
node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110)
node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0))
node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0))
node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107)
node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3))
node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109)
node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0)
node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111)
node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15)
node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100)
node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101)
node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102)
node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103)
node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0))
node res_ignore_7 = and(default, _res_ignore_T_7)
node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0)
node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15)
node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120)
node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122)
node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3)
node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124)
node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127)
node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129)
node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0)
node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132)
node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133)
node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135)
node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120)
node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122)
node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3)
node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124)
node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127)
node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129)
node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0)
node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7)
node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133)
node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135)
node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7)
node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0)
node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21)
node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22)
node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0))
node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1)
node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7)
node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0))
node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1))
node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r)
node _res_T_321 = eq(_res_T_320, UInt<1>(0h0))
node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r)
node _res_T_323 = eq(_res_T_322, UInt<1>(0h1))
node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r)
node _res_T_325 = eq(_res_T_324, UInt<2>(0h3))
node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r)
node _res_T_327 = eq(_res_T_326, UInt<3>(0h4))
node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r)
node _res_T_329 = eq(_res_T_328, UInt<3>(0h5))
node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r)
node _res_T_331 = eq(_res_T_330, UInt<3>(0h7))
node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_333 = and(_res_T_332, res_hit_7)
node _res_T_334 = and(_res_T_333, res_aligned_7)
node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_336 = and(_res_T_334, _res_T_335)
node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_338 = and(_res_T_337, res_aligned_7)
node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_340 = and(_res_T_338, _res_T_339)
node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_342 = and(_res_T_341, res_hit_7)
node _res_T_343 = and(_res_T_342, res_aligned_7)
node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_345 = and(_res_T_343, _res_T_344)
node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_347 = and(_res_T_346, res_aligned_7)
node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_349 = and(_res_T_347, _res_T_348)
node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_351 = and(_res_T_350, res_hit_7)
node _res_T_352 = and(_res_T_351, res_aligned_7)
node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_354 = and(_res_T_352, _res_T_353)
node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_356 = and(_res_T_355, res_aligned_7)
node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_358 = and(_res_T_356, _res_T_357)
wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_7, io.pmp[0]
node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7)
node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14)
connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15
node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7)
node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14)
connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15
node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7)
node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14)
connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15
node res = mux(res_hit_7, res_cur_7, _res_T_314)
connect io.r, res.cfg.r
connect io.w, res.cfg.w
connect io.x, res.cfg.x | module PMPChecker_s3_1( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5]
wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27]
wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39]
wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53]
wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30]
wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16]
wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147]
wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71]
assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_3; // @[package.scala:243:71]
assign _res_hit_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_16; // @[package.scala:243:71]
assign _res_hit_T_16 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_29; // @[package.scala:243:71]
assign _res_hit_T_29 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_42; // @[package.scala:243:71]
assign _res_hit_T_42 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_55; // @[package.scala:243:71]
assign _res_hit_T_55 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_68; // @[package.scala:243:71]
assign _res_hit_T_68 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_81; // @[package.scala:243:71]
assign _res_hit_T_81 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_94; // @[package.scala:243:71]
assign _res_hit_T_94 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71]
wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46]
wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46]
wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}]
wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46]
wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48]
wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}]
wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}]
wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}]
wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46]
wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a26d64s10k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a26d64s10k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [25:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [25:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
reg full; // @[Repeater.scala:20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [9:0] saved_source; // @[Repeater.scala:21:18]
reg [25:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32]
wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}]
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35]
if (_GEN) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18]
saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18]
saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18]
saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18]
saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18]
saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18]
saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20))
wire _source_ok_WIRE : UInt<1>[7]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2])
node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5])
node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = and(_T_11, _T_24)
node _T_81 = and(_T_80, _T_37)
node _T_82 = and(_T_81, _T_50)
node _T_83 = and(_T_82, _T_63)
node _T_84 = and(_T_83, _T_71)
node _T_85 = and(_T_84, _T_79)
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_85, UInt<1>(0h1), "") : assert_1
node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_89 :
node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<1>(0h0))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_100 = shr(io.in.a.bits.source, 2)
node _T_101 = eq(_T_100, UInt<1>(0h1))
node _T_102 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_103 = and(_T_101, _T_102)
node _T_104 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_105 = and(_T_103, _T_104)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_106 = shr(io.in.a.bits.source, 2)
node _T_107 = eq(_T_106, UInt<2>(0h2))
node _T_108 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_109 = and(_T_107, _T_108)
node _T_110 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_111 = and(_T_109, _T_110)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<2>(0h3))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_119 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_120 = or(_T_93, _T_99)
node _T_121 = or(_T_120, _T_105)
node _T_122 = or(_T_121, _T_111)
node _T_123 = or(_T_122, _T_117)
node _T_124 = or(_T_123, _T_118)
node _T_125 = or(_T_124, _T_119)
node _T_126 = and(_T_92, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_129 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_130 = cvt(_T_129)
node _T_131 = and(_T_130, asSInt(UInt<14>(0h2000)))
node _T_132 = asSInt(_T_131)
node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0)))
node _T_134 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<13>(0h1000)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<17>(0h10000)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<18>(0h2f000)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<17>(0h10000)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<27>(0h4000000)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<19>(0h40000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = or(_T_133, _T_138)
node _T_170 = or(_T_169, _T_143)
node _T_171 = or(_T_170, _T_148)
node _T_172 = or(_T_171, _T_153)
node _T_173 = or(_T_172, _T_158)
node _T_174 = or(_T_173, _T_163)
node _T_175 = or(_T_174, _T_168)
node _T_176 = and(_T_128, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = and(_T_127, _T_177)
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_T_178, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_178, UInt<1>(0h1), "") : assert_2
node _T_182 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_183 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_184 = and(_T_182, _T_183)
node _T_185 = or(UInt<1>(0h0), _T_184)
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<14>(0h2000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<13>(0h1000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<18>(0h2f000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<17>(0h10000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<19>(0h40000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = or(_T_190, _T_195)
node _T_227 = or(_T_226, _T_200)
node _T_228 = or(_T_227, _T_205)
node _T_229 = or(_T_228, _T_210)
node _T_230 = or(_T_229, _T_215)
node _T_231 = or(_T_230, _T_220)
node _T_232 = or(_T_231, _T_225)
node _T_233 = and(_T_185, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(UInt<1>(0h0), _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_293 = or(_T_266, _T_272)
node _T_294 = or(_T_293, _T_278)
node _T_295 = or(_T_294, _T_284)
node _T_296 = or(_T_295, _T_290)
node _T_297 = or(_T_296, _T_291)
node _T_298 = or(_T_297, _T_292)
node _T_299 = and(_T_265, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_302 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<14>(0h2000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<17>(0h10000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<18>(0h2f000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<17>(0h10000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_328 = cvt(_T_327)
node _T_329 = and(_T_328, asSInt(UInt<27>(0h4000000)))
node _T_330 = asSInt(_T_329)
node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0)))
node _T_332 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<19>(0h40000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = or(_T_306, _T_311)
node _T_343 = or(_T_342, _T_316)
node _T_344 = or(_T_343, _T_321)
node _T_345 = or(_T_344, _T_326)
node _T_346 = or(_T_345, _T_331)
node _T_347 = or(_T_346, _T_336)
node _T_348 = or(_T_347, _T_341)
node _T_349 = and(_T_301, _T_348)
node _T_350 = or(UInt<1>(0h0), _T_349)
node _T_351 = and(_T_300, _T_350)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_351, UInt<1>(0h1), "") : assert_10
node _T_355 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_356 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_357 = and(_T_355, _T_356)
node _T_358 = or(UInt<1>(0h0), _T_357)
node _T_359 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<14>(0h2000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_365 = cvt(_T_364)
node _T_366 = and(_T_365, asSInt(UInt<13>(0h1000)))
node _T_367 = asSInt(_T_366)
node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0)))
node _T_369 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<17>(0h10000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_375 = cvt(_T_374)
node _T_376 = and(_T_375, asSInt(UInt<18>(0h2f000)))
node _T_377 = asSInt(_T_376)
node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0)))
node _T_379 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<17>(0h10000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<27>(0h4000000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<19>(0h40000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = or(_T_363, _T_368)
node _T_400 = or(_T_399, _T_373)
node _T_401 = or(_T_400, _T_378)
node _T_402 = or(_T_401, _T_383)
node _T_403 = or(_T_402, _T_388)
node _T_404 = or(_T_403, _T_393)
node _T_405 = or(_T_404, _T_398)
node _T_406 = and(_T_358, _T_405)
node _T_407 = or(UInt<1>(0h0), _T_406)
node _T_408 = and(UInt<1>(0h0), _T_407)
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_408, UInt<1>(0h1), "") : assert_11
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(source_ok, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_415, UInt<1>(0h1), "") : assert_13
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(is_aligned, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_422, UInt<1>(0h1), "") : assert_15
node _T_426 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_426, UInt<1>(0h1), "") : assert_16
node _T_430 = not(io.in.a.bits.mask)
node _T_431 = eq(_T_430, UInt<1>(0h0))
node _T_432 = asUInt(reset)
node _T_433 = eq(_T_432, UInt<1>(0h0))
when _T_433 :
node _T_434 = eq(_T_431, UInt<1>(0h0))
when _T_434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_431, UInt<1>(0h1), "") : assert_17
node _T_435 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_435, UInt<1>(0h1), "") : assert_18
node _T_439 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_439 :
node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_444 = shr(io.in.a.bits.source, 2)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_447 = and(_T_445, _T_446)
node _T_448 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_449 = and(_T_447, _T_448)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_450 = shr(io.in.a.bits.source, 2)
node _T_451 = eq(_T_450, UInt<1>(0h1))
node _T_452 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_453 = and(_T_451, _T_452)
node _T_454 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_455 = and(_T_453, _T_454)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_456 = shr(io.in.a.bits.source, 2)
node _T_457 = eq(_T_456, UInt<2>(0h2))
node _T_458 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_459 = and(_T_457, _T_458)
node _T_460 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_461 = and(_T_459, _T_460)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_462 = shr(io.in.a.bits.source, 2)
node _T_463 = eq(_T_462, UInt<2>(0h3))
node _T_464 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_465 = and(_T_463, _T_464)
node _T_466 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_467 = and(_T_465, _T_466)
node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_470 = or(_T_443, _T_449)
node _T_471 = or(_T_470, _T_455)
node _T_472 = or(_T_471, _T_461)
node _T_473 = or(_T_472, _T_467)
node _T_474 = or(_T_473, _T_468)
node _T_475 = or(_T_474, _T_469)
node _T_476 = and(_T_442, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_477, UInt<1>(0h1), "") : assert_19
node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_482 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_483 = and(_T_481, _T_482)
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_486 = cvt(_T_485)
node _T_487 = and(_T_486, asSInt(UInt<13>(0h1000)))
node _T_488 = asSInt(_T_487)
node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0)))
node _T_490 = and(_T_484, _T_489)
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_493 = and(_T_491, _T_492)
node _T_494 = or(UInt<1>(0h0), _T_493)
node _T_495 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_496 = cvt(_T_495)
node _T_497 = and(_T_496, asSInt(UInt<14>(0h2000)))
node _T_498 = asSInt(_T_497)
node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0)))
node _T_500 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_501 = cvt(_T_500)
node _T_502 = and(_T_501, asSInt(UInt<17>(0h10000)))
node _T_503 = asSInt(_T_502)
node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0)))
node _T_505 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_506 = cvt(_T_505)
node _T_507 = and(_T_506, asSInt(UInt<18>(0h2f000)))
node _T_508 = asSInt(_T_507)
node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0)))
node _T_510 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_511 = cvt(_T_510)
node _T_512 = and(_T_511, asSInt(UInt<17>(0h10000)))
node _T_513 = asSInt(_T_512)
node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0)))
node _T_515 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_516 = cvt(_T_515)
node _T_517 = and(_T_516, asSInt(UInt<27>(0h4000000)))
node _T_518 = asSInt(_T_517)
node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0)))
node _T_520 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_521 = cvt(_T_520)
node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000)))
node _T_523 = asSInt(_T_522)
node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0)))
node _T_525 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_526 = cvt(_T_525)
node _T_527 = and(_T_526, asSInt(UInt<19>(0h40000)))
node _T_528 = asSInt(_T_527)
node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0)))
node _T_530 = or(_T_499, _T_504)
node _T_531 = or(_T_530, _T_509)
node _T_532 = or(_T_531, _T_514)
node _T_533 = or(_T_532, _T_519)
node _T_534 = or(_T_533, _T_524)
node _T_535 = or(_T_534, _T_529)
node _T_536 = and(_T_494, _T_535)
node _T_537 = or(UInt<1>(0h0), _T_490)
node _T_538 = or(_T_537, _T_536)
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_538, UInt<1>(0h1), "") : assert_20
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(source_ok, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(is_aligned, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_548 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_548, UInt<1>(0h1), "") : assert_23
node _T_552 = eq(io.in.a.bits.mask, mask)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_552, UInt<1>(0h1), "") : assert_24
node _T_556 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_556, UInt<1>(0h1), "") : assert_25
node _T_560 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_560 :
node _T_561 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_562 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_563 = and(_T_561, _T_562)
node _T_564 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<1>(0h0))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<1>(0h1))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_577 = shr(io.in.a.bits.source, 2)
node _T_578 = eq(_T_577, UInt<2>(0h2))
node _T_579 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_580 = and(_T_578, _T_579)
node _T_581 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_582 = and(_T_580, _T_581)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_583 = shr(io.in.a.bits.source, 2)
node _T_584 = eq(_T_583, UInt<2>(0h3))
node _T_585 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_586 = and(_T_584, _T_585)
node _T_587 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_588 = and(_T_586, _T_587)
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_591 = or(_T_564, _T_570)
node _T_592 = or(_T_591, _T_576)
node _T_593 = or(_T_592, _T_582)
node _T_594 = or(_T_593, _T_588)
node _T_595 = or(_T_594, _T_589)
node _T_596 = or(_T_595, _T_590)
node _T_597 = and(_T_563, _T_596)
node _T_598 = or(UInt<1>(0h0), _T_597)
node _T_599 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_600 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_601 = and(_T_599, _T_600)
node _T_602 = or(UInt<1>(0h0), _T_601)
node _T_603 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_604 = cvt(_T_603)
node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000)))
node _T_606 = asSInt(_T_605)
node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0)))
node _T_608 = and(_T_602, _T_607)
node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_611 = and(_T_609, _T_610)
node _T_612 = or(UInt<1>(0h0), _T_611)
node _T_613 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<14>(0h2000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<18>(0h2f000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<27>(0h4000000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_634 = cvt(_T_633)
node _T_635 = and(_T_634, asSInt(UInt<13>(0h1000)))
node _T_636 = asSInt(_T_635)
node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0)))
node _T_638 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_639 = cvt(_T_638)
node _T_640 = and(_T_639, asSInt(UInt<19>(0h40000)))
node _T_641 = asSInt(_T_640)
node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0)))
node _T_643 = or(_T_617, _T_622)
node _T_644 = or(_T_643, _T_627)
node _T_645 = or(_T_644, _T_632)
node _T_646 = or(_T_645, _T_637)
node _T_647 = or(_T_646, _T_642)
node _T_648 = and(_T_612, _T_647)
node _T_649 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_650 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = and(_T_649, _T_654)
node _T_656 = or(UInt<1>(0h0), _T_608)
node _T_657 = or(_T_656, _T_648)
node _T_658 = or(_T_657, _T_655)
node _T_659 = and(_T_598, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_659, UInt<1>(0h1), "") : assert_26
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(source_ok, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(is_aligned, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_669, UInt<1>(0h1), "") : assert_29
node _T_673 = eq(io.in.a.bits.mask, mask)
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_673, UInt<1>(0h1), "") : assert_30
node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_677 :
node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_680 = and(_T_678, _T_679)
node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_682 = shr(io.in.a.bits.source, 2)
node _T_683 = eq(_T_682, UInt<1>(0h0))
node _T_684 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_685 = and(_T_683, _T_684)
node _T_686 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_687 = and(_T_685, _T_686)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_688 = shr(io.in.a.bits.source, 2)
node _T_689 = eq(_T_688, UInt<1>(0h1))
node _T_690 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_691 = and(_T_689, _T_690)
node _T_692 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_693 = and(_T_691, _T_692)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_694 = shr(io.in.a.bits.source, 2)
node _T_695 = eq(_T_694, UInt<2>(0h2))
node _T_696 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_697 = and(_T_695, _T_696)
node _T_698 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_699 = and(_T_697, _T_698)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_700 = shr(io.in.a.bits.source, 2)
node _T_701 = eq(_T_700, UInt<2>(0h3))
node _T_702 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_703 = and(_T_701, _T_702)
node _T_704 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_705 = and(_T_703, _T_704)
node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_708 = or(_T_681, _T_687)
node _T_709 = or(_T_708, _T_693)
node _T_710 = or(_T_709, _T_699)
node _T_711 = or(_T_710, _T_705)
node _T_712 = or(_T_711, _T_706)
node _T_713 = or(_T_712, _T_707)
node _T_714 = and(_T_680, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_717 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_718 = and(_T_716, _T_717)
node _T_719 = or(UInt<1>(0h0), _T_718)
node _T_720 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_721 = cvt(_T_720)
node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000)))
node _T_723 = asSInt(_T_722)
node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0)))
node _T_725 = and(_T_719, _T_724)
node _T_726 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_727 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_728 = and(_T_726, _T_727)
node _T_729 = or(UInt<1>(0h0), _T_728)
node _T_730 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_731 = cvt(_T_730)
node _T_732 = and(_T_731, asSInt(UInt<14>(0h2000)))
node _T_733 = asSInt(_T_732)
node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0)))
node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_736 = cvt(_T_735)
node _T_737 = and(_T_736, asSInt(UInt<18>(0h2f000)))
node _T_738 = asSInt(_T_737)
node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0)))
node _T_740 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_741 = cvt(_T_740)
node _T_742 = and(_T_741, asSInt(UInt<17>(0h10000)))
node _T_743 = asSInt(_T_742)
node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0)))
node _T_745 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_746 = cvt(_T_745)
node _T_747 = and(_T_746, asSInt(UInt<27>(0h4000000)))
node _T_748 = asSInt(_T_747)
node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0)))
node _T_750 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_751 = cvt(_T_750)
node _T_752 = and(_T_751, asSInt(UInt<13>(0h1000)))
node _T_753 = asSInt(_T_752)
node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0)))
node _T_755 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<19>(0h40000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = or(_T_734, _T_739)
node _T_761 = or(_T_760, _T_744)
node _T_762 = or(_T_761, _T_749)
node _T_763 = or(_T_762, _T_754)
node _T_764 = or(_T_763, _T_759)
node _T_765 = and(_T_729, _T_764)
node _T_766 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_767 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_768 = cvt(_T_767)
node _T_769 = and(_T_768, asSInt(UInt<17>(0h10000)))
node _T_770 = asSInt(_T_769)
node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0)))
node _T_772 = and(_T_766, _T_771)
node _T_773 = or(UInt<1>(0h0), _T_725)
node _T_774 = or(_T_773, _T_765)
node _T_775 = or(_T_774, _T_772)
node _T_776 = and(_T_715, _T_775)
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(_T_776, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_776, UInt<1>(0h1), "") : assert_31
node _T_780 = asUInt(reset)
node _T_781 = eq(_T_780, UInt<1>(0h0))
when _T_781 :
node _T_782 = eq(source_ok, UInt<1>(0h0))
when _T_782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(is_aligned, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_786 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_786, UInt<1>(0h1), "") : assert_34
node _T_790 = not(mask)
node _T_791 = and(io.in.a.bits.mask, _T_790)
node _T_792 = eq(_T_791, UInt<1>(0h0))
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(_T_792, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_792, UInt<1>(0h1), "") : assert_35
node _T_796 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_796 :
node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_799 = and(_T_797, _T_798)
node _T_800 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_801 = shr(io.in.a.bits.source, 2)
node _T_802 = eq(_T_801, UInt<1>(0h0))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_806 = and(_T_804, _T_805)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_807 = shr(io.in.a.bits.source, 2)
node _T_808 = eq(_T_807, UInt<1>(0h1))
node _T_809 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_810 = and(_T_808, _T_809)
node _T_811 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_812 = and(_T_810, _T_811)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_813 = shr(io.in.a.bits.source, 2)
node _T_814 = eq(_T_813, UInt<2>(0h2))
node _T_815 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_816 = and(_T_814, _T_815)
node _T_817 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_818 = and(_T_816, _T_817)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_819 = shr(io.in.a.bits.source, 2)
node _T_820 = eq(_T_819, UInt<2>(0h3))
node _T_821 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_822 = and(_T_820, _T_821)
node _T_823 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_824 = and(_T_822, _T_823)
node _T_825 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_826 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_827 = or(_T_800, _T_806)
node _T_828 = or(_T_827, _T_812)
node _T_829 = or(_T_828, _T_818)
node _T_830 = or(_T_829, _T_824)
node _T_831 = or(_T_830, _T_825)
node _T_832 = or(_T_831, _T_826)
node _T_833 = and(_T_799, _T_832)
node _T_834 = or(UInt<1>(0h0), _T_833)
node _T_835 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_836 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_837 = and(_T_835, _T_836)
node _T_838 = or(UInt<1>(0h0), _T_837)
node _T_839 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<14>(0h2000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<13>(0h1000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<18>(0h2f000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<17>(0h10000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<27>(0h4000000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<13>(0h1000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<19>(0h40000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = or(_T_843, _T_848)
node _T_875 = or(_T_874, _T_853)
node _T_876 = or(_T_875, _T_858)
node _T_877 = or(_T_876, _T_863)
node _T_878 = or(_T_877, _T_868)
node _T_879 = or(_T_878, _T_873)
node _T_880 = and(_T_838, _T_879)
node _T_881 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_882 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_883 = cvt(_T_882)
node _T_884 = and(_T_883, asSInt(UInt<17>(0h10000)))
node _T_885 = asSInt(_T_884)
node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0)))
node _T_887 = and(_T_881, _T_886)
node _T_888 = or(UInt<1>(0h0), _T_880)
node _T_889 = or(_T_888, _T_887)
node _T_890 = and(_T_834, _T_889)
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_890, UInt<1>(0h1), "") : assert_36
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(source_ok, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(is_aligned, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_900 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_900, UInt<1>(0h1), "") : assert_39
node _T_904 = eq(io.in.a.bits.mask, mask)
node _T_905 = asUInt(reset)
node _T_906 = eq(_T_905, UInt<1>(0h0))
when _T_906 :
node _T_907 = eq(_T_904, UInt<1>(0h0))
when _T_907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_904, UInt<1>(0h1), "") : assert_40
node _T_908 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_908 :
node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_913 = shr(io.in.a.bits.source, 2)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_916 = and(_T_914, _T_915)
node _T_917 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_918 = and(_T_916, _T_917)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_919 = shr(io.in.a.bits.source, 2)
node _T_920 = eq(_T_919, UInt<1>(0h1))
node _T_921 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_922 = and(_T_920, _T_921)
node _T_923 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_924 = and(_T_922, _T_923)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_925 = shr(io.in.a.bits.source, 2)
node _T_926 = eq(_T_925, UInt<2>(0h2))
node _T_927 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_928 = and(_T_926, _T_927)
node _T_929 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_930 = and(_T_928, _T_929)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_931 = shr(io.in.a.bits.source, 2)
node _T_932 = eq(_T_931, UInt<2>(0h3))
node _T_933 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_934 = and(_T_932, _T_933)
node _T_935 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_936 = and(_T_934, _T_935)
node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_939 = or(_T_912, _T_918)
node _T_940 = or(_T_939, _T_924)
node _T_941 = or(_T_940, _T_930)
node _T_942 = or(_T_941, _T_936)
node _T_943 = or(_T_942, _T_937)
node _T_944 = or(_T_943, _T_938)
node _T_945 = and(_T_911, _T_944)
node _T_946 = or(UInt<1>(0h0), _T_945)
node _T_947 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_948 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _T_950 = or(UInt<1>(0h0), _T_949)
node _T_951 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_952 = cvt(_T_951)
node _T_953 = and(_T_952, asSInt(UInt<14>(0h2000)))
node _T_954 = asSInt(_T_953)
node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0)))
node _T_956 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_957 = cvt(_T_956)
node _T_958 = and(_T_957, asSInt(UInt<13>(0h1000)))
node _T_959 = asSInt(_T_958)
node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0)))
node _T_961 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_962 = cvt(_T_961)
node _T_963 = and(_T_962, asSInt(UInt<18>(0h2f000)))
node _T_964 = asSInt(_T_963)
node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0)))
node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_967 = cvt(_T_966)
node _T_968 = and(_T_967, asSInt(UInt<17>(0h10000)))
node _T_969 = asSInt(_T_968)
node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0)))
node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_972 = cvt(_T_971)
node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000)))
node _T_974 = asSInt(_T_973)
node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0)))
node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_977 = cvt(_T_976)
node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000)))
node _T_979 = asSInt(_T_978)
node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0)))
node _T_981 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_982 = cvt(_T_981)
node _T_983 = and(_T_982, asSInt(UInt<19>(0h40000)))
node _T_984 = asSInt(_T_983)
node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0)))
node _T_986 = or(_T_955, _T_960)
node _T_987 = or(_T_986, _T_965)
node _T_988 = or(_T_987, _T_970)
node _T_989 = or(_T_988, _T_975)
node _T_990 = or(_T_989, _T_980)
node _T_991 = or(_T_990, _T_985)
node _T_992 = and(_T_950, _T_991)
node _T_993 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_994 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = and(_T_993, _T_998)
node _T_1000 = or(UInt<1>(0h0), _T_992)
node _T_1001 = or(_T_1000, _T_999)
node _T_1002 = and(_T_946, _T_1001)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_41
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(source_ok, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(is_aligned, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1012 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_44
node _T_1016 = eq(io.in.a.bits.mask, mask)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_45
node _T_1020 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1020 :
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1025 = shr(io.in.a.bits.source, 2)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
node _T_1027 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1030 = and(_T_1028, _T_1029)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1031 = shr(io.in.a.bits.source, 2)
node _T_1032 = eq(_T_1031, UInt<1>(0h1))
node _T_1033 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1034 = and(_T_1032, _T_1033)
node _T_1035 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1036 = and(_T_1034, _T_1035)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1037 = shr(io.in.a.bits.source, 2)
node _T_1038 = eq(_T_1037, UInt<2>(0h2))
node _T_1039 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1042 = and(_T_1040, _T_1041)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<2>(0h3))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _T_1049 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1050 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1051 = or(_T_1024, _T_1030)
node _T_1052 = or(_T_1051, _T_1036)
node _T_1053 = or(_T_1052, _T_1042)
node _T_1054 = or(_T_1053, _T_1048)
node _T_1055 = or(_T_1054, _T_1049)
node _T_1056 = or(_T_1055, _T_1050)
node _T_1057 = and(_T_1023, _T_1056)
node _T_1058 = or(UInt<1>(0h0), _T_1057)
node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = or(UInt<1>(0h0), _T_1061)
node _T_1063 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1064 = cvt(_T_1063)
node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000)))
node _T_1066 = asSInt(_T_1065)
node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0)))
node _T_1068 = and(_T_1062, _T_1067)
node _T_1069 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1070 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1071 = cvt(_T_1070)
node _T_1072 = and(_T_1071, asSInt(UInt<14>(0h2000)))
node _T_1073 = asSInt(_T_1072)
node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0)))
node _T_1075 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1076 = cvt(_T_1075)
node _T_1077 = and(_T_1076, asSInt(UInt<17>(0h10000)))
node _T_1078 = asSInt(_T_1077)
node _T_1079 = eq(_T_1078, asSInt(UInt<1>(0h0)))
node _T_1080 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1081 = cvt(_T_1080)
node _T_1082 = and(_T_1081, asSInt(UInt<18>(0h2f000)))
node _T_1083 = asSInt(_T_1082)
node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0)))
node _T_1085 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1086 = cvt(_T_1085)
node _T_1087 = and(_T_1086, asSInt(UInt<17>(0h10000)))
node _T_1088 = asSInt(_T_1087)
node _T_1089 = eq(_T_1088, asSInt(UInt<1>(0h0)))
node _T_1090 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1091 = cvt(_T_1090)
node _T_1092 = and(_T_1091, asSInt(UInt<27>(0h4000000)))
node _T_1093 = asSInt(_T_1092)
node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0)))
node _T_1095 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<13>(0h1000)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1101 = cvt(_T_1100)
node _T_1102 = and(_T_1101, asSInt(UInt<19>(0h40000)))
node _T_1103 = asSInt(_T_1102)
node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0)))
node _T_1105 = or(_T_1074, _T_1079)
node _T_1106 = or(_T_1105, _T_1084)
node _T_1107 = or(_T_1106, _T_1089)
node _T_1108 = or(_T_1107, _T_1094)
node _T_1109 = or(_T_1108, _T_1099)
node _T_1110 = or(_T_1109, _T_1104)
node _T_1111 = and(_T_1069, _T_1110)
node _T_1112 = or(UInt<1>(0h0), _T_1068)
node _T_1113 = or(_T_1112, _T_1111)
node _T_1114 = and(_T_1058, _T_1113)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_46
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(source_ok, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(is_aligned, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1124 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_49
node _T_1128 = eq(io.in.a.bits.mask, mask)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_50
node _T_1132 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1136 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_52
node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_33 = shr(io.in.d.bits.source, 2)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<6>(0h20))
wire _source_ok_WIRE_1 : UInt<1>[7]
connect _source_ok_WIRE_1[0], _source_ok_T_32
connect _source_ok_WIRE_1[1], _source_ok_T_38
connect _source_ok_WIRE_1[2], _source_ok_T_44
connect _source_ok_WIRE_1[3], _source_ok_T_50
connect _source_ok_WIRE_1[4], _source_ok_T_56
connect _source_ok_WIRE_1[5], _source_ok_T_57
connect _source_ok_WIRE_1[6], _source_ok_T_58
node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5])
node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1140 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1140 :
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(source_ok_1, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1144 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_54
node _T_1148 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_55
node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_56
node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_57
node _T_1160 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1160 :
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok_1, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(sink_ok, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1167 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_60
node _T_1171 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_61
node _T_1175 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_62
node _T_1179 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1180 = asUInt(reset)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(_T_1179, UInt<1>(0h0))
when _T_1182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1179, UInt<1>(0h1), "") : assert_63
node _T_1183 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1184 = or(UInt<1>(0h1), _T_1183)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_64
node _T_1188 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1188 :
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(source_ok_1, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(sink_ok, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1195 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_67
node _T_1199 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_68
node _T_1203 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_69
node _T_1207 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1208 = or(_T_1207, io.in.d.bits.corrupt)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_70
node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1213 = or(UInt<1>(0h1), _T_1212)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_71
node _T_1217 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(source_ok_1, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1221 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_73
node _T_1225 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_74
node _T_1229 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1230 = or(UInt<1>(0h1), _T_1229)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_75
node _T_1234 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1234 :
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(source_ok_1, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1238 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_77
node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1243 = or(_T_1242, io.in.d.bits.corrupt)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_78
node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1248 = or(UInt<1>(0h1), _T_1247)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_79
node _T_1252 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1252 :
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(source_ok_1, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1256 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_81
node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_82
node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1265 = or(UInt<1>(0h1), _T_1264)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1269 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1273 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1277 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(_T_1277, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1277, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1281 = eq(a_first, UInt<1>(0h0))
node _T_1282 = and(io.in.a.valid, _T_1281)
when _T_1282 :
node _T_1283 = eq(io.in.a.bits.opcode, opcode)
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_87
node _T_1287 = eq(io.in.a.bits.param, param)
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_88
node _T_1291 = eq(io.in.a.bits.size, size)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_89
node _T_1295 = eq(io.in.a.bits.source, source)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_90
node _T_1299 = eq(io.in.a.bits.address, address)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_91
node _T_1303 = and(io.in.a.ready, io.in.a.valid)
node _T_1304 = and(_T_1303, a_first)
when _T_1304 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1305 = eq(d_first, UInt<1>(0h0))
node _T_1306 = and(io.in.d.valid, _T_1305)
when _T_1306 :
node _T_1307 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_92
node _T_1311 = eq(io.in.d.bits.param, param_1)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_93
node _T_1315 = eq(io.in.d.bits.size, size_1)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_94
node _T_1319 = eq(io.in.d.bits.source, source_1)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_95
node _T_1323 = eq(io.in.d.bits.sink, sink)
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_96
node _T_1327 = eq(io.in.d.bits.denied, denied)
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_97
node _T_1331 = and(io.in.d.ready, io.in.d.valid)
node _T_1332 = and(_T_1331, d_first)
when _T_1332 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<34>, clock, reset, UInt<34>(0h0)
regreset inflight_opcodes : UInt<136>, clock, reset, UInt<136>(0h0)
regreset inflight_sizes : UInt<272>, clock, reset, UInt<272>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<34>
connect a_set, UInt<34>(0h0)
wire a_set_wo_ready : UInt<34>
connect a_set_wo_ready, UInt<34>(0h0)
wire a_opcodes_set : UInt<136>
connect a_opcodes_set, UInt<136>(0h0)
wire a_sizes_set : UInt<272>
connect a_sizes_set, UInt<272>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1333 = and(io.in.a.valid, a_first_1)
node _T_1334 = and(_T_1333, UInt<1>(0h1))
when _T_1334 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1335 = and(io.in.a.ready, io.in.a.valid)
node _T_1336 = and(_T_1335, a_first_1)
node _T_1337 = and(_T_1336, UInt<1>(0h1))
when _T_1337 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1338 = dshr(inflight, io.in.a.bits.source)
node _T_1339 = bits(_T_1338, 0, 0)
node _T_1340 = eq(_T_1339, UInt<1>(0h0))
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<34>
connect d_clr, UInt<34>(0h0)
wire d_clr_wo_ready : UInt<34>
connect d_clr_wo_ready, UInt<34>(0h0)
wire d_opcodes_clr : UInt<136>
connect d_opcodes_clr, UInt<136>(0h0)
wire d_sizes_clr : UInt<272>
connect d_sizes_clr, UInt<272>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1344 = and(io.in.d.valid, d_first_1)
node _T_1345 = and(_T_1344, UInt<1>(0h1))
node _T_1346 = eq(d_release_ack, UInt<1>(0h0))
node _T_1347 = and(_T_1345, _T_1346)
when _T_1347 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1348 = and(io.in.d.ready, io.in.d.valid)
node _T_1349 = and(_T_1348, d_first_1)
node _T_1350 = and(_T_1349, UInt<1>(0h1))
node _T_1351 = eq(d_release_ack, UInt<1>(0h0))
node _T_1352 = and(_T_1350, _T_1351)
when _T_1352 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1353 = and(io.in.d.valid, d_first_1)
node _T_1354 = and(_T_1353, UInt<1>(0h1))
node _T_1355 = eq(d_release_ack, UInt<1>(0h0))
node _T_1356 = and(_T_1354, _T_1355)
when _T_1356 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1357 = dshr(inflight, io.in.d.bits.source)
node _T_1358 = bits(_T_1357, 0, 0)
node _T_1359 = or(_T_1358, same_cycle_resp)
node _T_1360 = asUInt(reset)
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(_T_1359, UInt<1>(0h0))
when _T_1362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1359, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1363 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1364 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1365 = or(_T_1363, _T_1364)
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_100
node _T_1369 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1370 = asUInt(reset)
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(_T_1369, UInt<1>(0h0))
when _T_1372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1369, UInt<1>(0h1), "") : assert_101
else :
node _T_1373 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1374 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1375 = or(_T_1373, _T_1374)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_102
node _T_1379 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_103
node _T_1383 = and(io.in.d.valid, d_first_1)
node _T_1384 = and(_T_1383, a_first_1)
node _T_1385 = and(_T_1384, io.in.a.valid)
node _T_1386 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1387 = and(_T_1385, _T_1386)
node _T_1388 = eq(d_release_ack, UInt<1>(0h0))
node _T_1389 = and(_T_1387, _T_1388)
when _T_1389 :
node _T_1390 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1391 = or(_T_1390, io.in.a.ready)
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(_T_1391, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1391, UInt<1>(0h1), "") : assert_104
node _T_1395 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1396 = orr(a_set_wo_ready)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
node _T_1398 = or(_T_1395, _T_1397)
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_32
node _T_1402 = orr(inflight)
node _T_1403 = eq(_T_1402, UInt<1>(0h0))
node _T_1404 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1405 = or(_T_1403, _T_1404)
node _T_1406 = lt(watchdog, plusarg_reader.out)
node _T_1407 = or(_T_1405, _T_1406)
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1411 = and(io.in.a.ready, io.in.a.valid)
node _T_1412 = and(io.in.d.ready, io.in.d.valid)
node _T_1413 = or(_T_1411, _T_1412)
when _T_1413 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<34>, clock, reset, UInt<34>(0h0)
regreset inflight_opcodes_1 : UInt<136>, clock, reset, UInt<136>(0h0)
regreset inflight_sizes_1 : UInt<272>, clock, reset, UInt<272>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<34>
connect c_set, UInt<34>(0h0)
wire c_set_wo_ready : UInt<34>
connect c_set_wo_ready, UInt<34>(0h0)
wire c_opcodes_set : UInt<136>
connect c_opcodes_set, UInt<136>(0h0)
wire c_sizes_set : UInt<272>
connect c_sizes_set, UInt<272>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1414 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1415 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1416 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1417 = and(_T_1415, _T_1416)
node _T_1418 = and(_T_1414, _T_1417)
when _T_1418 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1419 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1420 = and(_T_1419, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1421 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1422 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1423 = and(_T_1421, _T_1422)
node _T_1424 = and(_T_1420, _T_1423)
when _T_1424 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1425 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1426 = bits(_T_1425, 0, 0)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<34>
connect d_clr_1, UInt<34>(0h0)
wire d_clr_wo_ready_1 : UInt<34>
connect d_clr_wo_ready_1, UInt<34>(0h0)
wire d_opcodes_clr_1 : UInt<136>
connect d_opcodes_clr_1, UInt<136>(0h0)
wire d_sizes_clr_1 : UInt<272>
connect d_sizes_clr_1, UInt<272>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1431 = and(io.in.d.valid, d_first_2)
node _T_1432 = and(_T_1431, UInt<1>(0h1))
node _T_1433 = and(_T_1432, d_release_ack_1)
when _T_1433 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1434 = and(io.in.d.ready, io.in.d.valid)
node _T_1435 = and(_T_1434, d_first_2)
node _T_1436 = and(_T_1435, UInt<1>(0h1))
node _T_1437 = and(_T_1436, d_release_ack_1)
when _T_1437 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1438 = and(io.in.d.valid, d_first_2)
node _T_1439 = and(_T_1438, UInt<1>(0h1))
node _T_1440 = and(_T_1439, d_release_ack_1)
when _T_1440 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1441 = dshr(inflight_1, io.in.d.bits.source)
node _T_1442 = bits(_T_1441, 0, 0)
node _T_1443 = or(_T_1442, same_cycle_resp_1)
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(_T_1443, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1443, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1447 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_109
else :
node _T_1451 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_110
node _T_1455 = and(io.in.d.valid, d_first_2)
node _T_1456 = and(_T_1455, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1457 = and(_T_1456, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1458 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1459 = and(_T_1457, _T_1458)
node _T_1460 = and(_T_1459, d_release_ack_1)
node _T_1461 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1462 = and(_T_1460, _T_1461)
when _T_1462 :
node _T_1463 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1464 = or(_T_1463, _WIRE_23.ready)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_111
node _T_1468 = orr(c_set_wo_ready)
when _T_1468 :
node _T_1469 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(_T_1469, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1469, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_33
node _T_1473 = orr(inflight_1)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
node _T_1475 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1476 = or(_T_1474, _T_1475)
node _T_1477 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1478 = or(_T_1476, _T_1477)
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(_T_1478, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1478, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1482 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1483 = and(io.in.d.ready, io.in.d.valid)
node _T_1484 = or(_T_1482, _T_1483)
when _T_1484 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_34 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_35 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_16( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [271:0] c_sizes_set = 272'h0; // @[Monitor.scala:741:34]
wire [135:0] c_opcodes_set = 136'h0; // @[Monitor.scala:740:34]
wire [33:0] c_set = 34'h0; // @[Monitor.scala:738:34]
wire [33:0] c_set_wo_ready = 34'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_33 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_39 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = _source_ok_T_45 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = _source_ok_T_51 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire _source_ok_T_57 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1411 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1411; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1411; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1484; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1484; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1484; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [33:0] inflight; // @[Monitor.scala:614:27]
reg [135:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [271:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [33:0] a_set; // @[Monitor.scala:626:34]
wire [33:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [135:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [271:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [135:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [135:0] _a_opcode_lookup_T_6 = {132'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [135:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [271:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [271:0] _a_size_lookup_T_6 = {264'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [271:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[271:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire _T_1337 = _T_1411 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1337 ? _a_set_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1337 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1337 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1337 ? _a_opcodes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1337 ? _a_sizes_set_T_1[271:0] : 272'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [33:0] d_clr; // @[Monitor.scala:664:34]
wire [33:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [135:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [271:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1383 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1383 & ~d_release_ack ? _d_clr_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire _T_1352 = _T_1484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1352 ? _d_clr_T[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1352 ? _d_opcodes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1352 ? _d_sizes_clr_T_5[271:0] : 272'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [33:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [33:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [33:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [135:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [135:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [135:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [271:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [271:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [271:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [33:0] inflight_1; // @[Monitor.scala:726:35]
wire [33:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [135:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [135:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [271:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [271:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [135:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [135:0] _c_opcode_lookup_T_6 = {132'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [135:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [271:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [271:0] _c_size_lookup_T_6 = {264'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [271:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[271:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [33:0] d_clr_1; // @[Monitor.scala:774:34]
wire [33:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [135:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [271:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1455 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1455 & d_release_ack_1 ? _d_clr_wo_ready_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire _T_1437 = _T_1484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1437 ? _d_clr_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1437 ? _d_opcodes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1437 ? _d_sizes_clr_T_11[271:0] : 272'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [33:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [33:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [135:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [135:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [271:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [271:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_81 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}}
wire _in_flight_WIRE : UInt<1>[2]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(_T_12, _T_19)
node _T_35 = or(_T_34, _T_26)
node _T_36 = or(_T_35, _T_33)
node _T_37 = or(_T_5, _T_36)
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_37, UInt<1>(0h1), "") : assert_1
node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_42 = or(_T_41, UInt<1>(0h0))
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 | module NoCMonitor_81( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module RVCExpander :
input clock : Clock
input reset : Reset
output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, ill : UInt<1>}
node _io_rvc_T = bits(io.in, 1, 0)
node _io_rvc_T_1 = neq(_io_rvc_T, UInt<2>(0h3))
connect io.rvc, _io_rvc_T_1
node _io_out_s_opc_T = bits(io.in, 12, 5)
node _io_out_s_opc_T_1 = orr(_io_out_s_opc_T)
node io_out_s_opc = mux(_io_out_s_opc_T_1, UInt<7>(0h13), UInt<7>(0h1f))
node _io_out_s_T = bits(io.in, 10, 7)
node _io_out_s_T_1 = bits(io.in, 12, 11)
node _io_out_s_T_2 = bits(io.in, 5, 5)
node _io_out_s_T_3 = bits(io.in, 6, 6)
node io_out_s_lo = cat(_io_out_s_T_3, UInt<2>(0h0))
node io_out_s_hi_hi = cat(_io_out_s_T, _io_out_s_T_1)
node io_out_s_hi = cat(io_out_s_hi_hi, _io_out_s_T_2)
node _io_out_s_T_4 = cat(io_out_s_hi, io_out_s_lo)
node _io_out_s_T_5 = bits(io.in, 4, 2)
node _io_out_s_T_6 = cat(UInt<2>(0h1), _io_out_s_T_5)
node io_out_s_lo_1 = cat(_io_out_s_T_6, io_out_s_opc)
node io_out_s_hi_hi_1 = cat(_io_out_s_T_4, UInt<5>(0h2))
node io_out_s_hi_1 = cat(io_out_s_hi_hi_1, UInt<3>(0h0))
node _io_out_s_T_7 = cat(io_out_s_hi_1, io_out_s_lo_1)
node _io_out_s_T_8 = bits(io.in, 4, 2)
node _io_out_s_T_9 = cat(UInt<2>(0h1), _io_out_s_T_8)
node _io_out_s_T_10 = bits(io.in, 4, 2)
node _io_out_s_T_11 = cat(UInt<2>(0h1), _io_out_s_T_10)
node _io_out_s_T_12 = bits(io.in, 31, 27)
wire io_out_s_0 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_0.bits, _io_out_s_T_7
connect io_out_s_0.rd, _io_out_s_T_9
connect io_out_s_0.rs1, UInt<5>(0h2)
connect io_out_s_0.rs2, _io_out_s_T_11
connect io_out_s_0.rs3, _io_out_s_T_12
node _io_out_s_T_13 = bits(io.in, 6, 5)
node _io_out_s_T_14 = bits(io.in, 12, 10)
node io_out_s_hi_2 = cat(_io_out_s_T_13, _io_out_s_T_14)
node _io_out_s_T_15 = cat(io_out_s_hi_2, UInt<3>(0h0))
node _io_out_s_T_16 = bits(io.in, 9, 7)
node _io_out_s_T_17 = cat(UInt<2>(0h1), _io_out_s_T_16)
node _io_out_s_T_18 = bits(io.in, 4, 2)
node _io_out_s_T_19 = cat(UInt<2>(0h1), _io_out_s_T_18)
node io_out_s_lo_2 = cat(_io_out_s_T_19, UInt<7>(0h7))
node io_out_s_hi_hi_2 = cat(_io_out_s_T_15, _io_out_s_T_17)
node io_out_s_hi_3 = cat(io_out_s_hi_hi_2, UInt<3>(0h3))
node _io_out_s_T_20 = cat(io_out_s_hi_3, io_out_s_lo_2)
node _io_out_s_T_21 = bits(io.in, 4, 2)
node _io_out_s_T_22 = cat(UInt<2>(0h1), _io_out_s_T_21)
node _io_out_s_T_23 = bits(io.in, 9, 7)
node _io_out_s_T_24 = cat(UInt<2>(0h1), _io_out_s_T_23)
node _io_out_s_T_25 = bits(io.in, 4, 2)
node _io_out_s_T_26 = cat(UInt<2>(0h1), _io_out_s_T_25)
node _io_out_s_T_27 = bits(io.in, 31, 27)
wire io_out_s_1 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_1.bits, _io_out_s_T_20
connect io_out_s_1.rd, _io_out_s_T_22
connect io_out_s_1.rs1, _io_out_s_T_24
connect io_out_s_1.rs2, _io_out_s_T_26
connect io_out_s_1.rs3, _io_out_s_T_27
node _io_out_s_T_28 = bits(io.in, 5, 5)
node _io_out_s_T_29 = bits(io.in, 12, 10)
node _io_out_s_T_30 = bits(io.in, 6, 6)
node io_out_s_lo_3 = cat(_io_out_s_T_30, UInt<2>(0h0))
node io_out_s_hi_4 = cat(_io_out_s_T_28, _io_out_s_T_29)
node _io_out_s_T_31 = cat(io_out_s_hi_4, io_out_s_lo_3)
node _io_out_s_T_32 = bits(io.in, 9, 7)
node _io_out_s_T_33 = cat(UInt<2>(0h1), _io_out_s_T_32)
node _io_out_s_T_34 = bits(io.in, 4, 2)
node _io_out_s_T_35 = cat(UInt<2>(0h1), _io_out_s_T_34)
node io_out_s_lo_4 = cat(_io_out_s_T_35, UInt<7>(0h3))
node io_out_s_hi_hi_3 = cat(_io_out_s_T_31, _io_out_s_T_33)
node io_out_s_hi_5 = cat(io_out_s_hi_hi_3, UInt<3>(0h2))
node _io_out_s_T_36 = cat(io_out_s_hi_5, io_out_s_lo_4)
node _io_out_s_T_37 = bits(io.in, 4, 2)
node _io_out_s_T_38 = cat(UInt<2>(0h1), _io_out_s_T_37)
node _io_out_s_T_39 = bits(io.in, 9, 7)
node _io_out_s_T_40 = cat(UInt<2>(0h1), _io_out_s_T_39)
node _io_out_s_T_41 = bits(io.in, 4, 2)
node _io_out_s_T_42 = cat(UInt<2>(0h1), _io_out_s_T_41)
node _io_out_s_T_43 = bits(io.in, 31, 27)
wire io_out_s_2 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_2.bits, _io_out_s_T_36
connect io_out_s_2.rd, _io_out_s_T_38
connect io_out_s_2.rs1, _io_out_s_T_40
connect io_out_s_2.rs2, _io_out_s_T_42
connect io_out_s_2.rs3, _io_out_s_T_43
node _io_out_s_T_44 = bits(io.in, 6, 5)
node _io_out_s_T_45 = bits(io.in, 12, 10)
node io_out_s_hi_6 = cat(_io_out_s_T_44, _io_out_s_T_45)
node _io_out_s_T_46 = cat(io_out_s_hi_6, UInt<3>(0h0))
node _io_out_s_T_47 = bits(io.in, 9, 7)
node _io_out_s_T_48 = cat(UInt<2>(0h1), _io_out_s_T_47)
node _io_out_s_T_49 = bits(io.in, 4, 2)
node _io_out_s_T_50 = cat(UInt<2>(0h1), _io_out_s_T_49)
node io_out_s_lo_5 = cat(_io_out_s_T_50, UInt<7>(0h3))
node io_out_s_hi_hi_4 = cat(_io_out_s_T_46, _io_out_s_T_48)
node io_out_s_hi_7 = cat(io_out_s_hi_hi_4, UInt<3>(0h3))
node _io_out_s_T_51 = cat(io_out_s_hi_7, io_out_s_lo_5)
node _io_out_s_T_52 = bits(io.in, 4, 2)
node _io_out_s_T_53 = cat(UInt<2>(0h1), _io_out_s_T_52)
node _io_out_s_T_54 = bits(io.in, 9, 7)
node _io_out_s_T_55 = cat(UInt<2>(0h1), _io_out_s_T_54)
node _io_out_s_T_56 = bits(io.in, 4, 2)
node _io_out_s_T_57 = cat(UInt<2>(0h1), _io_out_s_T_56)
node _io_out_s_T_58 = bits(io.in, 31, 27)
wire io_out_s_3 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_3.bits, _io_out_s_T_51
connect io_out_s_3.rd, _io_out_s_T_53
connect io_out_s_3.rs1, _io_out_s_T_55
connect io_out_s_3.rs2, _io_out_s_T_57
connect io_out_s_3.rs3, _io_out_s_T_58
node _io_out_s_T_59 = bits(io.in, 5, 5)
node _io_out_s_T_60 = bits(io.in, 12, 10)
node _io_out_s_T_61 = bits(io.in, 6, 6)
node io_out_s_lo_6 = cat(_io_out_s_T_61, UInt<2>(0h0))
node io_out_s_hi_8 = cat(_io_out_s_T_59, _io_out_s_T_60)
node _io_out_s_T_62 = cat(io_out_s_hi_8, io_out_s_lo_6)
node _io_out_s_T_63 = shr(_io_out_s_T_62, 5)
node _io_out_s_T_64 = bits(io.in, 4, 2)
node _io_out_s_T_65 = cat(UInt<2>(0h1), _io_out_s_T_64)
node _io_out_s_T_66 = bits(io.in, 9, 7)
node _io_out_s_T_67 = cat(UInt<2>(0h1), _io_out_s_T_66)
node _io_out_s_T_68 = bits(io.in, 5, 5)
node _io_out_s_T_69 = bits(io.in, 12, 10)
node _io_out_s_T_70 = bits(io.in, 6, 6)
node io_out_s_lo_7 = cat(_io_out_s_T_70, UInt<2>(0h0))
node io_out_s_hi_9 = cat(_io_out_s_T_68, _io_out_s_T_69)
node _io_out_s_T_71 = cat(io_out_s_hi_9, io_out_s_lo_7)
node _io_out_s_T_72 = bits(_io_out_s_T_71, 4, 0)
node io_out_s_lo_hi = cat(UInt<3>(0h2), _io_out_s_T_72)
node io_out_s_lo_8 = cat(io_out_s_lo_hi, UInt<7>(0h3f))
node io_out_s_hi_hi_5 = cat(_io_out_s_T_63, _io_out_s_T_65)
node io_out_s_hi_10 = cat(io_out_s_hi_hi_5, _io_out_s_T_67)
node _io_out_s_T_73 = cat(io_out_s_hi_10, io_out_s_lo_8)
node _io_out_s_T_74 = bits(io.in, 4, 2)
node _io_out_s_T_75 = cat(UInt<2>(0h1), _io_out_s_T_74)
node _io_out_s_T_76 = bits(io.in, 9, 7)
node _io_out_s_T_77 = cat(UInt<2>(0h1), _io_out_s_T_76)
node _io_out_s_T_78 = bits(io.in, 4, 2)
node _io_out_s_T_79 = cat(UInt<2>(0h1), _io_out_s_T_78)
node _io_out_s_T_80 = bits(io.in, 31, 27)
wire io_out_s_4 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_4.bits, _io_out_s_T_73
connect io_out_s_4.rd, _io_out_s_T_75
connect io_out_s_4.rs1, _io_out_s_T_77
connect io_out_s_4.rs2, _io_out_s_T_79
connect io_out_s_4.rs3, _io_out_s_T_80
node _io_out_s_T_81 = bits(io.in, 6, 5)
node _io_out_s_T_82 = bits(io.in, 12, 10)
node io_out_s_hi_11 = cat(_io_out_s_T_81, _io_out_s_T_82)
node _io_out_s_T_83 = cat(io_out_s_hi_11, UInt<3>(0h0))
node _io_out_s_T_84 = shr(_io_out_s_T_83, 5)
node _io_out_s_T_85 = bits(io.in, 4, 2)
node _io_out_s_T_86 = cat(UInt<2>(0h1), _io_out_s_T_85)
node _io_out_s_T_87 = bits(io.in, 9, 7)
node _io_out_s_T_88 = cat(UInt<2>(0h1), _io_out_s_T_87)
node _io_out_s_T_89 = bits(io.in, 6, 5)
node _io_out_s_T_90 = bits(io.in, 12, 10)
node io_out_s_hi_12 = cat(_io_out_s_T_89, _io_out_s_T_90)
node _io_out_s_T_91 = cat(io_out_s_hi_12, UInt<3>(0h0))
node _io_out_s_T_92 = bits(_io_out_s_T_91, 4, 0)
node io_out_s_lo_hi_1 = cat(UInt<3>(0h3), _io_out_s_T_92)
node io_out_s_lo_9 = cat(io_out_s_lo_hi_1, UInt<7>(0h27))
node io_out_s_hi_hi_6 = cat(_io_out_s_T_84, _io_out_s_T_86)
node io_out_s_hi_13 = cat(io_out_s_hi_hi_6, _io_out_s_T_88)
node _io_out_s_T_93 = cat(io_out_s_hi_13, io_out_s_lo_9)
node _io_out_s_T_94 = bits(io.in, 4, 2)
node _io_out_s_T_95 = cat(UInt<2>(0h1), _io_out_s_T_94)
node _io_out_s_T_96 = bits(io.in, 9, 7)
node _io_out_s_T_97 = cat(UInt<2>(0h1), _io_out_s_T_96)
node _io_out_s_T_98 = bits(io.in, 4, 2)
node _io_out_s_T_99 = cat(UInt<2>(0h1), _io_out_s_T_98)
node _io_out_s_T_100 = bits(io.in, 31, 27)
wire io_out_s_5 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_5.bits, _io_out_s_T_93
connect io_out_s_5.rd, _io_out_s_T_95
connect io_out_s_5.rs1, _io_out_s_T_97
connect io_out_s_5.rs2, _io_out_s_T_99
connect io_out_s_5.rs3, _io_out_s_T_100
node _io_out_s_T_101 = bits(io.in, 5, 5)
node _io_out_s_T_102 = bits(io.in, 12, 10)
node _io_out_s_T_103 = bits(io.in, 6, 6)
node io_out_s_lo_10 = cat(_io_out_s_T_103, UInt<2>(0h0))
node io_out_s_hi_14 = cat(_io_out_s_T_101, _io_out_s_T_102)
node _io_out_s_T_104 = cat(io_out_s_hi_14, io_out_s_lo_10)
node _io_out_s_T_105 = shr(_io_out_s_T_104, 5)
node _io_out_s_T_106 = bits(io.in, 4, 2)
node _io_out_s_T_107 = cat(UInt<2>(0h1), _io_out_s_T_106)
node _io_out_s_T_108 = bits(io.in, 9, 7)
node _io_out_s_T_109 = cat(UInt<2>(0h1), _io_out_s_T_108)
node _io_out_s_T_110 = bits(io.in, 5, 5)
node _io_out_s_T_111 = bits(io.in, 12, 10)
node _io_out_s_T_112 = bits(io.in, 6, 6)
node io_out_s_lo_11 = cat(_io_out_s_T_112, UInt<2>(0h0))
node io_out_s_hi_15 = cat(_io_out_s_T_110, _io_out_s_T_111)
node _io_out_s_T_113 = cat(io_out_s_hi_15, io_out_s_lo_11)
node _io_out_s_T_114 = bits(_io_out_s_T_113, 4, 0)
node io_out_s_lo_hi_2 = cat(UInt<3>(0h2), _io_out_s_T_114)
node io_out_s_lo_12 = cat(io_out_s_lo_hi_2, UInt<7>(0h23))
node io_out_s_hi_hi_7 = cat(_io_out_s_T_105, _io_out_s_T_107)
node io_out_s_hi_16 = cat(io_out_s_hi_hi_7, _io_out_s_T_109)
node _io_out_s_T_115 = cat(io_out_s_hi_16, io_out_s_lo_12)
node _io_out_s_T_116 = bits(io.in, 4, 2)
node _io_out_s_T_117 = cat(UInt<2>(0h1), _io_out_s_T_116)
node _io_out_s_T_118 = bits(io.in, 9, 7)
node _io_out_s_T_119 = cat(UInt<2>(0h1), _io_out_s_T_118)
node _io_out_s_T_120 = bits(io.in, 4, 2)
node _io_out_s_T_121 = cat(UInt<2>(0h1), _io_out_s_T_120)
node _io_out_s_T_122 = bits(io.in, 31, 27)
wire io_out_s_6 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_6.bits, _io_out_s_T_115
connect io_out_s_6.rd, _io_out_s_T_117
connect io_out_s_6.rs1, _io_out_s_T_119
connect io_out_s_6.rs2, _io_out_s_T_121
connect io_out_s_6.rs3, _io_out_s_T_122
node _io_out_s_T_123 = bits(io.in, 6, 5)
node _io_out_s_T_124 = bits(io.in, 12, 10)
node io_out_s_hi_17 = cat(_io_out_s_T_123, _io_out_s_T_124)
node _io_out_s_T_125 = cat(io_out_s_hi_17, UInt<3>(0h0))
node _io_out_s_T_126 = shr(_io_out_s_T_125, 5)
node _io_out_s_T_127 = bits(io.in, 4, 2)
node _io_out_s_T_128 = cat(UInt<2>(0h1), _io_out_s_T_127)
node _io_out_s_T_129 = bits(io.in, 9, 7)
node _io_out_s_T_130 = cat(UInt<2>(0h1), _io_out_s_T_129)
node _io_out_s_T_131 = bits(io.in, 6, 5)
node _io_out_s_T_132 = bits(io.in, 12, 10)
node io_out_s_hi_18 = cat(_io_out_s_T_131, _io_out_s_T_132)
node _io_out_s_T_133 = cat(io_out_s_hi_18, UInt<3>(0h0))
node _io_out_s_T_134 = bits(_io_out_s_T_133, 4, 0)
node io_out_s_lo_hi_3 = cat(UInt<3>(0h3), _io_out_s_T_134)
node io_out_s_lo_13 = cat(io_out_s_lo_hi_3, UInt<7>(0h23))
node io_out_s_hi_hi_8 = cat(_io_out_s_T_126, _io_out_s_T_128)
node io_out_s_hi_19 = cat(io_out_s_hi_hi_8, _io_out_s_T_130)
node _io_out_s_T_135 = cat(io_out_s_hi_19, io_out_s_lo_13)
node _io_out_s_T_136 = bits(io.in, 4, 2)
node _io_out_s_T_137 = cat(UInt<2>(0h1), _io_out_s_T_136)
node _io_out_s_T_138 = bits(io.in, 9, 7)
node _io_out_s_T_139 = cat(UInt<2>(0h1), _io_out_s_T_138)
node _io_out_s_T_140 = bits(io.in, 4, 2)
node _io_out_s_T_141 = cat(UInt<2>(0h1), _io_out_s_T_140)
node _io_out_s_T_142 = bits(io.in, 31, 27)
wire io_out_s_7 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_7.bits, _io_out_s_T_135
connect io_out_s_7.rd, _io_out_s_T_137
connect io_out_s_7.rs1, _io_out_s_T_139
connect io_out_s_7.rs2, _io_out_s_T_141
connect io_out_s_7.rs3, _io_out_s_T_142
node _io_out_s_T_143 = bits(io.in, 12, 12)
node _io_out_s_T_144 = mux(_io_out_s_T_143, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_145 = bits(io.in, 6, 2)
node _io_out_s_T_146 = cat(_io_out_s_T_144, _io_out_s_T_145)
node _io_out_s_T_147 = bits(io.in, 11, 7)
node _io_out_s_T_148 = bits(io.in, 11, 7)
node io_out_s_lo_14 = cat(_io_out_s_T_148, UInt<7>(0h13))
node io_out_s_hi_hi_9 = cat(_io_out_s_T_146, _io_out_s_T_147)
node io_out_s_hi_20 = cat(io_out_s_hi_hi_9, UInt<3>(0h0))
node _io_out_s_T_149 = cat(io_out_s_hi_20, io_out_s_lo_14)
node _io_out_s_T_150 = bits(io.in, 11, 7)
node _io_out_s_T_151 = bits(io.in, 11, 7)
node _io_out_s_T_152 = bits(io.in, 4, 2)
node _io_out_s_T_153 = cat(UInt<2>(0h1), _io_out_s_T_152)
node _io_out_s_T_154 = bits(io.in, 31, 27)
wire io_out_s_8 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_8.bits, _io_out_s_T_149
connect io_out_s_8.rd, _io_out_s_T_150
connect io_out_s_8.rs1, _io_out_s_T_151
connect io_out_s_8.rs2, _io_out_s_T_153
connect io_out_s_8.rs3, _io_out_s_T_154
node _io_out_s_opc_T_2 = bits(io.in, 11, 7)
node _io_out_s_opc_T_3 = orr(_io_out_s_opc_T_2)
node io_out_s_opc_1 = mux(_io_out_s_opc_T_3, UInt<7>(0h1b), UInt<7>(0h1f))
node _io_out_s_T_155 = bits(io.in, 12, 12)
node _io_out_s_T_156 = mux(_io_out_s_T_155, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_157 = bits(io.in, 6, 2)
node _io_out_s_T_158 = cat(_io_out_s_T_156, _io_out_s_T_157)
node _io_out_s_T_159 = bits(io.in, 11, 7)
node _io_out_s_T_160 = bits(io.in, 11, 7)
node io_out_s_lo_15 = cat(_io_out_s_T_160, io_out_s_opc_1)
node io_out_s_hi_hi_10 = cat(_io_out_s_T_158, _io_out_s_T_159)
node io_out_s_hi_21 = cat(io_out_s_hi_hi_10, UInt<3>(0h0))
node _io_out_s_T_161 = cat(io_out_s_hi_21, io_out_s_lo_15)
node _io_out_s_T_162 = bits(io.in, 11, 7)
node _io_out_s_T_163 = bits(io.in, 11, 7)
node _io_out_s_T_164 = bits(io.in, 4, 2)
node _io_out_s_T_165 = cat(UInt<2>(0h1), _io_out_s_T_164)
node _io_out_s_T_166 = bits(io.in, 31, 27)
wire io_out_s_9 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_9.bits, _io_out_s_T_161
connect io_out_s_9.rd, _io_out_s_T_162
connect io_out_s_9.rs1, _io_out_s_T_163
connect io_out_s_9.rs2, _io_out_s_T_165
connect io_out_s_9.rs3, _io_out_s_T_166
node _io_out_s_T_167 = bits(io.in, 12, 12)
node _io_out_s_T_168 = mux(_io_out_s_T_167, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_169 = bits(io.in, 6, 2)
node _io_out_s_T_170 = cat(_io_out_s_T_168, _io_out_s_T_169)
node _io_out_s_T_171 = bits(io.in, 11, 7)
node io_out_s_lo_16 = cat(_io_out_s_T_171, UInt<7>(0h13))
node io_out_s_hi_hi_11 = cat(_io_out_s_T_170, UInt<5>(0h0))
node io_out_s_hi_22 = cat(io_out_s_hi_hi_11, UInt<3>(0h0))
node _io_out_s_T_172 = cat(io_out_s_hi_22, io_out_s_lo_16)
node _io_out_s_T_173 = bits(io.in, 11, 7)
node _io_out_s_T_174 = bits(io.in, 4, 2)
node _io_out_s_T_175 = cat(UInt<2>(0h1), _io_out_s_T_174)
node _io_out_s_T_176 = bits(io.in, 31, 27)
wire io_out_s_10 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_10.bits, _io_out_s_T_172
connect io_out_s_10.rd, _io_out_s_T_173
connect io_out_s_10.rs1, UInt<5>(0h0)
connect io_out_s_10.rs2, _io_out_s_T_175
connect io_out_s_10.rs3, _io_out_s_T_176
node _io_out_s_opc_T_4 = bits(io.in, 12, 12)
node _io_out_s_opc_T_5 = mux(_io_out_s_opc_T_4, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_opc_T_6 = bits(io.in, 6, 2)
node _io_out_s_opc_T_7 = cat(_io_out_s_opc_T_5, _io_out_s_opc_T_6)
node _io_out_s_opc_T_8 = orr(_io_out_s_opc_T_7)
node io_out_s_opc_2 = mux(_io_out_s_opc_T_8, UInt<7>(0h37), UInt<7>(0h3f))
node _io_out_s_me_T = bits(io.in, 12, 12)
node _io_out_s_me_T_1 = mux(_io_out_s_me_T, UInt<15>(0h7fff), UInt<15>(0h0))
node _io_out_s_me_T_2 = bits(io.in, 6, 2)
node io_out_s_me_hi = cat(_io_out_s_me_T_1, _io_out_s_me_T_2)
node _io_out_s_me_T_3 = cat(io_out_s_me_hi, UInt<12>(0h0))
node _io_out_s_me_T_4 = bits(_io_out_s_me_T_3, 31, 12)
node _io_out_s_me_T_5 = bits(io.in, 11, 7)
node io_out_s_me_hi_1 = cat(_io_out_s_me_T_4, _io_out_s_me_T_5)
node _io_out_s_me_T_6 = cat(io_out_s_me_hi_1, io_out_s_opc_2)
node _io_out_s_me_T_7 = bits(io.in, 11, 7)
node _io_out_s_me_T_8 = bits(io.in, 11, 7)
node _io_out_s_me_T_9 = bits(io.in, 4, 2)
node _io_out_s_me_T_10 = cat(UInt<2>(0h1), _io_out_s_me_T_9)
node _io_out_s_me_T_11 = bits(io.in, 31, 27)
wire io_out_s_me : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_me.bits, _io_out_s_me_T_6
connect io_out_s_me.rd, _io_out_s_me_T_7
connect io_out_s_me.rs1, _io_out_s_me_T_8
connect io_out_s_me.rs2, _io_out_s_me_T_10
connect io_out_s_me.rs3, _io_out_s_me_T_11
node _io_out_s_T_177 = bits(io.in, 11, 7)
node _io_out_s_T_178 = eq(_io_out_s_T_177, UInt<5>(0h0))
node _io_out_s_T_179 = bits(io.in, 11, 7)
node _io_out_s_T_180 = eq(_io_out_s_T_179, UInt<5>(0h2))
node _io_out_s_T_181 = or(_io_out_s_T_178, _io_out_s_T_180)
node _io_out_s_opc_T_9 = bits(io.in, 12, 12)
node _io_out_s_opc_T_10 = mux(_io_out_s_opc_T_9, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_opc_T_11 = bits(io.in, 6, 2)
node _io_out_s_opc_T_12 = cat(_io_out_s_opc_T_10, _io_out_s_opc_T_11)
node _io_out_s_opc_T_13 = orr(_io_out_s_opc_T_12)
node io_out_s_opc_3 = mux(_io_out_s_opc_T_13, UInt<7>(0h13), UInt<7>(0h1f))
node _io_out_s_T_182 = bits(io.in, 12, 12)
node _io_out_s_T_183 = mux(_io_out_s_T_182, UInt<3>(0h7), UInt<3>(0h0))
node _io_out_s_T_184 = bits(io.in, 4, 3)
node _io_out_s_T_185 = bits(io.in, 5, 5)
node _io_out_s_T_186 = bits(io.in, 2, 2)
node _io_out_s_T_187 = bits(io.in, 6, 6)
node io_out_s_lo_hi_4 = cat(_io_out_s_T_186, _io_out_s_T_187)
node io_out_s_lo_17 = cat(io_out_s_lo_hi_4, UInt<4>(0h0))
node io_out_s_hi_hi_12 = cat(_io_out_s_T_183, _io_out_s_T_184)
node io_out_s_hi_23 = cat(io_out_s_hi_hi_12, _io_out_s_T_185)
node _io_out_s_T_188 = cat(io_out_s_hi_23, io_out_s_lo_17)
node _io_out_s_T_189 = bits(io.in, 11, 7)
node _io_out_s_T_190 = bits(io.in, 11, 7)
node io_out_s_lo_18 = cat(_io_out_s_T_190, io_out_s_opc_3)
node io_out_s_hi_hi_13 = cat(_io_out_s_T_188, _io_out_s_T_189)
node io_out_s_hi_24 = cat(io_out_s_hi_hi_13, UInt<3>(0h0))
node _io_out_s_T_191 = cat(io_out_s_hi_24, io_out_s_lo_18)
node _io_out_s_T_192 = bits(io.in, 11, 7)
node _io_out_s_T_193 = bits(io.in, 11, 7)
node _io_out_s_T_194 = bits(io.in, 4, 2)
node _io_out_s_T_195 = cat(UInt<2>(0h1), _io_out_s_T_194)
node _io_out_s_T_196 = bits(io.in, 31, 27)
wire io_out_s_res : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_res.bits, _io_out_s_T_191
connect io_out_s_res.rd, _io_out_s_T_192
connect io_out_s_res.rs1, _io_out_s_T_193
connect io_out_s_res.rs2, _io_out_s_T_195
connect io_out_s_res.rs3, _io_out_s_T_196
node io_out_s_11 = mux(_io_out_s_T_181, io_out_s_res, io_out_s_me)
node _io_out_s_T_197 = bits(io.in, 12, 12)
node _io_out_s_T_198 = bits(io.in, 6, 2)
node _io_out_s_T_199 = cat(_io_out_s_T_197, _io_out_s_T_198)
node _io_out_s_T_200 = bits(io.in, 9, 7)
node _io_out_s_T_201 = cat(UInt<2>(0h1), _io_out_s_T_200)
node _io_out_s_T_202 = bits(io.in, 9, 7)
node _io_out_s_T_203 = cat(UInt<2>(0h1), _io_out_s_T_202)
node io_out_s_lo_19 = cat(_io_out_s_T_203, UInt<7>(0h13))
node io_out_s_hi_hi_14 = cat(_io_out_s_T_199, _io_out_s_T_201)
node io_out_s_hi_25 = cat(io_out_s_hi_hi_14, UInt<3>(0h5))
node _io_out_s_T_204 = cat(io_out_s_hi_25, io_out_s_lo_19)
node _io_out_s_T_205 = bits(io.in, 12, 12)
node _io_out_s_T_206 = bits(io.in, 6, 2)
node _io_out_s_T_207 = cat(_io_out_s_T_205, _io_out_s_T_206)
node _io_out_s_T_208 = bits(io.in, 9, 7)
node _io_out_s_T_209 = cat(UInt<2>(0h1), _io_out_s_T_208)
node _io_out_s_T_210 = bits(io.in, 9, 7)
node _io_out_s_T_211 = cat(UInt<2>(0h1), _io_out_s_T_210)
node io_out_s_lo_20 = cat(_io_out_s_T_211, UInt<7>(0h13))
node io_out_s_hi_hi_15 = cat(_io_out_s_T_207, _io_out_s_T_209)
node io_out_s_hi_26 = cat(io_out_s_hi_hi_15, UInt<3>(0h5))
node _io_out_s_T_212 = cat(io_out_s_hi_26, io_out_s_lo_20)
node _io_out_s_T_213 = or(_io_out_s_T_212, UInt<31>(0h40000000))
node _io_out_s_T_214 = bits(io.in, 12, 12)
node _io_out_s_T_215 = mux(_io_out_s_T_214, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_216 = bits(io.in, 6, 2)
node _io_out_s_T_217 = cat(_io_out_s_T_215, _io_out_s_T_216)
node _io_out_s_T_218 = bits(io.in, 9, 7)
node _io_out_s_T_219 = cat(UInt<2>(0h1), _io_out_s_T_218)
node _io_out_s_T_220 = bits(io.in, 9, 7)
node _io_out_s_T_221 = cat(UInt<2>(0h1), _io_out_s_T_220)
node io_out_s_lo_21 = cat(_io_out_s_T_221, UInt<7>(0h13))
node io_out_s_hi_hi_16 = cat(_io_out_s_T_217, _io_out_s_T_219)
node io_out_s_hi_27 = cat(io_out_s_hi_hi_16, UInt<3>(0h7))
node _io_out_s_T_222 = cat(io_out_s_hi_27, io_out_s_lo_21)
node _io_out_s_funct_T = bits(io.in, 12, 12)
node _io_out_s_funct_T_1 = bits(io.in, 6, 5)
node _io_out_s_funct_T_2 = cat(_io_out_s_funct_T, _io_out_s_funct_T_1)
node _io_out_s_funct_T_3 = eq(_io_out_s_funct_T_2, UInt<1>(0h1))
node _io_out_s_funct_T_4 = mux(_io_out_s_funct_T_3, UInt<3>(0h4), UInt<1>(0h0))
node _io_out_s_funct_T_5 = eq(_io_out_s_funct_T_2, UInt<2>(0h2))
node _io_out_s_funct_T_6 = mux(_io_out_s_funct_T_5, UInt<3>(0h6), _io_out_s_funct_T_4)
node _io_out_s_funct_T_7 = eq(_io_out_s_funct_T_2, UInt<2>(0h3))
node _io_out_s_funct_T_8 = mux(_io_out_s_funct_T_7, UInt<3>(0h7), _io_out_s_funct_T_6)
node _io_out_s_funct_T_9 = eq(_io_out_s_funct_T_2, UInt<3>(0h4))
node _io_out_s_funct_T_10 = mux(_io_out_s_funct_T_9, UInt<1>(0h0), _io_out_s_funct_T_8)
node _io_out_s_funct_T_11 = eq(_io_out_s_funct_T_2, UInt<3>(0h5))
node _io_out_s_funct_T_12 = mux(_io_out_s_funct_T_11, UInt<1>(0h0), _io_out_s_funct_T_10)
node _io_out_s_funct_T_13 = eq(_io_out_s_funct_T_2, UInt<3>(0h6))
node _io_out_s_funct_T_14 = mux(_io_out_s_funct_T_13, UInt<2>(0h2), _io_out_s_funct_T_12)
node _io_out_s_funct_T_15 = eq(_io_out_s_funct_T_2, UInt<3>(0h7))
node io_out_s_funct = mux(_io_out_s_funct_T_15, UInt<2>(0h3), _io_out_s_funct_T_14)
node _io_out_s_sub_T = bits(io.in, 6, 5)
node _io_out_s_sub_T_1 = eq(_io_out_s_sub_T, UInt<1>(0h0))
node io_out_s_sub = mux(_io_out_s_sub_T_1, UInt<31>(0h40000000), UInt<1>(0h0))
node _io_out_s_opc_T_14 = bits(io.in, 12, 12)
node io_out_s_opc_4 = mux(_io_out_s_opc_T_14, UInt<7>(0h3b), UInt<7>(0h33))
node _io_out_s_T_223 = bits(io.in, 4, 2)
node _io_out_s_T_224 = cat(UInt<2>(0h1), _io_out_s_T_223)
node _io_out_s_T_225 = bits(io.in, 9, 7)
node _io_out_s_T_226 = cat(UInt<2>(0h1), _io_out_s_T_225)
node _io_out_s_T_227 = bits(io.in, 9, 7)
node _io_out_s_T_228 = cat(UInt<2>(0h1), _io_out_s_T_227)
node io_out_s_lo_22 = cat(_io_out_s_T_228, io_out_s_opc_4)
node io_out_s_hi_hi_17 = cat(_io_out_s_T_224, _io_out_s_T_226)
node io_out_s_hi_28 = cat(io_out_s_hi_hi_17, io_out_s_funct)
node _io_out_s_T_229 = cat(io_out_s_hi_28, io_out_s_lo_22)
node _io_out_s_T_230 = or(_io_out_s_T_229, io_out_s_sub)
node _io_out_s_T_231 = bits(io.in, 11, 10)
node _io_out_s_T_232 = eq(_io_out_s_T_231, UInt<1>(0h1))
node _io_out_s_T_233 = mux(_io_out_s_T_232, _io_out_s_T_213, _io_out_s_T_204)
node _io_out_s_T_234 = eq(_io_out_s_T_231, UInt<2>(0h2))
node _io_out_s_T_235 = mux(_io_out_s_T_234, _io_out_s_T_222, _io_out_s_T_233)
node _io_out_s_T_236 = eq(_io_out_s_T_231, UInt<2>(0h3))
node _io_out_s_T_237 = mux(_io_out_s_T_236, _io_out_s_T_230, _io_out_s_T_235)
node _io_out_s_T_238 = bits(io.in, 9, 7)
node _io_out_s_T_239 = cat(UInt<2>(0h1), _io_out_s_T_238)
node _io_out_s_T_240 = bits(io.in, 9, 7)
node _io_out_s_T_241 = cat(UInt<2>(0h1), _io_out_s_T_240)
node _io_out_s_T_242 = bits(io.in, 4, 2)
node _io_out_s_T_243 = cat(UInt<2>(0h1), _io_out_s_T_242)
node _io_out_s_T_244 = bits(io.in, 31, 27)
wire io_out_s_12 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_12.bits, _io_out_s_T_237
connect io_out_s_12.rd, _io_out_s_T_239
connect io_out_s_12.rs1, _io_out_s_T_241
connect io_out_s_12.rs2, _io_out_s_T_243
connect io_out_s_12.rs3, _io_out_s_T_244
node _io_out_s_T_245 = bits(io.in, 12, 12)
node _io_out_s_T_246 = mux(_io_out_s_T_245, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_247 = bits(io.in, 8, 8)
node _io_out_s_T_248 = bits(io.in, 10, 9)
node _io_out_s_T_249 = bits(io.in, 6, 6)
node _io_out_s_T_250 = bits(io.in, 7, 7)
node _io_out_s_T_251 = bits(io.in, 2, 2)
node _io_out_s_T_252 = bits(io.in, 11, 11)
node _io_out_s_T_253 = bits(io.in, 5, 3)
node io_out_s_lo_lo = cat(_io_out_s_T_253, UInt<1>(0h0))
node io_out_s_lo_hi_5 = cat(_io_out_s_T_251, _io_out_s_T_252)
node io_out_s_lo_23 = cat(io_out_s_lo_hi_5, io_out_s_lo_lo)
node io_out_s_hi_lo = cat(_io_out_s_T_249, _io_out_s_T_250)
node io_out_s_hi_hi_hi = cat(_io_out_s_T_246, _io_out_s_T_247)
node io_out_s_hi_hi_18 = cat(io_out_s_hi_hi_hi, _io_out_s_T_248)
node io_out_s_hi_29 = cat(io_out_s_hi_hi_18, io_out_s_hi_lo)
node _io_out_s_T_254 = cat(io_out_s_hi_29, io_out_s_lo_23)
node _io_out_s_T_255 = bits(_io_out_s_T_254, 20, 20)
node _io_out_s_T_256 = bits(io.in, 12, 12)
node _io_out_s_T_257 = mux(_io_out_s_T_256, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_258 = bits(io.in, 8, 8)
node _io_out_s_T_259 = bits(io.in, 10, 9)
node _io_out_s_T_260 = bits(io.in, 6, 6)
node _io_out_s_T_261 = bits(io.in, 7, 7)
node _io_out_s_T_262 = bits(io.in, 2, 2)
node _io_out_s_T_263 = bits(io.in, 11, 11)
node _io_out_s_T_264 = bits(io.in, 5, 3)
node io_out_s_lo_lo_1 = cat(_io_out_s_T_264, UInt<1>(0h0))
node io_out_s_lo_hi_6 = cat(_io_out_s_T_262, _io_out_s_T_263)
node io_out_s_lo_24 = cat(io_out_s_lo_hi_6, io_out_s_lo_lo_1)
node io_out_s_hi_lo_1 = cat(_io_out_s_T_260, _io_out_s_T_261)
node io_out_s_hi_hi_hi_1 = cat(_io_out_s_T_257, _io_out_s_T_258)
node io_out_s_hi_hi_19 = cat(io_out_s_hi_hi_hi_1, _io_out_s_T_259)
node io_out_s_hi_30 = cat(io_out_s_hi_hi_19, io_out_s_hi_lo_1)
node _io_out_s_T_265 = cat(io_out_s_hi_30, io_out_s_lo_24)
node _io_out_s_T_266 = bits(_io_out_s_T_265, 10, 1)
node _io_out_s_T_267 = bits(io.in, 12, 12)
node _io_out_s_T_268 = mux(_io_out_s_T_267, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_269 = bits(io.in, 8, 8)
node _io_out_s_T_270 = bits(io.in, 10, 9)
node _io_out_s_T_271 = bits(io.in, 6, 6)
node _io_out_s_T_272 = bits(io.in, 7, 7)
node _io_out_s_T_273 = bits(io.in, 2, 2)
node _io_out_s_T_274 = bits(io.in, 11, 11)
node _io_out_s_T_275 = bits(io.in, 5, 3)
node io_out_s_lo_lo_2 = cat(_io_out_s_T_275, UInt<1>(0h0))
node io_out_s_lo_hi_7 = cat(_io_out_s_T_273, _io_out_s_T_274)
node io_out_s_lo_25 = cat(io_out_s_lo_hi_7, io_out_s_lo_lo_2)
node io_out_s_hi_lo_2 = cat(_io_out_s_T_271, _io_out_s_T_272)
node io_out_s_hi_hi_hi_2 = cat(_io_out_s_T_268, _io_out_s_T_269)
node io_out_s_hi_hi_20 = cat(io_out_s_hi_hi_hi_2, _io_out_s_T_270)
node io_out_s_hi_31 = cat(io_out_s_hi_hi_20, io_out_s_hi_lo_2)
node _io_out_s_T_276 = cat(io_out_s_hi_31, io_out_s_lo_25)
node _io_out_s_T_277 = bits(_io_out_s_T_276, 11, 11)
node _io_out_s_T_278 = bits(io.in, 12, 12)
node _io_out_s_T_279 = mux(_io_out_s_T_278, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_280 = bits(io.in, 8, 8)
node _io_out_s_T_281 = bits(io.in, 10, 9)
node _io_out_s_T_282 = bits(io.in, 6, 6)
node _io_out_s_T_283 = bits(io.in, 7, 7)
node _io_out_s_T_284 = bits(io.in, 2, 2)
node _io_out_s_T_285 = bits(io.in, 11, 11)
node _io_out_s_T_286 = bits(io.in, 5, 3)
node io_out_s_lo_lo_3 = cat(_io_out_s_T_286, UInt<1>(0h0))
node io_out_s_lo_hi_8 = cat(_io_out_s_T_284, _io_out_s_T_285)
node io_out_s_lo_26 = cat(io_out_s_lo_hi_8, io_out_s_lo_lo_3)
node io_out_s_hi_lo_3 = cat(_io_out_s_T_282, _io_out_s_T_283)
node io_out_s_hi_hi_hi_3 = cat(_io_out_s_T_279, _io_out_s_T_280)
node io_out_s_hi_hi_21 = cat(io_out_s_hi_hi_hi_3, _io_out_s_T_281)
node io_out_s_hi_32 = cat(io_out_s_hi_hi_21, io_out_s_hi_lo_3)
node _io_out_s_T_287 = cat(io_out_s_hi_32, io_out_s_lo_26)
node _io_out_s_T_288 = bits(_io_out_s_T_287, 19, 12)
node io_out_s_lo_hi_9 = cat(_io_out_s_T_288, UInt<5>(0h0))
node io_out_s_lo_27 = cat(io_out_s_lo_hi_9, UInt<7>(0h6f))
node io_out_s_hi_hi_22 = cat(_io_out_s_T_255, _io_out_s_T_266)
node io_out_s_hi_33 = cat(io_out_s_hi_hi_22, _io_out_s_T_277)
node _io_out_s_T_289 = cat(io_out_s_hi_33, io_out_s_lo_27)
node _io_out_s_T_290 = bits(io.in, 9, 7)
node _io_out_s_T_291 = cat(UInt<2>(0h1), _io_out_s_T_290)
node _io_out_s_T_292 = bits(io.in, 4, 2)
node _io_out_s_T_293 = cat(UInt<2>(0h1), _io_out_s_T_292)
node _io_out_s_T_294 = bits(io.in, 31, 27)
wire io_out_s_13 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_13.bits, _io_out_s_T_289
connect io_out_s_13.rd, UInt<5>(0h0)
connect io_out_s_13.rs1, _io_out_s_T_291
connect io_out_s_13.rs2, _io_out_s_T_293
connect io_out_s_13.rs3, _io_out_s_T_294
node _io_out_s_T_295 = bits(io.in, 12, 12)
node _io_out_s_T_296 = mux(_io_out_s_T_295, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_297 = bits(io.in, 6, 5)
node _io_out_s_T_298 = bits(io.in, 2, 2)
node _io_out_s_T_299 = bits(io.in, 11, 10)
node _io_out_s_T_300 = bits(io.in, 4, 3)
node io_out_s_lo_hi_10 = cat(_io_out_s_T_299, _io_out_s_T_300)
node io_out_s_lo_28 = cat(io_out_s_lo_hi_10, UInt<1>(0h0))
node io_out_s_hi_hi_23 = cat(_io_out_s_T_296, _io_out_s_T_297)
node io_out_s_hi_34 = cat(io_out_s_hi_hi_23, _io_out_s_T_298)
node _io_out_s_T_301 = cat(io_out_s_hi_34, io_out_s_lo_28)
node _io_out_s_T_302 = bits(_io_out_s_T_301, 12, 12)
node _io_out_s_T_303 = bits(io.in, 12, 12)
node _io_out_s_T_304 = mux(_io_out_s_T_303, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_305 = bits(io.in, 6, 5)
node _io_out_s_T_306 = bits(io.in, 2, 2)
node _io_out_s_T_307 = bits(io.in, 11, 10)
node _io_out_s_T_308 = bits(io.in, 4, 3)
node io_out_s_lo_hi_11 = cat(_io_out_s_T_307, _io_out_s_T_308)
node io_out_s_lo_29 = cat(io_out_s_lo_hi_11, UInt<1>(0h0))
node io_out_s_hi_hi_24 = cat(_io_out_s_T_304, _io_out_s_T_305)
node io_out_s_hi_35 = cat(io_out_s_hi_hi_24, _io_out_s_T_306)
node _io_out_s_T_309 = cat(io_out_s_hi_35, io_out_s_lo_29)
node _io_out_s_T_310 = bits(_io_out_s_T_309, 10, 5)
node _io_out_s_T_311 = bits(io.in, 9, 7)
node _io_out_s_T_312 = cat(UInt<2>(0h1), _io_out_s_T_311)
node _io_out_s_T_313 = bits(io.in, 12, 12)
node _io_out_s_T_314 = mux(_io_out_s_T_313, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_315 = bits(io.in, 6, 5)
node _io_out_s_T_316 = bits(io.in, 2, 2)
node _io_out_s_T_317 = bits(io.in, 11, 10)
node _io_out_s_T_318 = bits(io.in, 4, 3)
node io_out_s_lo_hi_12 = cat(_io_out_s_T_317, _io_out_s_T_318)
node io_out_s_lo_30 = cat(io_out_s_lo_hi_12, UInt<1>(0h0))
node io_out_s_hi_hi_25 = cat(_io_out_s_T_314, _io_out_s_T_315)
node io_out_s_hi_36 = cat(io_out_s_hi_hi_25, _io_out_s_T_316)
node _io_out_s_T_319 = cat(io_out_s_hi_36, io_out_s_lo_30)
node _io_out_s_T_320 = bits(_io_out_s_T_319, 4, 1)
node _io_out_s_T_321 = bits(io.in, 12, 12)
node _io_out_s_T_322 = mux(_io_out_s_T_321, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_323 = bits(io.in, 6, 5)
node _io_out_s_T_324 = bits(io.in, 2, 2)
node _io_out_s_T_325 = bits(io.in, 11, 10)
node _io_out_s_T_326 = bits(io.in, 4, 3)
node io_out_s_lo_hi_13 = cat(_io_out_s_T_325, _io_out_s_T_326)
node io_out_s_lo_31 = cat(io_out_s_lo_hi_13, UInt<1>(0h0))
node io_out_s_hi_hi_26 = cat(_io_out_s_T_322, _io_out_s_T_323)
node io_out_s_hi_37 = cat(io_out_s_hi_hi_26, _io_out_s_T_324)
node _io_out_s_T_327 = cat(io_out_s_hi_37, io_out_s_lo_31)
node _io_out_s_T_328 = bits(_io_out_s_T_327, 11, 11)
node io_out_s_lo_lo_4 = cat(_io_out_s_T_328, UInt<7>(0h63))
node io_out_s_lo_hi_14 = cat(UInt<3>(0h0), _io_out_s_T_320)
node io_out_s_lo_32 = cat(io_out_s_lo_hi_14, io_out_s_lo_lo_4)
node io_out_s_hi_lo_4 = cat(UInt<5>(0h0), _io_out_s_T_312)
node io_out_s_hi_hi_27 = cat(_io_out_s_T_302, _io_out_s_T_310)
node io_out_s_hi_38 = cat(io_out_s_hi_hi_27, io_out_s_hi_lo_4)
node _io_out_s_T_329 = cat(io_out_s_hi_38, io_out_s_lo_32)
node _io_out_s_T_330 = bits(io.in, 9, 7)
node _io_out_s_T_331 = cat(UInt<2>(0h1), _io_out_s_T_330)
node _io_out_s_T_332 = bits(io.in, 9, 7)
node _io_out_s_T_333 = cat(UInt<2>(0h1), _io_out_s_T_332)
node _io_out_s_T_334 = bits(io.in, 31, 27)
wire io_out_s_14 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_14.bits, _io_out_s_T_329
connect io_out_s_14.rd, _io_out_s_T_331
connect io_out_s_14.rs1, _io_out_s_T_333
connect io_out_s_14.rs2, UInt<5>(0h0)
connect io_out_s_14.rs3, _io_out_s_T_334
node _io_out_s_T_335 = bits(io.in, 12, 12)
node _io_out_s_T_336 = mux(_io_out_s_T_335, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_337 = bits(io.in, 6, 5)
node _io_out_s_T_338 = bits(io.in, 2, 2)
node _io_out_s_T_339 = bits(io.in, 11, 10)
node _io_out_s_T_340 = bits(io.in, 4, 3)
node io_out_s_lo_hi_15 = cat(_io_out_s_T_339, _io_out_s_T_340)
node io_out_s_lo_33 = cat(io_out_s_lo_hi_15, UInt<1>(0h0))
node io_out_s_hi_hi_28 = cat(_io_out_s_T_336, _io_out_s_T_337)
node io_out_s_hi_39 = cat(io_out_s_hi_hi_28, _io_out_s_T_338)
node _io_out_s_T_341 = cat(io_out_s_hi_39, io_out_s_lo_33)
node _io_out_s_T_342 = bits(_io_out_s_T_341, 12, 12)
node _io_out_s_T_343 = bits(io.in, 12, 12)
node _io_out_s_T_344 = mux(_io_out_s_T_343, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_345 = bits(io.in, 6, 5)
node _io_out_s_T_346 = bits(io.in, 2, 2)
node _io_out_s_T_347 = bits(io.in, 11, 10)
node _io_out_s_T_348 = bits(io.in, 4, 3)
node io_out_s_lo_hi_16 = cat(_io_out_s_T_347, _io_out_s_T_348)
node io_out_s_lo_34 = cat(io_out_s_lo_hi_16, UInt<1>(0h0))
node io_out_s_hi_hi_29 = cat(_io_out_s_T_344, _io_out_s_T_345)
node io_out_s_hi_40 = cat(io_out_s_hi_hi_29, _io_out_s_T_346)
node _io_out_s_T_349 = cat(io_out_s_hi_40, io_out_s_lo_34)
node _io_out_s_T_350 = bits(_io_out_s_T_349, 10, 5)
node _io_out_s_T_351 = bits(io.in, 9, 7)
node _io_out_s_T_352 = cat(UInt<2>(0h1), _io_out_s_T_351)
node _io_out_s_T_353 = bits(io.in, 12, 12)
node _io_out_s_T_354 = mux(_io_out_s_T_353, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_355 = bits(io.in, 6, 5)
node _io_out_s_T_356 = bits(io.in, 2, 2)
node _io_out_s_T_357 = bits(io.in, 11, 10)
node _io_out_s_T_358 = bits(io.in, 4, 3)
node io_out_s_lo_hi_17 = cat(_io_out_s_T_357, _io_out_s_T_358)
node io_out_s_lo_35 = cat(io_out_s_lo_hi_17, UInt<1>(0h0))
node io_out_s_hi_hi_30 = cat(_io_out_s_T_354, _io_out_s_T_355)
node io_out_s_hi_41 = cat(io_out_s_hi_hi_30, _io_out_s_T_356)
node _io_out_s_T_359 = cat(io_out_s_hi_41, io_out_s_lo_35)
node _io_out_s_T_360 = bits(_io_out_s_T_359, 4, 1)
node _io_out_s_T_361 = bits(io.in, 12, 12)
node _io_out_s_T_362 = mux(_io_out_s_T_361, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_363 = bits(io.in, 6, 5)
node _io_out_s_T_364 = bits(io.in, 2, 2)
node _io_out_s_T_365 = bits(io.in, 11, 10)
node _io_out_s_T_366 = bits(io.in, 4, 3)
node io_out_s_lo_hi_18 = cat(_io_out_s_T_365, _io_out_s_T_366)
node io_out_s_lo_36 = cat(io_out_s_lo_hi_18, UInt<1>(0h0))
node io_out_s_hi_hi_31 = cat(_io_out_s_T_362, _io_out_s_T_363)
node io_out_s_hi_42 = cat(io_out_s_hi_hi_31, _io_out_s_T_364)
node _io_out_s_T_367 = cat(io_out_s_hi_42, io_out_s_lo_36)
node _io_out_s_T_368 = bits(_io_out_s_T_367, 11, 11)
node io_out_s_lo_lo_5 = cat(_io_out_s_T_368, UInt<7>(0h63))
node io_out_s_lo_hi_19 = cat(UInt<3>(0h1), _io_out_s_T_360)
node io_out_s_lo_37 = cat(io_out_s_lo_hi_19, io_out_s_lo_lo_5)
node io_out_s_hi_lo_5 = cat(UInt<5>(0h0), _io_out_s_T_352)
node io_out_s_hi_hi_32 = cat(_io_out_s_T_342, _io_out_s_T_350)
node io_out_s_hi_43 = cat(io_out_s_hi_hi_32, io_out_s_hi_lo_5)
node _io_out_s_T_369 = cat(io_out_s_hi_43, io_out_s_lo_37)
node _io_out_s_T_370 = bits(io.in, 9, 7)
node _io_out_s_T_371 = cat(UInt<2>(0h1), _io_out_s_T_370)
node _io_out_s_T_372 = bits(io.in, 31, 27)
wire io_out_s_15 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_15.bits, _io_out_s_T_369
connect io_out_s_15.rd, UInt<5>(0h0)
connect io_out_s_15.rs1, _io_out_s_T_371
connect io_out_s_15.rs2, UInt<5>(0h0)
connect io_out_s_15.rs3, _io_out_s_T_372
node _io_out_s_load_opc_T = bits(io.in, 11, 7)
node _io_out_s_load_opc_T_1 = orr(_io_out_s_load_opc_T)
node io_out_s_load_opc = mux(_io_out_s_load_opc_T_1, UInt<7>(0h3), UInt<7>(0h1f))
node _io_out_s_T_373 = bits(io.in, 12, 12)
node _io_out_s_T_374 = bits(io.in, 6, 2)
node _io_out_s_T_375 = cat(_io_out_s_T_373, _io_out_s_T_374)
node _io_out_s_T_376 = bits(io.in, 11, 7)
node _io_out_s_T_377 = bits(io.in, 11, 7)
node io_out_s_lo_38 = cat(_io_out_s_T_377, UInt<7>(0h13))
node io_out_s_hi_hi_33 = cat(_io_out_s_T_375, _io_out_s_T_376)
node io_out_s_hi_44 = cat(io_out_s_hi_hi_33, UInt<3>(0h1))
node _io_out_s_T_378 = cat(io_out_s_hi_44, io_out_s_lo_38)
node _io_out_s_T_379 = bits(io.in, 11, 7)
node _io_out_s_T_380 = bits(io.in, 11, 7)
node _io_out_s_T_381 = bits(io.in, 6, 2)
node _io_out_s_T_382 = bits(io.in, 31, 27)
wire io_out_s_16 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_16.bits, _io_out_s_T_378
connect io_out_s_16.rd, _io_out_s_T_379
connect io_out_s_16.rs1, _io_out_s_T_380
connect io_out_s_16.rs2, _io_out_s_T_381
connect io_out_s_16.rs3, _io_out_s_T_382
node _io_out_s_T_383 = bits(io.in, 4, 2)
node _io_out_s_T_384 = bits(io.in, 12, 12)
node _io_out_s_T_385 = bits(io.in, 6, 5)
node io_out_s_lo_39 = cat(_io_out_s_T_385, UInt<3>(0h0))
node io_out_s_hi_45 = cat(_io_out_s_T_383, _io_out_s_T_384)
node _io_out_s_T_386 = cat(io_out_s_hi_45, io_out_s_lo_39)
node _io_out_s_T_387 = bits(io.in, 11, 7)
node io_out_s_lo_40 = cat(_io_out_s_T_387, UInt<7>(0h7))
node io_out_s_hi_hi_34 = cat(_io_out_s_T_386, UInt<5>(0h2))
node io_out_s_hi_46 = cat(io_out_s_hi_hi_34, UInt<3>(0h3))
node _io_out_s_T_388 = cat(io_out_s_hi_46, io_out_s_lo_40)
node _io_out_s_T_389 = bits(io.in, 11, 7)
node _io_out_s_T_390 = bits(io.in, 6, 2)
node _io_out_s_T_391 = bits(io.in, 31, 27)
wire io_out_s_17 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_17.bits, _io_out_s_T_388
connect io_out_s_17.rd, _io_out_s_T_389
connect io_out_s_17.rs1, UInt<5>(0h2)
connect io_out_s_17.rs2, _io_out_s_T_390
connect io_out_s_17.rs3, _io_out_s_T_391
node _io_out_s_T_392 = bits(io.in, 3, 2)
node _io_out_s_T_393 = bits(io.in, 12, 12)
node _io_out_s_T_394 = bits(io.in, 6, 4)
node io_out_s_lo_41 = cat(_io_out_s_T_394, UInt<2>(0h0))
node io_out_s_hi_47 = cat(_io_out_s_T_392, _io_out_s_T_393)
node _io_out_s_T_395 = cat(io_out_s_hi_47, io_out_s_lo_41)
node _io_out_s_T_396 = bits(io.in, 11, 7)
node io_out_s_lo_42 = cat(_io_out_s_T_396, io_out_s_load_opc)
node io_out_s_hi_hi_35 = cat(_io_out_s_T_395, UInt<5>(0h2))
node io_out_s_hi_48 = cat(io_out_s_hi_hi_35, UInt<3>(0h2))
node _io_out_s_T_397 = cat(io_out_s_hi_48, io_out_s_lo_42)
node _io_out_s_T_398 = bits(io.in, 11, 7)
node _io_out_s_T_399 = bits(io.in, 6, 2)
node _io_out_s_T_400 = bits(io.in, 31, 27)
wire io_out_s_18 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_18.bits, _io_out_s_T_397
connect io_out_s_18.rd, _io_out_s_T_398
connect io_out_s_18.rs1, UInt<5>(0h2)
connect io_out_s_18.rs2, _io_out_s_T_399
connect io_out_s_18.rs3, _io_out_s_T_400
node _io_out_s_T_401 = bits(io.in, 4, 2)
node _io_out_s_T_402 = bits(io.in, 12, 12)
node _io_out_s_T_403 = bits(io.in, 6, 5)
node io_out_s_lo_43 = cat(_io_out_s_T_403, UInt<3>(0h0))
node io_out_s_hi_49 = cat(_io_out_s_T_401, _io_out_s_T_402)
node _io_out_s_T_404 = cat(io_out_s_hi_49, io_out_s_lo_43)
node _io_out_s_T_405 = bits(io.in, 11, 7)
node io_out_s_lo_44 = cat(_io_out_s_T_405, io_out_s_load_opc)
node io_out_s_hi_hi_36 = cat(_io_out_s_T_404, UInt<5>(0h2))
node io_out_s_hi_50 = cat(io_out_s_hi_hi_36, UInt<3>(0h3))
node _io_out_s_T_406 = cat(io_out_s_hi_50, io_out_s_lo_44)
node _io_out_s_T_407 = bits(io.in, 11, 7)
node _io_out_s_T_408 = bits(io.in, 6, 2)
node _io_out_s_T_409 = bits(io.in, 31, 27)
wire io_out_s_19 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_19.bits, _io_out_s_T_406
connect io_out_s_19.rd, _io_out_s_T_407
connect io_out_s_19.rs1, UInt<5>(0h2)
connect io_out_s_19.rs2, _io_out_s_T_408
connect io_out_s_19.rs3, _io_out_s_T_409
node _io_out_s_mv_T = bits(io.in, 6, 2)
node _io_out_s_mv_T_1 = bits(io.in, 11, 7)
node io_out_s_mv_lo = cat(_io_out_s_mv_T_1, UInt<7>(0h33))
node io_out_s_mv_hi_hi = cat(_io_out_s_mv_T, UInt<5>(0h0))
node io_out_s_mv_hi = cat(io_out_s_mv_hi_hi, UInt<3>(0h0))
node _io_out_s_mv_T_2 = cat(io_out_s_mv_hi, io_out_s_mv_lo)
node _io_out_s_mv_T_3 = bits(io.in, 11, 7)
node _io_out_s_mv_T_4 = bits(io.in, 6, 2)
node _io_out_s_mv_T_5 = bits(io.in, 31, 27)
wire io_out_s_mv : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_mv.bits, _io_out_s_mv_T_2
connect io_out_s_mv.rd, _io_out_s_mv_T_3
connect io_out_s_mv.rs1, UInt<5>(0h0)
connect io_out_s_mv.rs2, _io_out_s_mv_T_4
connect io_out_s_mv.rs3, _io_out_s_mv_T_5
node _io_out_s_add_T = bits(io.in, 6, 2)
node _io_out_s_add_T_1 = bits(io.in, 11, 7)
node _io_out_s_add_T_2 = bits(io.in, 11, 7)
node io_out_s_add_lo = cat(_io_out_s_add_T_2, UInt<7>(0h33))
node io_out_s_add_hi_hi = cat(_io_out_s_add_T, _io_out_s_add_T_1)
node io_out_s_add_hi = cat(io_out_s_add_hi_hi, UInt<3>(0h0))
node _io_out_s_add_T_3 = cat(io_out_s_add_hi, io_out_s_add_lo)
node _io_out_s_add_T_4 = bits(io.in, 11, 7)
node _io_out_s_add_T_5 = bits(io.in, 11, 7)
node _io_out_s_add_T_6 = bits(io.in, 6, 2)
node _io_out_s_add_T_7 = bits(io.in, 31, 27)
wire io_out_s_add : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_add.bits, _io_out_s_add_T_3
connect io_out_s_add.rd, _io_out_s_add_T_4
connect io_out_s_add.rs1, _io_out_s_add_T_5
connect io_out_s_add.rs2, _io_out_s_add_T_6
connect io_out_s_add.rs3, _io_out_s_add_T_7
node _io_out_s_jr_T = bits(io.in, 6, 2)
node _io_out_s_jr_T_1 = bits(io.in, 11, 7)
node io_out_s_jr_lo = cat(UInt<5>(0h0), UInt<7>(0h67))
node io_out_s_jr_hi_hi = cat(_io_out_s_jr_T, _io_out_s_jr_T_1)
node io_out_s_jr_hi = cat(io_out_s_jr_hi_hi, UInt<3>(0h0))
node io_out_s_jr = cat(io_out_s_jr_hi, io_out_s_jr_lo)
node _io_out_s_reserved_T = shr(io_out_s_jr, 7)
node io_out_s_reserved = cat(_io_out_s_reserved_T, UInt<7>(0h1f))
node _io_out_s_jr_reserved_T = bits(io.in, 11, 7)
node _io_out_s_jr_reserved_T_1 = orr(_io_out_s_jr_reserved_T)
node _io_out_s_jr_reserved_T_2 = mux(_io_out_s_jr_reserved_T_1, io_out_s_jr, io_out_s_reserved)
node _io_out_s_jr_reserved_T_3 = bits(io.in, 11, 7)
node _io_out_s_jr_reserved_T_4 = bits(io.in, 6, 2)
node _io_out_s_jr_reserved_T_5 = bits(io.in, 31, 27)
wire io_out_s_jr_reserved : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_jr_reserved.bits, _io_out_s_jr_reserved_T_2
connect io_out_s_jr_reserved.rd, UInt<5>(0h0)
connect io_out_s_jr_reserved.rs1, _io_out_s_jr_reserved_T_3
connect io_out_s_jr_reserved.rs2, _io_out_s_jr_reserved_T_4
connect io_out_s_jr_reserved.rs3, _io_out_s_jr_reserved_T_5
node _io_out_s_jr_mv_T = bits(io.in, 6, 2)
node _io_out_s_jr_mv_T_1 = orr(_io_out_s_jr_mv_T)
node io_out_s_jr_mv = mux(_io_out_s_jr_mv_T_1, io_out_s_mv, io_out_s_jr_reserved)
node _io_out_s_jalr_T = bits(io.in, 6, 2)
node _io_out_s_jalr_T_1 = bits(io.in, 11, 7)
node io_out_s_jalr_lo = cat(UInt<5>(0h1), UInt<7>(0h67))
node io_out_s_jalr_hi_hi = cat(_io_out_s_jalr_T, _io_out_s_jalr_T_1)
node io_out_s_jalr_hi = cat(io_out_s_jalr_hi_hi, UInt<3>(0h0))
node io_out_s_jalr = cat(io_out_s_jalr_hi, io_out_s_jalr_lo)
node _io_out_s_ebreak_T = shr(io_out_s_jr, 7)
node _io_out_s_ebreak_T_1 = cat(_io_out_s_ebreak_T, UInt<7>(0h73))
node io_out_s_ebreak = or(_io_out_s_ebreak_T_1, UInt<21>(0h100000))
node _io_out_s_jalr_ebreak_T = bits(io.in, 11, 7)
node _io_out_s_jalr_ebreak_T_1 = orr(_io_out_s_jalr_ebreak_T)
node _io_out_s_jalr_ebreak_T_2 = mux(_io_out_s_jalr_ebreak_T_1, io_out_s_jalr, io_out_s_ebreak)
node _io_out_s_jalr_ebreak_T_3 = bits(io.in, 11, 7)
node _io_out_s_jalr_ebreak_T_4 = bits(io.in, 6, 2)
node _io_out_s_jalr_ebreak_T_5 = bits(io.in, 31, 27)
wire io_out_s_jalr_ebreak : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_jalr_ebreak.bits, _io_out_s_jalr_ebreak_T_2
connect io_out_s_jalr_ebreak.rd, UInt<5>(0h1)
connect io_out_s_jalr_ebreak.rs1, _io_out_s_jalr_ebreak_T_3
connect io_out_s_jalr_ebreak.rs2, _io_out_s_jalr_ebreak_T_4
connect io_out_s_jalr_ebreak.rs3, _io_out_s_jalr_ebreak_T_5
node _io_out_s_jalr_add_T = bits(io.in, 6, 2)
node _io_out_s_jalr_add_T_1 = orr(_io_out_s_jalr_add_T)
node io_out_s_jalr_add = mux(_io_out_s_jalr_add_T_1, io_out_s_add, io_out_s_jalr_ebreak)
node _io_out_s_T_410 = bits(io.in, 12, 12)
node io_out_s_20 = mux(_io_out_s_T_410, io_out_s_jalr_add, io_out_s_jr_mv)
node _io_out_s_T_411 = bits(io.in, 9, 7)
node _io_out_s_T_412 = bits(io.in, 12, 10)
node io_out_s_hi_51 = cat(_io_out_s_T_411, _io_out_s_T_412)
node _io_out_s_T_413 = cat(io_out_s_hi_51, UInt<3>(0h0))
node _io_out_s_T_414 = shr(_io_out_s_T_413, 5)
node _io_out_s_T_415 = bits(io.in, 6, 2)
node _io_out_s_T_416 = bits(io.in, 9, 7)
node _io_out_s_T_417 = bits(io.in, 12, 10)
node io_out_s_hi_52 = cat(_io_out_s_T_416, _io_out_s_T_417)
node _io_out_s_T_418 = cat(io_out_s_hi_52, UInt<3>(0h0))
node _io_out_s_T_419 = bits(_io_out_s_T_418, 4, 0)
node io_out_s_lo_hi_20 = cat(UInt<3>(0h3), _io_out_s_T_419)
node io_out_s_lo_45 = cat(io_out_s_lo_hi_20, UInt<7>(0h27))
node io_out_s_hi_hi_37 = cat(_io_out_s_T_414, _io_out_s_T_415)
node io_out_s_hi_53 = cat(io_out_s_hi_hi_37, UInt<5>(0h2))
node _io_out_s_T_420 = cat(io_out_s_hi_53, io_out_s_lo_45)
node _io_out_s_T_421 = bits(io.in, 11, 7)
node _io_out_s_T_422 = bits(io.in, 6, 2)
node _io_out_s_T_423 = bits(io.in, 31, 27)
wire io_out_s_21 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_21.bits, _io_out_s_T_420
connect io_out_s_21.rd, _io_out_s_T_421
connect io_out_s_21.rs1, UInt<5>(0h2)
connect io_out_s_21.rs2, _io_out_s_T_422
connect io_out_s_21.rs3, _io_out_s_T_423
node _io_out_s_T_424 = bits(io.in, 8, 7)
node _io_out_s_T_425 = bits(io.in, 12, 9)
node io_out_s_hi_54 = cat(_io_out_s_T_424, _io_out_s_T_425)
node _io_out_s_T_426 = cat(io_out_s_hi_54, UInt<2>(0h0))
node _io_out_s_T_427 = shr(_io_out_s_T_426, 5)
node _io_out_s_T_428 = bits(io.in, 6, 2)
node _io_out_s_T_429 = bits(io.in, 8, 7)
node _io_out_s_T_430 = bits(io.in, 12, 9)
node io_out_s_hi_55 = cat(_io_out_s_T_429, _io_out_s_T_430)
node _io_out_s_T_431 = cat(io_out_s_hi_55, UInt<2>(0h0))
node _io_out_s_T_432 = bits(_io_out_s_T_431, 4, 0)
node io_out_s_lo_hi_21 = cat(UInt<3>(0h2), _io_out_s_T_432)
node io_out_s_lo_46 = cat(io_out_s_lo_hi_21, UInt<7>(0h23))
node io_out_s_hi_hi_38 = cat(_io_out_s_T_427, _io_out_s_T_428)
node io_out_s_hi_56 = cat(io_out_s_hi_hi_38, UInt<5>(0h2))
node _io_out_s_T_433 = cat(io_out_s_hi_56, io_out_s_lo_46)
node _io_out_s_T_434 = bits(io.in, 11, 7)
node _io_out_s_T_435 = bits(io.in, 6, 2)
node _io_out_s_T_436 = bits(io.in, 31, 27)
wire io_out_s_22 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_22.bits, _io_out_s_T_433
connect io_out_s_22.rd, _io_out_s_T_434
connect io_out_s_22.rs1, UInt<5>(0h2)
connect io_out_s_22.rs2, _io_out_s_T_435
connect io_out_s_22.rs3, _io_out_s_T_436
node _io_out_s_T_437 = bits(io.in, 9, 7)
node _io_out_s_T_438 = bits(io.in, 12, 10)
node io_out_s_hi_57 = cat(_io_out_s_T_437, _io_out_s_T_438)
node _io_out_s_T_439 = cat(io_out_s_hi_57, UInt<3>(0h0))
node _io_out_s_T_440 = shr(_io_out_s_T_439, 5)
node _io_out_s_T_441 = bits(io.in, 6, 2)
node _io_out_s_T_442 = bits(io.in, 9, 7)
node _io_out_s_T_443 = bits(io.in, 12, 10)
node io_out_s_hi_58 = cat(_io_out_s_T_442, _io_out_s_T_443)
node _io_out_s_T_444 = cat(io_out_s_hi_58, UInt<3>(0h0))
node _io_out_s_T_445 = bits(_io_out_s_T_444, 4, 0)
node io_out_s_lo_hi_22 = cat(UInt<3>(0h3), _io_out_s_T_445)
node io_out_s_lo_47 = cat(io_out_s_lo_hi_22, UInt<7>(0h23))
node io_out_s_hi_hi_39 = cat(_io_out_s_T_440, _io_out_s_T_441)
node io_out_s_hi_59 = cat(io_out_s_hi_hi_39, UInt<5>(0h2))
node _io_out_s_T_446 = cat(io_out_s_hi_59, io_out_s_lo_47)
node _io_out_s_T_447 = bits(io.in, 11, 7)
node _io_out_s_T_448 = bits(io.in, 6, 2)
node _io_out_s_T_449 = bits(io.in, 31, 27)
wire io_out_s_23 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_23.bits, _io_out_s_T_446
connect io_out_s_23.rd, _io_out_s_T_447
connect io_out_s_23.rs1, UInt<5>(0h2)
connect io_out_s_23.rs2, _io_out_s_T_448
connect io_out_s_23.rs3, _io_out_s_T_449
node _io_out_s_T_450 = bits(io.in, 11, 7)
node _io_out_s_T_451 = bits(io.in, 19, 15)
node _io_out_s_T_452 = bits(io.in, 24, 20)
node _io_out_s_T_453 = bits(io.in, 31, 27)
wire io_out_s_24 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_24.bits, io.in
connect io_out_s_24.rd, _io_out_s_T_450
connect io_out_s_24.rs1, _io_out_s_T_451
connect io_out_s_24.rs2, _io_out_s_T_452
connect io_out_s_24.rs3, _io_out_s_T_453
node _io_out_s_T_454 = bits(io.in, 11, 7)
node _io_out_s_T_455 = bits(io.in, 19, 15)
node _io_out_s_T_456 = bits(io.in, 24, 20)
node _io_out_s_T_457 = bits(io.in, 31, 27)
wire io_out_s_25 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_25.bits, io.in
connect io_out_s_25.rd, _io_out_s_T_454
connect io_out_s_25.rs1, _io_out_s_T_455
connect io_out_s_25.rs2, _io_out_s_T_456
connect io_out_s_25.rs3, _io_out_s_T_457
node _io_out_s_T_458 = bits(io.in, 11, 7)
node _io_out_s_T_459 = bits(io.in, 19, 15)
node _io_out_s_T_460 = bits(io.in, 24, 20)
node _io_out_s_T_461 = bits(io.in, 31, 27)
wire io_out_s_26 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_26.bits, io.in
connect io_out_s_26.rd, _io_out_s_T_458
connect io_out_s_26.rs1, _io_out_s_T_459
connect io_out_s_26.rs2, _io_out_s_T_460
connect io_out_s_26.rs3, _io_out_s_T_461
node _io_out_s_T_462 = bits(io.in, 11, 7)
node _io_out_s_T_463 = bits(io.in, 19, 15)
node _io_out_s_T_464 = bits(io.in, 24, 20)
node _io_out_s_T_465 = bits(io.in, 31, 27)
wire io_out_s_27 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_27.bits, io.in
connect io_out_s_27.rd, _io_out_s_T_462
connect io_out_s_27.rs1, _io_out_s_T_463
connect io_out_s_27.rs2, _io_out_s_T_464
connect io_out_s_27.rs3, _io_out_s_T_465
node _io_out_s_T_466 = bits(io.in, 11, 7)
node _io_out_s_T_467 = bits(io.in, 19, 15)
node _io_out_s_T_468 = bits(io.in, 24, 20)
node _io_out_s_T_469 = bits(io.in, 31, 27)
wire io_out_s_28 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_28.bits, io.in
connect io_out_s_28.rd, _io_out_s_T_466
connect io_out_s_28.rs1, _io_out_s_T_467
connect io_out_s_28.rs2, _io_out_s_T_468
connect io_out_s_28.rs3, _io_out_s_T_469
node _io_out_s_T_470 = bits(io.in, 11, 7)
node _io_out_s_T_471 = bits(io.in, 19, 15)
node _io_out_s_T_472 = bits(io.in, 24, 20)
node _io_out_s_T_473 = bits(io.in, 31, 27)
wire io_out_s_29 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_29.bits, io.in
connect io_out_s_29.rd, _io_out_s_T_470
connect io_out_s_29.rs1, _io_out_s_T_471
connect io_out_s_29.rs2, _io_out_s_T_472
connect io_out_s_29.rs3, _io_out_s_T_473
node _io_out_s_T_474 = bits(io.in, 11, 7)
node _io_out_s_T_475 = bits(io.in, 19, 15)
node _io_out_s_T_476 = bits(io.in, 24, 20)
node _io_out_s_T_477 = bits(io.in, 31, 27)
wire io_out_s_30 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_30.bits, io.in
connect io_out_s_30.rd, _io_out_s_T_474
connect io_out_s_30.rs1, _io_out_s_T_475
connect io_out_s_30.rs2, _io_out_s_T_476
connect io_out_s_30.rs3, _io_out_s_T_477
node _io_out_s_T_478 = bits(io.in, 11, 7)
node _io_out_s_T_479 = bits(io.in, 19, 15)
node _io_out_s_T_480 = bits(io.in, 24, 20)
node _io_out_s_T_481 = bits(io.in, 31, 27)
wire io_out_s_31 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_31.bits, io.in
connect io_out_s_31.rd, _io_out_s_T_478
connect io_out_s_31.rs1, _io_out_s_T_479
connect io_out_s_31.rs2, _io_out_s_T_480
connect io_out_s_31.rs3, _io_out_s_T_481
node _io_out_T = bits(io.in, 1, 0)
node _io_out_T_1 = bits(io.in, 15, 13)
node _io_out_T_2 = cat(_io_out_T, _io_out_T_1)
node _io_out_T_3 = eq(_io_out_T_2, UInt<1>(0h1))
node _io_out_T_4 = mux(_io_out_T_3, io_out_s_1, io_out_s_0)
node _io_out_T_5 = eq(_io_out_T_2, UInt<2>(0h2))
node _io_out_T_6 = mux(_io_out_T_5, io_out_s_2, _io_out_T_4)
node _io_out_T_7 = eq(_io_out_T_2, UInt<2>(0h3))
node _io_out_T_8 = mux(_io_out_T_7, io_out_s_3, _io_out_T_6)
node _io_out_T_9 = eq(_io_out_T_2, UInt<3>(0h4))
node _io_out_T_10 = mux(_io_out_T_9, io_out_s_4, _io_out_T_8)
node _io_out_T_11 = eq(_io_out_T_2, UInt<3>(0h5))
node _io_out_T_12 = mux(_io_out_T_11, io_out_s_5, _io_out_T_10)
node _io_out_T_13 = eq(_io_out_T_2, UInt<3>(0h6))
node _io_out_T_14 = mux(_io_out_T_13, io_out_s_6, _io_out_T_12)
node _io_out_T_15 = eq(_io_out_T_2, UInt<3>(0h7))
node _io_out_T_16 = mux(_io_out_T_15, io_out_s_7, _io_out_T_14)
node _io_out_T_17 = eq(_io_out_T_2, UInt<4>(0h8))
node _io_out_T_18 = mux(_io_out_T_17, io_out_s_8, _io_out_T_16)
node _io_out_T_19 = eq(_io_out_T_2, UInt<4>(0h9))
node _io_out_T_20 = mux(_io_out_T_19, io_out_s_9, _io_out_T_18)
node _io_out_T_21 = eq(_io_out_T_2, UInt<4>(0ha))
node _io_out_T_22 = mux(_io_out_T_21, io_out_s_10, _io_out_T_20)
node _io_out_T_23 = eq(_io_out_T_2, UInt<4>(0hb))
node _io_out_T_24 = mux(_io_out_T_23, io_out_s_11, _io_out_T_22)
node _io_out_T_25 = eq(_io_out_T_2, UInt<4>(0hc))
node _io_out_T_26 = mux(_io_out_T_25, io_out_s_12, _io_out_T_24)
node _io_out_T_27 = eq(_io_out_T_2, UInt<4>(0hd))
node _io_out_T_28 = mux(_io_out_T_27, io_out_s_13, _io_out_T_26)
node _io_out_T_29 = eq(_io_out_T_2, UInt<4>(0he))
node _io_out_T_30 = mux(_io_out_T_29, io_out_s_14, _io_out_T_28)
node _io_out_T_31 = eq(_io_out_T_2, UInt<4>(0hf))
node _io_out_T_32 = mux(_io_out_T_31, io_out_s_15, _io_out_T_30)
node _io_out_T_33 = eq(_io_out_T_2, UInt<5>(0h10))
node _io_out_T_34 = mux(_io_out_T_33, io_out_s_16, _io_out_T_32)
node _io_out_T_35 = eq(_io_out_T_2, UInt<5>(0h11))
node _io_out_T_36 = mux(_io_out_T_35, io_out_s_17, _io_out_T_34)
node _io_out_T_37 = eq(_io_out_T_2, UInt<5>(0h12))
node _io_out_T_38 = mux(_io_out_T_37, io_out_s_18, _io_out_T_36)
node _io_out_T_39 = eq(_io_out_T_2, UInt<5>(0h13))
node _io_out_T_40 = mux(_io_out_T_39, io_out_s_19, _io_out_T_38)
node _io_out_T_41 = eq(_io_out_T_2, UInt<5>(0h14))
node _io_out_T_42 = mux(_io_out_T_41, io_out_s_20, _io_out_T_40)
node _io_out_T_43 = eq(_io_out_T_2, UInt<5>(0h15))
node _io_out_T_44 = mux(_io_out_T_43, io_out_s_21, _io_out_T_42)
node _io_out_T_45 = eq(_io_out_T_2, UInt<5>(0h16))
node _io_out_T_46 = mux(_io_out_T_45, io_out_s_22, _io_out_T_44)
node _io_out_T_47 = eq(_io_out_T_2, UInt<5>(0h17))
node _io_out_T_48 = mux(_io_out_T_47, io_out_s_23, _io_out_T_46)
node _io_out_T_49 = eq(_io_out_T_2, UInt<5>(0h18))
node _io_out_T_50 = mux(_io_out_T_49, io_out_s_24, _io_out_T_48)
node _io_out_T_51 = eq(_io_out_T_2, UInt<5>(0h19))
node _io_out_T_52 = mux(_io_out_T_51, io_out_s_25, _io_out_T_50)
node _io_out_T_53 = eq(_io_out_T_2, UInt<5>(0h1a))
node _io_out_T_54 = mux(_io_out_T_53, io_out_s_26, _io_out_T_52)
node _io_out_T_55 = eq(_io_out_T_2, UInt<5>(0h1b))
node _io_out_T_56 = mux(_io_out_T_55, io_out_s_27, _io_out_T_54)
node _io_out_T_57 = eq(_io_out_T_2, UInt<5>(0h1c))
node _io_out_T_58 = mux(_io_out_T_57, io_out_s_28, _io_out_T_56)
node _io_out_T_59 = eq(_io_out_T_2, UInt<5>(0h1d))
node _io_out_T_60 = mux(_io_out_T_59, io_out_s_29, _io_out_T_58)
node _io_out_T_61 = eq(_io_out_T_2, UInt<5>(0h1e))
node _io_out_T_62 = mux(_io_out_T_61, io_out_s_30, _io_out_T_60)
node _io_out_T_63 = eq(_io_out_T_2, UInt<5>(0h1f))
node _io_out_T_64 = mux(_io_out_T_63, io_out_s_31, _io_out_T_62)
connect io.out, _io_out_T_64
node _io_ill_s_T = bits(io.in, 12, 2)
node _io_ill_s_T_1 = orr(_io_ill_s_T)
node io_ill_s_0 = eq(_io_ill_s_T_1, UInt<1>(0h0))
node _io_ill_s_T_2 = bits(io.in, 11, 7)
node io_ill_s_9 = eq(_io_ill_s_T_2, UInt<1>(0h0))
node _io_ill_s_T_3 = bits(io.in, 12, 12)
node _io_ill_s_T_4 = bits(io.in, 6, 2)
node _io_ill_s_T_5 = orr(_io_ill_s_T_4)
node _io_ill_s_T_6 = or(_io_ill_s_T_3, _io_ill_s_T_5)
node io_ill_s_11 = eq(_io_ill_s_T_6, UInt<1>(0h0))
node _io_ill_s_T_7 = bits(io.in, 12, 10)
node _io_ill_s_T_8 = andr(_io_ill_s_T_7)
node _io_ill_s_T_9 = bits(io.in, 6, 6)
node _io_ill_s_T_10 = eq(_io_ill_s_T_9, UInt<1>(0h1))
node io_ill_s_12 = and(_io_ill_s_T_8, _io_ill_s_T_10)
node _io_ill_s_T_11 = bits(io.in, 11, 7)
node io_ill_s_18 = eq(_io_ill_s_T_11, UInt<1>(0h0))
node _io_ill_s_T_12 = bits(io.in, 11, 7)
node io_ill_s_19 = eq(_io_ill_s_T_12, UInt<1>(0h0))
node _io_ill_s_T_13 = bits(io.in, 12, 2)
node _io_ill_s_T_14 = orr(_io_ill_s_T_13)
node io_ill_s_20 = eq(_io_ill_s_T_14, UInt<1>(0h0))
node _io_ill_T = bits(io.in, 1, 0)
node _io_ill_T_1 = bits(io.in, 15, 13)
node _io_ill_T_2 = cat(_io_ill_T, _io_ill_T_1)
node _io_ill_T_3 = eq(_io_ill_T_2, UInt<1>(0h1))
node _io_ill_T_4 = mux(_io_ill_T_3, UInt<1>(0h0), io_ill_s_0)
node _io_ill_T_5 = eq(_io_ill_T_2, UInt<2>(0h2))
node _io_ill_T_6 = mux(_io_ill_T_5, UInt<1>(0h0), _io_ill_T_4)
node _io_ill_T_7 = eq(_io_ill_T_2, UInt<2>(0h3))
node _io_ill_T_8 = mux(_io_ill_T_7, UInt<1>(0h0), _io_ill_T_6)
node _io_ill_T_9 = eq(_io_ill_T_2, UInt<3>(0h4))
node _io_ill_T_10 = mux(_io_ill_T_9, UInt<1>(0h1), _io_ill_T_8)
node _io_ill_T_11 = eq(_io_ill_T_2, UInt<3>(0h5))
node _io_ill_T_12 = mux(_io_ill_T_11, UInt<1>(0h0), _io_ill_T_10)
node _io_ill_T_13 = eq(_io_ill_T_2, UInt<3>(0h6))
node _io_ill_T_14 = mux(_io_ill_T_13, UInt<1>(0h0), _io_ill_T_12)
node _io_ill_T_15 = eq(_io_ill_T_2, UInt<3>(0h7))
node _io_ill_T_16 = mux(_io_ill_T_15, UInt<1>(0h0), _io_ill_T_14)
node _io_ill_T_17 = eq(_io_ill_T_2, UInt<4>(0h8))
node _io_ill_T_18 = mux(_io_ill_T_17, UInt<1>(0h0), _io_ill_T_16)
node _io_ill_T_19 = eq(_io_ill_T_2, UInt<4>(0h9))
node _io_ill_T_20 = mux(_io_ill_T_19, io_ill_s_9, _io_ill_T_18)
node _io_ill_T_21 = eq(_io_ill_T_2, UInt<4>(0ha))
node _io_ill_T_22 = mux(_io_ill_T_21, UInt<1>(0h0), _io_ill_T_20)
node _io_ill_T_23 = eq(_io_ill_T_2, UInt<4>(0hb))
node _io_ill_T_24 = mux(_io_ill_T_23, io_ill_s_11, _io_ill_T_22)
node _io_ill_T_25 = eq(_io_ill_T_2, UInt<4>(0hc))
node _io_ill_T_26 = mux(_io_ill_T_25, io_ill_s_12, _io_ill_T_24)
node _io_ill_T_27 = eq(_io_ill_T_2, UInt<4>(0hd))
node _io_ill_T_28 = mux(_io_ill_T_27, UInt<1>(0h0), _io_ill_T_26)
node _io_ill_T_29 = eq(_io_ill_T_2, UInt<4>(0he))
node _io_ill_T_30 = mux(_io_ill_T_29, UInt<1>(0h0), _io_ill_T_28)
node _io_ill_T_31 = eq(_io_ill_T_2, UInt<4>(0hf))
node _io_ill_T_32 = mux(_io_ill_T_31, UInt<1>(0h0), _io_ill_T_30)
node _io_ill_T_33 = eq(_io_ill_T_2, UInt<5>(0h10))
node _io_ill_T_34 = mux(_io_ill_T_33, UInt<1>(0h0), _io_ill_T_32)
node _io_ill_T_35 = eq(_io_ill_T_2, UInt<5>(0h11))
node _io_ill_T_36 = mux(_io_ill_T_35, UInt<1>(0h0), _io_ill_T_34)
node _io_ill_T_37 = eq(_io_ill_T_2, UInt<5>(0h12))
node _io_ill_T_38 = mux(_io_ill_T_37, io_ill_s_18, _io_ill_T_36)
node _io_ill_T_39 = eq(_io_ill_T_2, UInt<5>(0h13))
node _io_ill_T_40 = mux(_io_ill_T_39, io_ill_s_19, _io_ill_T_38)
node _io_ill_T_41 = eq(_io_ill_T_2, UInt<5>(0h14))
node _io_ill_T_42 = mux(_io_ill_T_41, io_ill_s_20, _io_ill_T_40)
node _io_ill_T_43 = eq(_io_ill_T_2, UInt<5>(0h15))
node _io_ill_T_44 = mux(_io_ill_T_43, UInt<1>(0h0), _io_ill_T_42)
node _io_ill_T_45 = eq(_io_ill_T_2, UInt<5>(0h16))
node _io_ill_T_46 = mux(_io_ill_T_45, UInt<1>(0h0), _io_ill_T_44)
node _io_ill_T_47 = eq(_io_ill_T_2, UInt<5>(0h17))
node _io_ill_T_48 = mux(_io_ill_T_47, UInt<1>(0h0), _io_ill_T_46)
node _io_ill_T_49 = eq(_io_ill_T_2, UInt<5>(0h18))
node _io_ill_T_50 = mux(_io_ill_T_49, UInt<1>(0h0), _io_ill_T_48)
node _io_ill_T_51 = eq(_io_ill_T_2, UInt<5>(0h19))
node _io_ill_T_52 = mux(_io_ill_T_51, UInt<1>(0h0), _io_ill_T_50)
node _io_ill_T_53 = eq(_io_ill_T_2, UInt<5>(0h1a))
node _io_ill_T_54 = mux(_io_ill_T_53, UInt<1>(0h0), _io_ill_T_52)
node _io_ill_T_55 = eq(_io_ill_T_2, UInt<5>(0h1b))
node _io_ill_T_56 = mux(_io_ill_T_55, UInt<1>(0h0), _io_ill_T_54)
node _io_ill_T_57 = eq(_io_ill_T_2, UInt<5>(0h1c))
node _io_ill_T_58 = mux(_io_ill_T_57, UInt<1>(0h0), _io_ill_T_56)
node _io_ill_T_59 = eq(_io_ill_T_2, UInt<5>(0h1d))
node _io_ill_T_60 = mux(_io_ill_T_59, UInt<1>(0h0), _io_ill_T_58)
node _io_ill_T_61 = eq(_io_ill_T_2, UInt<5>(0h1e))
node _io_ill_T_62 = mux(_io_ill_T_61, UInt<1>(0h0), _io_ill_T_60)
node _io_ill_T_63 = eq(_io_ill_T_2, UInt<5>(0h1f))
node _io_ill_T_64 = mux(_io_ill_T_63, UInt<1>(0h0), _io_ill_T_62)
connect io.ill, _io_ill_T_64 | module RVCExpander( // @[RVC.scala:190:7]
input [31:0] io_in, // @[RVC.scala:191:14]
output [31:0] io_out_bits, // @[RVC.scala:191:14]
output [4:0] io_out_rd, // @[RVC.scala:191:14]
output [4:0] io_out_rs1, // @[RVC.scala:191:14]
output [4:0] io_out_rs2, // @[RVC.scala:191:14]
output [4:0] io_out_rs3, // @[RVC.scala:191:14]
output io_rvc // @[RVC.scala:191:14]
);
wire [4:0] io_out_s_7_rd = {2'h1, io_in[4:2]}; // @[package.scala:39:86]
wire [2:0] _io_out_s_funct_T_2 = {io_in[12], io_in[6:5]}; // @[RVC.scala:36:20, :43:30, :102:68]
wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_2 == 3'h1, 2'h0}; // @[package.scala:39:{76,86}]
wire [7:0][2:0] _GEN = {{3'h3}, {3'h2}, {3'h0}, {3'h0}, {3'h7}, {3'h6}, {_io_out_s_funct_T_4}, {_io_out_s_funct_T_4}}; // @[package.scala:39:{76,86}]
wire [3:0] _GEN_0 = {4{io_in[12]}}; // @[RVC.scala:43:30, :95:24]
wire [6:0] io_out_s_load_opc = (|(io_in[11:7])) ? 7'h3 : 7'h1F; // @[RVC.scala:33:13, :113:{23,27}]
wire [4:0] _io_out_T_2 = {io_in[1:0], io_in[15:13]}; // @[RVC.scala:154:{10,20}, :199:20]
wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86]
wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86]
wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86]
wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86]
wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86]
wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86]
wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86]
wire [31:0] _io_out_T_42_bits =
_io_out_T_41
? {7'h0, io_in[12] ? ((|(io_in[6:2])) ? {io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 7'h33} : (|(io_in[11:7])) ? {io_in[6:2], io_in[11:7], 15'hE7} : {io_in[6:3], 1'h1, io_in[11:7], 15'h73}) : {io_in[6:2], (|(io_in[6:2])) ? {8'h0, io_in[11:7], 7'h33} : {io_in[11:7], (|(io_in[11:7])) ? 15'h67 : 15'h1F}}}
: _io_out_T_39
? {3'h0, io_in[4:2], io_in[12], io_in[6:5], 11'h13, io_in[11:7], io_out_s_load_opc}
: _io_out_T_37
? {4'h0, io_in[3:2], io_in[12], io_in[6:4], 10'h12, io_in[11:7], io_out_s_load_opc}
: _io_out_T_35
? {3'h0, io_in[4:2], io_in[12], io_in[6:5], 11'h13, io_in[11:7], 7'h7}
: _io_out_T_33
? {6'h0, io_in[12], io_in[6:2], io_in[11:7], 3'h1, io_in[11:7], 7'h13}
: _io_out_T_31
? {_GEN_0, io_in[6:5], io_in[2], 7'h1, io_in[9:7], 3'h1, io_in[11:10], io_in[4:3], io_in[12], 7'h63}
: _io_out_T_29
? {_GEN_0, io_in[6:5], io_in[2], 7'h1, io_in[9:7], 3'h0, io_in[11:10], io_in[4:3], io_in[12], 7'h63}
: _io_out_T_2 == 5'hD ? {io_in[12], io_in[8], io_in[10:9], io_in[6], io_in[7], io_in[2], io_in[11], io_in[5:3], {9{io_in[12]}}, 12'h6F} : _io_out_T_2 == 5'hC ? ((&(io_in[11:10])) ? {1'h0, io_in[6:5] == 2'h0, 7'h1, io_in[4:2], 2'h1, io_in[9:7], _GEN[_io_out_s_funct_T_2], 2'h1, io_in[9:7], 3'h3, io_in[12], 3'h3} : {io_in[11:10] == 2'h2 ? {{7{io_in[12]}}, io_in[6:2], 2'h1, io_in[9:7], 5'h1D} : {1'h0, io_in[11:10] == 2'h1, 4'h0, io_in[12], io_in[6:2], 2'h1, io_in[9:7], 5'h15}, io_in[9:7], 7'h13}) : _io_out_T_2 == 5'hB ? {{3{io_in[12]}}, io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? {io_in[4:3], io_in[5], io_in[2], io_in[6], 4'h0, io_in[11:7], 3'h0, io_in[11:7], (|{{7{io_in[12]}}, io_in[6:2]}) ? 7'h13 : 7'h1F} : {{12{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h3, {{7{io_in[12]}}, io_in[6:2]} == 12'h0, 3'h7}} : _io_out_T_2 == 5'hA ? {{7{io_in[12]}}, io_in[6:2], 8'h0, io_in[11:7], 7'h13} : _io_out_T_2 == 5'h9 ? {{7{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 4'h3, io_in[11:7] == 5'h0, 2'h3} : _io_out_T_2 == 5'h8 ? {{7{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 7'h13} : _io_out_T_2 == 5'h7 ? {4'h0, io_in[6:5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h3, io_in[11:10], 10'h23} : _io_out_T_2 == 5'h6 ? {5'h0, io_in[5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h2, io_in[11:10], io_in[6], 9'h23} : _io_out_T_2 == 5'h5 ? {4'h0, io_in[6:5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h3, io_in[11:10], 10'h27} : _io_out_T_2 == 5'h4 ? {5'h0, io_in[5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h2, io_in[11:10], io_in[6], 9'h3F} : _io_out_T_2 == 5'h3 ? {4'h0, io_in[6:5], io_in[12:10], 5'h1, io_in[9:7], 5'hD, io_in[4:2], 7'h3} : _io_out_T_2 == 5'h2 ? {5'h0, io_in[5], io_in[12:10], io_in[6], 4'h1, io_in[9:7], 5'h9, io_in[4:2], 7'h3} : _io_out_T_2 == 5'h1 ? {4'h0, io_in[6:5], io_in[12:10], 5'h1, io_in[9:7], 5'hD, io_in[4:2], 7'h7} : {2'h0, io_in[10:7], io_in[12:11], io_in[5], io_in[6], 12'h41, io_in[4:2], (|(io_in[12:5])) ? 7'h13 : 7'h1F}; // @[package.scala:39:{76,86}]
wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86]
wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86]
wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86]
wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86]
wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86]
wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86]
wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86]
wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86]
wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86]
wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86]
wire [31:0][4:0] _GEN_1 = {{io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[12] ? ((|(io_in[6:2])) ? io_in[11:7] : 5'h1) : (|(io_in[6:2])) ? io_in[11:7] : 5'h0}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {5'h0}, {{2'h1, io_in[9:7]}}, {5'h0}, {{2'h1, io_in[9:7]}}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_in[11:7]}, {io_out_s_7_rd}, {io_out_s_7_rd}, {io_out_s_7_rd}, {io_out_s_7_rd}, {io_out_s_7_rd}, {io_out_s_7_rd}, {io_out_s_7_rd}, {io_out_s_7_rd}}; // @[package.scala:39:{76,86}]
wire [31:0][4:0] _GEN_2 = {{io_in[19:15]}, {io_in[19:15]}, {io_in[19:15]}, {io_in[19:15]}, {io_in[19:15]}, {io_in[19:15]}, {io_in[19:15]}, {io_in[19:15]}, {5'h2}, {5'h2}, {5'h2}, {io_in[12] | ~(|(io_in[6:2])) ? io_in[11:7] : 5'h0}, {5'h2}, {5'h2}, {5'h2}, {io_in[11:7]}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {io_in[11:7]}, {5'h0}, {io_in[11:7]}, {io_in[11:7]}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {{2'h1, io_in[9:7]}}, {5'h2}}; // @[package.scala:39:{76,86}]
assign io_out_bits = (&_io_out_T_2) | _io_out_T_61 | _io_out_T_59 | _io_out_T_57 | _io_out_T_55 | _io_out_T_53 | _io_out_T_51 | _io_out_T_49 ? io_in : _io_out_T_47 ? {3'h0, io_in[9:7], io_in[12], io_in[6:2], 8'h13, io_in[11:10], 10'h23} : _io_out_T_45 ? {4'h0, io_in[8:7], io_in[12], io_in[6:2], 8'h12, io_in[11:9], 9'h23} : _io_out_T_43 ? {3'h0, io_in[9:7], io_in[12], io_in[6:2], 8'h13, io_in[11:10], 10'h27} : _io_out_T_42_bits; // @[package.scala:39:{76,86}]
assign io_out_rd = _GEN_1[_io_out_T_2]; // @[package.scala:39:{76,86}]
assign io_out_rs1 = _GEN_2[_io_out_T_2]; // @[package.scala:39:{76,86}]
assign io_out_rs2 = (&_io_out_T_2) | _io_out_T_61 | _io_out_T_59 | _io_out_T_57 | _io_out_T_55 | _io_out_T_53 | _io_out_T_51 | _io_out_T_49 ? io_in[24:20] : _io_out_T_47 | _io_out_T_45 | _io_out_T_43 | _io_out_T_41 | _io_out_T_39 | _io_out_T_37 | _io_out_T_35 | _io_out_T_33 ? io_in[6:2] : _io_out_T_31 | _io_out_T_29 ? 5'h0 : {2'h1, io_in[4:2]}; // @[package.scala:39:{76,86}]
assign io_out_rs3 = io_in[31:27]; // @[RVC.scala:20:101, :190:7]
assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala:190:7, :199:{20,26}]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0hf))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0hf))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0hf))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_69 = cvt(_T_68)
node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000)))
node _T_71 = asSInt(_T_70)
node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0)))
node _T_73 = or(_T_37, _T_42)
node _T_74 = or(_T_73, _T_47)
node _T_75 = or(_T_74, _T_52)
node _T_76 = or(_T_75, _T_57)
node _T_77 = or(_T_76, _T_62)
node _T_78 = or(_T_77, _T_67)
node _T_79 = or(_T_78, _T_72)
node _T_80 = and(_T_32, _T_79)
node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_82 = or(UInt<1>(0h0), _T_81)
node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_84 = cvt(_T_83)
node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000)))
node _T_86 = asSInt(_T_85)
node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0)))
node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_89 = cvt(_T_88)
node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000)))
node _T_91 = asSInt(_T_90)
node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = or(_T_87, _T_92)
node _T_94 = and(_T_82, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_80)
node _T_96 = or(_T_95, _T_94)
node _T_97 = and(_T_31, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_97, UInt<1>(0h1), "") : assert_2
node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_103 = and(_T_101, _T_102)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_151 = cvt(_T_150)
node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000)))
node _T_153 = asSInt(_T_152)
node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0)))
node _T_155 = or(_T_109, _T_114)
node _T_156 = or(_T_155, _T_119)
node _T_157 = or(_T_156, _T_124)
node _T_158 = or(_T_157, _T_129)
node _T_159 = or(_T_158, _T_134)
node _T_160 = or(_T_159, _T_139)
node _T_161 = or(_T_160, _T_144)
node _T_162 = or(_T_161, _T_149)
node _T_163 = or(_T_162, _T_154)
node _T_164 = and(_T_104, _T_163)
node _T_165 = or(UInt<1>(0h0), _T_164)
node _T_166 = and(UInt<1>(0h0), _T_165)
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(_T_166, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_166, UInt<1>(0h1), "") : assert_3
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_173, UInt<1>(0h1), "") : assert_5
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(is_aligned, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_180, UInt<1>(0h1), "") : assert_7
node _T_184 = not(io.in.a.bits.mask)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_185, UInt<1>(0h1), "") : assert_8
node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_189, UInt<1>(0h1), "") : assert_9
node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_193 :
node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_197 = shr(io.in.a.bits.source, 4)
node _T_198 = eq(_T_197, UInt<1>(0h0))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_2, UInt<4>(0hf))
node _T_202 = and(_T_200, _T_201)
node _T_203 = and(_T_196, _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = or(_T_210, _T_215)
node _T_247 = or(_T_246, _T_220)
node _T_248 = or(_T_247, _T_225)
node _T_249 = or(_T_248, _T_230)
node _T_250 = or(_T_249, _T_235)
node _T_251 = or(_T_250, _T_240)
node _T_252 = or(_T_251, _T_245)
node _T_253 = and(_T_205, _T_252)
node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_255 = or(UInt<1>(0h0), _T_254)
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_260, _T_265)
node _T_267 = and(_T_255, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_253)
node _T_269 = or(_T_268, _T_267)
node _T_270 = and(_T_204, _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_270, UInt<1>(0h1), "") : assert_10
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = or(_T_282, _T_287)
node _T_329 = or(_T_328, _T_292)
node _T_330 = or(_T_329, _T_297)
node _T_331 = or(_T_330, _T_302)
node _T_332 = or(_T_331, _T_307)
node _T_333 = or(_T_332, _T_312)
node _T_334 = or(_T_333, _T_317)
node _T_335 = or(_T_334, _T_322)
node _T_336 = or(_T_335, _T_327)
node _T_337 = and(_T_277, _T_336)
node _T_338 = or(UInt<1>(0h0), _T_337)
node _T_339 = and(UInt<1>(0h0), _T_338)
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_339, UInt<1>(0h1), "") : assert_11
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_346, UInt<1>(0h1), "") : assert_13
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(is_aligned, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(_T_353, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_353, UInt<1>(0h1), "") : assert_15
node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_357, UInt<1>(0h1), "") : assert_16
node _T_361 = not(io.in.a.bits.mask)
node _T_362 = eq(_T_361, UInt<1>(0h0))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_362, UInt<1>(0h1), "") : assert_17
node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_366, UInt<1>(0h1), "") : assert_18
node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_370 :
node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_373 = and(_T_371, _T_372)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_374 = shr(io.in.a.bits.source, 4)
node _T_375 = eq(_T_374, UInt<1>(0h0))
node _T_376 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_377 = and(_T_375, _T_376)
node _T_378 = leq(uncommonBits_3, UInt<4>(0hf))
node _T_379 = and(_T_377, _T_378)
node _T_380 = and(_T_373, _T_379)
node _T_381 = or(UInt<1>(0h0), _T_380)
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_381, UInt<1>(0h1), "") : assert_19
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = and(_T_388, _T_393)
node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_397 = and(_T_395, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = or(_T_403, _T_408)
node _T_445 = or(_T_444, _T_413)
node _T_446 = or(_T_445, _T_418)
node _T_447 = or(_T_446, _T_423)
node _T_448 = or(_T_447, _T_428)
node _T_449 = or(_T_448, _T_433)
node _T_450 = or(_T_449, _T_438)
node _T_451 = or(_T_450, _T_443)
node _T_452 = and(_T_398, _T_451)
node _T_453 = or(UInt<1>(0h0), _T_394)
node _T_454 = or(_T_453, _T_452)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_454, UInt<1>(0h1), "") : assert_20
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(is_aligned, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_464, UInt<1>(0h1), "") : assert_23
node _T_468 = eq(io.in.a.bits.mask, mask)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_468, UInt<1>(0h1), "") : assert_24
node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_472, UInt<1>(0h1), "") : assert_25
node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_476 :
node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_480 = shr(io.in.a.bits.source, 4)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_485 = and(_T_483, _T_484)
node _T_486 = and(_T_479, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_490 = and(_T_488, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = and(_T_491, _T_496)
node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_500 = and(_T_498, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_523 = cvt(_T_522)
node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000)))
node _T_525 = asSInt(_T_524)
node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0)))
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = or(_T_506, _T_511)
node _T_543 = or(_T_542, _T_516)
node _T_544 = or(_T_543, _T_521)
node _T_545 = or(_T_544, _T_526)
node _T_546 = or(_T_545, _T_531)
node _T_547 = or(_T_546, _T_536)
node _T_548 = or(_T_547, _T_541)
node _T_549 = and(_T_501, _T_548)
node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_497)
node _T_558 = or(_T_557, _T_549)
node _T_559 = or(_T_558, _T_556)
node _T_560 = and(_T_487, _T_559)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_560, UInt<1>(0h1), "") : assert_26
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(is_aligned, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_570, UInt<1>(0h1), "") : assert_29
node _T_574 = eq(io.in.a.bits.mask, mask)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_574, UInt<1>(0h1), "") : assert_30
node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_578 :
node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_582 = shr(io.in.a.bits.source, 4)
node _T_583 = eq(_T_582, UInt<1>(0h0))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_587 = and(_T_585, _T_586)
node _T_588 = and(_T_581, _T_587)
node _T_589 = or(UInt<1>(0h0), _T_588)
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = and(_T_593, _T_598)
node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_602 = and(_T_600, _T_601)
node _T_603 = or(UInt<1>(0h0), _T_602)
node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = or(_T_608, _T_613)
node _T_645 = or(_T_644, _T_618)
node _T_646 = or(_T_645, _T_623)
node _T_647 = or(_T_646, _T_628)
node _T_648 = or(_T_647, _T_633)
node _T_649 = or(_T_648, _T_638)
node _T_650 = or(_T_649, _T_643)
node _T_651 = and(_T_603, _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_599)
node _T_660 = or(_T_659, _T_651)
node _T_661 = or(_T_660, _T_658)
node _T_662 = and(_T_589, _T_661)
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(_T_662, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_662, UInt<1>(0h1), "") : assert_31
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(is_aligned, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_672, UInt<1>(0h1), "") : assert_34
node _T_676 = not(mask)
node _T_677 = and(io.in.a.bits.mask, _T_676)
node _T_678 = eq(_T_677, UInt<1>(0h0))
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_678, UInt<1>(0h1), "") : assert_35
node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_686 = shr(io.in.a.bits.source, 4)
node _T_687 = eq(_T_686, UInt<1>(0h0))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_6, UInt<4>(0hf))
node _T_691 = and(_T_689, _T_690)
node _T_692 = and(_T_685, _T_691)
node _T_693 = or(UInt<1>(0h0), _T_692)
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_696 = and(_T_694, _T_695)
node _T_697 = or(UInt<1>(0h0), _T_696)
node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<27>(0h4000000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = or(_T_702, _T_707)
node _T_734 = or(_T_733, _T_712)
node _T_735 = or(_T_734, _T_717)
node _T_736 = or(_T_735, _T_722)
node _T_737 = or(_T_736, _T_727)
node _T_738 = or(_T_737, _T_732)
node _T_739 = and(_T_697, _T_738)
node _T_740 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_741 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<17>(0h10000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = and(_T_740, _T_745)
node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_757 = cvt(_T_756)
node _T_758 = and(_T_757, asSInt(UInt<29>(0h10000000)))
node _T_759 = asSInt(_T_758)
node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0)))
node _T_761 = or(_T_755, _T_760)
node _T_762 = and(_T_750, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_739)
node _T_764 = or(_T_763, _T_746)
node _T_765 = or(_T_764, _T_762)
node _T_766 = and(_T_693, _T_765)
node _T_767 = asUInt(reset)
node _T_768 = eq(_T_767, UInt<1>(0h0))
when _T_768 :
node _T_769 = eq(_T_766, UInt<1>(0h0))
when _T_769 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_766, UInt<1>(0h1), "") : assert_36
node _T_770 = asUInt(reset)
node _T_771 = eq(_T_770, UInt<1>(0h0))
when _T_771 :
node _T_772 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(is_aligned, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_776 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(_T_776, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_776, UInt<1>(0h1), "") : assert_39
node _T_780 = eq(io.in.a.bits.mask, mask)
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(_T_780, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_780, UInt<1>(0h1), "") : assert_40
node _T_784 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_784 :
node _T_785 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_786 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_787 = and(_T_785, _T_786)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_788 = shr(io.in.a.bits.source, 4)
node _T_789 = eq(_T_788, UInt<1>(0h0))
node _T_790 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_791 = and(_T_789, _T_790)
node _T_792 = leq(uncommonBits_7, UInt<4>(0hf))
node _T_793 = and(_T_791, _T_792)
node _T_794 = and(_T_787, _T_793)
node _T_795 = or(UInt<1>(0h0), _T_794)
node _T_796 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_797 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_798 = and(_T_796, _T_797)
node _T_799 = or(UInt<1>(0h0), _T_798)
node _T_800 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<14>(0h2000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<13>(0h1000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<18>(0h2f000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<13>(0h1000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = or(_T_804, _T_809)
node _T_836 = or(_T_835, _T_814)
node _T_837 = or(_T_836, _T_819)
node _T_838 = or(_T_837, _T_824)
node _T_839 = or(_T_838, _T_829)
node _T_840 = or(_T_839, _T_834)
node _T_841 = and(_T_799, _T_840)
node _T_842 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_843 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<17>(0h10000)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = and(_T_842, _T_847)
node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_850 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_851 = and(_T_849, _T_850)
node _T_852 = or(UInt<1>(0h0), _T_851)
node _T_853 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_854 = cvt(_T_853)
node _T_855 = and(_T_854, asSInt(UInt<17>(0h10000)))
node _T_856 = asSInt(_T_855)
node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0)))
node _T_858 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_859 = cvt(_T_858)
node _T_860 = and(_T_859, asSInt(UInt<29>(0h10000000)))
node _T_861 = asSInt(_T_860)
node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0)))
node _T_863 = or(_T_857, _T_862)
node _T_864 = and(_T_852, _T_863)
node _T_865 = or(UInt<1>(0h0), _T_841)
node _T_866 = or(_T_865, _T_848)
node _T_867 = or(_T_866, _T_864)
node _T_868 = and(_T_795, _T_867)
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_868, UInt<1>(0h1), "") : assert_41
node _T_872 = asUInt(reset)
node _T_873 = eq(_T_872, UInt<1>(0h0))
when _T_873 :
node _T_874 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_874 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(is_aligned, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_878 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_878, UInt<1>(0h1), "") : assert_44
node _T_882 = eq(io.in.a.bits.mask, mask)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_882, UInt<1>(0h1), "") : assert_45
node _T_886 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_886 :
node _T_887 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_888 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_889 = and(_T_887, _T_888)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_890 = shr(io.in.a.bits.source, 4)
node _T_891 = eq(_T_890, UInt<1>(0h0))
node _T_892 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_893 = and(_T_891, _T_892)
node _T_894 = leq(uncommonBits_8, UInt<4>(0hf))
node _T_895 = and(_T_893, _T_894)
node _T_896 = and(_T_889, _T_895)
node _T_897 = or(UInt<1>(0h0), _T_896)
node _T_898 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_899 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_900 = and(_T_898, _T_899)
node _T_901 = or(UInt<1>(0h0), _T_900)
node _T_902 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_903 = cvt(_T_902)
node _T_904 = and(_T_903, asSInt(UInt<13>(0h1000)))
node _T_905 = asSInt(_T_904)
node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0)))
node _T_907 = and(_T_901, _T_906)
node _T_908 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_909 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<14>(0h2000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<18>(0h2f000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<27>(0h4000000)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = or(_T_913, _T_918)
node _T_945 = or(_T_944, _T_923)
node _T_946 = or(_T_945, _T_928)
node _T_947 = or(_T_946, _T_933)
node _T_948 = or(_T_947, _T_938)
node _T_949 = or(_T_948, _T_943)
node _T_950 = and(_T_908, _T_949)
node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_952 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_953 = and(_T_951, _T_952)
node _T_954 = or(UInt<1>(0h0), _T_953)
node _T_955 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_956 = cvt(_T_955)
node _T_957 = and(_T_956, asSInt(UInt<17>(0h10000)))
node _T_958 = asSInt(_T_957)
node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0)))
node _T_960 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_961 = cvt(_T_960)
node _T_962 = and(_T_961, asSInt(UInt<29>(0h10000000)))
node _T_963 = asSInt(_T_962)
node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0)))
node _T_965 = or(_T_959, _T_964)
node _T_966 = and(_T_954, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_907)
node _T_968 = or(_T_967, _T_950)
node _T_969 = or(_T_968, _T_966)
node _T_970 = and(_T_897, _T_969)
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_970, UInt<1>(0h1), "") : assert_46
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(is_aligned, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_980 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_980, UInt<1>(0h1), "") : assert_49
node _T_984 = eq(io.in.a.bits.mask, mask)
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(_T_984, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_984, UInt<1>(0h1), "") : assert_50
node _T_988 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_988, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_992 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(_T_992, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_992, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0hf))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_996 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_996 :
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_1000 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_54
node _T_1004 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_55
node _T_1008 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(_T_1008, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1008, UInt<1>(0h1), "") : assert_56
node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_57
node _T_1016 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1016 :
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(sink_ok, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1023 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_60
node _T_1027 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_61
node _T_1031 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_62
node _T_1035 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_T_1035, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1035, UInt<1>(0h1), "") : assert_63
node _T_1039 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1040 = or(UInt<1>(0h1), _T_1039)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_64
node _T_1044 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1044 :
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1048 = asUInt(reset)
node _T_1049 = eq(_T_1048, UInt<1>(0h0))
when _T_1049 :
node _T_1050 = eq(sink_ok, UInt<1>(0h0))
when _T_1050 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1051 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_67
node _T_1055 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_68
node _T_1059 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_69
node _T_1063 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1064 = or(_T_1063, io.in.d.bits.corrupt)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_70
node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1069 = or(UInt<1>(0h1), _T_1068)
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_71
node _T_1073 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1077 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_73
node _T_1081 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_T_1081, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1081, UInt<1>(0h1), "") : assert_74
node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1086 = or(UInt<1>(0h1), _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_75
node _T_1090 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1090 :
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_77
node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1099 = or(_T_1098, io.in.d.bits.corrupt)
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_78
node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1104 = or(UInt<1>(0h1), _T_1103)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_79
node _T_1108 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1108 :
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1112 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_81
node _T_1116 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_82
node _T_1120 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1121 = or(UInt<1>(0h1), _T_1120)
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1125 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1129 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1133 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1137 = eq(a_first, UInt<1>(0h0))
node _T_1138 = and(io.in.a.valid, _T_1137)
when _T_1138 :
node _T_1139 = eq(io.in.a.bits.opcode, opcode)
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_87
node _T_1143 = eq(io.in.a.bits.param, param)
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(_T_1143, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1143, UInt<1>(0h1), "") : assert_88
node _T_1147 = eq(io.in.a.bits.size, size)
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_89
node _T_1151 = eq(io.in.a.bits.source, source)
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_90
node _T_1155 = eq(io.in.a.bits.address, address)
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_91
node _T_1159 = and(io.in.a.ready, io.in.a.valid)
node _T_1160 = and(_T_1159, a_first)
when _T_1160 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1161 = eq(d_first, UInt<1>(0h0))
node _T_1162 = and(io.in.d.valid, _T_1161)
when _T_1162 :
node _T_1163 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_92
node _T_1167 = eq(io.in.d.bits.param, param_1)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_93
node _T_1171 = eq(io.in.d.bits.size, size_1)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_94
node _T_1175 = eq(io.in.d.bits.source, source_1)
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_95
node _T_1179 = eq(io.in.d.bits.sink, sink)
node _T_1180 = asUInt(reset)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(_T_1179, UInt<1>(0h0))
when _T_1182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1179, UInt<1>(0h1), "") : assert_96
node _T_1183 = eq(io.in.d.bits.denied, denied)
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(_T_1183, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1183, UInt<1>(0h1), "") : assert_97
node _T_1187 = and(io.in.d.ready, io.in.d.valid)
node _T_1188 = and(_T_1187, d_first)
when _T_1188 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1189 = and(io.in.a.valid, a_first_1)
node _T_1190 = and(_T_1189, UInt<1>(0h1))
when _T_1190 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1191 = and(io.in.a.ready, io.in.a.valid)
node _T_1192 = and(_T_1191, a_first_1)
node _T_1193 = and(_T_1192, UInt<1>(0h1))
when _T_1193 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1194 = dshr(inflight, io.in.a.bits.source)
node _T_1195 = bits(_T_1194, 0, 0)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
node _T_1197 = asUInt(reset)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
when _T_1198 :
node _T_1199 = eq(_T_1196, UInt<1>(0h0))
when _T_1199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1196, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1200 = and(io.in.d.valid, d_first_1)
node _T_1201 = and(_T_1200, UInt<1>(0h1))
node _T_1202 = eq(d_release_ack, UInt<1>(0h0))
node _T_1203 = and(_T_1201, _T_1202)
when _T_1203 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1204 = and(io.in.d.ready, io.in.d.valid)
node _T_1205 = and(_T_1204, d_first_1)
node _T_1206 = and(_T_1205, UInt<1>(0h1))
node _T_1207 = eq(d_release_ack, UInt<1>(0h0))
node _T_1208 = and(_T_1206, _T_1207)
when _T_1208 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1209 = and(io.in.d.valid, d_first_1)
node _T_1210 = and(_T_1209, UInt<1>(0h1))
node _T_1211 = eq(d_release_ack, UInt<1>(0h0))
node _T_1212 = and(_T_1210, _T_1211)
when _T_1212 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1213 = dshr(inflight, io.in.d.bits.source)
node _T_1214 = bits(_T_1213, 0, 0)
node _T_1215 = or(_T_1214, same_cycle_resp)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1219 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1221 = or(_T_1219, _T_1220)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_100
node _T_1225 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_101
else :
node _T_1229 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1230 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1231 = or(_T_1229, _T_1230)
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_102
node _T_1235 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_103
node _T_1239 = and(io.in.d.valid, d_first_1)
node _T_1240 = and(_T_1239, a_first_1)
node _T_1241 = and(_T_1240, io.in.a.valid)
node _T_1242 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1243 = and(_T_1241, _T_1242)
node _T_1244 = eq(d_release_ack, UInt<1>(0h0))
node _T_1245 = and(_T_1243, _T_1244)
when _T_1245 :
node _T_1246 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1247 = or(_T_1246, io.in.a.ready)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_104
node _T_1251 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1252 = orr(a_set_wo_ready)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
node _T_1254 = or(_T_1251, _T_1253)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_90
node _T_1258 = orr(inflight)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
node _T_1260 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1261 = or(_T_1259, _T_1260)
node _T_1262 = lt(watchdog, plusarg_reader.out)
node _T_1263 = or(_T_1261, _T_1262)
node _T_1264 = asUInt(reset)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
when _T_1265 :
node _T_1266 = eq(_T_1263, UInt<1>(0h0))
when _T_1266 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1263, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1267 = and(io.in.a.ready, io.in.a.valid)
node _T_1268 = and(io.in.d.ready, io.in.d.valid)
node _T_1269 = or(_T_1267, _T_1268)
when _T_1269 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<128>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1270 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1271 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1272 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1273 = and(_T_1271, _T_1272)
node _T_1274 = and(_T_1270, _T_1273)
when _T_1274 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1275 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1276 = and(_T_1275, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1277 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1278 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = and(_T_1276, _T_1279)
when _T_1280 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1281 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1282 = bits(_T_1281, 0, 0)
node _T_1283 = eq(_T_1282, UInt<1>(0h0))
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1287 = and(io.in.d.valid, d_first_2)
node _T_1288 = and(_T_1287, UInt<1>(0h1))
node _T_1289 = and(_T_1288, d_release_ack_1)
when _T_1289 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1290 = and(io.in.d.ready, io.in.d.valid)
node _T_1291 = and(_T_1290, d_first_2)
node _T_1292 = and(_T_1291, UInt<1>(0h1))
node _T_1293 = and(_T_1292, d_release_ack_1)
when _T_1293 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1294 = and(io.in.d.valid, d_first_2)
node _T_1295 = and(_T_1294, UInt<1>(0h1))
node _T_1296 = and(_T_1295, d_release_ack_1)
when _T_1296 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1297 = dshr(inflight_1, io.in.d.bits.source)
node _T_1298 = bits(_T_1297, 0, 0)
node _T_1299 = or(_T_1298, same_cycle_resp_1)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1303 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_109
else :
node _T_1307 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_110
node _T_1311 = and(io.in.d.valid, d_first_2)
node _T_1312 = and(_T_1311, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1313 = and(_T_1312, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<128>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1314 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1315 = and(_T_1313, _T_1314)
node _T_1316 = and(_T_1315, d_release_ack_1)
node _T_1317 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1318 = and(_T_1316, _T_1317)
when _T_1318 :
node _T_1319 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<128>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1320 = or(_T_1319, _WIRE_23.ready)
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(_T_1320, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1320, UInt<1>(0h1), "") : assert_111
node _T_1324 = orr(c_set_wo_ready)
when _T_1324 :
node _T_1325 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1326 = asUInt(reset)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
when _T_1327 :
node _T_1328 = eq(_T_1325, UInt<1>(0h0))
when _T_1328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1325, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_91
node _T_1329 = orr(inflight_1)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
node _T_1331 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1332 = or(_T_1330, _T_1331)
node _T_1333 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1334 = or(_T_1332, _T_1333)
node _T_1335 = asUInt(reset)
node _T_1336 = eq(_T_1335, UInt<1>(0h0))
when _T_1336 :
node _T_1337 = eq(_T_1334, UInt<1>(0h0))
when _T_1337 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:27)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1334, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1338 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1339 = and(io.in.d.ready, io.in.d.valid)
node _T_1340 = or(_T_1338, _T_1339)
when _T_1340 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_45( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1267 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1267; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1267; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1340 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1340; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1340; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1340; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1193 = _T_1267 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1193 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1239 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1208 = _T_1340 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1208 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1208 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1208 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1311 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1311 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1293 = _T_1340 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1293 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1293 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1293 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE : UInt<1>[8]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6])
node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<3>(0h4))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = and(_T_11, _T_24)
node _T_94 = and(_T_93, _T_37)
node _T_95 = and(_T_94, _T_50)
node _T_96 = and(_T_95, _T_63)
node _T_97 = and(_T_96, _T_76)
node _T_98 = and(_T_97, _T_84)
node _T_99 = and(_T_98, _T_92)
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_99, UInt<1>(0h1), "") : assert_1
node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_103 :
node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_108 = shr(io.in.a.bits.source, 2)
node _T_109 = eq(_T_108, UInt<1>(0h0))
node _T_110 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_111 = and(_T_109, _T_110)
node _T_112 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_113 = and(_T_111, _T_112)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_114 = shr(io.in.a.bits.source, 2)
node _T_115 = eq(_T_114, UInt<1>(0h1))
node _T_116 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_117 = and(_T_115, _T_116)
node _T_118 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_119 = and(_T_117, _T_118)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_120 = shr(io.in.a.bits.source, 2)
node _T_121 = eq(_T_120, UInt<2>(0h2))
node _T_122 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_123 = and(_T_121, _T_122)
node _T_124 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_125 = and(_T_123, _T_124)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_126 = shr(io.in.a.bits.source, 2)
node _T_127 = eq(_T_126, UInt<2>(0h3))
node _T_128 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_129 = and(_T_127, _T_128)
node _T_130 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_131 = and(_T_129, _T_130)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_132 = shr(io.in.a.bits.source, 3)
node _T_133 = eq(_T_132, UInt<3>(0h4))
node _T_134 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_135 = and(_T_133, _T_134)
node _T_136 = leq(uncommonBits_9, UInt<3>(0h7))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_140 = or(_T_107, _T_113)
node _T_141 = or(_T_140, _T_119)
node _T_142 = or(_T_141, _T_125)
node _T_143 = or(_T_142, _T_131)
node _T_144 = or(_T_143, _T_137)
node _T_145 = or(_T_144, _T_138)
node _T_146 = or(_T_145, _T_139)
node _T_147 = and(_T_106, _T_146)
node _T_148 = or(UInt<1>(0h0), _T_147)
node _T_149 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_150 = or(UInt<1>(0h0), _T_149)
node _T_151 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<17>(0h101c0)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<29>(0h100001c0)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = or(_T_155, _T_160)
node _T_162 = and(_T_150, _T_161)
node _T_163 = or(UInt<1>(0h0), _T_162)
node _T_164 = and(_T_148, _T_163)
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_164, UInt<1>(0h1), "") : assert_2
node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_169 = shr(io.in.a.bits.source, 2)
node _T_170 = eq(_T_169, UInt<1>(0h0))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_175 = shr(io.in.a.bits.source, 2)
node _T_176 = eq(_T_175, UInt<1>(0h1))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<2>(0h2))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_187 = shr(io.in.a.bits.source, 2)
node _T_188 = eq(_T_187, UInt<2>(0h3))
node _T_189 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_190 = and(_T_188, _T_189)
node _T_191 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_192 = and(_T_190, _T_191)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0)
node _T_193 = shr(io.in.a.bits.source, 3)
node _T_194 = eq(_T_193, UInt<3>(0h4))
node _T_195 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_196 = and(_T_194, _T_195)
node _T_197 = leq(uncommonBits_14, UInt<3>(0h7))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _WIRE : UInt<1>[8]
connect _WIRE[0], _T_168
connect _WIRE[1], _T_174
connect _WIRE[2], _T_180
connect _WIRE[3], _T_186
connect _WIRE[4], _T_192
connect _WIRE[5], _T_198
connect _WIRE[6], _T_199
connect _WIRE[7], _T_200
node _T_201 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_202 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_204 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_205 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_207 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[6], _T_201, UInt<1>(0h0))
node _T_209 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = or(_T_202, _T_203)
node _T_211 = or(_T_210, _T_204)
node _T_212 = or(_T_211, _T_205)
node _T_213 = or(_T_212, _T_206)
node _T_214 = or(_T_213, _T_207)
node _T_215 = or(_T_214, _T_208)
node _T_216 = or(_T_215, _T_209)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_216
node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_219 = and(_T_217, _T_218)
node _T_220 = or(UInt<1>(0h0), _T_219)
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<17>(0h101c0)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<29>(0h100001c0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = and(_T_220, _T_231)
node _T_233 = or(UInt<1>(0h0), _T_232)
node _T_234 = and(_WIRE_1, _T_233)
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_234, UInt<1>(0h1), "") : assert_3
node _T_238 = asUInt(reset)
node _T_239 = eq(_T_238, UInt<1>(0h0))
when _T_239 :
node _T_240 = eq(source_ok, UInt<1>(0h0))
when _T_240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_241 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_242 = asUInt(reset)
node _T_243 = eq(_T_242, UInt<1>(0h0))
when _T_243 :
node _T_244 = eq(_T_241, UInt<1>(0h0))
when _T_244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_241, UInt<1>(0h1), "") : assert_5
node _T_245 = asUInt(reset)
node _T_246 = eq(_T_245, UInt<1>(0h0))
when _T_246 :
node _T_247 = eq(is_aligned, UInt<1>(0h0))
when _T_247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_248, UInt<1>(0h1), "") : assert_7
node _T_252 = not(io.in.a.bits.mask)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_253, UInt<1>(0h1), "") : assert_8
node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_T_257, UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_257, UInt<1>(0h1), "") : assert_9
node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_261 :
node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<1>(0h1))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h2))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<2>(0h3))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_290 = shr(io.in.a.bits.source, 3)
node _T_291 = eq(_T_290, UInt<3>(0h4))
node _T_292 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_293 = and(_T_291, _T_292)
node _T_294 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_298 = or(_T_265, _T_271)
node _T_299 = or(_T_298, _T_277)
node _T_300 = or(_T_299, _T_283)
node _T_301 = or(_T_300, _T_289)
node _T_302 = or(_T_301, _T_295)
node _T_303 = or(_T_302, _T_296)
node _T_304 = or(_T_303, _T_297)
node _T_305 = and(_T_264, _T_304)
node _T_306 = or(UInt<1>(0h0), _T_305)
node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_310 = cvt(_T_309)
node _T_311 = and(_T_310, asSInt(UInt<17>(0h101c0)))
node _T_312 = asSInt(_T_311)
node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0)))
node _T_314 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<29>(0h100001c0)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = or(_T_313, _T_318)
node _T_320 = and(_T_308, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = and(_T_306, _T_321)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_322, UInt<1>(0h1), "") : assert_10
node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_327 = shr(io.in.a.bits.source, 2)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_330 = and(_T_328, _T_329)
node _T_331 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_333 = shr(io.in.a.bits.source, 2)
node _T_334 = eq(_T_333, UInt<1>(0h1))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_338 = and(_T_336, _T_337)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_339 = shr(io.in.a.bits.source, 2)
node _T_340 = eq(_T_339, UInt<2>(0h2))
node _T_341 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_342 = and(_T_340, _T_341)
node _T_343 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_344 = and(_T_342, _T_343)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_345 = shr(io.in.a.bits.source, 2)
node _T_346 = eq(_T_345, UInt<2>(0h3))
node _T_347 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_348 = and(_T_346, _T_347)
node _T_349 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_350 = and(_T_348, _T_349)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_351 = shr(io.in.a.bits.source, 3)
node _T_352 = eq(_T_351, UInt<3>(0h4))
node _T_353 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_354 = and(_T_352, _T_353)
node _T_355 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _WIRE_2 : UInt<1>[8]
connect _WIRE_2[0], _T_326
connect _WIRE_2[1], _T_332
connect _WIRE_2[2], _T_338
connect _WIRE_2[3], _T_344
connect _WIRE_2[4], _T_350
connect _WIRE_2[5], _T_356
connect _WIRE_2[6], _T_357
connect _WIRE_2[7], _T_358
node _T_359 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_360 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_364 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_366 = mux(_WIRE_2[6], _T_359, UInt<1>(0h0))
node _T_367 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = or(_T_360, _T_361)
node _T_369 = or(_T_368, _T_362)
node _T_370 = or(_T_369, _T_363)
node _T_371 = or(_T_370, _T_364)
node _T_372 = or(_T_371, _T_365)
node _T_373 = or(_T_372, _T_366)
node _T_374 = or(_T_373, _T_367)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_374
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<17>(0h101c0)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<29>(0h100001c0)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = or(_T_383, _T_388)
node _T_390 = and(_T_378, _T_389)
node _T_391 = or(UInt<1>(0h0), _T_390)
node _T_392 = and(_WIRE_3, _T_391)
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_392, UInt<1>(0h1), "") : assert_11
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(source_ok, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_399 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_399, UInt<1>(0h1), "") : assert_13
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(is_aligned, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_406 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_406, UInt<1>(0h1), "") : assert_15
node _T_410 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_411 = asUInt(reset)
node _T_412 = eq(_T_411, UInt<1>(0h0))
when _T_412 :
node _T_413 = eq(_T_410, UInt<1>(0h0))
when _T_413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_410, UInt<1>(0h1), "") : assert_16
node _T_414 = not(io.in.a.bits.mask)
node _T_415 = eq(_T_414, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_415, UInt<1>(0h1), "") : assert_17
node _T_419 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_419, UInt<1>(0h1), "") : assert_18
node _T_423 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_423 :
node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_428 = shr(io.in.a.bits.source, 2)
node _T_429 = eq(_T_428, UInt<1>(0h0))
node _T_430 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_431 = and(_T_429, _T_430)
node _T_432 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_433 = and(_T_431, _T_432)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_434 = shr(io.in.a.bits.source, 2)
node _T_435 = eq(_T_434, UInt<1>(0h1))
node _T_436 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_437 = and(_T_435, _T_436)
node _T_438 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_439 = and(_T_437, _T_438)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_440 = shr(io.in.a.bits.source, 2)
node _T_441 = eq(_T_440, UInt<2>(0h2))
node _T_442 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_443 = and(_T_441, _T_442)
node _T_444 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_445 = and(_T_443, _T_444)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_446 = shr(io.in.a.bits.source, 2)
node _T_447 = eq(_T_446, UInt<2>(0h3))
node _T_448 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_449 = and(_T_447, _T_448)
node _T_450 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_451 = and(_T_449, _T_450)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0)
node _T_452 = shr(io.in.a.bits.source, 3)
node _T_453 = eq(_T_452, UInt<3>(0h4))
node _T_454 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_455 = and(_T_453, _T_454)
node _T_456 = leq(uncommonBits_29, UInt<3>(0h7))
node _T_457 = and(_T_455, _T_456)
node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_460 = or(_T_427, _T_433)
node _T_461 = or(_T_460, _T_439)
node _T_462 = or(_T_461, _T_445)
node _T_463 = or(_T_462, _T_451)
node _T_464 = or(_T_463, _T_457)
node _T_465 = or(_T_464, _T_458)
node _T_466 = or(_T_465, _T_459)
node _T_467 = and(_T_426, _T_466)
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_468, UInt<1>(0h1), "") : assert_19
node _T_472 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_473 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_474 = and(_T_472, _T_473)
node _T_475 = or(UInt<1>(0h0), _T_474)
node _T_476 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<17>(0h101c0)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_482 = cvt(_T_481)
node _T_483 = and(_T_482, asSInt(UInt<29>(0h100001c0)))
node _T_484 = asSInt(_T_483)
node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0)))
node _T_486 = or(_T_480, _T_485)
node _T_487 = and(_T_475, _T_486)
node _T_488 = or(UInt<1>(0h0), _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_488, UInt<1>(0h1), "") : assert_20
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(source_ok, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_498 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_498, UInt<1>(0h1), "") : assert_23
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_502, UInt<1>(0h1), "") : assert_24
node _T_506 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_507 = asUInt(reset)
node _T_508 = eq(_T_507, UInt<1>(0h0))
when _T_508 :
node _T_509 = eq(_T_506, UInt<1>(0h0))
when _T_509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_506, UInt<1>(0h1), "") : assert_25
node _T_510 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_510 :
node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_512 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_513 = and(_T_511, _T_512)
node _T_514 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_515 = shr(io.in.a.bits.source, 2)
node _T_516 = eq(_T_515, UInt<1>(0h0))
node _T_517 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_518 = and(_T_516, _T_517)
node _T_519 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_520 = and(_T_518, _T_519)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_521 = shr(io.in.a.bits.source, 2)
node _T_522 = eq(_T_521, UInt<1>(0h1))
node _T_523 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_524 = and(_T_522, _T_523)
node _T_525 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_526 = and(_T_524, _T_525)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_527 = shr(io.in.a.bits.source, 2)
node _T_528 = eq(_T_527, UInt<2>(0h2))
node _T_529 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_530 = and(_T_528, _T_529)
node _T_531 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_532 = and(_T_530, _T_531)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_533 = shr(io.in.a.bits.source, 2)
node _T_534 = eq(_T_533, UInt<2>(0h3))
node _T_535 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_536 = and(_T_534, _T_535)
node _T_537 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_538 = and(_T_536, _T_537)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_539 = shr(io.in.a.bits.source, 3)
node _T_540 = eq(_T_539, UInt<3>(0h4))
node _T_541 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_542 = and(_T_540, _T_541)
node _T_543 = leq(uncommonBits_34, UInt<3>(0h7))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_547 = or(_T_514, _T_520)
node _T_548 = or(_T_547, _T_526)
node _T_549 = or(_T_548, _T_532)
node _T_550 = or(_T_549, _T_538)
node _T_551 = or(_T_550, _T_544)
node _T_552 = or(_T_551, _T_545)
node _T_553 = or(_T_552, _T_546)
node _T_554 = and(_T_513, _T_553)
node _T_555 = or(UInt<1>(0h0), _T_554)
node _T_556 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_557 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_561 = cvt(_T_560)
node _T_562 = and(_T_561, asSInt(UInt<17>(0h101c0)))
node _T_563 = asSInt(_T_562)
node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0)))
node _T_565 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_566 = cvt(_T_565)
node _T_567 = and(_T_566, asSInt(UInt<29>(0h100001c0)))
node _T_568 = asSInt(_T_567)
node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0)))
node _T_570 = or(_T_564, _T_569)
node _T_571 = and(_T_559, _T_570)
node _T_572 = or(UInt<1>(0h0), _T_571)
node _T_573 = and(_T_555, _T_572)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_573, UInt<1>(0h1), "") : assert_26
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(source_ok, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(is_aligned, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_584 = asUInt(reset)
node _T_585 = eq(_T_584, UInt<1>(0h0))
when _T_585 :
node _T_586 = eq(_T_583, UInt<1>(0h0))
when _T_586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_583, UInt<1>(0h1), "") : assert_29
node _T_587 = eq(io.in.a.bits.mask, mask)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_587, UInt<1>(0h1), "") : assert_30
node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_591 :
node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_594 = and(_T_592, _T_593)
node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_596 = shr(io.in.a.bits.source, 2)
node _T_597 = eq(_T_596, UInt<1>(0h0))
node _T_598 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_599 = and(_T_597, _T_598)
node _T_600 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_601 = and(_T_599, _T_600)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_602 = shr(io.in.a.bits.source, 2)
node _T_603 = eq(_T_602, UInt<1>(0h1))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_607 = and(_T_605, _T_606)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_608 = shr(io.in.a.bits.source, 2)
node _T_609 = eq(_T_608, UInt<2>(0h2))
node _T_610 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_611 = and(_T_609, _T_610)
node _T_612 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_613 = and(_T_611, _T_612)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_614 = shr(io.in.a.bits.source, 2)
node _T_615 = eq(_T_614, UInt<2>(0h3))
node _T_616 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_617 = and(_T_615, _T_616)
node _T_618 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_619 = and(_T_617, _T_618)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_620 = shr(io.in.a.bits.source, 3)
node _T_621 = eq(_T_620, UInt<3>(0h4))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_625 = and(_T_623, _T_624)
node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_628 = or(_T_595, _T_601)
node _T_629 = or(_T_628, _T_607)
node _T_630 = or(_T_629, _T_613)
node _T_631 = or(_T_630, _T_619)
node _T_632 = or(_T_631, _T_625)
node _T_633 = or(_T_632, _T_626)
node _T_634 = or(_T_633, _T_627)
node _T_635 = and(_T_594, _T_634)
node _T_636 = or(UInt<1>(0h0), _T_635)
node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_638 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_639 = and(_T_637, _T_638)
node _T_640 = or(UInt<1>(0h0), _T_639)
node _T_641 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_642 = cvt(_T_641)
node _T_643 = and(_T_642, asSInt(UInt<17>(0h101c0)))
node _T_644 = asSInt(_T_643)
node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0)))
node _T_646 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_647 = cvt(_T_646)
node _T_648 = and(_T_647, asSInt(UInt<29>(0h100001c0)))
node _T_649 = asSInt(_T_648)
node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0)))
node _T_651 = or(_T_645, _T_650)
node _T_652 = and(_T_640, _T_651)
node _T_653 = or(UInt<1>(0h0), _T_652)
node _T_654 = and(_T_636, _T_653)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_654, UInt<1>(0h1), "") : assert_31
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(source_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(is_aligned, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_665 = asUInt(reset)
node _T_666 = eq(_T_665, UInt<1>(0h0))
when _T_666 :
node _T_667 = eq(_T_664, UInt<1>(0h0))
when _T_667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_664, UInt<1>(0h1), "") : assert_34
node _T_668 = not(mask)
node _T_669 = and(io.in.a.bits.mask, _T_668)
node _T_670 = eq(_T_669, UInt<1>(0h0))
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(_T_670, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_670, UInt<1>(0h1), "") : assert_35
node _T_674 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_674 :
node _T_675 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_676 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_677 = and(_T_675, _T_676)
node _T_678 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_679 = shr(io.in.a.bits.source, 2)
node _T_680 = eq(_T_679, UInt<1>(0h0))
node _T_681 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_682 = and(_T_680, _T_681)
node _T_683 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_684 = and(_T_682, _T_683)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_685 = shr(io.in.a.bits.source, 2)
node _T_686 = eq(_T_685, UInt<1>(0h1))
node _T_687 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_688 = and(_T_686, _T_687)
node _T_689 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_690 = and(_T_688, _T_689)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_691 = shr(io.in.a.bits.source, 2)
node _T_692 = eq(_T_691, UInt<2>(0h2))
node _T_693 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_694 = and(_T_692, _T_693)
node _T_695 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_696 = and(_T_694, _T_695)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_697 = shr(io.in.a.bits.source, 2)
node _T_698 = eq(_T_697, UInt<2>(0h3))
node _T_699 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_700 = and(_T_698, _T_699)
node _T_701 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_702 = and(_T_700, _T_701)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0)
node _T_703 = shr(io.in.a.bits.source, 3)
node _T_704 = eq(_T_703, UInt<3>(0h4))
node _T_705 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_706 = and(_T_704, _T_705)
node _T_707 = leq(uncommonBits_44, UInt<3>(0h7))
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_711 = or(_T_678, _T_684)
node _T_712 = or(_T_711, _T_690)
node _T_713 = or(_T_712, _T_696)
node _T_714 = or(_T_713, _T_702)
node _T_715 = or(_T_714, _T_708)
node _T_716 = or(_T_715, _T_709)
node _T_717 = or(_T_716, _T_710)
node _T_718 = and(_T_677, _T_717)
node _T_719 = or(UInt<1>(0h0), _T_718)
node _T_720 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_721 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_722 = and(_T_720, _T_721)
node _T_723 = or(UInt<1>(0h0), _T_722)
node _T_724 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_725 = cvt(_T_724)
node _T_726 = and(_T_725, asSInt(UInt<17>(0h101c0)))
node _T_727 = asSInt(_T_726)
node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0)))
node _T_729 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_730 = cvt(_T_729)
node _T_731 = and(_T_730, asSInt(UInt<29>(0h100001c0)))
node _T_732 = asSInt(_T_731)
node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0)))
node _T_734 = or(_T_728, _T_733)
node _T_735 = and(_T_723, _T_734)
node _T_736 = or(UInt<1>(0h0), _T_735)
node _T_737 = and(_T_719, _T_736)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_737, UInt<1>(0h1), "") : assert_36
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(source_ok, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_744 = asUInt(reset)
node _T_745 = eq(_T_744, UInt<1>(0h0))
when _T_745 :
node _T_746 = eq(is_aligned, UInt<1>(0h0))
when _T_746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_747 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_748 = asUInt(reset)
node _T_749 = eq(_T_748, UInt<1>(0h0))
when _T_749 :
node _T_750 = eq(_T_747, UInt<1>(0h0))
when _T_750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_747, UInt<1>(0h1), "") : assert_39
node _T_751 = eq(io.in.a.bits.mask, mask)
node _T_752 = asUInt(reset)
node _T_753 = eq(_T_752, UInt<1>(0h0))
when _T_753 :
node _T_754 = eq(_T_751, UInt<1>(0h0))
when _T_754 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_751, UInt<1>(0h1), "") : assert_40
node _T_755 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_755 :
node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_758 = and(_T_756, _T_757)
node _T_759 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_760 = shr(io.in.a.bits.source, 2)
node _T_761 = eq(_T_760, UInt<1>(0h0))
node _T_762 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_763 = and(_T_761, _T_762)
node _T_764 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_765 = and(_T_763, _T_764)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_766 = shr(io.in.a.bits.source, 2)
node _T_767 = eq(_T_766, UInt<1>(0h1))
node _T_768 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_769 = and(_T_767, _T_768)
node _T_770 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_771 = and(_T_769, _T_770)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_772 = shr(io.in.a.bits.source, 2)
node _T_773 = eq(_T_772, UInt<2>(0h2))
node _T_774 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_775 = and(_T_773, _T_774)
node _T_776 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_777 = and(_T_775, _T_776)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_778 = shr(io.in.a.bits.source, 2)
node _T_779 = eq(_T_778, UInt<2>(0h3))
node _T_780 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_781 = and(_T_779, _T_780)
node _T_782 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_783 = and(_T_781, _T_782)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_784 = shr(io.in.a.bits.source, 3)
node _T_785 = eq(_T_784, UInt<3>(0h4))
node _T_786 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_787 = and(_T_785, _T_786)
node _T_788 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_789 = and(_T_787, _T_788)
node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_792 = or(_T_759, _T_765)
node _T_793 = or(_T_792, _T_771)
node _T_794 = or(_T_793, _T_777)
node _T_795 = or(_T_794, _T_783)
node _T_796 = or(_T_795, _T_789)
node _T_797 = or(_T_796, _T_790)
node _T_798 = or(_T_797, _T_791)
node _T_799 = and(_T_758, _T_798)
node _T_800 = or(UInt<1>(0h0), _T_799)
node _T_801 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_802 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_803 = and(_T_801, _T_802)
node _T_804 = or(UInt<1>(0h0), _T_803)
node _T_805 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<17>(0h101c0)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<29>(0h100001c0)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = or(_T_809, _T_814)
node _T_816 = and(_T_804, _T_815)
node _T_817 = or(UInt<1>(0h0), _T_816)
node _T_818 = and(_T_800, _T_817)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_818, UInt<1>(0h1), "") : assert_41
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(source_ok, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(is_aligned, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_828, UInt<1>(0h1), "") : assert_44
node _T_832 = eq(io.in.a.bits.mask, mask)
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_832, UInt<1>(0h1), "") : assert_45
node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_836 :
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_841 = shr(io.in.a.bits.source, 2)
node _T_842 = eq(_T_841, UInt<1>(0h0))
node _T_843 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_844 = and(_T_842, _T_843)
node _T_845 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_846 = and(_T_844, _T_845)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_847 = shr(io.in.a.bits.source, 2)
node _T_848 = eq(_T_847, UInt<1>(0h1))
node _T_849 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_850 = and(_T_848, _T_849)
node _T_851 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_852 = and(_T_850, _T_851)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_853 = shr(io.in.a.bits.source, 2)
node _T_854 = eq(_T_853, UInt<2>(0h2))
node _T_855 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_856 = and(_T_854, _T_855)
node _T_857 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_858 = and(_T_856, _T_857)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_859 = shr(io.in.a.bits.source, 2)
node _T_860 = eq(_T_859, UInt<2>(0h3))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_865 = shr(io.in.a.bits.source, 3)
node _T_866 = eq(_T_865, UInt<3>(0h4))
node _T_867 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_868 = and(_T_866, _T_867)
node _T_869 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_873 = or(_T_840, _T_846)
node _T_874 = or(_T_873, _T_852)
node _T_875 = or(_T_874, _T_858)
node _T_876 = or(_T_875, _T_864)
node _T_877 = or(_T_876, _T_870)
node _T_878 = or(_T_877, _T_871)
node _T_879 = or(_T_878, _T_872)
node _T_880 = and(_T_839, _T_879)
node _T_881 = or(UInt<1>(0h0), _T_880)
node _T_882 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_883 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_884 = and(_T_882, _T_883)
node _T_885 = or(UInt<1>(0h0), _T_884)
node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<17>(0h101c0)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<29>(0h100001c0)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = or(_T_890, _T_895)
node _T_897 = and(_T_885, _T_896)
node _T_898 = or(UInt<1>(0h0), _T_897)
node _T_899 = and(_T_881, _T_898)
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_899, UInt<1>(0h1), "") : assert_46
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(source_ok, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(is_aligned, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(_T_909, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_909, UInt<1>(0h1), "") : assert_49
node _T_913 = eq(io.in.a.bits.mask, mask)
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_913, UInt<1>(0h1), "") : assert_50
node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_917, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_921, UInt<1>(0h1), "") : assert_52
node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_40 = shr(io.in.d.bits.source, 2)
node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0))
node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_46 = shr(io.in.d.bits.source, 2)
node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1))
node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_52 = shr(io.in.d.bits.source, 2)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_58 = shr(io.in.d.bits.source, 2)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0)
node _source_ok_T_64 = shr(io.in.d.bits.source, 3)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h7))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE_1 : UInt<1>[8]
connect _source_ok_WIRE_1[0], _source_ok_T_39
connect _source_ok_WIRE_1[1], _source_ok_T_45
connect _source_ok_WIRE_1[2], _source_ok_T_51
connect _source_ok_WIRE_1[3], _source_ok_T_57
connect _source_ok_WIRE_1[4], _source_ok_T_63
connect _source_ok_WIRE_1[5], _source_ok_T_69
connect _source_ok_WIRE_1[6], _source_ok_T_70
connect _source_ok_WIRE_1[7], _source_ok_T_71
node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6])
node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc))
node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_925 :
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(source_ok_1, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_929 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_929, UInt<1>(0h1), "") : assert_54
node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_933, UInt<1>(0h1), "") : assert_55
node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_937, UInt<1>(0h1), "") : assert_56
node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_941, UInt<1>(0h1), "") : assert_57
node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_945 :
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(source_ok_1, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(sink_ok, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_952 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_953 = asUInt(reset)
node _T_954 = eq(_T_953, UInt<1>(0h0))
when _T_954 :
node _T_955 = eq(_T_952, UInt<1>(0h0))
when _T_955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_952, UInt<1>(0h1), "") : assert_60
node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_957 = asUInt(reset)
node _T_958 = eq(_T_957, UInt<1>(0h0))
when _T_958 :
node _T_959 = eq(_T_956, UInt<1>(0h0))
when _T_959 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_956, UInt<1>(0h1), "") : assert_61
node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_960, UInt<1>(0h1), "") : assert_62
node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_964, UInt<1>(0h1), "") : assert_63
node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_969 = or(UInt<1>(0h1), _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_969, UInt<1>(0h1), "") : assert_64
node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_973 :
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(source_ok_1, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(sink_ok, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_980 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_980, UInt<1>(0h1), "") : assert_67
node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(_T_984, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_984, UInt<1>(0h1), "") : assert_68
node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_988, UInt<1>(0h1), "") : assert_69
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(_T_992, io.in.d.bits.corrupt)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_993, UInt<1>(0h1), "") : assert_70
node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_998 = or(UInt<1>(0h1), _T_997)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_998, UInt<1>(0h1), "") : assert_71
node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73
node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74
node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1015 = or(UInt<1>(0h1), _T_1014)
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75
node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1019 :
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(source_ok_1, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77
node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1028 = or(_T_1027, io.in.d.bits.corrupt)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78
node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1033 = or(UInt<1>(0h1), _T_1032)
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79
node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1037 :
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(source_ok_1, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81
node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82
node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1050 = or(UInt<1>(0h1), _T_1049)
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1054 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84
node _T_1058 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
node _T_1060 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1061 = cvt(_T_1060)
node _T_1062 = and(_T_1061, asSInt(UInt<1>(0h0)))
node _T_1063 = asSInt(_T_1062)
node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0)))
node _T_1065 = or(_T_1059, _T_1064)
node _uncommonBits_T_55 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1066 = shr(io.in.b.bits.source, 2)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
node _T_1068 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1069 = and(_T_1067, _T_1068)
node _T_1070 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
node _T_1073 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1074 = cvt(_T_1073)
node _T_1075 = and(_T_1074, asSInt(UInt<1>(0h0)))
node _T_1076 = asSInt(_T_1075)
node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0)))
node _T_1078 = or(_T_1072, _T_1077)
node _uncommonBits_T_56 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1079 = shr(io.in.b.bits.source, 2)
node _T_1080 = eq(_T_1079, UInt<1>(0h1))
node _T_1081 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
node _T_1086 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1087 = cvt(_T_1086)
node _T_1088 = and(_T_1087, asSInt(UInt<1>(0h0)))
node _T_1089 = asSInt(_T_1088)
node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0)))
node _T_1091 = or(_T_1085, _T_1090)
node _uncommonBits_T_57 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1092 = shr(io.in.b.bits.source, 2)
node _T_1093 = eq(_T_1092, UInt<2>(0h2))
node _T_1094 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1095 = and(_T_1093, _T_1094)
node _T_1096 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1097 = and(_T_1095, _T_1096)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
node _T_1099 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1100 = cvt(_T_1099)
node _T_1101 = and(_T_1100, asSInt(UInt<1>(0h0)))
node _T_1102 = asSInt(_T_1101)
node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0)))
node _T_1104 = or(_T_1098, _T_1103)
node _uncommonBits_T_58 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_1105 = shr(io.in.b.bits.source, 2)
node _T_1106 = eq(_T_1105, UInt<2>(0h3))
node _T_1107 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_1110 = and(_T_1108, _T_1109)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
node _T_1112 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1113 = cvt(_T_1112)
node _T_1114 = and(_T_1113, asSInt(UInt<1>(0h0)))
node _T_1115 = asSInt(_T_1114)
node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0)))
node _T_1117 = or(_T_1111, _T_1116)
node _uncommonBits_T_59 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0)
node _T_1118 = shr(io.in.b.bits.source, 3)
node _T_1119 = eq(_T_1118, UInt<3>(0h4))
node _T_1120 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1121 = and(_T_1119, _T_1120)
node _T_1122 = leq(uncommonBits_59, UInt<3>(0h7))
node _T_1123 = and(_T_1121, _T_1122)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
node _T_1125 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1126 = cvt(_T_1125)
node _T_1127 = and(_T_1126, asSInt(UInt<1>(0h0)))
node _T_1128 = asSInt(_T_1127)
node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0)))
node _T_1130 = or(_T_1124, _T_1129)
node _T_1131 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
node _T_1133 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1134 = cvt(_T_1133)
node _T_1135 = and(_T_1134, asSInt(UInt<1>(0h0)))
node _T_1136 = asSInt(_T_1135)
node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0)))
node _T_1138 = or(_T_1132, _T_1137)
node _T_1139 = eq(io.in.b.bits.source, UInt<6>(0h2a))
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
node _T_1141 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1142 = cvt(_T_1141)
node _T_1143 = and(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = asSInt(_T_1143)
node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0)))
node _T_1146 = or(_T_1140, _T_1145)
node _T_1147 = and(_T_1065, _T_1078)
node _T_1148 = and(_T_1147, _T_1091)
node _T_1149 = and(_T_1148, _T_1104)
node _T_1150 = and(_T_1149, _T_1117)
node _T_1151 = and(_T_1150, _T_1130)
node _T_1152 = and(_T_1151, _T_1138)
node _T_1153 = and(_T_1152, _T_1146)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3)
node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3)
node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1)
node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1)
node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1)
node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1)
node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11)
node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1)
node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12)
node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1)
node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13)
node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1)
node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14)
node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1)
node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_16 = and(mask_size_1, mask_eq_16)
node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_17 = and(mask_size_1, mask_eq_17)
node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_18 = and(mask_size_1, mask_eq_18)
node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_19 = and(mask_size_1, mask_eq_19)
node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_20 = and(mask_size_1, mask_eq_20)
node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_21 = and(mask_size_1, mask_eq_21)
node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_22 = and(mask_size_1, mask_eq_22)
node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_23 = and(mask_size_1, mask_eq_23)
node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1)
node _mask_acc_T_24 = and(mask_size_1, mask_eq_24)
node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1)
node _mask_acc_T_25 = and(mask_size_1, mask_eq_25)
node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1)
node _mask_acc_T_26 = and(mask_size_1, mask_eq_26)
node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1)
node _mask_acc_T_27 = and(mask_size_1, mask_eq_27)
node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1)
node _mask_acc_T_28 = and(mask_size_1, mask_eq_28)
node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1)
node _mask_acc_T_29 = and(mask_size_1, mask_eq_29)
node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1)
node _mask_acc_T_30 = and(mask_size_1, mask_eq_30)
node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1)
node _mask_acc_T_31 = and(mask_size_1, mask_eq_31)
node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31)
node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16)
node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18)
node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1)
node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20)
node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22)
node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24)
node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26)
node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1)
node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0)
node _legal_source_T_7 = shr(io.in.b.bits.source, 2)
node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1))
node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1)
node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3))
node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11)
node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0)
node _legal_source_T_13 = shr(io.in.b.bits.source, 2)
node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2))
node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2)
node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15)
node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3))
node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17)
node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0)
node _legal_source_T_19 = shr(io.in.b.bits.source, 2)
node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3))
node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3)
node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21)
node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3))
node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23)
node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0))
node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0)
node _legal_source_T_25 = shr(io.in.b.bits.source, 3)
node _legal_source_T_26 = eq(_legal_source_T_25, UInt<3>(0h4))
node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4)
node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27)
node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7))
node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29)
node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h2a))
wire _legal_source_WIRE : UInt<1>[8]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_12
connect _legal_source_WIRE[3], _legal_source_T_18
connect _legal_source_WIRE[4], _legal_source_T_24
connect _legal_source_WIRE[5], _legal_source_T_30
connect _legal_source_WIRE[6], _legal_source_T_31
connect _legal_source_WIRE[7], _legal_source_T_32
node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0))
node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0))
node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0))
node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0))
node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h28), UInt<1>(0h0))
node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2a), UInt<1>(0h0))
node _legal_source_T_41 = or(_legal_source_T_33, _legal_source_T_34)
node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_35)
node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_36)
node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_37)
node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_38)
node _legal_source_T_46 = or(_legal_source_T_45, _legal_source_T_39)
node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_40)
wire _legal_source_WIRE_1 : UInt<6>
connect _legal_source_WIRE_1, _legal_source_T_47
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1157 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1157 :
node _T_1158 = eq(io.in.b.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1159 = shr(io.in.b.bits.source, 2)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
node _T_1161 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1164 = and(_T_1162, _T_1163)
node _uncommonBits_T_61 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1165 = shr(io.in.b.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<1>(0h1))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _uncommonBits_T_62 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1171 = shr(io.in.b.bits.source, 2)
node _T_1172 = eq(_T_1171, UInt<2>(0h2))
node _T_1173 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1176 = and(_T_1174, _T_1175)
node _uncommonBits_T_63 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1177 = shr(io.in.b.bits.source, 2)
node _T_1178 = eq(_T_1177, UInt<2>(0h3))
node _T_1179 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1182 = and(_T_1180, _T_1181)
node _uncommonBits_T_64 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0)
node _T_1183 = shr(io.in.b.bits.source, 3)
node _T_1184 = eq(_T_1183, UInt<3>(0h4))
node _T_1185 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1186 = and(_T_1184, _T_1185)
node _T_1187 = leq(uncommonBits_64, UInt<3>(0h7))
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(io.in.b.bits.source, UInt<6>(0h28))
node _T_1190 = eq(io.in.b.bits.source, UInt<6>(0h2a))
wire _WIRE_4 : UInt<1>[8]
connect _WIRE_4[0], _T_1158
connect _WIRE_4[1], _T_1164
connect _WIRE_4[2], _T_1170
connect _WIRE_4[3], _T_1176
connect _WIRE_4[4], _T_1182
connect _WIRE_4[5], _T_1188
connect _WIRE_4[6], _T_1189
connect _WIRE_4[7], _T_1190
node _T_1191 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1192 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1193 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1194 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1195 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1196 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1197 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1198 = mux(_WIRE_4[6], _T_1191, UInt<1>(0h0))
node _T_1199 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1200 = or(_T_1192, _T_1193)
node _T_1201 = or(_T_1200, _T_1194)
node _T_1202 = or(_T_1201, _T_1195)
node _T_1203 = or(_T_1202, _T_1196)
node _T_1204 = or(_T_1203, _T_1197)
node _T_1205 = or(_T_1204, _T_1198)
node _T_1206 = or(_T_1205, _T_1199)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1206
node _T_1207 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1208 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1209 = and(_T_1207, _T_1208)
node _T_1210 = or(UInt<1>(0h0), _T_1209)
node _T_1211 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_1212 = cvt(_T_1211)
node _T_1213 = and(_T_1212, asSInt(UInt<17>(0h101c0)))
node _T_1214 = asSInt(_T_1213)
node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0)))
node _T_1216 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_1217 = cvt(_T_1216)
node _T_1218 = and(_T_1217, asSInt(UInt<29>(0h100001c0)))
node _T_1219 = asSInt(_T_1218)
node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0)))
node _T_1221 = or(_T_1215, _T_1220)
node _T_1222 = and(_T_1210, _T_1221)
node _T_1223 = or(UInt<1>(0h0), _T_1222)
node _T_1224 = and(_WIRE_5, _T_1223)
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_86
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(address_ok, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(legal_source, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1237 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_90
node _T_1241 = eq(io.in.b.bits.mask, mask_1)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_91
node _T_1245 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_92
node _T_1249 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1249 :
node _T_1250 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1251 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1252 = and(_T_1250, _T_1251)
node _T_1253 = or(UInt<1>(0h0), _T_1252)
node _T_1254 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<17>(0h101c0)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_1260 = cvt(_T_1259)
node _T_1261 = and(_T_1260, asSInt(UInt<29>(0h100001c0)))
node _T_1262 = asSInt(_T_1261)
node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0)))
node _T_1264 = or(_T_1258, _T_1263)
node _T_1265 = and(_T_1253, _T_1264)
node _T_1266 = or(UInt<1>(0h0), _T_1265)
node _T_1267 = and(UInt<1>(0h0), _T_1266)
node _T_1268 = asUInt(reset)
node _T_1269 = eq(_T_1268, UInt<1>(0h0))
when _T_1269 :
node _T_1270 = eq(_T_1267, UInt<1>(0h0))
when _T_1270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1267, UInt<1>(0h1), "") : assert_93
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(address_ok, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(legal_source, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1280 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_97
node _T_1284 = eq(io.in.b.bits.mask, mask_1)
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_98
node _T_1288 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_99
node _T_1292 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1294 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1295 = and(_T_1293, _T_1294)
node _T_1296 = or(UInt<1>(0h0), _T_1295)
node _T_1297 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_1298 = cvt(_T_1297)
node _T_1299 = and(_T_1298, asSInt(UInt<17>(0h101c0)))
node _T_1300 = asSInt(_T_1299)
node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0)))
node _T_1302 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_1303 = cvt(_T_1302)
node _T_1304 = and(_T_1303, asSInt(UInt<29>(0h100001c0)))
node _T_1305 = asSInt(_T_1304)
node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0)))
node _T_1307 = or(_T_1301, _T_1306)
node _T_1308 = and(_T_1296, _T_1307)
node _T_1309 = or(UInt<1>(0h0), _T_1308)
node _T_1310 = and(UInt<1>(0h0), _T_1309)
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_100
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(address_ok, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(legal_source, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1323 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_104
node _T_1327 = eq(io.in.b.bits.mask, mask_1)
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_105
node _T_1331 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1331 :
node _T_1332 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1333 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1334 = and(_T_1332, _T_1333)
node _T_1335 = or(UInt<1>(0h0), _T_1334)
node _T_1336 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_1337 = cvt(_T_1336)
node _T_1338 = and(_T_1337, asSInt(UInt<17>(0h101c0)))
node _T_1339 = asSInt(_T_1338)
node _T_1340 = eq(_T_1339, asSInt(UInt<1>(0h0)))
node _T_1341 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_1342 = cvt(_T_1341)
node _T_1343 = and(_T_1342, asSInt(UInt<29>(0h100001c0)))
node _T_1344 = asSInt(_T_1343)
node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0)))
node _T_1346 = or(_T_1340, _T_1345)
node _T_1347 = and(_T_1335, _T_1346)
node _T_1348 = or(UInt<1>(0h0), _T_1347)
node _T_1349 = and(UInt<1>(0h0), _T_1348)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_106
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(address_ok, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(legal_source, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1362 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_110
node _T_1366 = not(mask_1)
node _T_1367 = and(io.in.b.bits.mask, _T_1366)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_111
node _T_1372 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1372 :
node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1375 = and(_T_1373, _T_1374)
node _T_1376 = or(UInt<1>(0h0), _T_1375)
node _T_1377 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_1378 = cvt(_T_1377)
node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h101c0)))
node _T_1380 = asSInt(_T_1379)
node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0)))
node _T_1382 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_1383 = cvt(_T_1382)
node _T_1384 = and(_T_1383, asSInt(UInt<29>(0h100001c0)))
node _T_1385 = asSInt(_T_1384)
node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0)))
node _T_1387 = or(_T_1381, _T_1386)
node _T_1388 = and(_T_1376, _T_1387)
node _T_1389 = or(UInt<1>(0h0), _T_1388)
node _T_1390 = and(UInt<1>(0h0), _T_1389)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(address_ok, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(legal_source, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1403 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1404 = asUInt(reset)
node _T_1405 = eq(_T_1404, UInt<1>(0h0))
when _T_1405 :
node _T_1406 = eq(_T_1403, UInt<1>(0h0))
when _T_1406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1403, UInt<1>(0h1), "") : assert_116
node _T_1407 = eq(io.in.b.bits.mask, mask_1)
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_117
node _T_1411 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1411 :
node _T_1412 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1413 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1414 = and(_T_1412, _T_1413)
node _T_1415 = or(UInt<1>(0h0), _T_1414)
node _T_1416 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<17>(0h101c0)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_1422 = cvt(_T_1421)
node _T_1423 = and(_T_1422, asSInt(UInt<29>(0h100001c0)))
node _T_1424 = asSInt(_T_1423)
node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0)))
node _T_1426 = or(_T_1420, _T_1425)
node _T_1427 = and(_T_1415, _T_1426)
node _T_1428 = or(UInt<1>(0h0), _T_1427)
node _T_1429 = and(UInt<1>(0h0), _T_1428)
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(_T_1429, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1429, UInt<1>(0h1), "") : assert_118
node _T_1433 = asUInt(reset)
node _T_1434 = eq(_T_1433, UInt<1>(0h0))
when _T_1434 :
node _T_1435 = eq(address_ok, UInt<1>(0h0))
when _T_1435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(legal_source, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1439 = asUInt(reset)
node _T_1440 = eq(_T_1439, UInt<1>(0h0))
when _T_1440 :
node _T_1441 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1442 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1443 = asUInt(reset)
node _T_1444 = eq(_T_1443, UInt<1>(0h0))
when _T_1444 :
node _T_1445 = eq(_T_1442, UInt<1>(0h0))
when _T_1445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1442, UInt<1>(0h1), "") : assert_122
node _T_1446 = eq(io.in.b.bits.mask, mask_1)
node _T_1447 = asUInt(reset)
node _T_1448 = eq(_T_1447, UInt<1>(0h0))
when _T_1448 :
node _T_1449 = eq(_T_1446, UInt<1>(0h0))
when _T_1449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1446, UInt<1>(0h1), "") : assert_123
node _T_1450 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1450 :
node _T_1451 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1452 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1453 = and(_T_1451, _T_1452)
node _T_1454 = or(UInt<1>(0h0), _T_1453)
node _T_1455 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_1456 = cvt(_T_1455)
node _T_1457 = and(_T_1456, asSInt(UInt<17>(0h101c0)))
node _T_1458 = asSInt(_T_1457)
node _T_1459 = eq(_T_1458, asSInt(UInt<1>(0h0)))
node _T_1460 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_1461 = cvt(_T_1460)
node _T_1462 = and(_T_1461, asSInt(UInt<29>(0h100001c0)))
node _T_1463 = asSInt(_T_1462)
node _T_1464 = eq(_T_1463, asSInt(UInt<1>(0h0)))
node _T_1465 = or(_T_1459, _T_1464)
node _T_1466 = and(_T_1454, _T_1465)
node _T_1467 = or(UInt<1>(0h0), _T_1466)
node _T_1468 = and(UInt<1>(0h0), _T_1467)
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_124
node _T_1472 = asUInt(reset)
node _T_1473 = eq(_T_1472, UInt<1>(0h0))
when _T_1473 :
node _T_1474 = eq(address_ok, UInt<1>(0h0))
when _T_1474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1475 = asUInt(reset)
node _T_1476 = eq(_T_1475, UInt<1>(0h0))
when _T_1476 :
node _T_1477 = eq(legal_source, UInt<1>(0h0))
when _T_1477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1478 = asUInt(reset)
node _T_1479 = eq(_T_1478, UInt<1>(0h0))
when _T_1479 :
node _T_1480 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1481 = eq(io.in.b.bits.mask, mask_1)
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(_T_1481, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1481, UInt<1>(0h1), "") : assert_128
node _T_1485 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1489 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1490 = asUInt(reset)
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
when _T_1491 :
node _T_1492 = eq(_T_1489, UInt<1>(0h0))
when _T_1492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1489, UInt<1>(0h1), "") : assert_130
node _source_ok_T_78 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_79 = shr(io.in.c.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_85 = shr(io.in.c.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_91 = shr(io.in.c.bits.source, 2)
node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2))
node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_T_95 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_97 = shr(io.in.c.bits.source, 2)
node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3))
node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 2, 0)
node _source_ok_T_103 = shr(io.in.c.bits.source, 3)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<3>(0h7))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _source_ok_T_110 = eq(io.in.c.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE_2 : UInt<1>[8]
connect _source_ok_WIRE_2[0], _source_ok_T_78
connect _source_ok_WIRE_2[1], _source_ok_T_84
connect _source_ok_WIRE_2[2], _source_ok_T_90
connect _source_ok_WIRE_2[3], _source_ok_T_96
connect _source_ok_WIRE_2[4], _source_ok_T_102
connect _source_ok_WIRE_2[5], _source_ok_T_108
connect _source_ok_WIRE_2[6], _source_ok_T_109
connect _source_ok_WIRE_2[7], _source_ok_T_110
node _source_ok_T_111 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_2[2])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_2[3])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_2[4])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_2[5])
node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_2[6])
node source_ok_2 = or(_source_ok_T_116, _source_ok_WIRE_2[7])
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _T_1493 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _T_1494 = eq(_T_1493, UInt<1>(0h0))
node _T_1495 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1496 = cvt(_T_1495)
node _T_1497 = and(_T_1496, asSInt(UInt<1>(0h0)))
node _T_1498 = asSInt(_T_1497)
node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0)))
node _T_1500 = or(_T_1494, _T_1499)
node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_1501 = shr(io.in.c.bits.source, 2)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
node _T_1503 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1504 = and(_T_1502, _T_1503)
node _T_1505 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_1506 = and(_T_1504, _T_1505)
node _T_1507 = eq(_T_1506, UInt<1>(0h0))
node _T_1508 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1509 = cvt(_T_1508)
node _T_1510 = and(_T_1509, asSInt(UInt<1>(0h0)))
node _T_1511 = asSInt(_T_1510)
node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0)))
node _T_1513 = or(_T_1507, _T_1512)
node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_1514 = shr(io.in.c.bits.source, 2)
node _T_1515 = eq(_T_1514, UInt<1>(0h1))
node _T_1516 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_1517 = and(_T_1515, _T_1516)
node _T_1518 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_1519 = and(_T_1517, _T_1518)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
node _T_1521 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1522 = cvt(_T_1521)
node _T_1523 = and(_T_1522, asSInt(UInt<1>(0h0)))
node _T_1524 = asSInt(_T_1523)
node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0)))
node _T_1526 = or(_T_1520, _T_1525)
node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0)
node _T_1527 = shr(io.in.c.bits.source, 2)
node _T_1528 = eq(_T_1527, UInt<2>(0h2))
node _T_1529 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_1530 = and(_T_1528, _T_1529)
node _T_1531 = leq(uncommonBits_67, UInt<2>(0h3))
node _T_1532 = and(_T_1530, _T_1531)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
node _T_1534 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1535 = cvt(_T_1534)
node _T_1536 = and(_T_1535, asSInt(UInt<1>(0h0)))
node _T_1537 = asSInt(_T_1536)
node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0)))
node _T_1539 = or(_T_1533, _T_1538)
node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0)
node _T_1540 = shr(io.in.c.bits.source, 2)
node _T_1541 = eq(_T_1540, UInt<2>(0h3))
node _T_1542 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_1543 = and(_T_1541, _T_1542)
node _T_1544 = leq(uncommonBits_68, UInt<2>(0h3))
node _T_1545 = and(_T_1543, _T_1544)
node _T_1546 = eq(_T_1545, UInt<1>(0h0))
node _T_1547 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1548 = cvt(_T_1547)
node _T_1549 = and(_T_1548, asSInt(UInt<1>(0h0)))
node _T_1550 = asSInt(_T_1549)
node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0)))
node _T_1552 = or(_T_1546, _T_1551)
node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_1553 = shr(io.in.c.bits.source, 3)
node _T_1554 = eq(_T_1553, UInt<3>(0h4))
node _T_1555 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_1556 = and(_T_1554, _T_1555)
node _T_1557 = leq(uncommonBits_69, UInt<3>(0h7))
node _T_1558 = and(_T_1556, _T_1557)
node _T_1559 = eq(_T_1558, UInt<1>(0h0))
node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1561 = cvt(_T_1560)
node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0)))
node _T_1563 = asSInt(_T_1562)
node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0)))
node _T_1565 = or(_T_1559, _T_1564)
node _T_1566 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1567 = eq(_T_1566, UInt<1>(0h0))
node _T_1568 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1569 = cvt(_T_1568)
node _T_1570 = and(_T_1569, asSInt(UInt<1>(0h0)))
node _T_1571 = asSInt(_T_1570)
node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = or(_T_1567, _T_1572)
node _T_1574 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_1575 = eq(_T_1574, UInt<1>(0h0))
node _T_1576 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1577 = cvt(_T_1576)
node _T_1578 = and(_T_1577, asSInt(UInt<1>(0h0)))
node _T_1579 = asSInt(_T_1578)
node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0)))
node _T_1581 = or(_T_1575, _T_1580)
node _T_1582 = and(_T_1500, _T_1513)
node _T_1583 = and(_T_1582, _T_1526)
node _T_1584 = and(_T_1583, _T_1539)
node _T_1585 = and(_T_1584, _T_1552)
node _T_1586 = and(_T_1585, _T_1565)
node _T_1587 = and(_T_1586, _T_1573)
node _T_1588 = and(_T_1587, _T_1581)
node _T_1589 = asUInt(reset)
node _T_1590 = eq(_T_1589, UInt<1>(0h0))
when _T_1590 :
node _T_1591 = eq(_T_1588, UInt<1>(0h0))
when _T_1591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1588, UInt<1>(0h1), "") : assert_131
node _T_1592 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1592 :
node _T_1593 = asUInt(reset)
node _T_1594 = eq(_T_1593, UInt<1>(0h0))
when _T_1594 :
node _T_1595 = eq(address_ok_1, UInt<1>(0h0))
when _T_1595 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1596 = asUInt(reset)
node _T_1597 = eq(_T_1596, UInt<1>(0h0))
when _T_1597 :
node _T_1598 = eq(source_ok_2, UInt<1>(0h0))
when _T_1598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1599 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_134
node _T_1603 = asUInt(reset)
node _T_1604 = eq(_T_1603, UInt<1>(0h0))
when _T_1604 :
node _T_1605 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1606 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1607 = asUInt(reset)
node _T_1608 = eq(_T_1607, UInt<1>(0h0))
when _T_1608 :
node _T_1609 = eq(_T_1606, UInt<1>(0h0))
when _T_1609 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1606, UInt<1>(0h1), "") : assert_136
node _T_1610 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(_T_1610, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1610, UInt<1>(0h1), "") : assert_137
node _T_1614 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1614 :
node _T_1615 = asUInt(reset)
node _T_1616 = eq(_T_1615, UInt<1>(0h0))
when _T_1616 :
node _T_1617 = eq(address_ok_1, UInt<1>(0h0))
when _T_1617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1618 = asUInt(reset)
node _T_1619 = eq(_T_1618, UInt<1>(0h0))
when _T_1619 :
node _T_1620 = eq(source_ok_2, UInt<1>(0h0))
when _T_1620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1621 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_140
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1628 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_142
node _T_1632 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1632 :
node _T_1633 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1634 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1635 = and(_T_1633, _T_1634)
node _T_1636 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_1637 = shr(io.in.c.bits.source, 2)
node _T_1638 = eq(_T_1637, UInt<1>(0h0))
node _T_1639 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_1640 = and(_T_1638, _T_1639)
node _T_1641 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_1642 = and(_T_1640, _T_1641)
node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_1643 = shr(io.in.c.bits.source, 2)
node _T_1644 = eq(_T_1643, UInt<1>(0h1))
node _T_1645 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_1646 = and(_T_1644, _T_1645)
node _T_1647 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_1648 = and(_T_1646, _T_1647)
node _uncommonBits_T_72 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_1649 = shr(io.in.c.bits.source, 2)
node _T_1650 = eq(_T_1649, UInt<2>(0h2))
node _T_1651 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_1652 = and(_T_1650, _T_1651)
node _T_1653 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_1654 = and(_T_1652, _T_1653)
node _uncommonBits_T_73 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_1655 = shr(io.in.c.bits.source, 2)
node _T_1656 = eq(_T_1655, UInt<2>(0h3))
node _T_1657 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_1658 = and(_T_1656, _T_1657)
node _T_1659 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_1660 = and(_T_1658, _T_1659)
node _uncommonBits_T_74 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_1661 = shr(io.in.c.bits.source, 3)
node _T_1662 = eq(_T_1661, UInt<3>(0h4))
node _T_1663 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_1664 = and(_T_1662, _T_1663)
node _T_1665 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_1666 = and(_T_1664, _T_1665)
node _T_1667 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1668 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_1669 = or(_T_1636, _T_1642)
node _T_1670 = or(_T_1669, _T_1648)
node _T_1671 = or(_T_1670, _T_1654)
node _T_1672 = or(_T_1671, _T_1660)
node _T_1673 = or(_T_1672, _T_1666)
node _T_1674 = or(_T_1673, _T_1667)
node _T_1675 = or(_T_1674, _T_1668)
node _T_1676 = and(_T_1635, _T_1675)
node _T_1677 = or(UInt<1>(0h0), _T_1676)
node _T_1678 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1679 = or(UInt<1>(0h0), _T_1678)
node _T_1680 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_1681 = cvt(_T_1680)
node _T_1682 = and(_T_1681, asSInt(UInt<17>(0h101c0)))
node _T_1683 = asSInt(_T_1682)
node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0)))
node _T_1685 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_1686 = cvt(_T_1685)
node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h100001c0)))
node _T_1688 = asSInt(_T_1687)
node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0)))
node _T_1690 = or(_T_1684, _T_1689)
node _T_1691 = and(_T_1679, _T_1690)
node _T_1692 = or(UInt<1>(0h0), _T_1691)
node _T_1693 = and(_T_1677, _T_1692)
node _T_1694 = asUInt(reset)
node _T_1695 = eq(_T_1694, UInt<1>(0h0))
when _T_1695 :
node _T_1696 = eq(_T_1693, UInt<1>(0h0))
when _T_1696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1693, UInt<1>(0h1), "") : assert_143
node _T_1697 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_75 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_1698 = shr(io.in.c.bits.source, 2)
node _T_1699 = eq(_T_1698, UInt<1>(0h0))
node _T_1700 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1701 = and(_T_1699, _T_1700)
node _T_1702 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_1703 = and(_T_1701, _T_1702)
node _uncommonBits_T_76 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 1, 0)
node _T_1704 = shr(io.in.c.bits.source, 2)
node _T_1705 = eq(_T_1704, UInt<1>(0h1))
node _T_1706 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1707 = and(_T_1705, _T_1706)
node _T_1708 = leq(uncommonBits_76, UInt<2>(0h3))
node _T_1709 = and(_T_1707, _T_1708)
node _uncommonBits_T_77 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0)
node _T_1710 = shr(io.in.c.bits.source, 2)
node _T_1711 = eq(_T_1710, UInt<2>(0h2))
node _T_1712 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_1713 = and(_T_1711, _T_1712)
node _T_1714 = leq(uncommonBits_77, UInt<2>(0h3))
node _T_1715 = and(_T_1713, _T_1714)
node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0)
node _T_1716 = shr(io.in.c.bits.source, 2)
node _T_1717 = eq(_T_1716, UInt<2>(0h3))
node _T_1718 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_1719 = and(_T_1717, _T_1718)
node _T_1720 = leq(uncommonBits_78, UInt<2>(0h3))
node _T_1721 = and(_T_1719, _T_1720)
node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 2, 0)
node _T_1722 = shr(io.in.c.bits.source, 3)
node _T_1723 = eq(_T_1722, UInt<3>(0h4))
node _T_1724 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_1725 = and(_T_1723, _T_1724)
node _T_1726 = leq(uncommonBits_79, UInt<3>(0h7))
node _T_1727 = and(_T_1725, _T_1726)
node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1729 = eq(io.in.c.bits.source, UInt<6>(0h2a))
wire _WIRE_6 : UInt<1>[8]
connect _WIRE_6[0], _T_1697
connect _WIRE_6[1], _T_1703
connect _WIRE_6[2], _T_1709
connect _WIRE_6[3], _T_1715
connect _WIRE_6[4], _T_1721
connect _WIRE_6[5], _T_1727
connect _WIRE_6[6], _T_1728
connect _WIRE_6[7], _T_1729
node _T_1730 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1731 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1732 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1733 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1734 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1735 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1736 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1737 = mux(_WIRE_6[6], _T_1730, UInt<1>(0h0))
node _T_1738 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1739 = or(_T_1731, _T_1732)
node _T_1740 = or(_T_1739, _T_1733)
node _T_1741 = or(_T_1740, _T_1734)
node _T_1742 = or(_T_1741, _T_1735)
node _T_1743 = or(_T_1742, _T_1736)
node _T_1744 = or(_T_1743, _T_1737)
node _T_1745 = or(_T_1744, _T_1738)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1745
node _T_1746 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1747 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1748 = and(_T_1746, _T_1747)
node _T_1749 = or(UInt<1>(0h0), _T_1748)
node _T_1750 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_1751 = cvt(_T_1750)
node _T_1752 = and(_T_1751, asSInt(UInt<17>(0h101c0)))
node _T_1753 = asSInt(_T_1752)
node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0)))
node _T_1755 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_1756 = cvt(_T_1755)
node _T_1757 = and(_T_1756, asSInt(UInt<29>(0h100001c0)))
node _T_1758 = asSInt(_T_1757)
node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0)))
node _T_1760 = or(_T_1754, _T_1759)
node _T_1761 = and(_T_1749, _T_1760)
node _T_1762 = or(UInt<1>(0h0), _T_1761)
node _T_1763 = and(_WIRE_7, _T_1762)
node _T_1764 = asUInt(reset)
node _T_1765 = eq(_T_1764, UInt<1>(0h0))
when _T_1765 :
node _T_1766 = eq(_T_1763, UInt<1>(0h0))
when _T_1766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1763, UInt<1>(0h1), "") : assert_144
node _T_1767 = asUInt(reset)
node _T_1768 = eq(_T_1767, UInt<1>(0h0))
when _T_1768 :
node _T_1769 = eq(source_ok_2, UInt<1>(0h0))
when _T_1769 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1770 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1771 = asUInt(reset)
node _T_1772 = eq(_T_1771, UInt<1>(0h0))
when _T_1772 :
node _T_1773 = eq(_T_1770, UInt<1>(0h0))
when _T_1773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1770, UInt<1>(0h1), "") : assert_146
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1777 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1778 = asUInt(reset)
node _T_1779 = eq(_T_1778, UInt<1>(0h0))
when _T_1779 :
node _T_1780 = eq(_T_1777, UInt<1>(0h0))
when _T_1780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1777, UInt<1>(0h1), "") : assert_148
node _T_1781 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(_T_1781, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1781, UInt<1>(0h1), "") : assert_149
node _T_1785 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1785 :
node _T_1786 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1787 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1788 = and(_T_1786, _T_1787)
node _T_1789 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0)
node _T_1790 = shr(io.in.c.bits.source, 2)
node _T_1791 = eq(_T_1790, UInt<1>(0h0))
node _T_1792 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_1793 = and(_T_1791, _T_1792)
node _T_1794 = leq(uncommonBits_80, UInt<2>(0h3))
node _T_1795 = and(_T_1793, _T_1794)
node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0)
node _T_1796 = shr(io.in.c.bits.source, 2)
node _T_1797 = eq(_T_1796, UInt<1>(0h1))
node _T_1798 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_1799 = and(_T_1797, _T_1798)
node _T_1800 = leq(uncommonBits_81, UInt<2>(0h3))
node _T_1801 = and(_T_1799, _T_1800)
node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 1, 0)
node _T_1802 = shr(io.in.c.bits.source, 2)
node _T_1803 = eq(_T_1802, UInt<2>(0h2))
node _T_1804 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_1805 = and(_T_1803, _T_1804)
node _T_1806 = leq(uncommonBits_82, UInt<2>(0h3))
node _T_1807 = and(_T_1805, _T_1806)
node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 1, 0)
node _T_1808 = shr(io.in.c.bits.source, 2)
node _T_1809 = eq(_T_1808, UInt<2>(0h3))
node _T_1810 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_1811 = and(_T_1809, _T_1810)
node _T_1812 = leq(uncommonBits_83, UInt<2>(0h3))
node _T_1813 = and(_T_1811, _T_1812)
node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 2, 0)
node _T_1814 = shr(io.in.c.bits.source, 3)
node _T_1815 = eq(_T_1814, UInt<3>(0h4))
node _T_1816 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1817 = and(_T_1815, _T_1816)
node _T_1818 = leq(uncommonBits_84, UInt<3>(0h7))
node _T_1819 = and(_T_1817, _T_1818)
node _T_1820 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1821 = eq(io.in.c.bits.source, UInt<6>(0h2a))
node _T_1822 = or(_T_1789, _T_1795)
node _T_1823 = or(_T_1822, _T_1801)
node _T_1824 = or(_T_1823, _T_1807)
node _T_1825 = or(_T_1824, _T_1813)
node _T_1826 = or(_T_1825, _T_1819)
node _T_1827 = or(_T_1826, _T_1820)
node _T_1828 = or(_T_1827, _T_1821)
node _T_1829 = and(_T_1788, _T_1828)
node _T_1830 = or(UInt<1>(0h0), _T_1829)
node _T_1831 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1832 = or(UInt<1>(0h0), _T_1831)
node _T_1833 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_1834 = cvt(_T_1833)
node _T_1835 = and(_T_1834, asSInt(UInt<17>(0h101c0)))
node _T_1836 = asSInt(_T_1835)
node _T_1837 = eq(_T_1836, asSInt(UInt<1>(0h0)))
node _T_1838 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_1839 = cvt(_T_1838)
node _T_1840 = and(_T_1839, asSInt(UInt<29>(0h100001c0)))
node _T_1841 = asSInt(_T_1840)
node _T_1842 = eq(_T_1841, asSInt(UInt<1>(0h0)))
node _T_1843 = or(_T_1837, _T_1842)
node _T_1844 = and(_T_1832, _T_1843)
node _T_1845 = or(UInt<1>(0h0), _T_1844)
node _T_1846 = and(_T_1830, _T_1845)
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(_T_1846, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1846, UInt<1>(0h1), "") : assert_150
node _T_1850 = eq(io.in.c.bits.source, UInt<5>(0h10))
node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1851 = shr(io.in.c.bits.source, 2)
node _T_1852 = eq(_T_1851, UInt<1>(0h0))
node _T_1853 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1854 = and(_T_1852, _T_1853)
node _T_1855 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1856 = and(_T_1854, _T_1855)
node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1857 = shr(io.in.c.bits.source, 2)
node _T_1858 = eq(_T_1857, UInt<1>(0h1))
node _T_1859 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1860 = and(_T_1858, _T_1859)
node _T_1861 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1862 = and(_T_1860, _T_1861)
node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1863 = shr(io.in.c.bits.source, 2)
node _T_1864 = eq(_T_1863, UInt<2>(0h2))
node _T_1865 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1866 = and(_T_1864, _T_1865)
node _T_1867 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1868 = and(_T_1866, _T_1867)
node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0)
node _T_1869 = shr(io.in.c.bits.source, 2)
node _T_1870 = eq(_T_1869, UInt<2>(0h3))
node _T_1871 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1872 = and(_T_1870, _T_1871)
node _T_1873 = leq(uncommonBits_88, UInt<2>(0h3))
node _T_1874 = and(_T_1872, _T_1873)
node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0)
node _T_1875 = shr(io.in.c.bits.source, 3)
node _T_1876 = eq(_T_1875, UInt<3>(0h4))
node _T_1877 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1878 = and(_T_1876, _T_1877)
node _T_1879 = leq(uncommonBits_89, UInt<3>(0h7))
node _T_1880 = and(_T_1878, _T_1879)
node _T_1881 = eq(io.in.c.bits.source, UInt<6>(0h28))
node _T_1882 = eq(io.in.c.bits.source, UInt<6>(0h2a))
wire _WIRE_8 : UInt<1>[8]
connect _WIRE_8[0], _T_1850
connect _WIRE_8[1], _T_1856
connect _WIRE_8[2], _T_1862
connect _WIRE_8[3], _T_1868
connect _WIRE_8[4], _T_1874
connect _WIRE_8[5], _T_1880
connect _WIRE_8[6], _T_1881
connect _WIRE_8[7], _T_1882
node _T_1883 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1884 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1885 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1886 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1887 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1888 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1889 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1890 = mux(_WIRE_8[6], _T_1883, UInt<1>(0h0))
node _T_1891 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1892 = or(_T_1884, _T_1885)
node _T_1893 = or(_T_1892, _T_1886)
node _T_1894 = or(_T_1893, _T_1887)
node _T_1895 = or(_T_1894, _T_1888)
node _T_1896 = or(_T_1895, _T_1889)
node _T_1897 = or(_T_1896, _T_1890)
node _T_1898 = or(_T_1897, _T_1891)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_1898
node _T_1899 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1900 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1901 = and(_T_1899, _T_1900)
node _T_1902 = or(UInt<1>(0h0), _T_1901)
node _T_1903 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_1904 = cvt(_T_1903)
node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h101c0)))
node _T_1906 = asSInt(_T_1905)
node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0)))
node _T_1908 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_1909 = cvt(_T_1908)
node _T_1910 = and(_T_1909, asSInt(UInt<29>(0h100001c0)))
node _T_1911 = asSInt(_T_1910)
node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0)))
node _T_1913 = or(_T_1907, _T_1912)
node _T_1914 = and(_T_1902, _T_1913)
node _T_1915 = or(UInt<1>(0h0), _T_1914)
node _T_1916 = and(_WIRE_9, _T_1915)
node _T_1917 = asUInt(reset)
node _T_1918 = eq(_T_1917, UInt<1>(0h0))
when _T_1918 :
node _T_1919 = eq(_T_1916, UInt<1>(0h0))
when _T_1919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_1916, UInt<1>(0h1), "") : assert_151
node _T_1920 = asUInt(reset)
node _T_1921 = eq(_T_1920, UInt<1>(0h0))
when _T_1921 :
node _T_1922 = eq(source_ok_2, UInt<1>(0h0))
when _T_1922 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_1923 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1924 = asUInt(reset)
node _T_1925 = eq(_T_1924, UInt<1>(0h0))
when _T_1925 :
node _T_1926 = eq(_T_1923, UInt<1>(0h0))
when _T_1926 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_1923, UInt<1>(0h1), "") : assert_153
node _T_1927 = asUInt(reset)
node _T_1928 = eq(_T_1927, UInt<1>(0h0))
when _T_1928 :
node _T_1929 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1929 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_1930 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1931 = asUInt(reset)
node _T_1932 = eq(_T_1931, UInt<1>(0h0))
when _T_1932 :
node _T_1933 = eq(_T_1930, UInt<1>(0h0))
when _T_1933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_1930, UInt<1>(0h1), "") : assert_155
node _T_1934 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_1934 :
node _T_1935 = asUInt(reset)
node _T_1936 = eq(_T_1935, UInt<1>(0h0))
when _T_1936 :
node _T_1937 = eq(address_ok_1, UInt<1>(0h0))
when _T_1937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_1938 = asUInt(reset)
node _T_1939 = eq(_T_1938, UInt<1>(0h0))
when _T_1939 :
node _T_1940 = eq(source_ok_2, UInt<1>(0h0))
when _T_1940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_1941 = asUInt(reset)
node _T_1942 = eq(_T_1941, UInt<1>(0h0))
when _T_1942 :
node _T_1943 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_1944 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1945 = asUInt(reset)
node _T_1946 = eq(_T_1945, UInt<1>(0h0))
when _T_1946 :
node _T_1947 = eq(_T_1944, UInt<1>(0h0))
when _T_1947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_1944, UInt<1>(0h1), "") : assert_159
node _T_1948 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1949 = asUInt(reset)
node _T_1950 = eq(_T_1949, UInt<1>(0h0))
when _T_1950 :
node _T_1951 = eq(_T_1948, UInt<1>(0h0))
when _T_1951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_1948, UInt<1>(0h1), "") : assert_160
node _T_1952 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_1952 :
node _T_1953 = asUInt(reset)
node _T_1954 = eq(_T_1953, UInt<1>(0h0))
when _T_1954 :
node _T_1955 = eq(address_ok_1, UInt<1>(0h0))
when _T_1955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_1956 = asUInt(reset)
node _T_1957 = eq(_T_1956, UInt<1>(0h0))
when _T_1957 :
node _T_1958 = eq(source_ok_2, UInt<1>(0h0))
when _T_1958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_1959 = asUInt(reset)
node _T_1960 = eq(_T_1959, UInt<1>(0h0))
when _T_1960 :
node _T_1961 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_1962 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1963 = asUInt(reset)
node _T_1964 = eq(_T_1963, UInt<1>(0h0))
when _T_1964 :
node _T_1965 = eq(_T_1962, UInt<1>(0h0))
when _T_1965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_1962, UInt<1>(0h1), "") : assert_164
node _T_1966 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_1966 :
node _T_1967 = asUInt(reset)
node _T_1968 = eq(_T_1967, UInt<1>(0h0))
when _T_1968 :
node _T_1969 = eq(address_ok_1, UInt<1>(0h0))
when _T_1969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_1970 = asUInt(reset)
node _T_1971 = eq(_T_1970, UInt<1>(0h0))
when _T_1971 :
node _T_1972 = eq(source_ok_2, UInt<1>(0h0))
when _T_1972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_1973 = asUInt(reset)
node _T_1974 = eq(_T_1973, UInt<1>(0h0))
when _T_1974 :
node _T_1975 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_1976 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1977 = asUInt(reset)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
when _T_1978 :
node _T_1979 = eq(_T_1976, UInt<1>(0h0))
when _T_1979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_1976, UInt<1>(0h1), "") : assert_168
node _T_1980 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1981 = asUInt(reset)
node _T_1982 = eq(_T_1981, UInt<1>(0h0))
when _T_1982 :
node _T_1983 = eq(_T_1980, UInt<1>(0h0))
when _T_1983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_1980, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc))
node _T_1984 = asUInt(reset)
node _T_1985 = eq(_T_1984, UInt<1>(0h0))
when _T_1985 :
node _T_1986 = eq(sink_ok_1, UInt<1>(0h0))
when _T_1986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1987 = eq(a_first, UInt<1>(0h0))
node _T_1988 = and(io.in.a.valid, _T_1987)
when _T_1988 :
node _T_1989 = eq(io.in.a.bits.opcode, opcode)
node _T_1990 = asUInt(reset)
node _T_1991 = eq(_T_1990, UInt<1>(0h0))
when _T_1991 :
node _T_1992 = eq(_T_1989, UInt<1>(0h0))
when _T_1992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_1989, UInt<1>(0h1), "") : assert_171
node _T_1993 = eq(io.in.a.bits.param, param)
node _T_1994 = asUInt(reset)
node _T_1995 = eq(_T_1994, UInt<1>(0h0))
when _T_1995 :
node _T_1996 = eq(_T_1993, UInt<1>(0h0))
when _T_1996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_1993, UInt<1>(0h1), "") : assert_172
node _T_1997 = eq(io.in.a.bits.size, size)
node _T_1998 = asUInt(reset)
node _T_1999 = eq(_T_1998, UInt<1>(0h0))
when _T_1999 :
node _T_2000 = eq(_T_1997, UInt<1>(0h0))
when _T_2000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_1997, UInt<1>(0h1), "") : assert_173
node _T_2001 = eq(io.in.a.bits.source, source)
node _T_2002 = asUInt(reset)
node _T_2003 = eq(_T_2002, UInt<1>(0h0))
when _T_2003 :
node _T_2004 = eq(_T_2001, UInt<1>(0h0))
when _T_2004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2001, UInt<1>(0h1), "") : assert_174
node _T_2005 = eq(io.in.a.bits.address, address)
node _T_2006 = asUInt(reset)
node _T_2007 = eq(_T_2006, UInt<1>(0h0))
when _T_2007 :
node _T_2008 = eq(_T_2005, UInt<1>(0h0))
when _T_2008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2005, UInt<1>(0h1), "") : assert_175
node _T_2009 = and(io.in.a.ready, io.in.a.valid)
node _T_2010 = and(_T_2009, a_first)
when _T_2010 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2011 = eq(d_first, UInt<1>(0h0))
node _T_2012 = and(io.in.d.valid, _T_2011)
when _T_2012 :
node _T_2013 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2014 = asUInt(reset)
node _T_2015 = eq(_T_2014, UInt<1>(0h0))
when _T_2015 :
node _T_2016 = eq(_T_2013, UInt<1>(0h0))
when _T_2016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2013, UInt<1>(0h1), "") : assert_176
node _T_2017 = eq(io.in.d.bits.param, param_1)
node _T_2018 = asUInt(reset)
node _T_2019 = eq(_T_2018, UInt<1>(0h0))
when _T_2019 :
node _T_2020 = eq(_T_2017, UInt<1>(0h0))
when _T_2020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2017, UInt<1>(0h1), "") : assert_177
node _T_2021 = eq(io.in.d.bits.size, size_1)
node _T_2022 = asUInt(reset)
node _T_2023 = eq(_T_2022, UInt<1>(0h0))
when _T_2023 :
node _T_2024 = eq(_T_2021, UInt<1>(0h0))
when _T_2024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2021, UInt<1>(0h1), "") : assert_178
node _T_2025 = eq(io.in.d.bits.source, source_1)
node _T_2026 = asUInt(reset)
node _T_2027 = eq(_T_2026, UInt<1>(0h0))
when _T_2027 :
node _T_2028 = eq(_T_2025, UInt<1>(0h0))
when _T_2028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2025, UInt<1>(0h1), "") : assert_179
node _T_2029 = eq(io.in.d.bits.sink, sink)
node _T_2030 = asUInt(reset)
node _T_2031 = eq(_T_2030, UInt<1>(0h0))
when _T_2031 :
node _T_2032 = eq(_T_2029, UInt<1>(0h0))
when _T_2032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2029, UInt<1>(0h1), "") : assert_180
node _T_2033 = eq(io.in.d.bits.denied, denied)
node _T_2034 = asUInt(reset)
node _T_2035 = eq(_T_2034, UInt<1>(0h0))
when _T_2035 :
node _T_2036 = eq(_T_2033, UInt<1>(0h0))
when _T_2036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2033, UInt<1>(0h1), "") : assert_181
node _T_2037 = and(io.in.d.ready, io.in.d.valid)
node _T_2038 = and(_T_2037, d_first)
when _T_2038 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2039 = eq(b_first, UInt<1>(0h0))
node _T_2040 = and(io.in.b.valid, _T_2039)
when _T_2040 :
node _T_2041 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2042 = asUInt(reset)
node _T_2043 = eq(_T_2042, UInt<1>(0h0))
when _T_2043 :
node _T_2044 = eq(_T_2041, UInt<1>(0h0))
when _T_2044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2041, UInt<1>(0h1), "") : assert_182
node _T_2045 = eq(io.in.b.bits.param, param_2)
node _T_2046 = asUInt(reset)
node _T_2047 = eq(_T_2046, UInt<1>(0h0))
when _T_2047 :
node _T_2048 = eq(_T_2045, UInt<1>(0h0))
when _T_2048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2045, UInt<1>(0h1), "") : assert_183
node _T_2049 = eq(io.in.b.bits.size, size_2)
node _T_2050 = asUInt(reset)
node _T_2051 = eq(_T_2050, UInt<1>(0h0))
when _T_2051 :
node _T_2052 = eq(_T_2049, UInt<1>(0h0))
when _T_2052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2049, UInt<1>(0h1), "") : assert_184
node _T_2053 = eq(io.in.b.bits.source, source_2)
node _T_2054 = asUInt(reset)
node _T_2055 = eq(_T_2054, UInt<1>(0h0))
when _T_2055 :
node _T_2056 = eq(_T_2053, UInt<1>(0h0))
when _T_2056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2053, UInt<1>(0h1), "") : assert_185
node _T_2057 = eq(io.in.b.bits.address, address_1)
node _T_2058 = asUInt(reset)
node _T_2059 = eq(_T_2058, UInt<1>(0h0))
when _T_2059 :
node _T_2060 = eq(_T_2057, UInt<1>(0h0))
when _T_2060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2057, UInt<1>(0h1), "") : assert_186
node _T_2061 = and(io.in.b.ready, io.in.b.valid)
node _T_2062 = and(_T_2061, b_first)
when _T_2062 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2063 = eq(c_first, UInt<1>(0h0))
node _T_2064 = and(io.in.c.valid, _T_2063)
when _T_2064 :
node _T_2065 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2066 = asUInt(reset)
node _T_2067 = eq(_T_2066, UInt<1>(0h0))
when _T_2067 :
node _T_2068 = eq(_T_2065, UInt<1>(0h0))
when _T_2068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2065, UInt<1>(0h1), "") : assert_187
node _T_2069 = eq(io.in.c.bits.param, param_3)
node _T_2070 = asUInt(reset)
node _T_2071 = eq(_T_2070, UInt<1>(0h0))
when _T_2071 :
node _T_2072 = eq(_T_2069, UInt<1>(0h0))
when _T_2072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2069, UInt<1>(0h1), "") : assert_188
node _T_2073 = eq(io.in.c.bits.size, size_3)
node _T_2074 = asUInt(reset)
node _T_2075 = eq(_T_2074, UInt<1>(0h0))
when _T_2075 :
node _T_2076 = eq(_T_2073, UInt<1>(0h0))
when _T_2076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2073, UInt<1>(0h1), "") : assert_189
node _T_2077 = eq(io.in.c.bits.source, source_3)
node _T_2078 = asUInt(reset)
node _T_2079 = eq(_T_2078, UInt<1>(0h0))
when _T_2079 :
node _T_2080 = eq(_T_2077, UInt<1>(0h0))
when _T_2080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2077, UInt<1>(0h1), "") : assert_190
node _T_2081 = eq(io.in.c.bits.address, address_2)
node _T_2082 = asUInt(reset)
node _T_2083 = eq(_T_2082, UInt<1>(0h0))
when _T_2083 :
node _T_2084 = eq(_T_2081, UInt<1>(0h0))
when _T_2084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2081, UInt<1>(0h1), "") : assert_191
node _T_2085 = and(io.in.c.ready, io.in.c.valid)
node _T_2086 = and(_T_2085, c_first)
when _T_2086 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0)
regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0)
regreset inflight_sizes : UInt<172>, clock, reset, UInt<172>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<43>
connect a_set, UInt<43>(0h0)
wire a_set_wo_ready : UInt<43>
connect a_set_wo_ready, UInt<43>(0h0)
wire a_opcodes_set : UInt<172>
connect a_opcodes_set, UInt<172>(0h0)
wire a_sizes_set : UInt<172>
connect a_sizes_set, UInt<172>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_2087 = and(io.in.a.valid, a_first_1)
node _T_2088 = and(_T_2087, UInt<1>(0h1))
when _T_2088 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2089 = and(io.in.a.ready, io.in.a.valid)
node _T_2090 = and(_T_2089, a_first_1)
node _T_2091 = and(_T_2090, UInt<1>(0h1))
when _T_2091 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2092 = dshr(inflight, io.in.a.bits.source)
node _T_2093 = bits(_T_2092, 0, 0)
node _T_2094 = eq(_T_2093, UInt<1>(0h0))
node _T_2095 = asUInt(reset)
node _T_2096 = eq(_T_2095, UInt<1>(0h0))
when _T_2096 :
node _T_2097 = eq(_T_2094, UInt<1>(0h0))
when _T_2097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2094, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<43>
connect d_clr, UInt<43>(0h0)
wire d_clr_wo_ready : UInt<43>
connect d_clr_wo_ready, UInt<43>(0h0)
wire d_opcodes_clr : UInt<172>
connect d_opcodes_clr, UInt<172>(0h0)
wire d_sizes_clr : UInt<172>
connect d_sizes_clr, UInt<172>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2098 = and(io.in.d.valid, d_first_1)
node _T_2099 = and(_T_2098, UInt<1>(0h1))
node _T_2100 = eq(d_release_ack, UInt<1>(0h0))
node _T_2101 = and(_T_2099, _T_2100)
when _T_2101 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2102 = and(io.in.d.ready, io.in.d.valid)
node _T_2103 = and(_T_2102, d_first_1)
node _T_2104 = and(_T_2103, UInt<1>(0h1))
node _T_2105 = eq(d_release_ack, UInt<1>(0h0))
node _T_2106 = and(_T_2104, _T_2105)
when _T_2106 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2107 = and(io.in.d.valid, d_first_1)
node _T_2108 = and(_T_2107, UInt<1>(0h1))
node _T_2109 = eq(d_release_ack, UInt<1>(0h0))
node _T_2110 = and(_T_2108, _T_2109)
when _T_2110 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2111 = dshr(inflight, io.in.d.bits.source)
node _T_2112 = bits(_T_2111, 0, 0)
node _T_2113 = or(_T_2112, same_cycle_resp)
node _T_2114 = asUInt(reset)
node _T_2115 = eq(_T_2114, UInt<1>(0h0))
when _T_2115 :
node _T_2116 = eq(_T_2113, UInt<1>(0h0))
when _T_2116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2113, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2119 = or(_T_2117, _T_2118)
node _T_2120 = asUInt(reset)
node _T_2121 = eq(_T_2120, UInt<1>(0h0))
when _T_2121 :
node _T_2122 = eq(_T_2119, UInt<1>(0h0))
when _T_2122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2119, UInt<1>(0h1), "") : assert_194
node _T_2123 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2124 = asUInt(reset)
node _T_2125 = eq(_T_2124, UInt<1>(0h0))
when _T_2125 :
node _T_2126 = eq(_T_2123, UInt<1>(0h0))
when _T_2126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2123, UInt<1>(0h1), "") : assert_195
else :
node _T_2127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2129 = or(_T_2127, _T_2128)
node _T_2130 = asUInt(reset)
node _T_2131 = eq(_T_2130, UInt<1>(0h0))
when _T_2131 :
node _T_2132 = eq(_T_2129, UInt<1>(0h0))
when _T_2132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2129, UInt<1>(0h1), "") : assert_196
node _T_2133 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2134 = asUInt(reset)
node _T_2135 = eq(_T_2134, UInt<1>(0h0))
when _T_2135 :
node _T_2136 = eq(_T_2133, UInt<1>(0h0))
when _T_2136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2133, UInt<1>(0h1), "") : assert_197
node _T_2137 = and(io.in.d.valid, d_first_1)
node _T_2138 = and(_T_2137, a_first_1)
node _T_2139 = and(_T_2138, io.in.a.valid)
node _T_2140 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2141 = and(_T_2139, _T_2140)
node _T_2142 = eq(d_release_ack, UInt<1>(0h0))
node _T_2143 = and(_T_2141, _T_2142)
when _T_2143 :
node _T_2144 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2145 = or(_T_2144, io.in.a.ready)
node _T_2146 = asUInt(reset)
node _T_2147 = eq(_T_2146, UInt<1>(0h0))
when _T_2147 :
node _T_2148 = eq(_T_2145, UInt<1>(0h0))
when _T_2148 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2145, UInt<1>(0h1), "") : assert_198
node _T_2149 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2150 = orr(a_set_wo_ready)
node _T_2151 = eq(_T_2150, UInt<1>(0h0))
node _T_2152 = or(_T_2149, _T_2151)
node _T_2153 = asUInt(reset)
node _T_2154 = eq(_T_2153, UInt<1>(0h0))
when _T_2154 :
node _T_2155 = eq(_T_2152, UInt<1>(0h0))
when _T_2155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2152, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_130
node _T_2156 = orr(inflight)
node _T_2157 = eq(_T_2156, UInt<1>(0h0))
node _T_2158 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2159 = or(_T_2157, _T_2158)
node _T_2160 = lt(watchdog, plusarg_reader.out)
node _T_2161 = or(_T_2159, _T_2160)
node _T_2162 = asUInt(reset)
node _T_2163 = eq(_T_2162, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = eq(_T_2161, UInt<1>(0h0))
when _T_2164 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2161, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2165 = and(io.in.a.ready, io.in.a.valid)
node _T_2166 = and(io.in.d.ready, io.in.d.valid)
node _T_2167 = or(_T_2165, _T_2166)
when _T_2167 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0)
regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0)
regreset inflight_sizes_1 : UInt<172>, clock, reset, UInt<172>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<43>
connect c_set, UInt<43>(0h0)
wire c_set_wo_ready : UInt<43>
connect c_set_wo_ready, UInt<43>(0h0)
wire c_opcodes_set : UInt<172>
connect c_opcodes_set, UInt<172>(0h0)
wire c_sizes_set : UInt<172>
connect c_sizes_set, UInt<172>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_2168 = and(io.in.c.valid, c_first_1)
node _T_2169 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2170 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2171 = and(_T_2169, _T_2170)
node _T_2172 = and(_T_2168, _T_2171)
when _T_2172 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2173 = and(io.in.c.ready, io.in.c.valid)
node _T_2174 = and(_T_2173, c_first_1)
node _T_2175 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2176 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2177 = and(_T_2175, _T_2176)
node _T_2178 = and(_T_2174, _T_2177)
when _T_2178 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2179 = dshr(inflight_1, io.in.c.bits.source)
node _T_2180 = bits(_T_2179, 0, 0)
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
node _T_2182 = asUInt(reset)
node _T_2183 = eq(_T_2182, UInt<1>(0h0))
when _T_2183 :
node _T_2184 = eq(_T_2181, UInt<1>(0h0))
when _T_2184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2181, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<43>
connect d_clr_1, UInt<43>(0h0)
wire d_clr_wo_ready_1 : UInt<43>
connect d_clr_wo_ready_1, UInt<43>(0h0)
wire d_opcodes_clr_1 : UInt<172>
connect d_opcodes_clr_1, UInt<172>(0h0)
wire d_sizes_clr_1 : UInt<172>
connect d_sizes_clr_1, UInt<172>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2185 = and(io.in.d.valid, d_first_2)
node _T_2186 = and(_T_2185, UInt<1>(0h1))
node _T_2187 = and(_T_2186, d_release_ack_1)
when _T_2187 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2188 = and(io.in.d.ready, io.in.d.valid)
node _T_2189 = and(_T_2188, d_first_2)
node _T_2190 = and(_T_2189, UInt<1>(0h1))
node _T_2191 = and(_T_2190, d_release_ack_1)
when _T_2191 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2192 = and(io.in.d.valid, d_first_2)
node _T_2193 = and(_T_2192, UInt<1>(0h1))
node _T_2194 = and(_T_2193, d_release_ack_1)
when _T_2194 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2195 = dshr(inflight_1, io.in.d.bits.source)
node _T_2196 = bits(_T_2195, 0, 0)
node _T_2197 = or(_T_2196, same_cycle_resp_1)
node _T_2198 = asUInt(reset)
node _T_2199 = eq(_T_2198, UInt<1>(0h0))
when _T_2199 :
node _T_2200 = eq(_T_2197, UInt<1>(0h0))
when _T_2200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2197, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2201 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2202 = asUInt(reset)
node _T_2203 = eq(_T_2202, UInt<1>(0h0))
when _T_2203 :
node _T_2204 = eq(_T_2201, UInt<1>(0h0))
when _T_2204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2201, UInt<1>(0h1), "") : assert_203
else :
node _T_2205 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
node _T_2208 = eq(_T_2205, UInt<1>(0h0))
when _T_2208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2205, UInt<1>(0h1), "") : assert_204
node _T_2209 = and(io.in.d.valid, d_first_2)
node _T_2210 = and(_T_2209, c_first_1)
node _T_2211 = and(_T_2210, io.in.c.valid)
node _T_2212 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2213 = and(_T_2211, _T_2212)
node _T_2214 = and(_T_2213, d_release_ack_1)
node _T_2215 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2216 = and(_T_2214, _T_2215)
when _T_2216 :
node _T_2217 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2218 = or(_T_2217, io.in.c.ready)
node _T_2219 = asUInt(reset)
node _T_2220 = eq(_T_2219, UInt<1>(0h0))
when _T_2220 :
node _T_2221 = eq(_T_2218, UInt<1>(0h0))
when _T_2221 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2218, UInt<1>(0h1), "") : assert_205
node _T_2222 = orr(c_set_wo_ready)
when _T_2222 :
node _T_2223 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
node _T_2226 = eq(_T_2223, UInt<1>(0h0))
when _T_2226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2223, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_131
node _T_2227 = orr(inflight_1)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
node _T_2229 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2230 = or(_T_2228, _T_2229)
node _T_2231 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2232 = or(_T_2230, _T_2231)
node _T_2233 = asUInt(reset)
node _T_2234 = eq(_T_2233, UInt<1>(0h0))
when _T_2234 :
node _T_2235 = eq(_T_2232, UInt<1>(0h0))
when _T_2235 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2232, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2236 = and(io.in.c.ready, io.in.c.valid)
node _T_2237 = and(io.in.d.ready, io.in.d.valid)
node _T_2238 = or(_T_2236, _T_2237)
when _T_2238 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<12>
connect d_set, UInt<12>(0h0)
node _T_2239 = and(io.in.d.ready, io.in.d.valid)
node _T_2240 = and(_T_2239, d_first_3)
node _T_2241 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2242 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
node _T_2244 = and(_T_2241, _T_2243)
node _T_2245 = and(_T_2240, _T_2244)
when _T_2245 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2246 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2247 = bits(_T_2246, 0, 0)
node _T_2248 = eq(_T_2247, UInt<1>(0h0))
node _T_2249 = asUInt(reset)
node _T_2250 = eq(_T_2249, UInt<1>(0h0))
when _T_2250 :
node _T_2251 = eq(_T_2248, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2248, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<12>
connect e_clr, UInt<12>(0h0)
node _T_2252 = and(io.in.e.ready, io.in.e.valid)
node _T_2253 = and(_T_2252, UInt<1>(0h1))
node _T_2254 = and(_T_2253, UInt<1>(0h1))
when _T_2254 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2255 = or(d_set, inflight_2)
node _T_2256 = dshr(_T_2255, io.in.e.bits.sink)
node _T_2257 = bits(_T_2256, 0, 0)
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
node _T_2260 = eq(_T_2257, UInt<1>(0h0))
when _T_2260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2257, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_65( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20]
wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_6 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [5:0] io_in_b_bits_source = 6'h28; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_55 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_56 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_57 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_58 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_59 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_1 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_2 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_3 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_4 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_T_39 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_46 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_47 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _legal_source_WIRE_1 = 6'h28; // @[Mux.scala:30:73]
wire [5:0] _uncommonBits_T_60 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_61 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_62 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_63 = 6'h28; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_64 = 6'h28; // @[Parameters.scala:52:29]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _legal_source_T_25 = 3'h5; // @[Parameters.scala:54:10]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _legal_source_T_35 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14]
wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25]
wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59]
wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76]
wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_40 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [4:0] _legal_source_T_33 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_43 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_44 = 5'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_37 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_1 = 4'hA; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_7 = 4'hA; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_13 = 4'hA; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_19 = 4'hA; // @[Parameters.scala:54:10]
wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_77 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31]
wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h80001C0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h800001C0; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38]
wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38]
wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38]
wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38]
wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38]
wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38]
wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38]
wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38]
wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38]
wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38]
wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38]
wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38]
wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38]
wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38]
wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38]
wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_78 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_97 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_80 = _source_ok_T_79 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_92 = _source_ok_T_91 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_98 = _source_ok_T_97 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_4 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_103 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_104 = _source_ok_T_103 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_5 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_6 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_7 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_116 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h80001C0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h800001C0; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}]
wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31]
wire _T_2165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2165; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2165; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2239 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2239; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2239; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2239; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2239; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [1:0] b_first_counter; // @[Edges.scala:229:27]
wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2236 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2236; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2236; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [5:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [42:0] inflight; // @[Monitor.scala:614:27]
reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [171:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [42:0] a_set; // @[Monitor.scala:626:34]
wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [171:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99]
wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [171:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [171:0] _a_size_lookup_T_6 = {168'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [171:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[171:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2091 = _T_2165 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2091 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2091 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79]
wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2091 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2091 ? _a_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [42:0] d_clr; // @[Monitor.scala:664:34]
wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [171:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46]
wire _T_2137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2137 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2106 = _T_2239 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2106 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2106 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2106 ? _d_sizes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [42:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [171:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [171:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [171:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [171:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [42:0] inflight_1; // @[Monitor.scala:726:35]
reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [171:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [42:0] c_set; // @[Monitor.scala:738:34]
wire [42:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [171:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [171:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [171:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [171:0] _c_size_lookup_T_6 = {168'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [171:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[171:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2178 = _T_2236 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2178 ? _c_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2178 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2178 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77]
wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2178 ? _c_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2178 ? _c_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [42:0] d_clr_1; // @[Monitor.scala:774:34]
wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [171:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_2191 = _T_2239 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2191 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2191 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2191 ? _d_sizes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [42:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [171:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [171:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [171:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [11:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_set; // @[Monitor.scala:833:25]
wire _T_2245 = _T_2239 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35]
assign d_set = _T_2245 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
wire [11:0] e_clr; // @[Monitor.scala:839:25]
wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_68 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_68( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module IntXbar_i2_o1 :
output auto : { flip anon_in_1 : UInt<1>[1], flip anon_in_0 : UInt<1>[1], anon_out : UInt<1>[2]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire anonIn : UInt<1>[1]
invalidate anonIn[0]
wire anonIn_1 : UInt<1>[1]
invalidate anonIn_1[0]
wire anonOut : UInt<1>[2]
invalidate anonOut[0]
invalidate anonOut[1]
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonOut[0], anonIn[0]
connect anonOut[1], anonIn_1[0] | module IntXbar_i2_o1( // @[Xbar.scala:22:9]
input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1 // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9]
wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9]
wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9]
wire anonOut_0; // @[MixedNode.scala:542:17]
wire anonOut_1; // @[MixedNode.scala:542:17]
wire auto_anon_out_0_0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_0; // @[Xbar.scala:22:9]
assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9]
assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w118 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<118>, q : UInt<118>, flip en : UInt<1>}
reg cdc_reg : UInt<118>, clock
when io.en :
connect cdc_reg, io.d
connect io.q, cdc_reg | module ClockCrossingReg_w118( // @[SynchronizerReg.scala:191:7]
input clock, // @[SynchronizerReg.scala:191:7]
input reset, // @[SynchronizerReg.scala:191:7]
input [117:0] io_d, // @[SynchronizerReg.scala:195:14]
output [117:0] io_q, // @[SynchronizerReg.scala:195:14]
input io_en // @[SynchronizerReg.scala:195:14]
);
wire [117:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7]
wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7]
wire [117:0] io_q_0; // @[SynchronizerReg.scala:191:7]
reg [117:0] cdc_reg; // @[SynchronizerReg.scala:201:76]
assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge clock) begin // @[SynchronizerReg.scala:191:7]
if (io_en_0) // @[SynchronizerReg.scala:191:7]
cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge)
assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 5, 0)
node _source_ok_T = shr(io.in.a.bits.source, 6)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h1))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<6>(0h3f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 5, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 6)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<6>(0h3f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits = bits(_uncommonBits_T, 5, 0)
node _T_4 = shr(io.in.a.bits.source, 6)
node _T_5 = eq(_T_4, UInt<1>(0h1))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<6>(0h3f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 5, 0)
node _T_17 = shr(io.in.a.bits.source, 6)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<6>(0h3f))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _T_30 = and(_T_16, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_30, UInt<1>(0h1), "") : assert_1
node _T_34 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_34 :
node _T_35 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_36 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_37 = and(_T_35, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 5, 0)
node _T_38 = shr(io.in.a.bits.source, 6)
node _T_39 = eq(_T_38, UInt<1>(0h1))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<6>(0h3f))
node _T_43 = and(_T_41, _T_42)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 5, 0)
node _T_44 = shr(io.in.a.bits.source, 6)
node _T_45 = eq(_T_44, UInt<1>(0h0))
node _T_46 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_47 = and(_T_45, _T_46)
node _T_48 = leq(uncommonBits_3, UInt<6>(0h3f))
node _T_49 = and(_T_47, _T_48)
node _T_50 = or(_T_43, _T_49)
node _T_51 = and(_T_37, _T_50)
node _T_52 = or(UInt<1>(0h0), _T_51)
node _T_53 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_54 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<14>(0h2000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<18>(0h2f000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<17>(0h10000)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<27>(0h4000000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<13>(0h1000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = or(_T_58, _T_63)
node _T_95 = or(_T_94, _T_68)
node _T_96 = or(_T_95, _T_73)
node _T_97 = or(_T_96, _T_78)
node _T_98 = or(_T_97, _T_83)
node _T_99 = or(_T_98, _T_88)
node _T_100 = or(_T_99, _T_93)
node _T_101 = and(_T_53, _T_100)
node _T_102 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_103 = or(UInt<1>(0h0), _T_102)
node _T_104 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_105 = cvt(_T_104)
node _T_106 = and(_T_105, asSInt(UInt<17>(0h10000)))
node _T_107 = asSInt(_T_106)
node _T_108 = eq(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_110 = cvt(_T_109)
node _T_111 = and(_T_110, asSInt(UInt<29>(0h10000000)))
node _T_112 = asSInt(_T_111)
node _T_113 = eq(_T_112, asSInt(UInt<1>(0h0)))
node _T_114 = or(_T_108, _T_113)
node _T_115 = and(_T_103, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_101)
node _T_117 = or(_T_116, _T_115)
node _T_118 = and(_T_52, _T_117)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_118, UInt<1>(0h1), "") : assert_2
node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_124 = and(_T_122, _T_123)
node _T_125 = or(UInt<1>(0h0), _T_124)
node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = or(_T_130, _T_135)
node _T_177 = or(_T_176, _T_140)
node _T_178 = or(_T_177, _T_145)
node _T_179 = or(_T_178, _T_150)
node _T_180 = or(_T_179, _T_155)
node _T_181 = or(_T_180, _T_160)
node _T_182 = or(_T_181, _T_165)
node _T_183 = or(_T_182, _T_170)
node _T_184 = or(_T_183, _T_175)
node _T_185 = and(_T_125, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(UInt<1>(0h0), _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_187, UInt<1>(0h1), "") : assert_3
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(source_ok, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_194 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_194, UInt<1>(0h1), "") : assert_5
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(is_aligned, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_201, UInt<1>(0h1), "") : assert_7
node _T_205 = not(io.in.a.bits.mask)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_206, UInt<1>(0h1), "") : assert_8
node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_210, UInt<1>(0h1), "") : assert_9
node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_214 :
node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_217 = and(_T_215, _T_216)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_218 = shr(io.in.a.bits.source, 6)
node _T_219 = eq(_T_218, UInt<1>(0h1))
node _T_220 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_221 = and(_T_219, _T_220)
node _T_222 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_223 = and(_T_221, _T_222)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_224 = shr(io.in.a.bits.source, 6)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_229 = and(_T_227, _T_228)
node _T_230 = or(_T_223, _T_229)
node _T_231 = and(_T_217, _T_230)
node _T_232 = or(UInt<1>(0h0), _T_231)
node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_240 = cvt(_T_239)
node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000)))
node _T_242 = asSInt(_T_241)
node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0)))
node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_245 = cvt(_T_244)
node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000)))
node _T_247 = asSInt(_T_246)
node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0)))
node _T_249 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<18>(0h2f000)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<17>(0h10000)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<13>(0h1000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<27>(0h4000000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = or(_T_238, _T_243)
node _T_275 = or(_T_274, _T_248)
node _T_276 = or(_T_275, _T_253)
node _T_277 = or(_T_276, _T_258)
node _T_278 = or(_T_277, _T_263)
node _T_279 = or(_T_278, _T_268)
node _T_280 = or(_T_279, _T_273)
node _T_281 = and(_T_233, _T_280)
node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<17>(0h10000)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_290 = cvt(_T_289)
node _T_291 = and(_T_290, asSInt(UInt<29>(0h10000000)))
node _T_292 = asSInt(_T_291)
node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0)))
node _T_294 = or(_T_288, _T_293)
node _T_295 = and(_T_283, _T_294)
node _T_296 = or(UInt<1>(0h0), _T_281)
node _T_297 = or(_T_296, _T_295)
node _T_298 = and(_T_232, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_304 = and(_T_302, _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<14>(0h2000)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_317 = cvt(_T_316)
node _T_318 = and(_T_317, asSInt(UInt<17>(0h10000)))
node _T_319 = asSInt(_T_318)
node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0)))
node _T_321 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_322 = cvt(_T_321)
node _T_323 = and(_T_322, asSInt(UInt<18>(0h2f000)))
node _T_324 = asSInt(_T_323)
node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0)))
node _T_326 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<17>(0h10000)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<13>(0h1000)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<17>(0h10000)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<27>(0h4000000)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<13>(0h1000)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<29>(0h10000000)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_310, _T_315)
node _T_357 = or(_T_356, _T_320)
node _T_358 = or(_T_357, _T_325)
node _T_359 = or(_T_358, _T_330)
node _T_360 = or(_T_359, _T_335)
node _T_361 = or(_T_360, _T_340)
node _T_362 = or(_T_361, _T_345)
node _T_363 = or(_T_362, _T_350)
node _T_364 = or(_T_363, _T_355)
node _T_365 = and(_T_305, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = and(UInt<1>(0h0), _T_366)
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_367, UInt<1>(0h1), "") : assert_11
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(source_ok, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_374 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_374, UInt<1>(0h1), "") : assert_13
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(is_aligned, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_381 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_381, UInt<1>(0h1), "") : assert_15
node _T_385 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_385, UInt<1>(0h1), "") : assert_16
node _T_389 = not(io.in.a.bits.mask)
node _T_390 = eq(_T_389, UInt<1>(0h0))
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_390, UInt<1>(0h1), "") : assert_17
node _T_394 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_T_394, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_394, UInt<1>(0h1), "") : assert_18
node _T_398 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_398 :
node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_400 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 5, 0)
node _T_402 = shr(io.in.a.bits.source, 6)
node _T_403 = eq(_T_402, UInt<1>(0h1))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_6, UInt<6>(0h3f))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 5, 0)
node _T_408 = shr(io.in.a.bits.source, 6)
node _T_409 = eq(_T_408, UInt<1>(0h0))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_7, UInt<6>(0h3f))
node _T_413 = and(_T_411, _T_412)
node _T_414 = or(_T_407, _T_413)
node _T_415 = and(_T_401, _T_414)
node _T_416 = or(UInt<1>(0h0), _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_416, UInt<1>(0h1), "") : assert_19
node _T_420 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_421 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_422 = and(_T_420, _T_421)
node _T_423 = or(UInt<1>(0h0), _T_422)
node _T_424 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<13>(0h1000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = and(_T_423, _T_428)
node _T_430 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_431 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_432 = and(_T_430, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<14>(0h2000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<17>(0h10000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_445 = cvt(_T_444)
node _T_446 = and(_T_445, asSInt(UInt<18>(0h2f000)))
node _T_447 = asSInt(_T_446)
node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0)))
node _T_449 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_450 = cvt(_T_449)
node _T_451 = and(_T_450, asSInt(UInt<17>(0h10000)))
node _T_452 = asSInt(_T_451)
node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0)))
node _T_454 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_455 = cvt(_T_454)
node _T_456 = and(_T_455, asSInt(UInt<13>(0h1000)))
node _T_457 = asSInt(_T_456)
node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0)))
node _T_459 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_460 = cvt(_T_459)
node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000)))
node _T_462 = asSInt(_T_461)
node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0)))
node _T_464 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_465 = cvt(_T_464)
node _T_466 = and(_T_465, asSInt(UInt<27>(0h4000000)))
node _T_467 = asSInt(_T_466)
node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0)))
node _T_469 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_470 = cvt(_T_469)
node _T_471 = and(_T_470, asSInt(UInt<13>(0h1000)))
node _T_472 = asSInt(_T_471)
node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0)))
node _T_474 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_475 = cvt(_T_474)
node _T_476 = and(_T_475, asSInt(UInt<29>(0h10000000)))
node _T_477 = asSInt(_T_476)
node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0)))
node _T_479 = or(_T_438, _T_443)
node _T_480 = or(_T_479, _T_448)
node _T_481 = or(_T_480, _T_453)
node _T_482 = or(_T_481, _T_458)
node _T_483 = or(_T_482, _T_463)
node _T_484 = or(_T_483, _T_468)
node _T_485 = or(_T_484, _T_473)
node _T_486 = or(_T_485, _T_478)
node _T_487 = and(_T_433, _T_486)
node _T_488 = or(UInt<1>(0h0), _T_429)
node _T_489 = or(_T_488, _T_487)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_489, UInt<1>(0h1), "") : assert_20
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(source_ok, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(is_aligned, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_499 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_499, UInt<1>(0h1), "") : assert_23
node _T_503 = eq(io.in.a.bits.mask, mask)
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(_T_503, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_503, UInt<1>(0h1), "") : assert_24
node _T_507 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_508 = asUInt(reset)
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(_T_507, UInt<1>(0h0))
when _T_510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_507, UInt<1>(0h1), "") : assert_25
node _T_511 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_511 :
node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_514 = and(_T_512, _T_513)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 5, 0)
node _T_515 = shr(io.in.a.bits.source, 6)
node _T_516 = eq(_T_515, UInt<1>(0h1))
node _T_517 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_518 = and(_T_516, _T_517)
node _T_519 = leq(uncommonBits_8, UInt<6>(0h3f))
node _T_520 = and(_T_518, _T_519)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 5, 0)
node _T_521 = shr(io.in.a.bits.source, 6)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_524 = and(_T_522, _T_523)
node _T_525 = leq(uncommonBits_9, UInt<6>(0h3f))
node _T_526 = and(_T_524, _T_525)
node _T_527 = or(_T_520, _T_526)
node _T_528 = and(_T_514, _T_527)
node _T_529 = or(UInt<1>(0h0), _T_528)
node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_532 = and(_T_530, _T_531)
node _T_533 = or(UInt<1>(0h0), _T_532)
node _T_534 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<13>(0h1000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = and(_T_533, _T_538)
node _T_540 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_541 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_542 = and(_T_540, _T_541)
node _T_543 = or(UInt<1>(0h0), _T_542)
node _T_544 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<14>(0h2000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<18>(0h2f000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<17>(0h10000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<27>(0h4000000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<13>(0h1000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<29>(0h10000000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = or(_T_548, _T_553)
node _T_585 = or(_T_584, _T_558)
node _T_586 = or(_T_585, _T_563)
node _T_587 = or(_T_586, _T_568)
node _T_588 = or(_T_587, _T_573)
node _T_589 = or(_T_588, _T_578)
node _T_590 = or(_T_589, _T_583)
node _T_591 = and(_T_543, _T_590)
node _T_592 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_593 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_594 = cvt(_T_593)
node _T_595 = and(_T_594, asSInt(UInt<17>(0h10000)))
node _T_596 = asSInt(_T_595)
node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0)))
node _T_598 = and(_T_592, _T_597)
node _T_599 = or(UInt<1>(0h0), _T_539)
node _T_600 = or(_T_599, _T_591)
node _T_601 = or(_T_600, _T_598)
node _T_602 = and(_T_529, _T_601)
node _T_603 = asUInt(reset)
node _T_604 = eq(_T_603, UInt<1>(0h0))
when _T_604 :
node _T_605 = eq(_T_602, UInt<1>(0h0))
when _T_605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_602, UInt<1>(0h1), "") : assert_26
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(source_ok, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(is_aligned, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_612 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_612, UInt<1>(0h1), "") : assert_29
node _T_616 = eq(io.in.a.bits.mask, mask)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_616, UInt<1>(0h1), "") : assert_30
node _T_620 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_620 :
node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_624 = shr(io.in.a.bits.source, 6)
node _T_625 = eq(_T_624, UInt<1>(0h1))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_630 = shr(io.in.a.bits.source, 6)
node _T_631 = eq(_T_630, UInt<1>(0h0))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_635 = and(_T_633, _T_634)
node _T_636 = or(_T_629, _T_635)
node _T_637 = and(_T_623, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_640 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_641 = and(_T_639, _T_640)
node _T_642 = or(UInt<1>(0h0), _T_641)
node _T_643 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_644 = cvt(_T_643)
node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000)))
node _T_646 = asSInt(_T_645)
node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0)))
node _T_648 = and(_T_642, _T_647)
node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_651 = and(_T_649, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<18>(0h2f000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<17>(0h10000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<29>(0h10000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = or(_T_657, _T_662)
node _T_694 = or(_T_693, _T_667)
node _T_695 = or(_T_694, _T_672)
node _T_696 = or(_T_695, _T_677)
node _T_697 = or(_T_696, _T_682)
node _T_698 = or(_T_697, _T_687)
node _T_699 = or(_T_698, _T_692)
node _T_700 = and(_T_652, _T_699)
node _T_701 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_702 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_703 = cvt(_T_702)
node _T_704 = and(_T_703, asSInt(UInt<17>(0h10000)))
node _T_705 = asSInt(_T_704)
node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0)))
node _T_707 = and(_T_701, _T_706)
node _T_708 = or(UInt<1>(0h0), _T_648)
node _T_709 = or(_T_708, _T_700)
node _T_710 = or(_T_709, _T_707)
node _T_711 = and(_T_638, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_711, UInt<1>(0h1), "") : assert_31
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_721 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_721, UInt<1>(0h1), "") : assert_34
node _T_725 = not(mask)
node _T_726 = and(io.in.a.bits.mask, _T_725)
node _T_727 = eq(_T_726, UInt<1>(0h0))
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_727, UInt<1>(0h1), "") : assert_35
node _T_731 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_731 :
node _T_732 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_733 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_734 = and(_T_732, _T_733)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 5, 0)
node _T_735 = shr(io.in.a.bits.source, 6)
node _T_736 = eq(_T_735, UInt<1>(0h1))
node _T_737 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_738 = and(_T_736, _T_737)
node _T_739 = leq(uncommonBits_12, UInt<6>(0h3f))
node _T_740 = and(_T_738, _T_739)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 5, 0)
node _T_741 = shr(io.in.a.bits.source, 6)
node _T_742 = eq(_T_741, UInt<1>(0h0))
node _T_743 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_744 = and(_T_742, _T_743)
node _T_745 = leq(uncommonBits_13, UInt<6>(0h3f))
node _T_746 = and(_T_744, _T_745)
node _T_747 = or(_T_740, _T_746)
node _T_748 = and(_T_734, _T_747)
node _T_749 = or(UInt<1>(0h0), _T_748)
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_752 = and(_T_750, _T_751)
node _T_753 = or(UInt<1>(0h0), _T_752)
node _T_754 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<14>(0h2000)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<18>(0h2f000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_770 = cvt(_T_769)
node _T_771 = and(_T_770, asSInt(UInt<17>(0h10000)))
node _T_772 = asSInt(_T_771)
node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0)))
node _T_774 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_775 = cvt(_T_774)
node _T_776 = and(_T_775, asSInt(UInt<13>(0h1000)))
node _T_777 = asSInt(_T_776)
node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0)))
node _T_779 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_780 = cvt(_T_779)
node _T_781 = and(_T_780, asSInt(UInt<27>(0h4000000)))
node _T_782 = asSInt(_T_781)
node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0)))
node _T_784 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_785 = cvt(_T_784)
node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000)))
node _T_787 = asSInt(_T_786)
node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0)))
node _T_789 = or(_T_758, _T_763)
node _T_790 = or(_T_789, _T_768)
node _T_791 = or(_T_790, _T_773)
node _T_792 = or(_T_791, _T_778)
node _T_793 = or(_T_792, _T_783)
node _T_794 = or(_T_793, _T_788)
node _T_795 = and(_T_753, _T_794)
node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_797 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_798 = cvt(_T_797)
node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000)))
node _T_800 = asSInt(_T_799)
node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0)))
node _T_802 = and(_T_796, _T_801)
node _T_803 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_804 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_805 = and(_T_803, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_805)
node _T_807 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_808 = cvt(_T_807)
node _T_809 = and(_T_808, asSInt(UInt<17>(0h10000)))
node _T_810 = asSInt(_T_809)
node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0)))
node _T_812 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_813 = cvt(_T_812)
node _T_814 = and(_T_813, asSInt(UInt<29>(0h10000000)))
node _T_815 = asSInt(_T_814)
node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0)))
node _T_817 = or(_T_811, _T_816)
node _T_818 = and(_T_806, _T_817)
node _T_819 = or(UInt<1>(0h0), _T_795)
node _T_820 = or(_T_819, _T_802)
node _T_821 = or(_T_820, _T_818)
node _T_822 = and(_T_749, _T_821)
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_822, UInt<1>(0h1), "") : assert_36
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(source_ok, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(is_aligned, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_832 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_832, UInt<1>(0h1), "") : assert_39
node _T_836 = eq(io.in.a.bits.mask, mask)
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_836, UInt<1>(0h1), "") : assert_40
node _T_840 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_840 :
node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_843 = and(_T_841, _T_842)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 5, 0)
node _T_844 = shr(io.in.a.bits.source, 6)
node _T_845 = eq(_T_844, UInt<1>(0h1))
node _T_846 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_847 = and(_T_845, _T_846)
node _T_848 = leq(uncommonBits_14, UInt<6>(0h3f))
node _T_849 = and(_T_847, _T_848)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 5, 0)
node _T_850 = shr(io.in.a.bits.source, 6)
node _T_851 = eq(_T_850, UInt<1>(0h0))
node _T_852 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_853 = and(_T_851, _T_852)
node _T_854 = leq(uncommonBits_15, UInt<6>(0h3f))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(_T_849, _T_855)
node _T_857 = and(_T_843, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_860 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_861 = and(_T_859, _T_860)
node _T_862 = or(UInt<1>(0h0), _T_861)
node _T_863 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_864 = cvt(_T_863)
node _T_865 = and(_T_864, asSInt(UInt<14>(0h2000)))
node _T_866 = asSInt(_T_865)
node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0)))
node _T_868 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<13>(0h1000)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<18>(0h2f000)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_879 = cvt(_T_878)
node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000)))
node _T_881 = asSInt(_T_880)
node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0)))
node _T_883 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_884 = cvt(_T_883)
node _T_885 = and(_T_884, asSInt(UInt<13>(0h1000)))
node _T_886 = asSInt(_T_885)
node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0)))
node _T_888 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_889 = cvt(_T_888)
node _T_890 = and(_T_889, asSInt(UInt<27>(0h4000000)))
node _T_891 = asSInt(_T_890)
node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0)))
node _T_893 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_894 = cvt(_T_893)
node _T_895 = and(_T_894, asSInt(UInt<13>(0h1000)))
node _T_896 = asSInt(_T_895)
node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0)))
node _T_898 = or(_T_867, _T_872)
node _T_899 = or(_T_898, _T_877)
node _T_900 = or(_T_899, _T_882)
node _T_901 = or(_T_900, _T_887)
node _T_902 = or(_T_901, _T_892)
node _T_903 = or(_T_902, _T_897)
node _T_904 = and(_T_862, _T_903)
node _T_905 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_906 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = and(_T_905, _T_910)
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_914 = and(_T_912, _T_913)
node _T_915 = or(UInt<1>(0h0), _T_914)
node _T_916 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_917 = cvt(_T_916)
node _T_918 = and(_T_917, asSInt(UInt<17>(0h10000)))
node _T_919 = asSInt(_T_918)
node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0)))
node _T_921 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<29>(0h10000000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = or(_T_920, _T_925)
node _T_927 = and(_T_915, _T_926)
node _T_928 = or(UInt<1>(0h0), _T_904)
node _T_929 = or(_T_928, _T_911)
node _T_930 = or(_T_929, _T_927)
node _T_931 = and(_T_858, _T_930)
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(_T_931, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_931, UInt<1>(0h1), "") : assert_41
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(source_ok, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(is_aligned, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_941 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_941, UInt<1>(0h1), "") : assert_44
node _T_945 = eq(io.in.a.bits.mask, mask)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_945, UInt<1>(0h1), "") : assert_45
node _T_949 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_949 :
node _T_950 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_951 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_952 = and(_T_950, _T_951)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_953 = shr(io.in.a.bits.source, 6)
node _T_954 = eq(_T_953, UInt<1>(0h1))
node _T_955 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_956 = and(_T_954, _T_955)
node _T_957 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_958 = and(_T_956, _T_957)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_959 = shr(io.in.a.bits.source, 6)
node _T_960 = eq(_T_959, UInt<1>(0h0))
node _T_961 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_962 = and(_T_960, _T_961)
node _T_963 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_964 = and(_T_962, _T_963)
node _T_965 = or(_T_958, _T_964)
node _T_966 = and(_T_952, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_969 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_970 = and(_T_968, _T_969)
node _T_971 = or(UInt<1>(0h0), _T_970)
node _T_972 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_973 = cvt(_T_972)
node _T_974 = and(_T_973, asSInt(UInt<13>(0h1000)))
node _T_975 = asSInt(_T_974)
node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0)))
node _T_977 = and(_T_971, _T_976)
node _T_978 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_979 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_980 = cvt(_T_979)
node _T_981 = and(_T_980, asSInt(UInt<14>(0h2000)))
node _T_982 = asSInt(_T_981)
node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0)))
node _T_984 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_985 = cvt(_T_984)
node _T_986 = and(_T_985, asSInt(UInt<17>(0h10000)))
node _T_987 = asSInt(_T_986)
node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0)))
node _T_989 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<18>(0h2f000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1000 = cvt(_T_999)
node _T_1001 = and(_T_1000, asSInt(UInt<13>(0h1000)))
node _T_1002 = asSInt(_T_1001)
node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0)))
node _T_1004 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<27>(0h4000000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = or(_T_983, _T_988)
node _T_1015 = or(_T_1014, _T_993)
node _T_1016 = or(_T_1015, _T_998)
node _T_1017 = or(_T_1016, _T_1003)
node _T_1018 = or(_T_1017, _T_1008)
node _T_1019 = or(_T_1018, _T_1013)
node _T_1020 = and(_T_978, _T_1019)
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = or(UInt<1>(0h0), _T_1023)
node _T_1025 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1026 = cvt(_T_1025)
node _T_1027 = and(_T_1026, asSInt(UInt<17>(0h10000)))
node _T_1028 = asSInt(_T_1027)
node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0)))
node _T_1030 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1031 = cvt(_T_1030)
node _T_1032 = and(_T_1031, asSInt(UInt<29>(0h10000000)))
node _T_1033 = asSInt(_T_1032)
node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0)))
node _T_1035 = or(_T_1029, _T_1034)
node _T_1036 = and(_T_1024, _T_1035)
node _T_1037 = or(UInt<1>(0h0), _T_977)
node _T_1038 = or(_T_1037, _T_1020)
node _T_1039 = or(_T_1038, _T_1036)
node _T_1040 = and(_T_967, _T_1039)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_46
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(is_aligned, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1050 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_49
node _T_1054 = eq(io.in.a.bits.mask, mask)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_50
node _T_1058 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1062 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 5, 0)
node _source_ok_T_12 = shr(io.in.d.bits.source, 6)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<6>(0h3f))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 5, 0)
node _source_ok_T_18 = shr(io.in.d.bits.source, 6)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<6>(0h3f))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_17
connect _source_ok_WIRE_1[1], _source_ok_T_23
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_1066 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1066 :
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(source_ok_1, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1070 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_54
node _T_1074 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_55
node _T_1078 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_56
node _T_1082 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_57
node _T_1086 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1086 :
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(source_ok_1, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(sink_ok, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1093 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_60
node _T_1097 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_61
node _T_1101 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_62
node _T_1105 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_63
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h1), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_64
node _T_1114 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(sink_ok, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1121 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_67
node _T_1125 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_68
node _T_1129 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_69
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(_T_1133, io.in.d.bits.corrupt)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_70
node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1139 = or(UInt<1>(0h1), _T_1138)
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_71
node _T_1143 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(source_ok_1, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_73
node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_74
node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1156 = or(UInt<1>(0h1), _T_1155)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_75
node _T_1160 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1160 :
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok_1, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1164 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_77
node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1169 = or(_T_1168, io.in.d.bits.corrupt)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_78
node _T_1173 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1174 = or(UInt<1>(0h1), _T_1173)
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_79
node _T_1178 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1178 :
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(source_ok_1, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1182 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_81
node _T_1186 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_82
node _T_1190 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1191 = or(UInt<1>(0h1), _T_1190)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1195 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1199 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1203 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1207 = eq(a_first, UInt<1>(0h0))
node _T_1208 = and(io.in.a.valid, _T_1207)
when _T_1208 :
node _T_1209 = eq(io.in.a.bits.opcode, opcode)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_87
node _T_1213 = eq(io.in.a.bits.param, param)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_88
node _T_1217 = eq(io.in.a.bits.size, size)
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_89
node _T_1221 = eq(io.in.a.bits.source, source)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_90
node _T_1225 = eq(io.in.a.bits.address, address)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_91
node _T_1229 = and(io.in.a.ready, io.in.a.valid)
node _T_1230 = and(_T_1229, a_first)
when _T_1230 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1231 = eq(d_first, UInt<1>(0h0))
node _T_1232 = and(io.in.d.valid, _T_1231)
when _T_1232 :
node _T_1233 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_92
node _T_1237 = eq(io.in.d.bits.param, param_1)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_93
node _T_1241 = eq(io.in.d.bits.size, size_1)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_94
node _T_1245 = eq(io.in.d.bits.source, source_1)
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_95
node _T_1249 = eq(io.in.d.bits.sink, sink)
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_96
node _T_1253 = eq(io.in.d.bits.denied, denied)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_97
node _T_1257 = and(io.in.d.ready, io.in.d.valid)
node _T_1258 = and(_T_1257, d_first)
when _T_1258 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_opcodes : UInt<512>, clock, reset, UInt<512>(0h0)
regreset inflight_sizes : UInt<1024>, clock, reset, UInt<1024>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<128>
connect a_set, UInt<128>(0h0)
wire a_set_wo_ready : UInt<128>
connect a_set_wo_ready, UInt<128>(0h0)
wire a_opcodes_set : UInt<512>
connect a_opcodes_set, UInt<512>(0h0)
wire a_sizes_set : UInt<1024>
connect a_sizes_set, UInt<1024>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1259 = and(io.in.a.valid, a_first_1)
node _T_1260 = and(_T_1259, UInt<1>(0h1))
when _T_1260 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1261 = and(io.in.a.ready, io.in.a.valid)
node _T_1262 = and(_T_1261, a_first_1)
node _T_1263 = and(_T_1262, UInt<1>(0h1))
when _T_1263 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1264 = dshr(inflight, io.in.a.bits.source)
node _T_1265 = bits(_T_1264, 0, 0)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
node _T_1267 = asUInt(reset)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
when _T_1268 :
node _T_1269 = eq(_T_1266, UInt<1>(0h0))
when _T_1269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1266, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<128>
connect d_clr, UInt<128>(0h0)
wire d_clr_wo_ready : UInt<128>
connect d_clr_wo_ready, UInt<128>(0h0)
wire d_opcodes_clr : UInt<512>
connect d_opcodes_clr, UInt<512>(0h0)
wire d_sizes_clr : UInt<1024>
connect d_sizes_clr, UInt<1024>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1270 = and(io.in.d.valid, d_first_1)
node _T_1271 = and(_T_1270, UInt<1>(0h1))
node _T_1272 = eq(d_release_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1274 = and(io.in.d.ready, io.in.d.valid)
node _T_1275 = and(_T_1274, d_first_1)
node _T_1276 = and(_T_1275, UInt<1>(0h1))
node _T_1277 = eq(d_release_ack, UInt<1>(0h0))
node _T_1278 = and(_T_1276, _T_1277)
when _T_1278 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1279 = and(io.in.d.valid, d_first_1)
node _T_1280 = and(_T_1279, UInt<1>(0h1))
node _T_1281 = eq(d_release_ack, UInt<1>(0h0))
node _T_1282 = and(_T_1280, _T_1281)
when _T_1282 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1283 = dshr(inflight, io.in.d.bits.source)
node _T_1284 = bits(_T_1283, 0, 0)
node _T_1285 = or(_T_1284, same_cycle_resp)
node _T_1286 = asUInt(reset)
node _T_1287 = eq(_T_1286, UInt<1>(0h0))
when _T_1287 :
node _T_1288 = eq(_T_1285, UInt<1>(0h0))
when _T_1288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1285, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1289 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1290 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1291 = or(_T_1289, _T_1290)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_100
node _T_1295 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_101
else :
node _T_1299 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1300 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1301 = or(_T_1299, _T_1300)
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(_T_1301, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1301, UInt<1>(0h1), "") : assert_102
node _T_1305 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_103
node _T_1309 = and(io.in.d.valid, d_first_1)
node _T_1310 = and(_T_1309, a_first_1)
node _T_1311 = and(_T_1310, io.in.a.valid)
node _T_1312 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = eq(d_release_ack, UInt<1>(0h0))
node _T_1315 = and(_T_1313, _T_1314)
when _T_1315 :
node _T_1316 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1317 = or(_T_1316, io.in.a.ready)
node _T_1318 = asUInt(reset)
node _T_1319 = eq(_T_1318, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = eq(_T_1317, UInt<1>(0h0))
when _T_1320 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1317, UInt<1>(0h1), "") : assert_104
node _T_1321 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1322 = orr(a_set_wo_ready)
node _T_1323 = eq(_T_1322, UInt<1>(0h0))
node _T_1324 = or(_T_1321, _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_98
node _T_1328 = orr(inflight)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
node _T_1330 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = lt(watchdog, plusarg_reader.out)
node _T_1333 = or(_T_1331, _T_1332)
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1337 = and(io.in.a.ready, io.in.a.valid)
node _T_1338 = and(io.in.d.ready, io.in.d.valid)
node _T_1339 = or(_T_1337, _T_1338)
when _T_1339 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_opcodes_1 : UInt<512>, clock, reset, UInt<512>(0h0)
regreset inflight_sizes_1 : UInt<1024>, clock, reset, UInt<1024>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<128>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<128>
connect c_set, UInt<128>(0h0)
wire c_set_wo_ready : UInt<128>
connect c_set_wo_ready, UInt<128>(0h0)
wire c_opcodes_set : UInt<512>
connect c_opcodes_set, UInt<512>(0h0)
wire c_sizes_set : UInt<1024>
connect c_sizes_set, UInt<1024>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1340 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1341 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1342 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1343 = and(_T_1341, _T_1342)
node _T_1344 = and(_T_1340, _T_1343)
when _T_1344 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1345 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1346 = and(_T_1345, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1347 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1348 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1349 = and(_T_1347, _T_1348)
node _T_1350 = and(_T_1346, _T_1349)
when _T_1350 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1351 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1352 = bits(_T_1351, 0, 0)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<128>
connect d_clr_1, UInt<128>(0h0)
wire d_clr_wo_ready_1 : UInt<128>
connect d_clr_wo_ready_1, UInt<128>(0h0)
wire d_opcodes_clr_1 : UInt<512>
connect d_opcodes_clr_1, UInt<512>(0h0)
wire d_sizes_clr_1 : UInt<1024>
connect d_sizes_clr_1, UInt<1024>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1357 = and(io.in.d.valid, d_first_2)
node _T_1358 = and(_T_1357, UInt<1>(0h1))
node _T_1359 = and(_T_1358, d_release_ack_1)
when _T_1359 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1360 = and(io.in.d.ready, io.in.d.valid)
node _T_1361 = and(_T_1360, d_first_2)
node _T_1362 = and(_T_1361, UInt<1>(0h1))
node _T_1363 = and(_T_1362, d_release_ack_1)
when _T_1363 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1364 = and(io.in.d.valid, d_first_2)
node _T_1365 = and(_T_1364, UInt<1>(0h1))
node _T_1366 = and(_T_1365, d_release_ack_1)
when _T_1366 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1367 = dshr(inflight_1, io.in.d.bits.source)
node _T_1368 = bits(_T_1367, 0, 0)
node _T_1369 = or(_T_1368, same_cycle_resp_1)
node _T_1370 = asUInt(reset)
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(_T_1369, UInt<1>(0h0))
when _T_1372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1369, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1373 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(_T_1373, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1373, UInt<1>(0h1), "") : assert_109
else :
node _T_1377 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_110
node _T_1381 = and(io.in.d.valid, d_first_2)
node _T_1382 = and(_T_1381, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1383 = and(_T_1382, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<128>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1384 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1385 = and(_T_1383, _T_1384)
node _T_1386 = and(_T_1385, d_release_ack_1)
node _T_1387 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1388 = and(_T_1386, _T_1387)
when _T_1388 :
node _T_1389 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<128>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1390 = or(_T_1389, _WIRE_23.ready)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_111
node _T_1394 = orr(c_set_wo_ready)
when _T_1394 :
node _T_1395 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1396 = asUInt(reset)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(_T_1395, UInt<1>(0h0))
when _T_1398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1395, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_99
node _T_1399 = orr(inflight_1)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
node _T_1401 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1404 = or(_T_1402, _T_1403)
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1408 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = or(_T_1408, _T_1409)
when _T_1410 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_100 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_101 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_48( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] c_set = 128'h0; // @[Monitor.scala:738:34]
wire [127:0] c_set_wo_ready = 128'h0; // @[Monitor.scala:739:34]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [1023:0] c_sizes_set = 1024'h0; // @[Monitor.scala:741:34]
wire [511:0] c_opcodes_set = 512'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_6 = io_in_a_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [5:0] uncommonBits = _uncommonBits_T[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_1 = _uncommonBits_T_1[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_2 = _uncommonBits_T_2[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_3 = _uncommonBits_T_3[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_6 = _uncommonBits_T_6[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_7 = _uncommonBits_T_7[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_8 = _uncommonBits_T_8[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_9 = _uncommonBits_T_9[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_12 = _uncommonBits_T_12[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_13 = _uncommonBits_T_13[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_14 = _uncommonBits_T_14[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_15 = _uncommonBits_T_15[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_12 = io_in_d_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_18 = io_in_d_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1337 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1337; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1337; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1410 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1410; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [127:0] inflight; // @[Monitor.scala:614:27]
reg [511:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1023:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [127:0] a_set; // @[Monitor.scala:626:34]
wire [127:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [511:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1023:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [511:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [511:0] _a_opcode_lookup_T_6 = {508'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [511:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[511:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1023:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1023:0] _a_size_lookup_T_6 = {1016'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1023:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1023:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = {121'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_4 = 128'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 128'h0; // @[OneHot.scala:58:35]
wire _T_1263 = _T_1337 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1263 ? _a_set_T : 128'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1263 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1263 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1263 ? _a_opcodes_set_T_1[511:0] : 512'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1263 ? _a_sizes_set_T_1[1023:0] : 1024'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [127:0] d_clr; // @[Monitor.scala:664:34]
wire [127:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [511:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1023:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1309 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_6 = {121'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_7 = 128'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1309 & ~d_release_ack ? _d_clr_wo_ready_T : 128'h0; // @[OneHot.scala:58:35]
wire _T_1278 = _T_1410 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1278 ? _d_clr_T : 128'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1278 ? _d_opcodes_clr_T_5[511:0] : 512'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1278 ? _d_sizes_clr_T_5[1023:0] : 1024'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [127:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [127:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [127:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [511:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [511:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [511:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1023:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1023:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1023:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [127:0] inflight_1; // @[Monitor.scala:726:35]
wire [127:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [511:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [511:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1023:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1023:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [511:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [511:0] _c_opcode_lookup_T_6 = {508'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [511:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[511:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1023:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1023:0] _c_size_lookup_T_6 = {1016'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1023:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1023:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [127:0] d_clr_1; // @[Monitor.scala:774:34]
wire [127:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [511:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1023:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1381 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1381 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 128'h0; // @[OneHot.scala:58:35]
wire _T_1363 = _T_1410 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1363 ? _d_clr_T_1 : 128'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1363 ? _d_opcodes_clr_T_11[511:0] : 512'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1363 ? _d_sizes_clr_T_11[1023:0] : 1024'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [127:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [127:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [511:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [511:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1023:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1023:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_12 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_96
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_98
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_12( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_96 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_98 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LatencyInjectionQueue_19 :
input clock : Clock
input reset : Reset
output io : { flip latency_cycles : UInt<64>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}
regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0)
node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1))
node _cur_cycle_T_1 = tail(_cur_cycle_T, 1)
connect cur_cycle, _cur_cycle_T_1
inst queue of Queue8_TLBundleD_a32d256s2k3z4u_3
connect queue.clock, clock
connect queue.reset, reset
inst release_ready_cycle_q of Queue8_UInt64_7
connect release_ready_cycle_q.clock, clock
connect release_ready_cycle_q.reset, reset
node _release_ready_cycle_q_io_enq_bits_T = add(cur_cycle, io.latency_cycles)
node _release_ready_cycle_q_io_enq_bits_T_1 = tail(_release_ready_cycle_q_io_enq_bits_T, 1)
connect release_ready_cycle_q.io.enq.bits, _release_ready_cycle_q_io_enq_bits_T_1
connect queue.io.enq.bits.corrupt, io.enq.bits.corrupt
connect queue.io.enq.bits.data, io.enq.bits.data
connect queue.io.enq.bits.denied, io.enq.bits.denied
connect queue.io.enq.bits.sink, io.enq.bits.sink
connect queue.io.enq.bits.source, io.enq.bits.source
connect queue.io.enq.bits.size, io.enq.bits.size
connect queue.io.enq.bits.param, io.enq.bits.param
connect queue.io.enq.bits.opcode, io.enq.bits.opcode
connect io.deq.bits, queue.io.deq.bits
node _queue_io_enq_valid_T = and(release_ready_cycle_q.io.enq.ready, io.enq.valid)
connect queue.io.enq.valid, _queue_io_enq_valid_T
node _release_ready_cycle_q_io_enq_valid_T = and(queue.io.enq.ready, io.enq.valid)
connect release_ready_cycle_q.io.enq.valid, _release_ready_cycle_q_io_enq_valid_T
node _io_enq_ready_T = and(queue.io.enq.ready, release_ready_cycle_q.io.enq.ready)
connect io.enq.ready, _io_enq_ready_T
node _T = leq(release_ready_cycle_q.io.deq.bits, cur_cycle)
node _queue_io_deq_ready_T = and(release_ready_cycle_q.io.deq.valid, _T)
node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, io.deq.ready)
connect queue.io.deq.ready, _queue_io_deq_ready_T_1
node _release_ready_cycle_q_io_deq_ready_T = and(queue.io.deq.valid, _T)
node _release_ready_cycle_q_io_deq_ready_T_1 = and(_release_ready_cycle_q_io_deq_ready_T, io.deq.ready)
connect release_ready_cycle_q.io.deq.ready, _release_ready_cycle_q_io_deq_ready_T_1
node _io_deq_valid_T = and(queue.io.deq.valid, release_ready_cycle_q.io.deq.valid)
node _io_deq_valid_T_1 = and(_io_deq_valid_T, _T)
connect io.deq.valid, _io_deq_valid_T_1 | module LatencyInjectionQueue_19( // @[LatencyInjectionQueue.scala:9:7]
input clock, // @[LatencyInjectionQueue.scala:9:7]
input reset, // @[LatencyInjectionQueue.scala:9:7]
input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14]
output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14]
input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14]
input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14]
input [1:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14]
input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14]
input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14]
output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14]
output [1:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14]
);
wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37]
wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37]
wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37]
wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21]
wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21]
wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7]
wire _io_enq_ready_T; // @[Misc.scala:26:53]
wire _io_deq_valid_T_1; // @[Misc.scala:26:53]
wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26]
wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26]
wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26]
wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26]
wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50]
wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50]
wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53]
wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39]
wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53]
always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7]
if (reset) // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26]
else // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26]
always @(posedge)
Queue8_TLBundleD_a32d256s2k3z4u_3 queue ( // @[LatencyInjectionQueue.scala:18:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7]
.io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_queue_io_deq_valid),
.io_deq_bits_opcode (io_deq_bits_opcode),
.io_deq_bits_param (io_deq_bits_param),
.io_deq_bits_size (io_deq_bits_size),
.io_deq_bits_source (io_deq_bits_source_0),
.io_deq_bits_sink (io_deq_bits_sink),
.io_deq_bits_denied (io_deq_bits_denied),
.io_deq_bits_data (io_deq_bits_data_0),
.io_deq_bits_corrupt (io_deq_bits_corrupt)
); // @[LatencyInjectionQueue.scala:18:21]
Queue8_UInt64_7 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37]
.clock (clock),
.reset (reset),
.io_enq_ready (_release_ready_cycle_q_io_enq_ready),
.io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50]
.io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_release_ready_cycle_q_io_deq_valid),
.io_deq_bits (_release_ready_cycle_q_io_deq_bits)
); // @[LatencyInjectionQueue.scala:19:37]
assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x5_3 :
output auto : { flip in : { sync : UInt<1>[5]}, out : UInt<1>[5]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { sync : UInt<1>[5]}
invalidate nodeIn.sync[0]
invalidate nodeIn.sync[1]
invalidate nodeIn.sync[2]
invalidate nodeIn.sync[3]
invalidate nodeIn.sync[4]
wire nodeOut : UInt<1>[5]
invalidate nodeOut[0]
invalidate nodeOut[1]
invalidate nodeOut[2]
invalidate nodeOut[3]
invalidate nodeOut[4]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn.sync | module IntSyncSyncCrossingSink_n1x5_3( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_in_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_in_sync_2, // @[LazyModuleImp.scala:107:25]
input auto_in_sync_3, // @[LazyModuleImp.scala:107:25]
input auto_in_sync_4, // @[LazyModuleImp.scala:107:25]
output auto_out_0, // @[LazyModuleImp.scala:107:25]
output auto_out_1, // @[LazyModuleImp.scala:107:25]
output auto_out_2, // @[LazyModuleImp.scala:107:25]
output auto_out_3, // @[LazyModuleImp.scala:107:25]
output auto_out_4 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9]
wire auto_in_sync_2_0 = auto_in_sync_2; // @[Crossing.scala:96:9]
wire auto_in_sync_3_0 = auto_in_sync_3; // @[Crossing.scala:96:9]
wire auto_in_sync_4_0 = auto_in_sync_4; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9]
wire nodeIn_sync_2 = auto_in_sync_2_0; // @[Crossing.scala:96:9]
wire nodeIn_sync_3 = auto_in_sync_3_0; // @[Crossing.scala:96:9]
wire nodeIn_sync_4 = auto_in_sync_4_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire nodeOut_1; // @[MixedNode.scala:542:17]
wire nodeOut_2; // @[MixedNode.scala:542:17]
wire nodeOut_3; // @[MixedNode.scala:542:17]
wire nodeOut_4; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
wire auto_out_1_0; // @[Crossing.scala:96:9]
wire auto_out_2_0; // @[Crossing.scala:96:9]
wire auto_out_3_0; // @[Crossing.scala:96:9]
wire auto_out_4_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_2 = nodeIn_sync_2; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_3 = nodeIn_sync_3; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_4 = nodeIn_sync_4; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9]
assign auto_out_2_0 = nodeOut_2; // @[Crossing.scala:96:9]
assign auto_out_3_0 = nodeOut_3; // @[Crossing.scala:96:9]
assign auto_out_4_0 = nodeOut_4; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9]
assign auto_out_2 = auto_out_2_0; // @[Crossing.scala:96:9]
assign auto_out_3 = auto_out_3_0; // @[Crossing.scala:96:9]
assign auto_out_4 = auto_out_4_0; // @[Crossing.scala:96:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_130 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_151
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_130( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_151 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_357 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_357( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e11_s53_3 :
output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 63, 52)
node _rawA_isZero_T = bits(rawA_exp, 11, 9)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 11, 10)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 9, 9)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 64, 64)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 51, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 63, 52)
node _rawB_isZero_T = bits(rawB_exp, 11, 9)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 11, 10)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 9, 9)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 64, 64)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 51, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 63, 52)
node _rawC_isZero_T = bits(rawC_exp, 11, 9)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 11, 10)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawC_out_isNaN_T = bits(rawC_exp, 9, 9)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 9, 9)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 64, 64)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 51, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<12>(0h838)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 12, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<6>(0h35))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<8>(0ha1))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 7, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<8>(0ha1))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<111>(0h7fffffffffffffffffffffffffff), UInt<111>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 0)
wire reduced4CExtra_reducedVec : UInt<1>[14]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 27, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node _reduced4CExtra_reducedVec_7_T = bits(_reduced4CExtra_T, 31, 28)
node _reduced4CExtra_reducedVec_7_T_1 = orr(_reduced4CExtra_reducedVec_7_T)
connect reduced4CExtra_reducedVec[7], _reduced4CExtra_reducedVec_7_T_1
node _reduced4CExtra_reducedVec_8_T = bits(_reduced4CExtra_T, 35, 32)
node _reduced4CExtra_reducedVec_8_T_1 = orr(_reduced4CExtra_reducedVec_8_T)
connect reduced4CExtra_reducedVec[8], _reduced4CExtra_reducedVec_8_T_1
node _reduced4CExtra_reducedVec_9_T = bits(_reduced4CExtra_T, 39, 36)
node _reduced4CExtra_reducedVec_9_T_1 = orr(_reduced4CExtra_reducedVec_9_T)
connect reduced4CExtra_reducedVec[9], _reduced4CExtra_reducedVec_9_T_1
node _reduced4CExtra_reducedVec_10_T = bits(_reduced4CExtra_T, 43, 40)
node _reduced4CExtra_reducedVec_10_T_1 = orr(_reduced4CExtra_reducedVec_10_T)
connect reduced4CExtra_reducedVec[10], _reduced4CExtra_reducedVec_10_T_1
node _reduced4CExtra_reducedVec_11_T = bits(_reduced4CExtra_T, 47, 44)
node _reduced4CExtra_reducedVec_11_T_1 = orr(_reduced4CExtra_reducedVec_11_T)
connect reduced4CExtra_reducedVec[11], _reduced4CExtra_reducedVec_11_T_1
node _reduced4CExtra_reducedVec_12_T = bits(_reduced4CExtra_T, 51, 48)
node _reduced4CExtra_reducedVec_12_T_1 = orr(_reduced4CExtra_reducedVec_12_T)
connect reduced4CExtra_reducedVec[12], _reduced4CExtra_reducedVec_12_T_1
node _reduced4CExtra_reducedVec_13_T = bits(_reduced4CExtra_T, 53, 52)
node _reduced4CExtra_reducedVec_13_T_1 = orr(_reduced4CExtra_reducedVec_13_T)
connect reduced4CExtra_reducedVec[13], _reduced4CExtra_reducedVec_13_T_1
node reduced4CExtra_lo_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo_lo = cat(reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_lo_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_lo_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_lo_hi = cat(reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo)
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_lo_lo)
node reduced4CExtra_hi_lo_hi = cat(reduced4CExtra_reducedVec[9], reduced4CExtra_reducedVec[8])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec[7])
node reduced4CExtra_hi_hi_lo = cat(reduced4CExtra_reducedVec[11], reduced4CExtra_reducedVec[10])
node reduced4CExtra_hi_hi_hi = cat(reduced4CExtra_reducedVec[13], reduced4CExtra_reducedVec[12])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo)
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 36, 24)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 7, 0)
node _reduced4CExtra_T_5 = shl(UInt<4>(0hf), 4)
node _reduced4CExtra_T_6 = xor(UInt<8>(0hff), _reduced4CExtra_T_5)
node _reduced4CExtra_T_7 = shr(_reduced4CExtra_T_4, 4)
node _reduced4CExtra_T_8 = and(_reduced4CExtra_T_7, _reduced4CExtra_T_6)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 0)
node _reduced4CExtra_T_10 = shl(_reduced4CExtra_T_9, 4)
node _reduced4CExtra_T_11 = not(_reduced4CExtra_T_6)
node _reduced4CExtra_T_12 = and(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = or(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_6, 5, 0)
node _reduced4CExtra_T_15 = shl(_reduced4CExtra_T_14, 2)
node _reduced4CExtra_T_16 = xor(_reduced4CExtra_T_6, _reduced4CExtra_T_15)
node _reduced4CExtra_T_17 = shr(_reduced4CExtra_T_13, 2)
node _reduced4CExtra_T_18 = and(_reduced4CExtra_T_17, _reduced4CExtra_T_16)
node _reduced4CExtra_T_19 = bits(_reduced4CExtra_T_13, 5, 0)
node _reduced4CExtra_T_20 = shl(_reduced4CExtra_T_19, 2)
node _reduced4CExtra_T_21 = not(_reduced4CExtra_T_16)
node _reduced4CExtra_T_22 = and(_reduced4CExtra_T_20, _reduced4CExtra_T_21)
node _reduced4CExtra_T_23 = or(_reduced4CExtra_T_18, _reduced4CExtra_T_22)
node _reduced4CExtra_T_24 = bits(_reduced4CExtra_T_16, 6, 0)
node _reduced4CExtra_T_25 = shl(_reduced4CExtra_T_24, 1)
node _reduced4CExtra_T_26 = xor(_reduced4CExtra_T_16, _reduced4CExtra_T_25)
node _reduced4CExtra_T_27 = shr(_reduced4CExtra_T_23, 1)
node _reduced4CExtra_T_28 = and(_reduced4CExtra_T_27, _reduced4CExtra_T_26)
node _reduced4CExtra_T_29 = bits(_reduced4CExtra_T_23, 6, 0)
node _reduced4CExtra_T_30 = shl(_reduced4CExtra_T_29, 1)
node _reduced4CExtra_T_31 = not(_reduced4CExtra_T_26)
node _reduced4CExtra_T_32 = and(_reduced4CExtra_T_30, _reduced4CExtra_T_31)
node _reduced4CExtra_T_33 = or(_reduced4CExtra_T_28, _reduced4CExtra_T_32)
node _reduced4CExtra_T_34 = bits(_reduced4CExtra_T_3, 12, 8)
node _reduced4CExtra_T_35 = bits(_reduced4CExtra_T_34, 3, 0)
node _reduced4CExtra_T_36 = bits(_reduced4CExtra_T_35, 1, 0)
node _reduced4CExtra_T_37 = bits(_reduced4CExtra_T_36, 0, 0)
node _reduced4CExtra_T_38 = bits(_reduced4CExtra_T_36, 1, 1)
node _reduced4CExtra_T_39 = cat(_reduced4CExtra_T_37, _reduced4CExtra_T_38)
node _reduced4CExtra_T_40 = bits(_reduced4CExtra_T_35, 3, 2)
node _reduced4CExtra_T_41 = bits(_reduced4CExtra_T_40, 0, 0)
node _reduced4CExtra_T_42 = bits(_reduced4CExtra_T_40, 1, 1)
node _reduced4CExtra_T_43 = cat(_reduced4CExtra_T_41, _reduced4CExtra_T_42)
node _reduced4CExtra_T_44 = cat(_reduced4CExtra_T_39, _reduced4CExtra_T_43)
node _reduced4CExtra_T_45 = bits(_reduced4CExtra_T_34, 4, 4)
node _reduced4CExtra_T_46 = cat(_reduced4CExtra_T_44, _reduced4CExtra_T_45)
node _reduced4CExtra_T_47 = cat(_reduced4CExtra_T_33, _reduced4CExtra_T_46)
node _reduced4CExtra_T_48 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_47)
node reduced4CExtra = orr(_reduced4CExtra_T_48)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 106, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<7>(0h35)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 5, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 161, 107)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e11_s53_3( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [64:0] io_a, // @[MulAddRecFN.scala:74:16]
input [64:0] io_b, // @[MulAddRecFN.scala:74:16]
input [64:0] io_c, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [105:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [5:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [54:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [7:0] _reduced4CExtra_T_6 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_5 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_11 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_14 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_15 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_16 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_21 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_24 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_25 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_26 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_31 = 8'hAA; // @[primitives.scala:77:20]
wire [105:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [5:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [54:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [54:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [105:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawC_exp = io_c_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawC_out_sig_T_2 = io_c_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [13:0] _sExpAlignedProd_T = {rawA_sExp[12], rawA_sExp} + {rawB_sExp[12], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [14:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[13], _sExpAlignedProd_T} - 15'h7C8; // @[MulAddRecFN.scala:100:{19,32}]
wire [13:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[13:0]; // @[MulAddRecFN.scala:100:32]
wire [13:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [14:0] _GEN = {sExpAlignedProd[13], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [14:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[12]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [13:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[13:0]; // @[MulAddRecFN.scala:106:42]
wire [13:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [12:0] posNatCAlignDist = sNatCAlignDist[12:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 14'sh0; // @[MulAddRecFN.scala:106:42, :108:69, :130:11]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 13'h36; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 13'hA1; // @[MulAddRecFN.scala:107:42, :114:34]
wire [7:0] _CAlignDist_T_1 = posNatCAlignDist[7:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [7:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 8'hA1; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [53:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [110:0] _mainAlignedSigC_T_2 = {111{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [164:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [164:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [164:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_7; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_8; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_9; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_10; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_11; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_12; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_13; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[27:24]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_7_T = _reduced4CExtra_T[31:28]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_7_T_1 = |_reduced4CExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_7 = _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_8_T = _reduced4CExtra_T[35:32]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_8_T_1 = |_reduced4CExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_8 = _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_9_T = _reduced4CExtra_T[39:36]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_9_T_1 = |_reduced4CExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_9 = _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_10_T = _reduced4CExtra_T[43:40]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_10_T_1 = |_reduced4CExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_10 = _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_11_T = _reduced4CExtra_T[47:44]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_11_T_1 = |_reduced4CExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_11 = _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_12_T = _reduced4CExtra_T[51:48]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_12_T_1 = |_reduced4CExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_12 = _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54]
wire [1:0] _reduced4CExtra_reducedVec_13_T = _reduced4CExtra_T[53:52]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_13_T_1 = |_reduced4CExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_13 = _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo_lo = {reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_lo_hi = {reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_lo_lo}; // @[primitives.scala:124:20]
wire [1:0] reduced4CExtra_hi_lo_hi = {reduced4CExtra_reducedVec_9, reduced4CExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_hi_lo = {reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_lo = {reduced4CExtra_reducedVec_11, reduced4CExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_hi = {reduced4CExtra_reducedVec_13, reduced4CExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi_hi = {reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [13:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [5:0] _reduced4CExtra_T_2 = CAlignDist[7:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [12:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[36:24]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_7 = _reduced4CExtra_T_4[7:4]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_8 = {4'h0, _reduced4CExtra_T_7}; // @[primitives.scala:77:20, :120:54]
wire [3:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_10 = {_reduced4CExtra_T_9, 4'h0}; // @[primitives.scala:77:20, :120:54]
wire [7:0] _reduced4CExtra_T_12 = _reduced4CExtra_T_10 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_13 = _reduced4CExtra_T_8 | _reduced4CExtra_T_12; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_17 = _reduced4CExtra_T_13[7:2]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_18 = {2'h0, _reduced4CExtra_T_17 & 6'h33}; // @[primitives.scala:77:20, :123:57]
wire [5:0] _reduced4CExtra_T_19 = _reduced4CExtra_T_13[5:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_20 = {_reduced4CExtra_T_19, 2'h0}; // @[primitives.scala:77:20, :123:57]
wire [7:0] _reduced4CExtra_T_22 = _reduced4CExtra_T_20 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_23 = _reduced4CExtra_T_18 | _reduced4CExtra_T_22; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_27 = _reduced4CExtra_T_23[7:1]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_28 = {1'h0, _reduced4CExtra_T_27 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_29 = _reduced4CExtra_T_23[6:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_30 = {_reduced4CExtra_T_29, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_32 = _reduced4CExtra_T_30 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_33 = _reduced4CExtra_T_28 | _reduced4CExtra_T_32; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_34 = _reduced4CExtra_T_3[12:8]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_35 = _reduced4CExtra_T_34[3:0]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_36 = _reduced4CExtra_T_35[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_37 = _reduced4CExtra_T_36[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_38 = _reduced4CExtra_T_36[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_39 = {_reduced4CExtra_T_37, _reduced4CExtra_T_38}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_40 = _reduced4CExtra_T_35[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_41 = _reduced4CExtra_T_40[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_42 = _reduced4CExtra_T_40[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_43 = {_reduced4CExtra_T_41, _reduced4CExtra_T_42}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_44 = {_reduced4CExtra_T_39, _reduced4CExtra_T_43}; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_45 = _reduced4CExtra_T_34[4]; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_46 = {_reduced4CExtra_T_44, _reduced4CExtra_T_45}; // @[primitives.scala:77:20]
wire [12:0] _reduced4CExtra_T_47 = {_reduced4CExtra_T_33, _reduced4CExtra_T_46}; // @[primitives.scala:77:20]
wire [13:0] _reduced4CExtra_T_48 = {1'h0, _reduced4CExtra_T_1[12:0] & _reduced4CExtra_T_47}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_48; // @[MulAddRecFN.scala:122:68, :130:11]
wire [161:0] _alignedSigC_T = mainAlignedSigC[164:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [161:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [162:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[106:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [14:0] _io_toPostMul_sExpSum_T = _GEN - 15'h35; // @[MulAddRecFN.scala:106:42, :158:53]
wire [13:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[13:0]; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[12], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[12:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[5:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[161:107]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x2 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[2], out : { sync : UInt<1>[2]}}
wire nodeIn : UInt<1>[2]
invalidate nodeIn[0]
invalidate nodeIn[1]
wire nodeOut : { sync : UInt<1>[2]}
invalidate nodeOut.sync[0]
invalidate nodeOut.sync[1]
connect auto.out, nodeOut
connect nodeIn, auto.in
node _T = cat(nodeIn[1], nodeIn[0])
inst reg of AsyncResetRegVec_w2_i0
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, _T
connect reg.io.en, UInt<1>(0h1)
node _T_1 = bits(reg.io.q, 0, 0)
node _T_2 = bits(reg.io.q, 1, 1)
connect nodeOut.sync[0], _T_1
connect nodeOut.sync[1], _T_2 | module IntSyncCrossingSource_n1x2( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
input auto_in_1, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_1 // @[LazyModuleImp.scala:107:25]
);
wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21]
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire nodeOut_sync_1; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
wire auto_out_sync_1_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9]
assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21]
AsyncResetRegVec_w2_i0 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36]
.io_q (_reg_io_q)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Tile_1 :
input clock : Clock
input reset : Reset
output io : { flip in_a : { bits : UInt<32>}[1], flip in_b : { bits : UInt<32>}[1], flip in_d : { bits : UInt<32>}[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<4>[1], flip in_last : UInt<1>[1], out_a : { bits : UInt<32>}[1], out_c : { bits : UInt<32>}[1], out_b : { bits : UInt<32>}[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<4>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_17
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a.bits, io.in_a[0].bits
connect tile_0_0.io.in_b.bits, io.in_b[0].bits
connect tile_0_0.io.in_d.bits, io.in_d[0].bits
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_1( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [3:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [31:0] io_out_a_0_bits, // @[Tile.scala:17:14]
output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14]
output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [3:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [31:0] io_out_a_0_bits_0; // @[Tile.scala:16:7]
wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7]
wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_17 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7]
.io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7]
.io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7]
.io_out_a_bits (io_out_a_0_bits_0),
.io_out_b_bits (io_out_b_0_bits_0),
.io_out_c_bits (io_out_c_0_bits_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0_bits = io_out_a_0_bits_0; // @[Tile.scala:16:7]
assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7]
assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_5 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_5
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn_1.flit.bits.egress_id
invalidate ingressNodesIn_1.flit.bits.payload
invalidate ingressNodesIn_1.flit.bits.tail
invalidate ingressNodesIn_1.flit.bits.head
invalidate ingressNodesIn_1.flit.valid
invalidate ingressNodesIn_1.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_1.flit.bits.ingress_id
invalidate egressNodesOut_1.flit.bits.payload
invalidate egressNodesOut_1.flit.bits.tail
invalidate egressNodesOut_1.flit.bits.head
invalidate egressNodesOut_1.flit.valid
invalidate egressNodesOut_1.flit.ready
wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_2.flit.bits.ingress_id
invalidate egressNodesOut_2.flit.bits.payload
invalidate egressNodesOut_2.flit.bits.tail
invalidate egressNodesOut_2.flit.bits.head
invalidate egressNodesOut_2.flit.valid
invalidate egressNodesOut_2.flit.ready
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in_0
connect ingressNodesIn_1, auto.ingress_nodes_in_1
connect auto.egress_nodes_out_0, egressNodesOut
connect auto.egress_nodes_out_1, egressNodesOut_1
connect auto.egress_nodes_out_2, egressNodesOut_2
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_4 of InputUnit_5
connect input_unit_0_from_4.clock, clock
connect input_unit_0_from_4.reset, reset
inst ingress_unit_1_from_17 of IngressUnit_17
connect ingress_unit_1_from_17.clock, clock
connect ingress_unit_1_from_17.reset, reset
inst ingress_unit_2_from_18 of IngressUnit_18
connect ingress_unit_2_from_18.clock, clock
connect ingress_unit_2_from_18.reset, reset
inst output_unit_0_to_6 of OutputUnit_5
connect output_unit_0_to_6.clock, clock
connect output_unit_0_to_6.reset, reset
inst egress_unit_1_to_13 of EgressUnit_13
connect egress_unit_1_to_13.clock, clock
connect egress_unit_1_to_13.reset, reset
inst egress_unit_2_to_14 of EgressUnit_14
connect egress_unit_2_to_14.clock, clock
connect egress_unit_2_to_14.reset, reset
inst egress_unit_3_to_15 of EgressUnit_15
connect egress_unit_3_to_15.clock, clock
connect egress_unit_3_to_15.reset, reset
inst switch of Switch_5
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_5
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_5
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_5
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_4.io.in, destNodesIn
connect ingress_unit_1_from_17.io.in, ingressNodesIn.flit
connect ingress_unit_2_from_18.io.in, ingressNodesIn_1.flit
connect output_unit_0_to_6.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_6.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_6.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_13.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_13.io.out.valid
connect egress_unit_1_to_13.io.out.ready, egressNodesOut.flit.ready
connect egressNodesOut_1.flit.bits, egress_unit_2_to_14.io.out.bits
connect egressNodesOut_1.flit.valid, egress_unit_2_to_14.io.out.valid
connect egress_unit_2_to_14.io.out.ready, egressNodesOut_1.flit.ready
connect egressNodesOut_2.flit.bits, egress_unit_3_to_15.io.out.bits
connect egressNodesOut_2.flit.valid, egress_unit_3_to_15.io.out.valid
connect egress_unit_3_to_15.io.out.ready, egressNodesOut_2.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_4.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_17.io.router_req
connect route_computer.io.req.`2`, ingress_unit_2_from_18.io.router_req
connect input_unit_0_from_4.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_17.io.router_resp, route_computer.io.resp.`1`
connect ingress_unit_2_from_18.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_4.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_17.io.vcalloc_req
connect vc_allocator.io.req.`2`, ingress_unit_2_from_18.io.vcalloc_req
connect input_unit_0_from_4.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_17.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect ingress_unit_2_from_18.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_6.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_13.io.allocs, vc_allocator.io.out_allocs.`1`
connect egress_unit_2_to_14.io.allocs, vc_allocator.io.out_allocs.`2`
connect egress_unit_3_to_15.io.allocs, vc_allocator.io.out_allocs.`3`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_6.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_6.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_6.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_6.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_6.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_6.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_6.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_6.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_6.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_6.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_6.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_6.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_6.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_6.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_6.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_6.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_6.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_6.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_6.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_6.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_6.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_6.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_6.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_6.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_6.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_6.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_6.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_6.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_6.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_6.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_6.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_6.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_6.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_6.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_6.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_6.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_6.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_6.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_6.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_6.io.channel_status[7].occupied
connect vc_allocator.io.channel_status.`0`[8].flow.egress_node_id, output_unit_0_to_6.io.channel_status[8].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[8].flow.egress_node, output_unit_0_to_6.io.channel_status[8].flow.egress_node
connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[8].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[8].flow.ingress_node, output_unit_0_to_6.io.channel_status[8].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[8].flow.vnet_id, output_unit_0_to_6.io.channel_status[8].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[8].occupied, output_unit_0_to_6.io.channel_status[8].occupied
connect vc_allocator.io.channel_status.`0`[9].flow.egress_node_id, output_unit_0_to_6.io.channel_status[9].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[9].flow.egress_node, output_unit_0_to_6.io.channel_status[9].flow.egress_node
connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[9].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[9].flow.ingress_node, output_unit_0_to_6.io.channel_status[9].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[9].flow.vnet_id, output_unit_0_to_6.io.channel_status[9].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[9].occupied, output_unit_0_to_6.io.channel_status[9].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_13.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_13.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_13.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_13.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_13.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_13.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_14.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_14.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_14.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_14.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_14.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_14.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_15.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_15.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_15.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_15.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_15.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_15.io.channel_status[0].occupied
connect input_unit_0_from_4.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0]
connect input_unit_0_from_4.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1]
connect input_unit_0_from_4.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2]
connect input_unit_0_from_4.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3]
connect input_unit_0_from_4.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4]
connect input_unit_0_from_4.io.out_credit_available.`0`[5], output_unit_0_to_6.io.credit_available[5]
connect input_unit_0_from_4.io.out_credit_available.`0`[6], output_unit_0_to_6.io.credit_available[6]
connect input_unit_0_from_4.io.out_credit_available.`0`[7], output_unit_0_to_6.io.credit_available[7]
connect input_unit_0_from_4.io.out_credit_available.`0`[8], output_unit_0_to_6.io.credit_available[8]
connect input_unit_0_from_4.io.out_credit_available.`0`[9], output_unit_0_to_6.io.credit_available[9]
connect input_unit_0_from_4.io.out_credit_available.`1`[0], egress_unit_1_to_13.io.credit_available[0]
connect input_unit_0_from_4.io.out_credit_available.`2`[0], egress_unit_2_to_14.io.credit_available[0]
connect input_unit_0_from_4.io.out_credit_available.`3`[0], egress_unit_3_to_15.io.credit_available[0]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[5], output_unit_0_to_6.io.credit_available[5]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[6], output_unit_0_to_6.io.credit_available[6]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[7], output_unit_0_to_6.io.credit_available[7]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[8], output_unit_0_to_6.io.credit_available[8]
connect ingress_unit_1_from_17.io.out_credit_available.`0`[9], output_unit_0_to_6.io.credit_available[9]
connect ingress_unit_1_from_17.io.out_credit_available.`1`[0], egress_unit_1_to_13.io.credit_available[0]
connect ingress_unit_1_from_17.io.out_credit_available.`2`[0], egress_unit_2_to_14.io.credit_available[0]
connect ingress_unit_1_from_17.io.out_credit_available.`3`[0], egress_unit_3_to_15.io.credit_available[0]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[5], output_unit_0_to_6.io.credit_available[5]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[6], output_unit_0_to_6.io.credit_available[6]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[7], output_unit_0_to_6.io.credit_available[7]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[8], output_unit_0_to_6.io.credit_available[8]
connect ingress_unit_2_from_18.io.out_credit_available.`0`[9], output_unit_0_to_6.io.credit_available[9]
connect ingress_unit_2_from_18.io.out_credit_available.`1`[0], egress_unit_1_to_13.io.credit_available[0]
connect ingress_unit_2_from_18.io.out_credit_available.`2`[0], egress_unit_2_to_14.io.credit_available[0]
connect ingress_unit_2_from_18.io.out_credit_available.`3`[0], egress_unit_3_to_15.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_4.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_17.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_18.io.salloc_req[0]
connect output_unit_0_to_6.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_6.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_6.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_6.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_6.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_6.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_6.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_6.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_6.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_6.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_6.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_6.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect output_unit_0_to_6.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail
connect output_unit_0_to_6.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc
connect output_unit_0_to_6.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail
connect output_unit_0_to_6.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc
connect output_unit_0_to_6.io.credit_alloc[8].tail, switch_allocator.io.credit_alloc.`0`[8].tail
connect output_unit_0_to_6.io.credit_alloc[8].alloc, switch_allocator.io.credit_alloc.`0`[8].alloc
connect output_unit_0_to_6.io.credit_alloc[9].tail, switch_allocator.io.credit_alloc.`0`[9].tail
connect output_unit_0_to_6.io.credit_alloc[9].alloc, switch_allocator.io.credit_alloc.`0`[9].alloc
connect egress_unit_1_to_13.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_13.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect egress_unit_2_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect egress_unit_2_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect egress_unit_3_to_15.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail
connect egress_unit_3_to_15.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_4.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_17.io.out[0]
connect switch.io.in.`2`[0], ingress_unit_2_from_18.io.out[0]
connect output_unit_0_to_6.io.in, switch.io.out.`0`
connect egress_unit_1_to_13.io.in, switch.io.out.`1`
connect egress_unit_2_to_14.io.in, switch.io.out.`2`
connect egress_unit_3_to_15.io.in, switch.io.out.`3`
reg REG : { `3` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0]
connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0]
connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0]
connect input_unit_0_from_4.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_17.io.block, UInt<1>(0h0)
connect ingress_unit_2_from_18.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_4.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_17.io.debug.va_stall
connect debugNodeOut.va_stall[2], ingress_unit_2_from_18.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_4.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_17.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], ingress_unit_2_from_18.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_15
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 4 5 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i17 5 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d i18 5 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d 5 e13 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29
node _T_38 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid)
regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_8 = add(util_ctr_4, _T_38)
node _util_ctr_T_9 = tail(_util_ctr_T_8, 1)
connect util_ctr_4, _util_ctr_T_9
node _fired_T_4 = or(fired_4, _T_38)
connect fired_4, _fired_T_4
node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_41 = tail(_T_40, 1)
node _T_42 = eq(debug_sample, _T_41)
node _T_43 = and(_T_39, _T_42)
node _T_44 = and(_T_43, fired_4)
when _T_44 :
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "nocsample %d 5 e14 %d\n", debug_tsc, util_ctr_4) : printf_4
connect fired_4, _T_38
node _T_47 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid)
regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_10 = add(util_ctr_5, _T_47)
node _util_ctr_T_11 = tail(_util_ctr_T_10, 1)
connect util_ctr_5, _util_ctr_T_11
node _fired_T_5 = or(fired_5, _T_47)
connect fired_5, _fired_T_5
node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_50 = tail(_T_49, 1)
node _T_51 = eq(debug_sample, _T_50)
node _T_52 = and(_T_48, _T_51)
node _T_53 = and(_T_52, fired_5)
when _T_53 :
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "nocsample %d 5 e15 %d\n", debug_tsc, util_ctr_5) : printf_5
connect fired_5, _T_47 | module Router_5( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [3:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_8; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_9; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_8; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_9; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_15_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_15_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_15_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_2_to_14_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_14_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_14_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_13_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_13_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_13_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_6_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_8; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_9; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_8_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_9_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_2_from_18_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_18_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_18_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_18_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_18_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_18_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_18_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_18_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_18_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_18_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_17_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_17_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_17_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_17_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_17_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_17_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_17_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _input_unit_0_from_4_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_4_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_17_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_18_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_3_0_2_0; // @[Router.scala:178:14]
reg REG_3_0_1_0; // @[Router.scala:178:14]
reg REG_3_0_0_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_19 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_19
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_64
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_19( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_19 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_64 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BIMBranchPredictorBank_1 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 3)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 3)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
wire s2_meta : { bims : UInt<2>[4]}
node lo = cat(s2_meta.bims[1], s2_meta.bims[0])
node hi = cat(s2_meta.bims[3], s2_meta.bims[2])
node _T = cat(hi, lo)
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<11>, clock, reset, UInt<11>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T_1 = eq(reset_idx, UInt<11>(0h7ff))
when _T_1 :
connect doing_reset, UInt<1>(0h0)
smem data : UInt<2>[4] [2048]
wire _s2_req_rdata_WIRE : UInt<37>
invalidate _s2_req_rdata_WIRE
when io.f0_valid :
connect _s2_req_rdata_WIRE, s0_idx
node _s2_req_rdata_T = bits(_s2_req_rdata_WIRE, 10, 0)
read mport s2_req_rdata_MPORT = data[_s2_req_rdata_T], clock
reg s2_req_rdata : UInt<2>[4], clock
connect s2_req_rdata, s2_req_rdata_MPORT
wire s2_resp : UInt<1>[4]
node _s2_resp_0_T = bits(s2_req_rdata[0], 1, 1)
node _s2_resp_0_T_1 = and(s2_valid, _s2_resp_0_T)
node _s2_resp_0_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_resp_0_T_3 = and(_s2_resp_0_T_1, _s2_resp_0_T_2)
connect s2_resp[0], _s2_resp_0_T_3
connect s2_meta.bims[0], s2_req_rdata[0]
node _s2_resp_1_T = bits(s2_req_rdata[1], 1, 1)
node _s2_resp_1_T_1 = and(s2_valid, _s2_resp_1_T)
node _s2_resp_1_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_resp_1_T_3 = and(_s2_resp_1_T_1, _s2_resp_1_T_2)
connect s2_resp[1], _s2_resp_1_T_3
connect s2_meta.bims[1], s2_req_rdata[1]
node _s2_resp_2_T = bits(s2_req_rdata[2], 1, 1)
node _s2_resp_2_T_1 = and(s2_valid, _s2_resp_2_T)
node _s2_resp_2_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_resp_2_T_3 = and(_s2_resp_2_T_1, _s2_resp_2_T_2)
connect s2_resp[2], _s2_resp_2_T_3
connect s2_meta.bims[2], s2_req_rdata[2]
node _s2_resp_3_T = bits(s2_req_rdata[3], 1, 1)
node _s2_resp_3_T_1 = and(s2_valid, _s2_resp_3_T)
node _s2_resp_3_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_resp_3_T_3 = and(_s2_resp_3_T_1, _s2_resp_3_T_2)
connect s2_resp[3], _s2_resp_3_T_3
connect s2_meta.bims[3], s2_req_rdata[3]
wire s1_update_wdata : UInt<2>[4]
wire s1_update_wmask : UInt<1>[4]
wire s1_update_meta : { bims : UInt<2>[4]}
wire _s1_update_meta_WIRE : UInt<8>
connect _s1_update_meta_WIRE, s1_update.bits.meta
node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 1, 0)
connect s1_update_meta.bims[0], _s1_update_meta_T
node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 2)
connect s1_update_meta.bims[1], _s1_update_meta_T_1
node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 5, 4)
connect s1_update_meta.bims[2], _s1_update_meta_T_2
node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 6)
connect s1_update_meta.bims[3], _s1_update_meta_T_3
reg wrbypass_idxs : UInt<11>[2], clock
reg wrbypass : UInt<2>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = bits(s1_update_idx, 10, 0)
node _wrbypass_hits_T_2 = eq(wrbypass_idxs[0], _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = and(_wrbypass_hits_T, _wrbypass_hits_T_2)
node _wrbypass_hits_T_4 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_5 = bits(s1_update_idx, 10, 0)
node _wrbypass_hits_T_6 = eq(wrbypass_idxs[1], _wrbypass_hits_T_5)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_4, _wrbypass_hits_T_6)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_3
connect wrbypass_hits[1], _wrbypass_hits_T_7
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
connect s1_update_wmask[0], UInt<1>(0h0)
invalidate s1_update_wdata[0]
node _update_pc_T = add(s1_update.bits.pc, UInt<1>(0h0))
node update_pc = tail(_update_pc_T, 1)
node _T_2 = bits(s1_update.bits.br_mask, 0, 0)
node _T_3 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0))
node _T_4 = and(s1_update.bits.cfi_idx.valid, _T_3)
node _T_5 = or(_T_2, _T_4)
when _T_5 :
node _was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0))
node _was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _was_taken_T)
node _was_taken_T_2 = bits(s1_update.bits.br_mask, 0, 0)
node _was_taken_T_3 = and(s1_update.bits.cfi_is_br, _was_taken_T_2)
node _was_taken_T_4 = and(_was_taken_T_3, s1_update.bits.cfi_taken)
node _was_taken_T_5 = or(_was_taken_T_4, s1_update.bits.cfi_is_jal)
node was_taken = and(_was_taken_T_1, _was_taken_T_5)
node old_bim_value = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][0], s1_update_meta.bims[0])
connect s1_update_wmask[0], UInt<1>(0h1)
node s1_update_wdata_0_old_bim_sat_taken = eq(old_bim_value, UInt<2>(0h3))
node s1_update_wdata_0_old_bim_sat_ntaken = eq(old_bim_value, UInt<1>(0h0))
node _s1_update_wdata_0_T = and(s1_update_wdata_0_old_bim_sat_taken, was_taken)
node _s1_update_wdata_0_T_1 = eq(was_taken, UInt<1>(0h0))
node _s1_update_wdata_0_T_2 = and(s1_update_wdata_0_old_bim_sat_ntaken, _s1_update_wdata_0_T_1)
node _s1_update_wdata_0_T_3 = add(old_bim_value, UInt<1>(0h1))
node _s1_update_wdata_0_T_4 = tail(_s1_update_wdata_0_T_3, 1)
node _s1_update_wdata_0_T_5 = sub(old_bim_value, UInt<1>(0h1))
node _s1_update_wdata_0_T_6 = tail(_s1_update_wdata_0_T_5, 1)
node _s1_update_wdata_0_T_7 = mux(was_taken, _s1_update_wdata_0_T_4, _s1_update_wdata_0_T_6)
node _s1_update_wdata_0_T_8 = mux(_s1_update_wdata_0_T_2, UInt<1>(0h0), _s1_update_wdata_0_T_7)
node _s1_update_wdata_0_T_9 = mux(_s1_update_wdata_0_T, UInt<2>(0h3), _s1_update_wdata_0_T_8)
connect s1_update_wdata[0], _s1_update_wdata_0_T_9
connect s1_update_wmask[1], UInt<1>(0h0)
invalidate s1_update_wdata[1]
node _update_pc_T_1 = add(s1_update.bits.pc, UInt<2>(0h2))
node update_pc_1 = tail(_update_pc_T_1, 1)
node _T_6 = bits(s1_update.bits.br_mask, 1, 1)
node _T_7 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1))
node _T_8 = and(s1_update.bits.cfi_idx.valid, _T_7)
node _T_9 = or(_T_6, _T_8)
when _T_9 :
node _was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1))
node _was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_6)
node _was_taken_T_8 = bits(s1_update.bits.br_mask, 1, 1)
node _was_taken_T_9 = and(s1_update.bits.cfi_is_br, _was_taken_T_8)
node _was_taken_T_10 = and(_was_taken_T_9, s1_update.bits.cfi_taken)
node _was_taken_T_11 = or(_was_taken_T_10, s1_update.bits.cfi_is_jal)
node was_taken_1 = and(_was_taken_T_7, _was_taken_T_11)
node old_bim_value_1 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][1], s1_update_meta.bims[1])
connect s1_update_wmask[1], UInt<1>(0h1)
node s1_update_wdata_1_old_bim_sat_taken = eq(old_bim_value_1, UInt<2>(0h3))
node s1_update_wdata_1_old_bim_sat_ntaken = eq(old_bim_value_1, UInt<1>(0h0))
node _s1_update_wdata_1_T = and(s1_update_wdata_1_old_bim_sat_taken, was_taken_1)
node _s1_update_wdata_1_T_1 = eq(was_taken_1, UInt<1>(0h0))
node _s1_update_wdata_1_T_2 = and(s1_update_wdata_1_old_bim_sat_ntaken, _s1_update_wdata_1_T_1)
node _s1_update_wdata_1_T_3 = add(old_bim_value_1, UInt<1>(0h1))
node _s1_update_wdata_1_T_4 = tail(_s1_update_wdata_1_T_3, 1)
node _s1_update_wdata_1_T_5 = sub(old_bim_value_1, UInt<1>(0h1))
node _s1_update_wdata_1_T_6 = tail(_s1_update_wdata_1_T_5, 1)
node _s1_update_wdata_1_T_7 = mux(was_taken_1, _s1_update_wdata_1_T_4, _s1_update_wdata_1_T_6)
node _s1_update_wdata_1_T_8 = mux(_s1_update_wdata_1_T_2, UInt<1>(0h0), _s1_update_wdata_1_T_7)
node _s1_update_wdata_1_T_9 = mux(_s1_update_wdata_1_T, UInt<2>(0h3), _s1_update_wdata_1_T_8)
connect s1_update_wdata[1], _s1_update_wdata_1_T_9
connect s1_update_wmask[2], UInt<1>(0h0)
invalidate s1_update_wdata[2]
node _update_pc_T_2 = add(s1_update.bits.pc, UInt<3>(0h4))
node update_pc_2 = tail(_update_pc_T_2, 1)
node _T_10 = bits(s1_update.bits.br_mask, 2, 2)
node _T_11 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2))
node _T_12 = and(s1_update.bits.cfi_idx.valid, _T_11)
node _T_13 = or(_T_10, _T_12)
when _T_13 :
node _was_taken_T_12 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2))
node _was_taken_T_13 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_12)
node _was_taken_T_14 = bits(s1_update.bits.br_mask, 2, 2)
node _was_taken_T_15 = and(s1_update.bits.cfi_is_br, _was_taken_T_14)
node _was_taken_T_16 = and(_was_taken_T_15, s1_update.bits.cfi_taken)
node _was_taken_T_17 = or(_was_taken_T_16, s1_update.bits.cfi_is_jal)
node was_taken_2 = and(_was_taken_T_13, _was_taken_T_17)
node old_bim_value_2 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][2], s1_update_meta.bims[2])
connect s1_update_wmask[2], UInt<1>(0h1)
node s1_update_wdata_2_old_bim_sat_taken = eq(old_bim_value_2, UInt<2>(0h3))
node s1_update_wdata_2_old_bim_sat_ntaken = eq(old_bim_value_2, UInt<1>(0h0))
node _s1_update_wdata_2_T = and(s1_update_wdata_2_old_bim_sat_taken, was_taken_2)
node _s1_update_wdata_2_T_1 = eq(was_taken_2, UInt<1>(0h0))
node _s1_update_wdata_2_T_2 = and(s1_update_wdata_2_old_bim_sat_ntaken, _s1_update_wdata_2_T_1)
node _s1_update_wdata_2_T_3 = add(old_bim_value_2, UInt<1>(0h1))
node _s1_update_wdata_2_T_4 = tail(_s1_update_wdata_2_T_3, 1)
node _s1_update_wdata_2_T_5 = sub(old_bim_value_2, UInt<1>(0h1))
node _s1_update_wdata_2_T_6 = tail(_s1_update_wdata_2_T_5, 1)
node _s1_update_wdata_2_T_7 = mux(was_taken_2, _s1_update_wdata_2_T_4, _s1_update_wdata_2_T_6)
node _s1_update_wdata_2_T_8 = mux(_s1_update_wdata_2_T_2, UInt<1>(0h0), _s1_update_wdata_2_T_7)
node _s1_update_wdata_2_T_9 = mux(_s1_update_wdata_2_T, UInt<2>(0h3), _s1_update_wdata_2_T_8)
connect s1_update_wdata[2], _s1_update_wdata_2_T_9
connect s1_update_wmask[3], UInt<1>(0h0)
invalidate s1_update_wdata[3]
node _update_pc_T_3 = add(s1_update.bits.pc, UInt<3>(0h6))
node update_pc_3 = tail(_update_pc_T_3, 1)
node _T_14 = bits(s1_update.bits.br_mask, 3, 3)
node _T_15 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3))
node _T_16 = and(s1_update.bits.cfi_idx.valid, _T_15)
node _T_17 = or(_T_14, _T_16)
when _T_17 :
node _was_taken_T_18 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3))
node _was_taken_T_19 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_18)
node _was_taken_T_20 = bits(s1_update.bits.br_mask, 3, 3)
node _was_taken_T_21 = and(s1_update.bits.cfi_is_br, _was_taken_T_20)
node _was_taken_T_22 = and(_was_taken_T_21, s1_update.bits.cfi_taken)
node _was_taken_T_23 = or(_was_taken_T_22, s1_update.bits.cfi_is_jal)
node was_taken_3 = and(_was_taken_T_19, _was_taken_T_23)
node old_bim_value_3 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][3], s1_update_meta.bims[3])
connect s1_update_wmask[3], UInt<1>(0h1)
node s1_update_wdata_3_old_bim_sat_taken = eq(old_bim_value_3, UInt<2>(0h3))
node s1_update_wdata_3_old_bim_sat_ntaken = eq(old_bim_value_3, UInt<1>(0h0))
node _s1_update_wdata_3_T = and(s1_update_wdata_3_old_bim_sat_taken, was_taken_3)
node _s1_update_wdata_3_T_1 = eq(was_taken_3, UInt<1>(0h0))
node _s1_update_wdata_3_T_2 = and(s1_update_wdata_3_old_bim_sat_ntaken, _s1_update_wdata_3_T_1)
node _s1_update_wdata_3_T_3 = add(old_bim_value_3, UInt<1>(0h1))
node _s1_update_wdata_3_T_4 = tail(_s1_update_wdata_3_T_3, 1)
node _s1_update_wdata_3_T_5 = sub(old_bim_value_3, UInt<1>(0h1))
node _s1_update_wdata_3_T_6 = tail(_s1_update_wdata_3_T_5, 1)
node _s1_update_wdata_3_T_7 = mux(was_taken_3, _s1_update_wdata_3_T_4, _s1_update_wdata_3_T_6)
node _s1_update_wdata_3_T_8 = mux(_s1_update_wdata_3_T_2, UInt<1>(0h0), _s1_update_wdata_3_T_7)
node _s1_update_wdata_3_T_9 = mux(_s1_update_wdata_3_T, UInt<2>(0h3), _s1_update_wdata_3_T_8)
connect s1_update_wdata[3], _s1_update_wdata_3_T_9
node _T_18 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_19 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_20 = or(_T_18, _T_19)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = and(s1_update.valid, _T_21)
node _T_23 = or(doing_reset, _T_22)
when _T_23 :
node _T_24 = mux(doing_reset, reset_idx, s1_update_idx)
wire _WIRE : UInt<2>[4]
connect _WIRE[0], UInt<2>(0h2)
connect _WIRE[1], UInt<2>(0h2)
connect _WIRE[2], UInt<2>(0h2)
connect _WIRE[3], UInt<2>(0h2)
node _T_25 = mux(doing_reset, _WIRE, s1_update_wdata)
node _T_26 = not(UInt<4>(0h0))
node lo_1 = cat(s1_update_wmask[1], s1_update_wmask[0])
node hi_1 = cat(s1_update_wmask[3], s1_update_wmask[2])
node _T_27 = cat(hi_1, lo_1)
node _T_28 = mux(doing_reset, _T_26, _T_27)
node _T_29 = bits(_T_28, 0, 0)
node _T_30 = bits(_T_28, 1, 1)
node _T_31 = bits(_T_28, 2, 2)
node _T_32 = bits(_T_28, 3, 3)
node _T_33 = or(_T_24, UInt<11>(0h0))
node _T_34 = bits(_T_33, 10, 0)
write mport MPORT = data[_T_34], clock
when _T_29 :
connect MPORT[0], _T_25[0]
when _T_30 :
connect MPORT[1], _T_25[1]
when _T_31 :
connect MPORT[2], _T_25[2]
when _T_32 :
connect MPORT[3], _T_25[3]
node _T_35 = or(s1_update_wmask[0], s1_update_wmask[1])
node _T_36 = or(_T_35, s1_update_wmask[2])
node _T_37 = or(_T_36, s1_update_wmask[3])
node _T_38 = and(_T_37, s1_update.valid)
node _T_39 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_40 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_41 = or(_T_39, _T_40)
node _T_42 = eq(_T_41, UInt<1>(0h0))
node _T_43 = and(_T_38, _T_42)
when _T_43 :
when wrbypass_hit :
connect wrbypass[wrbypass_hit_idx], s1_update_wdata
else :
connect wrbypass[wrbypass_enq_idx], s1_update_wdata
connect wrbypass_idxs[wrbypass_enq_idx], s1_update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2
connect io.resp.f2[0].taken, s2_resp[0]
reg io_resp_f3_0_taken_REG : UInt<1>, clock
connect io_resp_f3_0_taken_REG, io.resp.f2[0].taken
connect io.resp.f3[0].taken, io_resp_f3_0_taken_REG
connect io.resp.f2[1].taken, s2_resp[1]
reg io_resp_f3_1_taken_REG : UInt<1>, clock
connect io_resp_f3_1_taken_REG, io.resp.f2[1].taken
connect io.resp.f3[1].taken, io_resp_f3_1_taken_REG
connect io.resp.f2[2].taken, s2_resp[2]
reg io_resp_f3_2_taken_REG : UInt<1>, clock
connect io_resp_f3_2_taken_REG, io.resp.f2[2].taken
connect io.resp.f3[2].taken, io_resp_f3_2_taken_REG
connect io.resp.f2[3].taken, s2_resp[3]
reg io_resp_f3_3_taken_REG : UInt<1>, clock
connect io_resp_f3_3_taken_REG, io.resp.f2[3].taken
connect io.resp.f3[3].taken, io_resp_f3_3_taken_REG
node io_f3_meta_lo = cat(s2_meta.bims[1], s2_meta.bims[0])
node io_f3_meta_hi = cat(s2_meta.bims[3], s2_meta.bims[2])
node _io_f3_meta_T = cat(io_f3_meta_hi, io_f3_meta_lo)
reg io_f3_meta_REG : UInt, clock
connect io_f3_meta_REG, _io_f3_meta_T
connect io.f3_meta, io_f3_meta_REG | module BIMBranchPredictorBank_1( // @[bim.scala:26:7]
input clock, // @[bim.scala:26:7]
input reset, // @[bim.scala:26:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire [1:0] data_MPORT_data_3; // @[bim.scala:112:10]
wire [1:0] data_MPORT_data_2; // @[bim.scala:112:10]
wire [1:0] data_MPORT_data_1; // @[bim.scala:112:10]
wire [1:0] data_MPORT_data_0; // @[bim.scala:112:10]
wire [7:0] _data_R0_data; // @[bim.scala:50:26]
wire io_f0_valid_0 = io_f0_valid; // @[bim.scala:26:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[bim.scala:26:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[bim.scala:26:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[bim.scala:26:7]
wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[bim.scala:26:7]
wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[bim.scala:26:7]
wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[bim.scala:26:7]
wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[bim.scala:26:7]
wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[bim.scala:26:7]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[bim.scala:26:7]
wire io_f3_fire_0 = io_f3_fire; // @[bim.scala:26:7]
wire io_update_valid_0 = io_update_valid; // @[bim.scala:26:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[bim.scala:26:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[bim.scala:26:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[bim.scala:26:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[bim.scala:26:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[bim.scala:26:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[bim.scala:26:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[bim.scala:26:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[bim.scala:26:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[bim.scala:26:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[bim.scala:26:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[bim.scala:26:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[bim.scala:26:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[bim.scala:26:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[bim.scala:26:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[bim.scala:26:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[bim.scala:26:7]
wire io_f1_lhist = 1'h0; // @[bim.scala:26:7]
wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[bim.scala:26:7]
wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[bim.scala:26:7]
wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[bim.scala:26:7]
wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[bim.scala:26:7]
wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[bim.scala:26:7]
wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[bim.scala:26:7]
wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[bim.scala:26:7]
wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[bim.scala:26:7]
wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[bim.scala:26:7]
wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[bim.scala:26:7]
wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[bim.scala:26:7]
wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[bim.scala:26:7]
wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[bim.scala:26:7]
wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[bim.scala:26:7]
wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[bim.scala:26:7]
wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[bim.scala:26:7]
wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[bim.scala:26:7]
wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[bim.scala:26:7]
wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[bim.scala:26:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[bim.scala:26:7]
wire s2_resp_0; // @[bim.scala:56:29]
wire s2_resp_1; // @[bim.scala:56:29]
wire s2_resp_2; // @[bim.scala:56:29]
wire s2_resp_3; // @[bim.scala:56:29]
wire io_resp_f2_0_taken_0; // @[bim.scala:26:7]
wire io_resp_f2_1_taken_0; // @[bim.scala:26:7]
wire io_resp_f2_2_taken_0; // @[bim.scala:26:7]
wire io_resp_f2_3_taken_0; // @[bim.scala:26:7]
wire io_resp_f3_0_taken_0; // @[bim.scala:26:7]
wire io_resp_f3_1_taken_0; // @[bim.scala:26:7]
wire io_resp_f3_2_taken_0; // @[bim.scala:26:7]
wire io_resp_f3_3_taken_0; // @[bim.scala:26:7]
wire [119:0] io_f3_meta_0; // @[bim.scala:26:7]
wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35]
wire [36:0] _s2_req_rdata_WIRE = s0_idx; // @[frontend.scala:162:35]
reg [36:0] s1_idx; // @[predictor.scala:163:29]
reg [36:0] s2_idx; // @[predictor.scala:164:29]
reg [36:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [36:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
wire [1:0] s2_meta_bims_0; // @[bim.scala:41:31]
wire [1:0] s2_meta_bims_1; // @[bim.scala:41:31]
wire [1:0] s2_meta_bims_2; // @[bim.scala:41:31]
wire [1:0] s2_meta_bims_3; // @[bim.scala:41:31]
wire [3:0] _GEN = {s2_meta_bims_1, s2_meta_bims_0}; // @[bim.scala:41:31, :42:35]
wire [3:0] lo; // @[bim.scala:42:35]
assign lo = _GEN; // @[bim.scala:42:35]
wire [3:0] io_f3_meta_lo; // @[bim.scala:130:33]
assign io_f3_meta_lo = _GEN; // @[bim.scala:42:35, :130:33]
wire [3:0] _GEN_0 = {s2_meta_bims_3, s2_meta_bims_2}; // @[bim.scala:41:31, :42:35]
wire [3:0] hi; // @[bim.scala:42:35]
assign hi = _GEN_0; // @[bim.scala:42:35]
wire [3:0] io_f3_meta_hi; // @[bim.scala:130:33]
assign io_f3_meta_hi = _GEN_0; // @[bim.scala:42:35, :130:33]
reg doing_reset; // @[bim.scala:44:28]
reg [10:0] reset_idx; // @[bim.scala:45:26]
wire [11:0] _reset_idx_T = {1'h0, reset_idx} + {11'h0, doing_reset}; // @[bim.scala:44:28, :45:26, :46:26]
wire [10:0] _reset_idx_T_1 = _reset_idx_T[10:0]; // @[bim.scala:46:26]
wire [10:0] _s2_req_rdata_T = _s2_req_rdata_WIRE[10:0]; // @[bim.scala:54:42]
reg [1:0] s2_req_rdata_0; // @[bim.scala:54:32]
assign s2_meta_bims_0 = s2_req_rdata_0; // @[bim.scala:41:31, :54:32]
reg [1:0] s2_req_rdata_1; // @[bim.scala:54:32]
assign s2_meta_bims_1 = s2_req_rdata_1; // @[bim.scala:41:31, :54:32]
reg [1:0] s2_req_rdata_2; // @[bim.scala:54:32]
assign s2_meta_bims_2 = s2_req_rdata_2; // @[bim.scala:41:31, :54:32]
reg [1:0] s2_req_rdata_3; // @[bim.scala:54:32]
assign s2_meta_bims_3 = s2_req_rdata_3; // @[bim.scala:41:31, :54:32]
wire _s2_resp_0_T_3; // @[bim.scala:60:57]
assign io_resp_f2_0_taken_0 = s2_resp_0; // @[bim.scala:26:7, :56:29]
wire _s2_resp_1_T_3; // @[bim.scala:60:57]
assign io_resp_f2_1_taken_0 = s2_resp_1; // @[bim.scala:26:7, :56:29]
wire _s2_resp_2_T_3; // @[bim.scala:60:57]
assign io_resp_f2_2_taken_0 = s2_resp_2; // @[bim.scala:26:7, :56:29]
wire _s2_resp_3_T_3; // @[bim.scala:60:57]
assign io_resp_f2_3_taken_0 = s2_resp_3; // @[bim.scala:26:7, :56:29]
wire _s2_resp_0_T = s2_req_rdata_0[1]; // @[bim.scala:54:32, :60:53]
wire _s2_resp_0_T_1 = s2_valid & _s2_resp_0_T; // @[predictor.scala:169:25]
wire _s2_resp_0_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60]
assign _s2_resp_0_T_3 = _s2_resp_0_T_1 & _s2_resp_0_T_2; // @[bim.scala:60:{35,57,60}]
assign s2_resp_0 = _s2_resp_0_T_3; // @[bim.scala:56:29, :60:57]
wire _s2_resp_1_T = s2_req_rdata_1[1]; // @[bim.scala:54:32, :60:53]
wire _s2_resp_1_T_1 = s2_valid & _s2_resp_1_T; // @[predictor.scala:169:25]
wire _s2_resp_1_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60]
assign _s2_resp_1_T_3 = _s2_resp_1_T_1 & _s2_resp_1_T_2; // @[bim.scala:60:{35,57,60}]
assign s2_resp_1 = _s2_resp_1_T_3; // @[bim.scala:56:29, :60:57]
wire _s2_resp_2_T = s2_req_rdata_2[1]; // @[bim.scala:54:32, :60:53]
wire _s2_resp_2_T_1 = s2_valid & _s2_resp_2_T; // @[predictor.scala:169:25]
wire _s2_resp_2_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60]
assign _s2_resp_2_T_3 = _s2_resp_2_T_1 & _s2_resp_2_T_2; // @[bim.scala:60:{35,57,60}]
assign s2_resp_2 = _s2_resp_2_T_3; // @[bim.scala:56:29, :60:57]
wire _s2_resp_3_T = s2_req_rdata_3[1]; // @[bim.scala:54:32, :60:53]
wire _s2_resp_3_T_1 = s2_valid & _s2_resp_3_T; // @[predictor.scala:169:25]
wire _s2_resp_3_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60]
assign _s2_resp_3_T_3 = _s2_resp_3_T_1 & _s2_resp_3_T_2; // @[bim.scala:60:{35,57,60}]
assign s2_resp_3 = _s2_resp_3_T_3; // @[bim.scala:56:29, :60:57]
wire [1:0] _s1_update_wdata_0_T_9; // @[bim.scala:37:8]
wire [1:0] _s1_update_wdata_1_T_9; // @[bim.scala:37:8]
wire [1:0] _s1_update_wdata_2_T_9; // @[bim.scala:37:8]
wire [1:0] _s1_update_wdata_3_T_9; // @[bim.scala:37:8]
wire [1:0] s1_update_wdata_0; // @[bim.scala:65:31]
wire [1:0] s1_update_wdata_1; // @[bim.scala:65:31]
wire [1:0] s1_update_wdata_2; // @[bim.scala:65:31]
wire [1:0] s1_update_wdata_3; // @[bim.scala:65:31]
wire s1_update_wmask_0; // @[bim.scala:66:31]
wire s1_update_wmask_1; // @[bim.scala:66:31]
wire s1_update_wmask_2; // @[bim.scala:66:31]
wire s1_update_wmask_3; // @[bim.scala:66:31]
wire [1:0] _s1_update_meta_T; // @[bim.scala:67:55]
wire [1:0] _s1_update_meta_T_1; // @[bim.scala:67:55]
wire [1:0] _s1_update_meta_T_2; // @[bim.scala:67:55]
wire [1:0] _s1_update_meta_T_3; // @[bim.scala:67:55]
wire [1:0] s1_update_meta_bims_0; // @[bim.scala:67:55]
wire [1:0] s1_update_meta_bims_1; // @[bim.scala:67:55]
wire [1:0] s1_update_meta_bims_2; // @[bim.scala:67:55]
wire [1:0] s1_update_meta_bims_3; // @[bim.scala:67:55]
wire [7:0] _s1_update_meta_WIRE = s1_update_bits_meta[7:0]; // @[predictor.scala:184:30]
assign _s1_update_meta_T = _s1_update_meta_WIRE[1:0]; // @[bim.scala:67:55]
assign s1_update_meta_bims_0 = _s1_update_meta_T; // @[bim.scala:67:55]
assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3:2]; // @[bim.scala:67:55]
assign s1_update_meta_bims_1 = _s1_update_meta_T_1; // @[bim.scala:67:55]
assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[5:4]; // @[bim.scala:67:55]
assign s1_update_meta_bims_2 = _s1_update_meta_T_2; // @[bim.scala:67:55]
assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7:6]; // @[bim.scala:67:55]
assign s1_update_meta_bims_3 = _s1_update_meta_T_3; // @[bim.scala:67:55]
reg [10:0] wrbypass_idxs_0; // @[bim.scala:70:26]
reg [10:0] wrbypass_idxs_1; // @[bim.scala:70:26]
reg [1:0] wrbypass_0_0; // @[bim.scala:71:26]
reg [1:0] wrbypass_0_1; // @[bim.scala:71:26]
reg [1:0] wrbypass_0_2; // @[bim.scala:71:26]
reg [1:0] wrbypass_0_3; // @[bim.scala:71:26]
reg [1:0] wrbypass_1_0; // @[bim.scala:71:26]
reg [1:0] wrbypass_1_1; // @[bim.scala:71:26]
reg [1:0] wrbypass_1_2; // @[bim.scala:71:26]
reg [1:0] wrbypass_1_3; // @[bim.scala:71:26]
reg wrbypass_enq_idx; // @[bim.scala:72:33]
wire _wrbypass_hits_T = ~doing_reset; // @[bim.scala:44:28, :60:60, :75:5]
wire [10:0] _wrbypass_hits_T_1 = s1_update_idx[10:0]; // @[predictor.scala:185:30]
wire [10:0] _wrbypass_hits_T_5 = s1_update_idx[10:0]; // @[predictor.scala:185:30]
wire _wrbypass_hits_T_2 = wrbypass_idxs_0 == _wrbypass_hits_T_1; // @[bim.scala:70:26, :76:{22,41}]
wire _wrbypass_hits_T_3 = _wrbypass_hits_T & _wrbypass_hits_T_2; // @[bim.scala:75:{5,18}, :76:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_3; // @[bim.scala:74:30, :75:18]
wire _wrbypass_hits_T_4 = ~doing_reset; // @[bim.scala:44:28, :60:60, :75:5]
wire _wrbypass_hits_T_6 = wrbypass_idxs_1 == _wrbypass_hits_T_5; // @[bim.scala:70:26, :76:{22,41}]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_4 & _wrbypass_hits_T_6; // @[bim.scala:75:{5,18}, :76:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_7; // @[bim.scala:74:30, :75:18]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[bim.scala:74:30, :78:44]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [40:0] _update_pc_T = {1'h0, s1_update_bits_pc}; // @[predictor.scala:184:30]
wire [39:0] update_pc = _update_pc_T[39:0]; // @[bim.scala:87:39]
wire _was_taken_T_2 = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30]
wire _was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[predictor.scala:184:30]
assign s1_update_wmask_0 = _was_taken_T_2 | s1_update_bits_cfi_idx_valid & _was_taken_T; // @[predictor.scala:184:30]
wire _was_taken_T_1 = s1_update_bits_cfi_idx_valid & _was_taken_T; // @[predictor.scala:184:30]
wire _was_taken_T_3 = s1_update_bits_cfi_is_br & _was_taken_T_2; // @[predictor.scala:184:30]
wire _was_taken_T_4 = _was_taken_T_3 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
wire _was_taken_T_5 = _was_taken_T_4 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
wire was_taken = _was_taken_T_1 & _was_taken_T_5; // @[bim.scala:92:38, :93:47, :95:95]
wire [1:0] old_bim_value = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0) : s1_update_meta_bims_0; // @[Mux.scala:50:70]
wire s1_update_wdata_0_old_bim_sat_taken = &old_bim_value; // @[bim.scala:35:32, :99:30]
wire s1_update_wdata_0_old_bim_sat_ntaken = old_bim_value == 2'h0; // @[bim.scala:36:32, :99:30]
wire _s1_update_wdata_0_T = s1_update_wdata_0_old_bim_sat_taken & was_taken; // @[bim.scala:35:32, :37:28, :93:47]
wire _s1_update_wdata_0_T_1 = ~was_taken; // @[bim.scala:38:33, :93:47]
wire _s1_update_wdata_0_T_2 = s1_update_wdata_0_old_bim_sat_ntaken & _s1_update_wdata_0_T_1; // @[bim.scala:36:32, :38:{30,33}]
wire [2:0] _GEN_1 = {1'h0, old_bim_value}; // @[bim.scala:39:20, :99:30]
wire [2:0] _s1_update_wdata_0_T_3 = _GEN_1 + 3'h1; // @[bim.scala:39:20]
wire [1:0] _s1_update_wdata_0_T_4 = _s1_update_wdata_0_T_3[1:0]; // @[bim.scala:39:20]
wire [2:0] _s1_update_wdata_0_T_5 = _GEN_1 - 3'h1; // @[bim.scala:39:{20,29}]
wire [1:0] _s1_update_wdata_0_T_6 = _s1_update_wdata_0_T_5[1:0]; // @[bim.scala:39:29]
wire [1:0] _s1_update_wdata_0_T_7 = was_taken ? _s1_update_wdata_0_T_4 : _s1_update_wdata_0_T_6; // @[bim.scala:39:{10,20,29}, :93:47]
wire [1:0] _s1_update_wdata_0_T_8 = _s1_update_wdata_0_T_2 ? 2'h0 : _s1_update_wdata_0_T_7; // @[bim.scala:38:{10,30}, :39:10]
assign _s1_update_wdata_0_T_9 = _s1_update_wdata_0_T ? 2'h3 : _s1_update_wdata_0_T_8; // @[bim.scala:37:{8,28}, :38:10]
assign s1_update_wdata_0 = _s1_update_wdata_0_T_9; // @[bim.scala:37:8, :65:31]
wire [40:0] _update_pc_T_1 = _update_pc_T + 41'h2; // @[bim.scala:87:39]
wire [39:0] update_pc_1 = _update_pc_T_1[39:0]; // @[bim.scala:87:39]
wire _was_taken_T_8 = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30]
wire _was_taken_T_6 = s1_update_bits_cfi_idx_bits == 2'h1; // @[predictor.scala:184:30]
assign s1_update_wmask_1 = _was_taken_T_8 | s1_update_bits_cfi_idx_valid & _was_taken_T_6; // @[predictor.scala:184:30]
wire _was_taken_T_7 = s1_update_bits_cfi_idx_valid & _was_taken_T_6; // @[predictor.scala:184:30]
wire _was_taken_T_9 = s1_update_bits_cfi_is_br & _was_taken_T_8; // @[predictor.scala:184:30]
wire _was_taken_T_10 = _was_taken_T_9 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
wire _was_taken_T_11 = _was_taken_T_10 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
wire was_taken_1 = _was_taken_T_7 & _was_taken_T_11; // @[bim.scala:92:38, :93:47, :95:95]
wire [1:0] old_bim_value_1 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1) : s1_update_meta_bims_1; // @[Mux.scala:50:70]
wire s1_update_wdata_1_old_bim_sat_taken = &old_bim_value_1; // @[bim.scala:35:32, :99:30]
wire s1_update_wdata_1_old_bim_sat_ntaken = old_bim_value_1 == 2'h0; // @[bim.scala:36:32, :99:30]
wire _s1_update_wdata_1_T = s1_update_wdata_1_old_bim_sat_taken & was_taken_1; // @[bim.scala:35:32, :37:28, :93:47]
wire _s1_update_wdata_1_T_1 = ~was_taken_1; // @[bim.scala:38:33, :93:47]
wire _s1_update_wdata_1_T_2 = s1_update_wdata_1_old_bim_sat_ntaken & _s1_update_wdata_1_T_1; // @[bim.scala:36:32, :38:{30,33}]
wire [2:0] _GEN_2 = {1'h0, old_bim_value_1}; // @[bim.scala:39:20, :99:30]
wire [2:0] _s1_update_wdata_1_T_3 = _GEN_2 + 3'h1; // @[bim.scala:39:20]
wire [1:0] _s1_update_wdata_1_T_4 = _s1_update_wdata_1_T_3[1:0]; // @[bim.scala:39:20]
wire [2:0] _s1_update_wdata_1_T_5 = _GEN_2 - 3'h1; // @[bim.scala:39:{20,29}]
wire [1:0] _s1_update_wdata_1_T_6 = _s1_update_wdata_1_T_5[1:0]; // @[bim.scala:39:29]
wire [1:0] _s1_update_wdata_1_T_7 = was_taken_1 ? _s1_update_wdata_1_T_4 : _s1_update_wdata_1_T_6; // @[bim.scala:39:{10,20,29}, :93:47]
wire [1:0] _s1_update_wdata_1_T_8 = _s1_update_wdata_1_T_2 ? 2'h0 : _s1_update_wdata_1_T_7; // @[bim.scala:38:{10,30}, :39:10]
assign _s1_update_wdata_1_T_9 = _s1_update_wdata_1_T ? 2'h3 : _s1_update_wdata_1_T_8; // @[bim.scala:37:{8,28}, :38:10]
assign s1_update_wdata_1 = _s1_update_wdata_1_T_9; // @[bim.scala:37:8, :65:31]
wire [40:0] _update_pc_T_2 = _update_pc_T + 41'h4; // @[bim.scala:87:39]
wire [39:0] update_pc_2 = _update_pc_T_2[39:0]; // @[bim.scala:87:39]
wire _was_taken_T_14 = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30]
wire _was_taken_T_12 = s1_update_bits_cfi_idx_bits == 2'h2; // @[predictor.scala:184:30]
assign s1_update_wmask_2 = _was_taken_T_14 | s1_update_bits_cfi_idx_valid & _was_taken_T_12; // @[predictor.scala:184:30]
wire _was_taken_T_13 = s1_update_bits_cfi_idx_valid & _was_taken_T_12; // @[predictor.scala:184:30]
wire _was_taken_T_15 = s1_update_bits_cfi_is_br & _was_taken_T_14; // @[predictor.scala:184:30]
wire _was_taken_T_16 = _was_taken_T_15 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
wire _was_taken_T_17 = _was_taken_T_16 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
wire was_taken_2 = _was_taken_T_13 & _was_taken_T_17; // @[bim.scala:92:38, :93:47, :95:95]
wire [1:0] old_bim_value_2 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2) : s1_update_meta_bims_2; // @[Mux.scala:50:70]
wire s1_update_wdata_2_old_bim_sat_taken = &old_bim_value_2; // @[bim.scala:35:32, :99:30]
wire s1_update_wdata_2_old_bim_sat_ntaken = old_bim_value_2 == 2'h0; // @[bim.scala:36:32, :99:30]
wire _s1_update_wdata_2_T = s1_update_wdata_2_old_bim_sat_taken & was_taken_2; // @[bim.scala:35:32, :37:28, :93:47]
wire _s1_update_wdata_2_T_1 = ~was_taken_2; // @[bim.scala:38:33, :93:47]
wire _s1_update_wdata_2_T_2 = s1_update_wdata_2_old_bim_sat_ntaken & _s1_update_wdata_2_T_1; // @[bim.scala:36:32, :38:{30,33}]
wire [2:0] _GEN_3 = {1'h0, old_bim_value_2}; // @[bim.scala:39:20, :99:30]
wire [2:0] _s1_update_wdata_2_T_3 = _GEN_3 + 3'h1; // @[bim.scala:39:20]
wire [1:0] _s1_update_wdata_2_T_4 = _s1_update_wdata_2_T_3[1:0]; // @[bim.scala:39:20]
wire [2:0] _s1_update_wdata_2_T_5 = _GEN_3 - 3'h1; // @[bim.scala:39:{20,29}]
wire [1:0] _s1_update_wdata_2_T_6 = _s1_update_wdata_2_T_5[1:0]; // @[bim.scala:39:29]
wire [1:0] _s1_update_wdata_2_T_7 = was_taken_2 ? _s1_update_wdata_2_T_4 : _s1_update_wdata_2_T_6; // @[bim.scala:39:{10,20,29}, :93:47]
wire [1:0] _s1_update_wdata_2_T_8 = _s1_update_wdata_2_T_2 ? 2'h0 : _s1_update_wdata_2_T_7; // @[bim.scala:38:{10,30}, :39:10]
assign _s1_update_wdata_2_T_9 = _s1_update_wdata_2_T ? 2'h3 : _s1_update_wdata_2_T_8; // @[bim.scala:37:{8,28}, :38:10]
assign s1_update_wdata_2 = _s1_update_wdata_2_T_9; // @[bim.scala:37:8, :65:31]
wire [40:0] _update_pc_T_3 = _update_pc_T + 41'h6; // @[bim.scala:87:39]
wire [39:0] update_pc_3 = _update_pc_T_3[39:0]; // @[bim.scala:87:39]
wire _was_taken_T_20 = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30]
assign s1_update_wmask_3 = _was_taken_T_20 | s1_update_bits_cfi_idx_valid & (&s1_update_bits_cfi_idx_bits); // @[predictor.scala:184:30]
wire _was_taken_T_18 = &s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
wire _was_taken_T_19 = s1_update_bits_cfi_idx_valid & _was_taken_T_18; // @[predictor.scala:184:30]
wire _was_taken_T_21 = s1_update_bits_cfi_is_br & _was_taken_T_20; // @[predictor.scala:184:30]
wire _was_taken_T_22 = _was_taken_T_21 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
wire _was_taken_T_23 = _was_taken_T_22 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
wire was_taken_3 = _was_taken_T_19 & _was_taken_T_23; // @[bim.scala:92:38, :93:47, :95:95]
wire [1:0] old_bim_value_3 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3) : s1_update_meta_bims_3; // @[Mux.scala:50:70]
wire s1_update_wdata_3_old_bim_sat_taken = &old_bim_value_3; // @[bim.scala:35:32, :99:30]
wire s1_update_wdata_3_old_bim_sat_ntaken = old_bim_value_3 == 2'h0; // @[bim.scala:36:32, :99:30]
wire _s1_update_wdata_3_T = s1_update_wdata_3_old_bim_sat_taken & was_taken_3; // @[bim.scala:35:32, :37:28, :93:47]
wire _s1_update_wdata_3_T_1 = ~was_taken_3; // @[bim.scala:38:33, :93:47]
wire _s1_update_wdata_3_T_2 = s1_update_wdata_3_old_bim_sat_ntaken & _s1_update_wdata_3_T_1; // @[bim.scala:36:32, :38:{30,33}]
wire [2:0] _GEN_4 = {1'h0, old_bim_value_3}; // @[bim.scala:39:20, :99:30]
wire [2:0] _s1_update_wdata_3_T_3 = _GEN_4 + 3'h1; // @[bim.scala:39:20]
wire [1:0] _s1_update_wdata_3_T_4 = _s1_update_wdata_3_T_3[1:0]; // @[bim.scala:39:20]
wire [2:0] _s1_update_wdata_3_T_5 = _GEN_4 - 3'h1; // @[bim.scala:39:{20,29}]
wire [1:0] _s1_update_wdata_3_T_6 = _s1_update_wdata_3_T_5[1:0]; // @[bim.scala:39:29]
wire [1:0] _s1_update_wdata_3_T_7 = was_taken_3 ? _s1_update_wdata_3_T_4 : _s1_update_wdata_3_T_6; // @[bim.scala:39:{10,20,29}, :93:47]
wire [1:0] _s1_update_wdata_3_T_8 = _s1_update_wdata_3_T_2 ? 2'h0 : _s1_update_wdata_3_T_7; // @[bim.scala:38:{10,30}, :39:10]
assign _s1_update_wdata_3_T_9 = _s1_update_wdata_3_T ? 2'h3 : _s1_update_wdata_3_T_8; // @[bim.scala:37:{8,28}, :38:10]
assign s1_update_wdata_3 = _s1_update_wdata_3_T_9; // @[bim.scala:37:8, :65:31]
wire [4:0] _GEN_5 = {s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30]
assign data_MPORT_data_0 = doing_reset ? 2'h2 : s1_update_wdata_0; // @[bim.scala:44:28, :65:31, :112:10]
assign data_MPORT_data_1 = doing_reset ? 2'h2 : s1_update_wdata_1; // @[bim.scala:44:28, :65:31, :112:10]
assign data_MPORT_data_2 = doing_reset ? 2'h2 : s1_update_wdata_2; // @[bim.scala:44:28, :65:31, :112:10]
assign data_MPORT_data_3 = doing_reset ? 2'h2 : s1_update_wdata_3; // @[bim.scala:44:28, :65:31, :112:10]
wire [1:0] lo_1 = {s1_update_wmask_1, s1_update_wmask_0}; // @[bim.scala:66:31, :113:63]
wire [1:0] hi_1 = {s1_update_wmask_3, s1_update_wmask_2}; // @[bim.scala:66:31, :113:63]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
reg io_resp_f3_0_taken_REG; // @[bim.scala:128:35]
assign io_resp_f3_0_taken_0 = io_resp_f3_0_taken_REG; // @[bim.scala:26:7, :128:35]
reg io_resp_f3_1_taken_REG; // @[bim.scala:128:35]
assign io_resp_f3_1_taken_0 = io_resp_f3_1_taken_REG; // @[bim.scala:26:7, :128:35]
reg io_resp_f3_2_taken_REG; // @[bim.scala:128:35]
assign io_resp_f3_2_taken_0 = io_resp_f3_2_taken_REG; // @[bim.scala:26:7, :128:35]
reg io_resp_f3_3_taken_REG; // @[bim.scala:128:35]
assign io_resp_f3_3_taken_0 = io_resp_f3_3_taken_REG; // @[bim.scala:26:7, :128:35]
wire [7:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[bim.scala:130:33]
reg [7:0] io_f3_meta_REG; // @[bim.scala:130:24]
assign io_f3_meta_0 = {112'h0, io_f3_meta_REG}; // @[bim.scala:26:7, :130:{14,24}]
wire _T_43 = (s1_update_wmask_0 | s1_update_wmask_1 | s1_update_wmask_2 | s1_update_wmask_3) & s1_update_valid & _GEN_5 == 5'h0; // @[predictor.scala:94:50, :96:69, :184:30]
wire _GEN_6 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
always @(posedge clock) begin // @[bim.scala:26:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
s2_req_rdata_0 <= _data_R0_data[1:0]; // @[bim.scala:50:26, :54:32]
s2_req_rdata_1 <= _data_R0_data[3:2]; // @[bim.scala:50:26, :54:32]
s2_req_rdata_2 <= _data_R0_data[5:4]; // @[bim.scala:50:26, :54:32]
s2_req_rdata_3 <= _data_R0_data[7:6]; // @[bim.scala:50:26, :54:32]
if (~_T_43 | wrbypass_hit | wrbypass_enq_idx) begin // @[bim.scala:70:26, :71:26, :72:33, :78:44, :116:{38,57,93}, :117:25, :121:39]
end
else // @[bim.scala:70:26, :116:93, :117:25, :121:39]
wrbypass_idxs_0 <= s1_update_idx[10:0]; // @[predictor.scala:185:30]
if (~_T_43 | wrbypass_hit | ~wrbypass_enq_idx) begin // @[bim.scala:70:26, :71:26, :72:33, :78:44, :116:{38,57,93}, :117:25, :121:39]
end
else // @[bim.scala:70:26, :116:93, :117:25, :121:39]
wrbypass_idxs_1 <= s1_update_idx[10:0]; // @[predictor.scala:185:30]
if (~_T_43 | _GEN_6) begin // @[bim.scala:71:26, :116:{38,57,93}, :117:25, :118:34, :120:39]
end
else begin // @[bim.scala:71:26, :116:93, :117:25]
wrbypass_0_0 <= s1_update_wdata_0; // @[bim.scala:65:31, :71:26]
wrbypass_0_1 <= s1_update_wdata_1; // @[bim.scala:65:31, :71:26]
wrbypass_0_2 <= s1_update_wdata_2; // @[bim.scala:65:31, :71:26]
wrbypass_0_3 <= s1_update_wdata_3; // @[bim.scala:65:31, :71:26]
end
if (_T_43 & _GEN_6) begin // @[bim.scala:71:26, :116:{38,57,93}, :117:25, :118:34, :120:39]
wrbypass_1_0 <= s1_update_wdata_0; // @[bim.scala:65:31, :71:26]
wrbypass_1_1 <= s1_update_wdata_1; // @[bim.scala:65:31, :71:26]
wrbypass_1_2 <= s1_update_wdata_2; // @[bim.scala:65:31, :71:26]
wrbypass_1_3 <= s1_update_wdata_3; // @[bim.scala:65:31, :71:26]
end
io_resp_f3_0_taken_REG <= io_resp_f2_0_taken_0; // @[bim.scala:26:7, :128:35]
io_resp_f3_1_taken_REG <= io_resp_f2_1_taken_0; // @[bim.scala:26:7, :128:35]
io_resp_f3_2_taken_REG <= io_resp_f2_2_taken_0; // @[bim.scala:26:7, :128:35]
io_resp_f3_3_taken_REG <= io_resp_f2_3_taken_0; // @[bim.scala:26:7, :128:35]
io_f3_meta_REG <= _io_f3_meta_T; // @[bim.scala:130:{24,33}]
if (reset) begin // @[bim.scala:26:7]
doing_reset <= 1'h1; // @[bim.scala:44:28]
reset_idx <= 11'h0; // @[bim.scala:45:26]
wrbypass_enq_idx <= 1'h0; // @[bim.scala:72:33]
end
else begin // @[bim.scala:26:7]
doing_reset <= reset_idx != 11'h7FF & doing_reset; // @[bim.scala:44:28, :45:26, :47:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[bim.scala:45:26, :46:26]
if (~_T_43 | wrbypass_hit) begin // @[bim.scala:71:26, :72:33, :78:44, :116:{38,57,93}, :117:25]
end
else // @[bim.scala:72:33, :116:93, :117:25]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
always @(posedge)
data_0 data ( // @[bim.scala:50:26]
.R0_addr (_s2_req_rdata_T), // @[bim.scala:54:42]
.R0_en (io_f0_valid_0), // @[bim.scala:26:7]
.R0_clk (clock),
.R0_data (_data_R0_data),
.W0_addr (doing_reset ? reset_idx : s1_update_idx[10:0]), // @[predictor.scala:185:30]
.W0_en (doing_reset | s1_update_valid & _GEN_5 == 5'h0), // @[predictor.scala:94:50, :96:69, :184:30]
.W0_clk (clock),
.W0_data ({data_MPORT_data_3, data_MPORT_data_2, data_MPORT_data_1, data_MPORT_data_0}), // @[bim.scala:50:26, :112:10]
.W0_mask (doing_reset ? 4'hF : {hi_1, lo_1}) // @[bim.scala:44:28, :113:{10,63}]
); // @[bim.scala:50:26]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[bim.scala:26:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[bim.scala:26:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[bim.scala:26:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[bim.scala:26:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[bim.scala:26:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[bim.scala:26:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[bim.scala:26:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[bim.scala:26:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[bim.scala:26:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[bim.scala:26:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[bim.scala:26:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[bim.scala:26:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[bim.scala:26:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[bim.scala:26:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[bim.scala:26:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[bim.scala:26:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[bim.scala:26:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[bim.scala:26:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[bim.scala:26:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[bim.scala:26:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[bim.scala:26:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[bim.scala:26:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[bim.scala:26:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[bim.scala:26:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[bim.scala:26:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[bim.scala:26:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[bim.scala:26:7]
assign io_f3_meta = io_f3_meta_0; // @[bim.scala:26:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_103
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_104
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_105 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_106 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_51( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49]
wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_898; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MultiHeadedQueue :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, deq : { valid : UInt<1>[2], bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}[2], flip pop : UInt<1>}, len : UInt<2>}
reg regs : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}[2], clock
regreset raddr : UInt<1>, clock, reset, UInt<1>(0h0)
regreset waddr : UInt<1>, clock, reset, UInt<1>(0h0)
regreset len : UInt<2>, clock, reset, UInt<2>(0h0)
node _io_enq_ready_T = lt(len, UInt<2>(0h2))
connect io.enq.ready, _io_enq_ready_T
connect io.len, len
node _io_deq_valid_0_T = gt(len, UInt<1>(0h0))
connect io.deq.valid[0], _io_deq_valid_0_T
node _io_deq_bits_0_T = leq(UInt<1>(0h0), UInt<1>(0h1))
node _io_deq_bits_0_T_1 = asUInt(reset)
node _io_deq_bits_0_T_2 = eq(_io_deq_bits_0_T_1, UInt<1>(0h0))
when _io_deq_bits_0_T_2 :
node _io_deq_bits_0_T_3 = eq(_io_deq_bits_0_T, UInt<1>(0h0))
when _io_deq_bits_0_T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max\n at Util.scala:12 assert(n <= max.U, \"cannot wrapAdd when n is larger than max\")\n") : io_deq_bits_0_printf
assert(clock, _io_deq_bits_0_T, UInt<1>(0h1), "") : io_deq_bits_0_assert
node _io_deq_bits_0_T_4 = sub(UInt<1>(0h1), UInt<1>(0h0))
node _io_deq_bits_0_T_5 = tail(_io_deq_bits_0_T_4, 1)
node _io_deq_bits_0_T_6 = add(_io_deq_bits_0_T_5, UInt<1>(0h1))
node _io_deq_bits_0_T_7 = tail(_io_deq_bits_0_T_6, 1)
node _io_deq_bits_0_T_8 = geq(raddr, _io_deq_bits_0_T_7)
node _io_deq_bits_0_T_9 = neq(UInt<1>(0h0), UInt<1>(0h0))
node _io_deq_bits_0_T_10 = and(_io_deq_bits_0_T_8, _io_deq_bits_0_T_9)
node _io_deq_bits_0_T_11 = sub(UInt<1>(0h1), raddr)
node _io_deq_bits_0_T_12 = tail(_io_deq_bits_0_T_11, 1)
node _io_deq_bits_0_T_13 = sub(UInt<1>(0h0), _io_deq_bits_0_T_12)
node _io_deq_bits_0_T_14 = tail(_io_deq_bits_0_T_13, 1)
node _io_deq_bits_0_T_15 = sub(_io_deq_bits_0_T_14, UInt<1>(0h1))
node _io_deq_bits_0_T_16 = tail(_io_deq_bits_0_T_15, 1)
node _io_deq_bits_0_T_17 = add(raddr, UInt<1>(0h0))
node _io_deq_bits_0_T_18 = tail(_io_deq_bits_0_T_17, 1)
node _io_deq_bits_0_T_19 = mux(_io_deq_bits_0_T_10, _io_deq_bits_0_T_16, _io_deq_bits_0_T_18)
connect io.deq.bits[0], regs[_io_deq_bits_0_T_19]
node _io_deq_valid_1_T = gt(len, UInt<1>(0h1))
connect io.deq.valid[1], _io_deq_valid_1_T
node _io_deq_bits_1_T = leq(UInt<1>(0h1), UInt<1>(0h1))
node _io_deq_bits_1_T_1 = asUInt(reset)
node _io_deq_bits_1_T_2 = eq(_io_deq_bits_1_T_1, UInt<1>(0h0))
when _io_deq_bits_1_T_2 :
node _io_deq_bits_1_T_3 = eq(_io_deq_bits_1_T, UInt<1>(0h0))
when _io_deq_bits_1_T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max\n at Util.scala:12 assert(n <= max.U, \"cannot wrapAdd when n is larger than max\")\n") : io_deq_bits_1_printf
assert(clock, _io_deq_bits_1_T, UInt<1>(0h1), "") : io_deq_bits_1_assert
node _io_deq_bits_1_T_4 = sub(UInt<1>(0h1), UInt<1>(0h1))
node _io_deq_bits_1_T_5 = tail(_io_deq_bits_1_T_4, 1)
node _io_deq_bits_1_T_6 = add(_io_deq_bits_1_T_5, UInt<1>(0h1))
node _io_deq_bits_1_T_7 = tail(_io_deq_bits_1_T_6, 1)
node _io_deq_bits_1_T_8 = geq(raddr, _io_deq_bits_1_T_7)
node _io_deq_bits_1_T_9 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _io_deq_bits_1_T_10 = and(_io_deq_bits_1_T_8, _io_deq_bits_1_T_9)
node _io_deq_bits_1_T_11 = sub(UInt<1>(0h1), raddr)
node _io_deq_bits_1_T_12 = tail(_io_deq_bits_1_T_11, 1)
node _io_deq_bits_1_T_13 = sub(UInt<1>(0h1), _io_deq_bits_1_T_12)
node _io_deq_bits_1_T_14 = tail(_io_deq_bits_1_T_13, 1)
node _io_deq_bits_1_T_15 = sub(_io_deq_bits_1_T_14, UInt<1>(0h1))
node _io_deq_bits_1_T_16 = tail(_io_deq_bits_1_T_15, 1)
node _io_deq_bits_1_T_17 = add(raddr, UInt<1>(0h1))
node _io_deq_bits_1_T_18 = tail(_io_deq_bits_1_T_17, 1)
node _io_deq_bits_1_T_19 = mux(_io_deq_bits_1_T_10, _io_deq_bits_1_T_16, _io_deq_bits_1_T_18)
connect io.deq.bits[1], regs[_io_deq_bits_1_T_19]
node _T = and(io.enq.ready, io.enq.valid)
when _T :
connect regs[waddr], io.enq.bits
node _waddr_T = leq(UInt<1>(0h1), UInt<1>(0h1))
node _waddr_T_1 = asUInt(reset)
node _waddr_T_2 = eq(_waddr_T_1, UInt<1>(0h0))
when _waddr_T_2 :
node _waddr_T_3 = eq(_waddr_T, UInt<1>(0h0))
when _waddr_T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max\n at Util.scala:12 assert(n <= max.U, \"cannot wrapAdd when n is larger than max\")\n") : waddr_printf
assert(clock, _waddr_T, UInt<1>(0h1), "") : waddr_assert
node _waddr_T_4 = sub(UInt<1>(0h1), UInt<1>(0h1))
node _waddr_T_5 = tail(_waddr_T_4, 1)
node _waddr_T_6 = add(_waddr_T_5, UInt<1>(0h1))
node _waddr_T_7 = tail(_waddr_T_6, 1)
node _waddr_T_8 = geq(waddr, _waddr_T_7)
node _waddr_T_9 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _waddr_T_10 = and(_waddr_T_8, _waddr_T_9)
node _waddr_T_11 = sub(UInt<1>(0h1), waddr)
node _waddr_T_12 = tail(_waddr_T_11, 1)
node _waddr_T_13 = sub(UInt<1>(0h1), _waddr_T_12)
node _waddr_T_14 = tail(_waddr_T_13, 1)
node _waddr_T_15 = sub(_waddr_T_14, UInt<1>(0h1))
node _waddr_T_16 = tail(_waddr_T_15, 1)
node _waddr_T_17 = add(waddr, UInt<1>(0h1))
node _waddr_T_18 = tail(_waddr_T_17, 1)
node _waddr_T_19 = mux(_waddr_T_10, _waddr_T_16, _waddr_T_18)
connect waddr, _waddr_T_19
node _len_T = add(len, UInt<1>(0h1))
node _len_T_1 = tail(_len_T, 1)
connect len, _len_T_1
node _T_1 = gt(io.deq.pop, UInt<1>(0h0))
when _T_1 :
node _raddr_T = leq(io.deq.pop, UInt<1>(0h1))
node _raddr_T_1 = asUInt(reset)
node _raddr_T_2 = eq(_raddr_T_1, UInt<1>(0h0))
when _raddr_T_2 :
node _raddr_T_3 = eq(_raddr_T, UInt<1>(0h0))
when _raddr_T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max\n at Util.scala:12 assert(n <= max.U, \"cannot wrapAdd when n is larger than max\")\n") : raddr_printf
assert(clock, _raddr_T, UInt<1>(0h1), "") : raddr_assert
node _raddr_T_4 = sub(UInt<1>(0h1), io.deq.pop)
node _raddr_T_5 = tail(_raddr_T_4, 1)
node _raddr_T_6 = add(_raddr_T_5, UInt<1>(0h1))
node _raddr_T_7 = tail(_raddr_T_6, 1)
node _raddr_T_8 = geq(raddr, _raddr_T_7)
node _raddr_T_9 = neq(io.deq.pop, UInt<1>(0h0))
node _raddr_T_10 = and(_raddr_T_8, _raddr_T_9)
node _raddr_T_11 = sub(UInt<1>(0h1), raddr)
node _raddr_T_12 = tail(_raddr_T_11, 1)
node _raddr_T_13 = sub(io.deq.pop, _raddr_T_12)
node _raddr_T_14 = tail(_raddr_T_13, 1)
node _raddr_T_15 = sub(_raddr_T_14, UInt<1>(0h1))
node _raddr_T_16 = tail(_raddr_T_15, 1)
node _raddr_T_17 = add(raddr, io.deq.pop)
node _raddr_T_18 = tail(_raddr_T_17, 1)
node _raddr_T_19 = mux(_raddr_T_10, _raddr_T_16, _raddr_T_18)
connect raddr, _raddr_T_19
node _len_T_2 = sub(len, io.deq.pop)
node _len_T_3 = tail(_len_T_2, 1)
node _len_T_4 = and(io.enq.ready, io.enq.valid)
node _len_T_5 = add(_len_T_3, _len_T_4)
node _len_T_6 = tail(_len_T_5, 1)
connect len, _len_T_6
node _T_2 = leq(io.deq.pop, len)
node _T_3 = leq(io.deq.pop, UInt<2>(0h2))
node _T_4 = and(_T_2, _T_3)
node _T_5 = leq(io.deq.pop, UInt<1>(0h1))
node _T_6 = and(_T_4, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MultiHeadedQueue.scala:48 assert(io.deq.pop <= len && io.deq.pop <= heads.U && io.deq.pop <= maxpop.U)\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert | module MultiHeadedQueue( // @[MultiHeadedQueue.scala:7:7]
input clock, // @[MultiHeadedQueue.scala:7:7]
input reset, // @[MultiHeadedQueue.scala:7:7]
output io_enq_ready, // @[MultiHeadedQueue.scala:8:14]
input io_enq_valid, // @[MultiHeadedQueue.scala:8:14]
input [6:0] io_enq_bits_cmd_inst_funct, // @[MultiHeadedQueue.scala:8:14]
input [4:0] io_enq_bits_cmd_inst_rs2, // @[MultiHeadedQueue.scala:8:14]
input [4:0] io_enq_bits_cmd_inst_rs1, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_inst_xd, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_inst_xs1, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_inst_xs2, // @[MultiHeadedQueue.scala:8:14]
input [4:0] io_enq_bits_cmd_inst_rd, // @[MultiHeadedQueue.scala:8:14]
input [6:0] io_enq_bits_cmd_inst_opcode, // @[MultiHeadedQueue.scala:8:14]
input [63:0] io_enq_bits_cmd_rs1, // @[MultiHeadedQueue.scala:8:14]
input [63:0] io_enq_bits_cmd_rs2, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_debug, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_cease, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_wfi, // @[MultiHeadedQueue.scala:8:14]
input [31:0] io_enq_bits_cmd_status_isa, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_dprv, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_dv, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_prv, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_v, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_sd, // @[MultiHeadedQueue.scala:8:14]
input [22:0] io_enq_bits_cmd_status_zero2, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_mpv, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_gva, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_mbe, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_sbe, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_sxl, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_uxl, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_sd_rv32, // @[MultiHeadedQueue.scala:8:14]
input [7:0] io_enq_bits_cmd_status_zero1, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_tsr, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_tw, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_tvm, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_mxr, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_sum, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_mprv, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_xs, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_fs, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_mpp, // @[MultiHeadedQueue.scala:8:14]
input [1:0] io_enq_bits_cmd_status_vs, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_spp, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_mpie, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_ube, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_spie, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_upie, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_mie, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_hie, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_sie, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_cmd_status_uie, // @[MultiHeadedQueue.scala:8:14]
input [5:0] io_enq_bits_rob_id_bits, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_from_matmul_fsm, // @[MultiHeadedQueue.scala:8:14]
input io_enq_bits_from_conv_fsm, // @[MultiHeadedQueue.scala:8:14]
output io_deq_valid_0, // @[MultiHeadedQueue.scala:8:14]
output io_deq_valid_1, // @[MultiHeadedQueue.scala:8:14]
output [6:0] io_deq_bits_0_cmd_inst_funct, // @[MultiHeadedQueue.scala:8:14]
output [4:0] io_deq_bits_0_cmd_inst_rs2, // @[MultiHeadedQueue.scala:8:14]
output [4:0] io_deq_bits_0_cmd_inst_rs1, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_inst_xd, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_inst_xs1, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_inst_xs2, // @[MultiHeadedQueue.scala:8:14]
output [4:0] io_deq_bits_0_cmd_inst_rd, // @[MultiHeadedQueue.scala:8:14]
output [6:0] io_deq_bits_0_cmd_inst_opcode, // @[MultiHeadedQueue.scala:8:14]
output [63:0] io_deq_bits_0_cmd_rs1, // @[MultiHeadedQueue.scala:8:14]
output [63:0] io_deq_bits_0_cmd_rs2, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_debug, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_cease, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_wfi, // @[MultiHeadedQueue.scala:8:14]
output [31:0] io_deq_bits_0_cmd_status_isa, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_dprv, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_dv, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_prv, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_v, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_sd, // @[MultiHeadedQueue.scala:8:14]
output [22:0] io_deq_bits_0_cmd_status_zero2, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_mpv, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_gva, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_mbe, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_sbe, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_sxl, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_uxl, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_sd_rv32, // @[MultiHeadedQueue.scala:8:14]
output [7:0] io_deq_bits_0_cmd_status_zero1, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_tsr, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_tw, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_tvm, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_mxr, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_sum, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_mprv, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_xs, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_fs, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_mpp, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_0_cmd_status_vs, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_spp, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_mpie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_ube, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_spie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_upie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_mie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_hie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_sie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_cmd_status_uie, // @[MultiHeadedQueue.scala:8:14]
output [5:0] io_deq_bits_0_rob_id_bits, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_from_matmul_fsm, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_0_from_conv_fsm, // @[MultiHeadedQueue.scala:8:14]
output [6:0] io_deq_bits_1_cmd_inst_funct, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_inst_xd, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_inst_xs1, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_inst_xs2, // @[MultiHeadedQueue.scala:8:14]
output [4:0] io_deq_bits_1_cmd_inst_rd, // @[MultiHeadedQueue.scala:8:14]
output [6:0] io_deq_bits_1_cmd_inst_opcode, // @[MultiHeadedQueue.scala:8:14]
output [63:0] io_deq_bits_1_cmd_rs1, // @[MultiHeadedQueue.scala:8:14]
output [63:0] io_deq_bits_1_cmd_rs2, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_debug, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_cease, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_wfi, // @[MultiHeadedQueue.scala:8:14]
output [31:0] io_deq_bits_1_cmd_status_isa, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_dprv, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_dv, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_prv, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_v, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_sd, // @[MultiHeadedQueue.scala:8:14]
output [22:0] io_deq_bits_1_cmd_status_zero2, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_mpv, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_gva, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_mbe, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_sbe, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_sxl, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_uxl, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_sd_rv32, // @[MultiHeadedQueue.scala:8:14]
output [7:0] io_deq_bits_1_cmd_status_zero1, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_tsr, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_tw, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_tvm, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_mxr, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_sum, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_mprv, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_xs, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_fs, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_mpp, // @[MultiHeadedQueue.scala:8:14]
output [1:0] io_deq_bits_1_cmd_status_vs, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_spp, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_mpie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_ube, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_spie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_upie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_mie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_hie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_sie, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_cmd_status_uie, // @[MultiHeadedQueue.scala:8:14]
output [5:0] io_deq_bits_1_rob_id_bits, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_from_matmul_fsm, // @[MultiHeadedQueue.scala:8:14]
output io_deq_bits_1_from_conv_fsm, // @[MultiHeadedQueue.scala:8:14]
input io_deq_pop // @[MultiHeadedQueue.scala:8:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[MultiHeadedQueue.scala:7:7]
wire [6:0] io_enq_bits_cmd_inst_funct_0 = io_enq_bits_cmd_inst_funct; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_enq_bits_cmd_inst_rs2_0 = io_enq_bits_cmd_inst_rs2; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_enq_bits_cmd_inst_rs1_0 = io_enq_bits_cmd_inst_rs1; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_inst_xd_0 = io_enq_bits_cmd_inst_xd; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_inst_xs1_0 = io_enq_bits_cmd_inst_xs1; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_inst_xs2_0 = io_enq_bits_cmd_inst_xs2; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_enq_bits_cmd_inst_rd_0 = io_enq_bits_cmd_inst_rd; // @[MultiHeadedQueue.scala:7:7]
wire [6:0] io_enq_bits_cmd_inst_opcode_0 = io_enq_bits_cmd_inst_opcode; // @[MultiHeadedQueue.scala:7:7]
wire [63:0] io_enq_bits_cmd_rs1_0 = io_enq_bits_cmd_rs1; // @[MultiHeadedQueue.scala:7:7]
wire [63:0] io_enq_bits_cmd_rs2_0 = io_enq_bits_cmd_rs2; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_debug_0 = io_enq_bits_cmd_status_debug; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_cease_0 = io_enq_bits_cmd_status_cease; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_wfi_0 = io_enq_bits_cmd_status_wfi; // @[MultiHeadedQueue.scala:7:7]
wire [31:0] io_enq_bits_cmd_status_isa_0 = io_enq_bits_cmd_status_isa; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_dprv_0 = io_enq_bits_cmd_status_dprv; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_dv_0 = io_enq_bits_cmd_status_dv; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_prv_0 = io_enq_bits_cmd_status_prv; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_v_0 = io_enq_bits_cmd_status_v; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_sd_0 = io_enq_bits_cmd_status_sd; // @[MultiHeadedQueue.scala:7:7]
wire [22:0] io_enq_bits_cmd_status_zero2_0 = io_enq_bits_cmd_status_zero2; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_mpv_0 = io_enq_bits_cmd_status_mpv; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_gva_0 = io_enq_bits_cmd_status_gva; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_mbe_0 = io_enq_bits_cmd_status_mbe; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_sbe_0 = io_enq_bits_cmd_status_sbe; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_sxl_0 = io_enq_bits_cmd_status_sxl; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_uxl_0 = io_enq_bits_cmd_status_uxl; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_sd_rv32_0 = io_enq_bits_cmd_status_sd_rv32; // @[MultiHeadedQueue.scala:7:7]
wire [7:0] io_enq_bits_cmd_status_zero1_0 = io_enq_bits_cmd_status_zero1; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_tsr_0 = io_enq_bits_cmd_status_tsr; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_tw_0 = io_enq_bits_cmd_status_tw; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_tvm_0 = io_enq_bits_cmd_status_tvm; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_mxr_0 = io_enq_bits_cmd_status_mxr; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_sum_0 = io_enq_bits_cmd_status_sum; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_mprv_0 = io_enq_bits_cmd_status_mprv; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_xs_0 = io_enq_bits_cmd_status_xs; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_fs_0 = io_enq_bits_cmd_status_fs; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_mpp_0 = io_enq_bits_cmd_status_mpp; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_enq_bits_cmd_status_vs_0 = io_enq_bits_cmd_status_vs; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_spp_0 = io_enq_bits_cmd_status_spp; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_mpie_0 = io_enq_bits_cmd_status_mpie; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_ube_0 = io_enq_bits_cmd_status_ube; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_spie_0 = io_enq_bits_cmd_status_spie; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_upie_0 = io_enq_bits_cmd_status_upie; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_mie_0 = io_enq_bits_cmd_status_mie; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_hie_0 = io_enq_bits_cmd_status_hie; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_sie_0 = io_enq_bits_cmd_status_sie; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_cmd_status_uie_0 = io_enq_bits_cmd_status_uie; // @[MultiHeadedQueue.scala:7:7]
wire [5:0] io_enq_bits_rob_id_bits_0 = io_enq_bits_rob_id_bits; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_from_matmul_fsm_0 = io_enq_bits_from_matmul_fsm; // @[MultiHeadedQueue.scala:7:7]
wire io_enq_bits_from_conv_fsm_0 = io_enq_bits_from_conv_fsm; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_pop_0 = io_deq_pop; // @[MultiHeadedQueue.scala:7:7]
wire _io_deq_bits_0_T_1 = reset; // @[Util.scala:12:13]
wire _io_deq_bits_1_T_1 = reset; // @[Util.scala:12:13]
wire _waddr_T_1 = reset; // @[Util.scala:12:13]
wire _raddr_T_1 = reset; // @[Util.scala:12:13]
wire io_enq_bits_rob_id_valid = 1'h1; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_rob_id_valid = 1'h1; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_rob_id_valid = 1'h1; // @[MultiHeadedQueue.scala:7:7]
wire _io_deq_bits_0_T = 1'h1; // @[Util.scala:12:16]
wire _io_deq_bits_0_T_5 = 1'h1; // @[Util.scala:13:22]
wire _io_deq_bits_0_T_8 = 1'h1; // @[Util.scala:13:13]
wire _io_deq_bits_1_T = 1'h1; // @[Util.scala:12:16]
wire _io_deq_bits_1_T_7 = 1'h1; // @[Util.scala:13:26]
wire _io_deq_bits_1_T_9 = 1'h1; // @[Util.scala:13:37]
wire _waddr_T = 1'h1; // @[Util.scala:12:16]
wire _waddr_T_7 = 1'h1; // @[Util.scala:13:26]
wire _waddr_T_9 = 1'h1; // @[Util.scala:13:37]
wire _raddr_T = 1'h1; // @[Util.scala:12:16]
wire _io_deq_bits_0_T_3 = 1'h0; // @[Util.scala:12:13]
wire _io_deq_bits_0_T_7 = 1'h0; // @[Util.scala:13:26]
wire _io_deq_bits_0_T_9 = 1'h0; // @[Util.scala:13:37]
wire _io_deq_bits_0_T_10 = 1'h0; // @[Util.scala:13:32]
wire _io_deq_bits_1_T_3 = 1'h0; // @[Util.scala:12:13]
wire _io_deq_bits_1_T_5 = 1'h0; // @[Util.scala:13:22]
wire _waddr_T_3 = 1'h0; // @[Util.scala:12:13]
wire _waddr_T_5 = 1'h0; // @[Util.scala:13:22]
wire _raddr_T_3 = 1'h0; // @[Util.scala:12:13]
wire [1:0] _io_deq_bits_0_T_4 = 2'h1; // @[Util.scala:13:22]
wire [1:0] _io_deq_bits_1_T_6 = 2'h1; // @[Util.scala:13:26]
wire [1:0] _waddr_T_6 = 2'h1; // @[Util.scala:13:26]
wire [1:0] _io_deq_bits_0_T_6 = 2'h2; // @[Util.scala:13:26]
wire _io_enq_ready_T; // @[MultiHeadedQueue.scala:27:23]
wire [1:0] _io_deq_bits_1_T_4 = 2'h0; // @[Util.scala:13:22]
wire [1:0] _waddr_T_4 = 2'h0; // @[Util.scala:13:22]
wire _io_deq_valid_0_T; // @[MultiHeadedQueue.scala:31:28]
wire _io_deq_valid_1_T; // @[MultiHeadedQueue.scala:31:28]
wire _raddr_T_9 = io_deq_pop_0; // @[Util.scala:13:37]
wire io_enq_ready_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_valid_0_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_valid_1_0; // @[MultiHeadedQueue.scala:7:7]
wire [6:0] io_deq_bits_0_cmd_inst_funct_0; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_deq_bits_0_cmd_inst_rs2_0; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_deq_bits_0_cmd_inst_rs1_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_inst_xd_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_inst_xs1_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_inst_xs2_0; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_deq_bits_0_cmd_inst_rd_0; // @[MultiHeadedQueue.scala:7:7]
wire [6:0] io_deq_bits_0_cmd_inst_opcode_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_debug_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_cease_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_wfi_0; // @[MultiHeadedQueue.scala:7:7]
wire [31:0] io_deq_bits_0_cmd_status_isa_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_dprv_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_dv_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_prv_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_v_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_sd_0; // @[MultiHeadedQueue.scala:7:7]
wire [22:0] io_deq_bits_0_cmd_status_zero2_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_mpv_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_gva_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_mbe_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_sbe_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_sxl_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_uxl_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_sd_rv32_0; // @[MultiHeadedQueue.scala:7:7]
wire [7:0] io_deq_bits_0_cmd_status_zero1_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_tsr_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_tw_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_tvm_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_mxr_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_sum_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_mprv_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_xs_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_fs_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_mpp_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_0_cmd_status_vs_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_spp_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_mpie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_ube_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_spie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_upie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_mie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_hie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_sie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_cmd_status_uie_0; // @[MultiHeadedQueue.scala:7:7]
wire [63:0] io_deq_bits_0_cmd_rs1_0; // @[MultiHeadedQueue.scala:7:7]
wire [63:0] io_deq_bits_0_cmd_rs2_0; // @[MultiHeadedQueue.scala:7:7]
wire [5:0] io_deq_bits_0_rob_id_bits_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_from_matmul_fsm_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_0_from_conv_fsm_0; // @[MultiHeadedQueue.scala:7:7]
wire [6:0] io_deq_bits_1_cmd_inst_funct_0; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_deq_bits_1_cmd_inst_rs2; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_deq_bits_1_cmd_inst_rs1; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_inst_xd_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_inst_xs1_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_inst_xs2_0; // @[MultiHeadedQueue.scala:7:7]
wire [4:0] io_deq_bits_1_cmd_inst_rd_0; // @[MultiHeadedQueue.scala:7:7]
wire [6:0] io_deq_bits_1_cmd_inst_opcode_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_debug_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_cease_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_wfi_0; // @[MultiHeadedQueue.scala:7:7]
wire [31:0] io_deq_bits_1_cmd_status_isa_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_dprv_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_dv_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_prv_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_v_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_sd_0; // @[MultiHeadedQueue.scala:7:7]
wire [22:0] io_deq_bits_1_cmd_status_zero2_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_mpv_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_gva_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_mbe_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_sbe_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_sxl_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_uxl_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_sd_rv32_0; // @[MultiHeadedQueue.scala:7:7]
wire [7:0] io_deq_bits_1_cmd_status_zero1_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_tsr_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_tw_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_tvm_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_mxr_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_sum_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_mprv_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_xs_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_fs_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_mpp_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_deq_bits_1_cmd_status_vs_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_spp_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_mpie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_ube_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_spie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_upie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_mie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_hie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_sie_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_cmd_status_uie_0; // @[MultiHeadedQueue.scala:7:7]
wire [63:0] io_deq_bits_1_cmd_rs1_0; // @[MultiHeadedQueue.scala:7:7]
wire [63:0] io_deq_bits_1_cmd_rs2_0; // @[MultiHeadedQueue.scala:7:7]
wire [5:0] io_deq_bits_1_rob_id_bits_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_from_matmul_fsm_0; // @[MultiHeadedQueue.scala:7:7]
wire io_deq_bits_1_from_conv_fsm_0; // @[MultiHeadedQueue.scala:7:7]
wire [1:0] io_len; // @[MultiHeadedQueue.scala:7:7]
reg [6:0] regs_0_cmd_inst_funct; // @[MultiHeadedQueue.scala:22:17]
reg [4:0] regs_0_cmd_inst_rs2; // @[MultiHeadedQueue.scala:22:17]
reg [4:0] regs_0_cmd_inst_rs1; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_inst_xd; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_inst_xs1; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_inst_xs2; // @[MultiHeadedQueue.scala:22:17]
reg [4:0] regs_0_cmd_inst_rd; // @[MultiHeadedQueue.scala:22:17]
reg [6:0] regs_0_cmd_inst_opcode; // @[MultiHeadedQueue.scala:22:17]
reg [63:0] regs_0_cmd_rs1; // @[MultiHeadedQueue.scala:22:17]
reg [63:0] regs_0_cmd_rs2; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_debug; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_cease; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_wfi; // @[MultiHeadedQueue.scala:22:17]
reg [31:0] regs_0_cmd_status_isa; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_dprv; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_dv; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_prv; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_v; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_sd; // @[MultiHeadedQueue.scala:22:17]
reg [22:0] regs_0_cmd_status_zero2; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_mpv; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_gva; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_mbe; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_sbe; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_sxl; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_uxl; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_sd_rv32; // @[MultiHeadedQueue.scala:22:17]
reg [7:0] regs_0_cmd_status_zero1; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_tsr; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_tw; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_tvm; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_mxr; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_sum; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_mprv; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_xs; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_fs; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_mpp; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_0_cmd_status_vs; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_spp; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_mpie; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_ube; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_spie; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_upie; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_mie; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_hie; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_sie; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_cmd_status_uie; // @[MultiHeadedQueue.scala:22:17]
reg [5:0] regs_0_rob_id_bits; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_from_matmul_fsm; // @[MultiHeadedQueue.scala:22:17]
reg regs_0_from_conv_fsm; // @[MultiHeadedQueue.scala:22:17]
reg [6:0] regs_1_cmd_inst_funct; // @[MultiHeadedQueue.scala:22:17]
reg [4:0] regs_1_cmd_inst_rs2; // @[MultiHeadedQueue.scala:22:17]
reg [4:0] regs_1_cmd_inst_rs1; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_inst_xd; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_inst_xs1; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_inst_xs2; // @[MultiHeadedQueue.scala:22:17]
reg [4:0] regs_1_cmd_inst_rd; // @[MultiHeadedQueue.scala:22:17]
reg [6:0] regs_1_cmd_inst_opcode; // @[MultiHeadedQueue.scala:22:17]
reg [63:0] regs_1_cmd_rs1; // @[MultiHeadedQueue.scala:22:17]
reg [63:0] regs_1_cmd_rs2; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_debug; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_cease; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_wfi; // @[MultiHeadedQueue.scala:22:17]
reg [31:0] regs_1_cmd_status_isa; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_dprv; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_dv; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_prv; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_v; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_sd; // @[MultiHeadedQueue.scala:22:17]
reg [22:0] regs_1_cmd_status_zero2; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_mpv; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_gva; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_mbe; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_sbe; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_sxl; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_uxl; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_sd_rv32; // @[MultiHeadedQueue.scala:22:17]
reg [7:0] regs_1_cmd_status_zero1; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_tsr; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_tw; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_tvm; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_mxr; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_sum; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_mprv; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_xs; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_fs; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_mpp; // @[MultiHeadedQueue.scala:22:17]
reg [1:0] regs_1_cmd_status_vs; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_spp; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_mpie; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_ube; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_spie; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_upie; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_mie; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_hie; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_sie; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_cmd_status_uie; // @[MultiHeadedQueue.scala:22:17]
reg [5:0] regs_1_rob_id_bits; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_from_matmul_fsm; // @[MultiHeadedQueue.scala:22:17]
reg regs_1_from_conv_fsm; // @[MultiHeadedQueue.scala:22:17]
reg raddr; // @[MultiHeadedQueue.scala:23:22]
wire _io_deq_bits_1_T_8 = raddr; // @[Util.scala:13:13]
reg waddr; // @[MultiHeadedQueue.scala:24:22]
wire _waddr_T_8 = waddr; // @[Util.scala:13:13]
reg [1:0] len; // @[MultiHeadedQueue.scala:25:20]
assign io_len = len; // @[MultiHeadedQueue.scala:7:7, :25:20]
assign _io_deq_valid_1_T = len[1]; // @[MultiHeadedQueue.scala:25:20, :27:23, :31:28]
assign _io_enq_ready_T = ~_io_deq_valid_1_T; // @[MultiHeadedQueue.scala:27:23, :31:28]
assign io_enq_ready_0 = _io_enq_ready_T; // @[MultiHeadedQueue.scala:7:7, :27:23]
assign _io_deq_valid_0_T = |len; // @[MultiHeadedQueue.scala:25:20, :31:28]
assign io_deq_valid_0_0 = _io_deq_valid_0_T; // @[MultiHeadedQueue.scala:7:7, :31:28]
wire _io_deq_bits_0_T_2 = ~_io_deq_bits_0_T_1; // @[Util.scala:12:13]
wire [1:0] _io_deq_bits_0_T_17 = {1'h0, raddr}; // @[Util.scala:13:{57,71}]
wire [1:0] _GEN = 2'h1 - _io_deq_bits_0_T_17; // @[Util.scala:13:{57,71}]
wire [1:0] _io_deq_bits_0_T_11; // @[Util.scala:13:57]
assign _io_deq_bits_0_T_11 = _GEN; // @[Util.scala:13:57]
wire [1:0] _io_deq_bits_1_T_11; // @[Util.scala:13:57]
assign _io_deq_bits_1_T_11 = _GEN; // @[Util.scala:13:57]
wire [1:0] _raddr_T_11; // @[Util.scala:13:57]
assign _raddr_T_11 = _GEN; // @[Util.scala:13:57]
wire _io_deq_bits_0_T_12 = _io_deq_bits_0_T_11[0]; // @[Util.scala:13:57]
wire [1:0] _io_deq_bits_0_T_13 = 2'h0 - {1'h0, _io_deq_bits_0_T_12}; // @[Util.scala:13:{48,57}]
wire _io_deq_bits_0_T_14 = _io_deq_bits_0_T_13[0]; // @[Util.scala:13:48]
wire [1:0] _io_deq_bits_0_T_15 = {1'h0, _io_deq_bits_0_T_14} - 2'h1; // @[Util.scala:13:{48,62}]
wire _io_deq_bits_0_T_16 = _io_deq_bits_0_T_15[0]; // @[Util.scala:13:62]
wire _io_deq_bits_0_T_18 = _io_deq_bits_0_T_17[0]; // @[Util.scala:13:71]
wire _io_deq_bits_0_T_19 = _io_deq_bits_0_T_18; // @[Util.scala:13:{10,71}]
assign io_deq_bits_0_cmd_inst_funct_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_funct : regs_0_cmd_inst_funct; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_inst_rs2_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_rs2 : regs_0_cmd_inst_rs2; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_inst_rs1_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_rs1 : regs_0_cmd_inst_rs1; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_inst_xd_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_xd : regs_0_cmd_inst_xd; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_inst_xs1_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_xs1 : regs_0_cmd_inst_xs1; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_inst_xs2_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_xs2 : regs_0_cmd_inst_xs2; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_inst_rd_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_rd : regs_0_cmd_inst_rd; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_inst_opcode_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_inst_opcode : regs_0_cmd_inst_opcode; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_rs1_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_rs1 : regs_0_cmd_rs1; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_rs2_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_rs2 : regs_0_cmd_rs2; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_debug_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_debug : regs_0_cmd_status_debug; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_cease_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_cease : regs_0_cmd_status_cease; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_wfi_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_wfi : regs_0_cmd_status_wfi; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_isa_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_isa : regs_0_cmd_status_isa; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_dprv_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_dprv : regs_0_cmd_status_dprv; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_dv_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_dv : regs_0_cmd_status_dv; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_prv_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_prv : regs_0_cmd_status_prv; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_v_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_v : regs_0_cmd_status_v; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_sd_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_sd : regs_0_cmd_status_sd; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_zero2_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_zero2 : regs_0_cmd_status_zero2; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_mpv_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_mpv : regs_0_cmd_status_mpv; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_gva_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_gva : regs_0_cmd_status_gva; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_mbe_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_mbe : regs_0_cmd_status_mbe; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_sbe_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_sbe : regs_0_cmd_status_sbe; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_sxl_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_sxl : regs_0_cmd_status_sxl; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_uxl_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_uxl : regs_0_cmd_status_uxl; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_sd_rv32_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_sd_rv32 : regs_0_cmd_status_sd_rv32; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_zero1_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_zero1 : regs_0_cmd_status_zero1; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_tsr_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_tsr : regs_0_cmd_status_tsr; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_tw_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_tw : regs_0_cmd_status_tw; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_tvm_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_tvm : regs_0_cmd_status_tvm; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_mxr_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_mxr : regs_0_cmd_status_mxr; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_sum_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_sum : regs_0_cmd_status_sum; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_mprv_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_mprv : regs_0_cmd_status_mprv; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_xs_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_xs : regs_0_cmd_status_xs; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_fs_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_fs : regs_0_cmd_status_fs; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_mpp_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_mpp : regs_0_cmd_status_mpp; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_vs_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_vs : regs_0_cmd_status_vs; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_spp_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_spp : regs_0_cmd_status_spp; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_mpie_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_mpie : regs_0_cmd_status_mpie; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_ube_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_ube : regs_0_cmd_status_ube; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_spie_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_spie : regs_0_cmd_status_spie; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_upie_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_upie : regs_0_cmd_status_upie; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_mie_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_mie : regs_0_cmd_status_mie; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_hie_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_hie : regs_0_cmd_status_hie; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_sie_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_sie : regs_0_cmd_status_sie; // @[Util.scala:13:10]
assign io_deq_bits_0_cmd_status_uie_0 = _io_deq_bits_0_T_19 ? regs_1_cmd_status_uie : regs_0_cmd_status_uie; // @[Util.scala:13:10]
assign io_deq_bits_0_rob_id_bits_0 = _io_deq_bits_0_T_19 ? regs_1_rob_id_bits : regs_0_rob_id_bits; // @[Util.scala:13:10]
assign io_deq_bits_0_from_matmul_fsm_0 = _io_deq_bits_0_T_19 ? regs_1_from_matmul_fsm : regs_0_from_matmul_fsm; // @[Util.scala:13:10]
assign io_deq_bits_0_from_conv_fsm_0 = _io_deq_bits_0_T_19 ? regs_1_from_conv_fsm : regs_0_from_conv_fsm; // @[Util.scala:13:10]
assign io_deq_valid_1_0 = _io_deq_valid_1_T; // @[MultiHeadedQueue.scala:7:7, :31:28]
wire _io_deq_bits_1_T_2 = ~_io_deq_bits_1_T_1; // @[Util.scala:12:13]
wire _io_deq_bits_1_T_10 = _io_deq_bits_1_T_8; // @[Util.scala:13:{13,32}]
wire _io_deq_bits_1_T_12 = _io_deq_bits_1_T_11[0]; // @[Util.scala:13:57]
wire [1:0] _io_deq_bits_1_T_13 = 2'h1 - {1'h0, _io_deq_bits_1_T_12}; // @[Util.scala:13:{48,57}]
wire _io_deq_bits_1_T_14 = _io_deq_bits_1_T_13[0]; // @[Util.scala:13:48]
wire [1:0] _io_deq_bits_1_T_15 = {1'h0, _io_deq_bits_1_T_14} - 2'h1; // @[Util.scala:13:{48,62}]
wire _io_deq_bits_1_T_16 = _io_deq_bits_1_T_15[0]; // @[Util.scala:13:62]
wire [1:0] _io_deq_bits_1_T_17 = _io_deq_bits_0_T_17 + 2'h1; // @[Util.scala:13:71]
wire _io_deq_bits_1_T_18 = _io_deq_bits_1_T_17[0]; // @[Util.scala:13:71]
wire _io_deq_bits_1_T_19 = _io_deq_bits_1_T_10 ? _io_deq_bits_1_T_16 : _io_deq_bits_1_T_18; // @[Util.scala:13:{10,32,62,71}]
assign io_deq_bits_1_cmd_inst_funct_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_funct : regs_0_cmd_inst_funct; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_inst_rs2 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_rs2 : regs_0_cmd_inst_rs2; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_inst_rs1 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_rs1 : regs_0_cmd_inst_rs1; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_inst_xd_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_xd : regs_0_cmd_inst_xd; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_inst_xs1_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_xs1 : regs_0_cmd_inst_xs1; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_inst_xs2_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_xs2 : regs_0_cmd_inst_xs2; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_inst_rd_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_rd : regs_0_cmd_inst_rd; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_inst_opcode_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_inst_opcode : regs_0_cmd_inst_opcode; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_rs1_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_rs1 : regs_0_cmd_rs1; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_rs2_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_rs2 : regs_0_cmd_rs2; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_debug_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_debug : regs_0_cmd_status_debug; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_cease_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_cease : regs_0_cmd_status_cease; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_wfi_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_wfi : regs_0_cmd_status_wfi; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_isa_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_isa : regs_0_cmd_status_isa; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_dprv_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_dprv : regs_0_cmd_status_dprv; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_dv_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_dv : regs_0_cmd_status_dv; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_prv_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_prv : regs_0_cmd_status_prv; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_v_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_v : regs_0_cmd_status_v; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_sd_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_sd : regs_0_cmd_status_sd; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_zero2_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_zero2 : regs_0_cmd_status_zero2; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_mpv_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_mpv : regs_0_cmd_status_mpv; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_gva_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_gva : regs_0_cmd_status_gva; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_mbe_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_mbe : regs_0_cmd_status_mbe; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_sbe_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_sbe : regs_0_cmd_status_sbe; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_sxl_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_sxl : regs_0_cmd_status_sxl; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_uxl_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_uxl : regs_0_cmd_status_uxl; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_sd_rv32_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_sd_rv32 : regs_0_cmd_status_sd_rv32; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_zero1_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_zero1 : regs_0_cmd_status_zero1; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_tsr_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_tsr : regs_0_cmd_status_tsr; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_tw_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_tw : regs_0_cmd_status_tw; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_tvm_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_tvm : regs_0_cmd_status_tvm; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_mxr_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_mxr : regs_0_cmd_status_mxr; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_sum_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_sum : regs_0_cmd_status_sum; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_mprv_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_mprv : regs_0_cmd_status_mprv; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_xs_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_xs : regs_0_cmd_status_xs; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_fs_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_fs : regs_0_cmd_status_fs; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_mpp_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_mpp : regs_0_cmd_status_mpp; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_vs_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_vs : regs_0_cmd_status_vs; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_spp_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_spp : regs_0_cmd_status_spp; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_mpie_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_mpie : regs_0_cmd_status_mpie; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_ube_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_ube : regs_0_cmd_status_ube; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_spie_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_spie : regs_0_cmd_status_spie; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_upie_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_upie : regs_0_cmd_status_upie; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_mie_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_mie : regs_0_cmd_status_mie; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_hie_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_hie : regs_0_cmd_status_hie; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_sie_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_sie : regs_0_cmd_status_sie; // @[Util.scala:13:10]
assign io_deq_bits_1_cmd_status_uie_0 = _io_deq_bits_1_T_19 ? regs_1_cmd_status_uie : regs_0_cmd_status_uie; // @[Util.scala:13:10]
assign io_deq_bits_1_rob_id_bits_0 = _io_deq_bits_1_T_19 ? regs_1_rob_id_bits : regs_0_rob_id_bits; // @[Util.scala:13:10]
assign io_deq_bits_1_from_matmul_fsm_0 = _io_deq_bits_1_T_19 ? regs_1_from_matmul_fsm : regs_0_from_matmul_fsm; // @[Util.scala:13:10]
assign io_deq_bits_1_from_conv_fsm_0 = _io_deq_bits_1_T_19 ? regs_1_from_conv_fsm : regs_0_from_conv_fsm; // @[Util.scala:13:10]
wire _len_T_4 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _waddr_T_2 = ~_waddr_T_1; // @[Util.scala:12:13]
wire _waddr_T_10 = _waddr_T_8; // @[Util.scala:13:{13,32}]
wire [1:0] _GEN_0 = {1'h0, waddr}; // @[Util.scala:13:57]
wire [1:0] _waddr_T_11 = 2'h1 - _GEN_0; // @[Util.scala:13:57]
wire _waddr_T_12 = _waddr_T_11[0]; // @[Util.scala:13:57]
wire [1:0] _waddr_T_13 = 2'h1 - {1'h0, _waddr_T_12}; // @[Util.scala:13:{48,57}]
wire _waddr_T_14 = _waddr_T_13[0]; // @[Util.scala:13:48]
wire [1:0] _waddr_T_15 = {1'h0, _waddr_T_14} - 2'h1; // @[Util.scala:13:{48,62}]
wire _waddr_T_16 = _waddr_T_15[0]; // @[Util.scala:13:62]
wire [1:0] _waddr_T_17 = _GEN_0 + 2'h1; // @[Util.scala:13:{57,71}]
wire _waddr_T_18 = _waddr_T_17[0]; // @[Util.scala:13:71]
wire _waddr_T_19 = _waddr_T_10 ? _waddr_T_16 : _waddr_T_18; // @[Util.scala:13:{10,32,62,71}]
wire [2:0] _GEN_1 = {1'h0, len}; // @[MultiHeadedQueue.scala:25:20, :39:16]
wire [2:0] _len_T = _GEN_1 + 3'h1; // @[MultiHeadedQueue.scala:39:16]
wire [1:0] _len_T_1 = _len_T[1:0]; // @[MultiHeadedQueue.scala:39:16]
wire _raddr_T_2 = ~_raddr_T_1; // @[Util.scala:12:13]
wire [1:0] _GEN_2 = {1'h0, io_deq_pop_0}; // @[Util.scala:13:22]
wire [1:0] _raddr_T_4 = 2'h1 - _GEN_2; // @[Util.scala:13:22]
wire _raddr_T_5 = _raddr_T_4[0]; // @[Util.scala:13:22]
wire [1:0] _raddr_T_6 = {1'h0, _raddr_T_5} + 2'h1; // @[Util.scala:13:{22,26}]
wire _raddr_T_7 = _raddr_T_6[0]; // @[Util.scala:13:26]
wire _raddr_T_8 = raddr >= _raddr_T_7; // @[Util.scala:13:{13,26}]
wire _raddr_T_10 = _raddr_T_8 & _raddr_T_9; // @[Util.scala:13:{13,32,37}]
wire _raddr_T_12 = _raddr_T_11[0]; // @[Util.scala:13:57]
wire [1:0] _raddr_T_13 = _GEN_2 - {1'h0, _raddr_T_12}; // @[Util.scala:13:{22,48,57}]
wire _raddr_T_14 = _raddr_T_13[0]; // @[Util.scala:13:48]
wire [1:0] _raddr_T_15 = {1'h0, _raddr_T_14} - 2'h1; // @[Util.scala:13:{48,62}]
wire _raddr_T_16 = _raddr_T_15[0]; // @[Util.scala:13:62]
wire [1:0] _raddr_T_17 = _io_deq_bits_0_T_17 + _GEN_2; // @[Util.scala:13:{22,71}]
wire _raddr_T_18 = _raddr_T_17[0]; // @[Util.scala:13:71]
wire _raddr_T_19 = _raddr_T_10 ? _raddr_T_16 : _raddr_T_18; // @[Util.scala:13:{10,32,62,71}]
wire [2:0] _len_T_2 = _GEN_1 - {2'h0, io_deq_pop_0}; // @[MultiHeadedQueue.scala:7:7, :39:16, :45:16]
wire [1:0] _len_T_3 = _len_T_2[1:0]; // @[MultiHeadedQueue.scala:45:16]
wire [2:0] _len_T_5 = {1'h0, _len_T_3} + {2'h0, _len_T_4}; // @[Decoupled.scala:51:35]
wire [1:0] _len_T_6 = _len_T_5[1:0]; // @[MultiHeadedQueue.scala:45:29] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_37 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_37( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_8 :
input clock : Clock
input reset : Reset
output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}}, resp : { `3` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `2` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `1` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `0` : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, channel_status : { flip `3` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6]}, out_allocs : { `3` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6]}}
regreset mask : UInt<4>, clock, reset, UInt<4>(0h0)
wire in_arb_reqs : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}[4]
wire in_arb_vals : UInt<1>[4]
node in_arb_filter_lo = cat(in_arb_vals[1], in_arb_vals[0])
node in_arb_filter_hi = cat(in_arb_vals[3], in_arb_vals[2])
node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo)
node in_arb_filter_lo_1 = cat(in_arb_vals[1], in_arb_vals[0])
node in_arb_filter_hi_1 = cat(in_arb_vals[3], in_arb_vals[2])
node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1)
node _in_arb_filter_T_2 = not(mask)
node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2)
node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3)
node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0)
node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1)
node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2)
node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3)
node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4)
node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5)
node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6)
node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7)
node _in_arb_filter_T_13 = mux(_in_arb_filter_T_12, UInt<8>(0h80), UInt<8>(0h0))
node _in_arb_filter_T_14 = mux(_in_arb_filter_T_11, UInt<8>(0h40), _in_arb_filter_T_13)
node _in_arb_filter_T_15 = mux(_in_arb_filter_T_10, UInt<8>(0h20), _in_arb_filter_T_14)
node _in_arb_filter_T_16 = mux(_in_arb_filter_T_9, UInt<8>(0h10), _in_arb_filter_T_15)
node _in_arb_filter_T_17 = mux(_in_arb_filter_T_8, UInt<8>(0h8), _in_arb_filter_T_16)
node _in_arb_filter_T_18 = mux(_in_arb_filter_T_7, UInt<8>(0h4), _in_arb_filter_T_17)
node _in_arb_filter_T_19 = mux(_in_arb_filter_T_6, UInt<8>(0h2), _in_arb_filter_T_18)
node in_arb_filter = mux(_in_arb_filter_T_5, UInt<8>(0h1), _in_arb_filter_T_19)
node _in_arb_sel_T = bits(in_arb_filter, 3, 0)
node _in_arb_sel_T_1 = shr(in_arb_filter, 4)
node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1)
node _T = or(in_arb_vals[0], in_arb_vals[1])
node _T_1 = or(_T, in_arb_vals[2])
node _T_2 = or(_T_1, in_arb_vals[3])
when _T_2 :
node _mask_T = not(UInt<1>(0h0))
node _mask_T_1 = not(UInt<2>(0h0))
node _mask_T_2 = not(UInt<3>(0h0))
node _mask_T_3 = not(UInt<4>(0h0))
node _mask_T_4 = bits(in_arb_sel, 0, 0)
node _mask_T_5 = bits(in_arb_sel, 1, 1)
node _mask_T_6 = bits(in_arb_sel, 2, 2)
node _mask_T_7 = bits(in_arb_sel, 3, 3)
node _mask_T_8 = mux(_mask_T_4, _mask_T, UInt<1>(0h0))
node _mask_T_9 = mux(_mask_T_5, _mask_T_1, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_6, _mask_T_2, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_7, _mask_T_3, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_8, _mask_T_9)
node _mask_T_13 = or(_mask_T_12, _mask_T_10)
node _mask_T_14 = or(_mask_T_13, _mask_T_11)
wire _mask_WIRE : UInt<4>
connect _mask_WIRE, _mask_T_14
connect mask, _mask_WIRE
node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T)
connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1
node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T)
connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1
node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T)
connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1
node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T)
connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1
node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T)
connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1
node _in_arb_reqs_0_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_5_T_1 = and(io.req.`0`.bits.vc_sel.`0`[5], _in_arb_reqs_0_0_5_T)
connect in_arb_reqs[0].`0`[5], _in_arb_reqs_0_0_5_T_1
node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T)
connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1
node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T)
connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1
node _in_arb_reqs_0_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_3_0_T_1 = and(io.req.`0`.bits.vc_sel.`3`[0], _in_arb_reqs_0_3_0_T)
connect in_arb_reqs[0].`3`[0], _in_arb_reqs_0_3_0_T_1
node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1])
node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2])
node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3])
node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4])
node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`0`[5])
node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`1`[0])
node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`2`[0])
node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`3`[0])
node _in_arb_vals_0_T_8 = and(io.req.`0`.valid, _in_arb_vals_0_T_7)
connect in_arb_vals[0], _in_arb_vals_0_T_8
node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T)
connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1
node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T)
connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1
node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T)
connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1
node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T)
connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1
node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T)
connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1
node _in_arb_reqs_1_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_5_T_1 = and(io.req.`1`.bits.vc_sel.`0`[5], _in_arb_reqs_1_0_5_T)
connect in_arb_reqs[1].`0`[5], _in_arb_reqs_1_0_5_T_1
node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T)
connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1
node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T)
connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1
node _in_arb_reqs_1_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_3_0_T_1 = and(io.req.`1`.bits.vc_sel.`3`[0], _in_arb_reqs_1_3_0_T)
connect in_arb_reqs[1].`3`[0], _in_arb_reqs_1_3_0_T_1
node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1])
node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2])
node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3])
node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4])
node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`0`[5])
node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`1`[0])
node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`2`[0])
node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`3`[0])
node _in_arb_vals_1_T_8 = and(io.req.`1`.valid, _in_arb_vals_1_T_7)
connect in_arb_vals[1], _in_arb_vals_1_T_8
node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T)
connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1
node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T)
connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1
node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T)
connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1
node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T)
connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1
node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T)
connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1
node _in_arb_reqs_2_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_5_T_1 = and(io.req.`2`.bits.vc_sel.`0`[5], _in_arb_reqs_2_0_5_T)
connect in_arb_reqs[2].`0`[5], _in_arb_reqs_2_0_5_T_1
node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T)
connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1
node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T)
connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1
node _in_arb_reqs_2_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_3_0_T_1 = and(io.req.`2`.bits.vc_sel.`3`[0], _in_arb_reqs_2_3_0_T)
connect in_arb_reqs[2].`3`[0], _in_arb_reqs_2_3_0_T_1
node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1])
node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2])
node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3])
node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4])
node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`0`[5])
node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`1`[0])
node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`2`[0])
node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`3`[0])
node _in_arb_vals_2_T_8 = and(io.req.`2`.valid, _in_arb_vals_2_T_7)
connect in_arb_vals[2], _in_arb_vals_2_T_8
node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T)
connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1
node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T)
connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1
node _in_arb_reqs_3_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_2_T_1 = and(io.req.`3`.bits.vc_sel.`0`[2], _in_arb_reqs_3_0_2_T)
connect in_arb_reqs[3].`0`[2], _in_arb_reqs_3_0_2_T_1
node _in_arb_reqs_3_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_3_T_1 = and(io.req.`3`.bits.vc_sel.`0`[3], _in_arb_reqs_3_0_3_T)
connect in_arb_reqs[3].`0`[3], _in_arb_reqs_3_0_3_T_1
node _in_arb_reqs_3_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_4_T_1 = and(io.req.`3`.bits.vc_sel.`0`[4], _in_arb_reqs_3_0_4_T)
connect in_arb_reqs[3].`0`[4], _in_arb_reqs_3_0_4_T_1
node _in_arb_reqs_3_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_5_T_1 = and(io.req.`3`.bits.vc_sel.`0`[5], _in_arb_reqs_3_0_5_T)
connect in_arb_reqs[3].`0`[5], _in_arb_reqs_3_0_5_T_1
node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T)
connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1
node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T)
connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1
node _in_arb_reqs_3_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_3_0_T_1 = and(io.req.`3`.bits.vc_sel.`3`[0], _in_arb_reqs_3_3_0_T)
connect in_arb_reqs[3].`3`[0], _in_arb_reqs_3_3_0_T_1
node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1])
node _in_arb_vals_3_T_1 = or(_in_arb_vals_3_T, in_arb_reqs[3].`0`[2])
node _in_arb_vals_3_T_2 = or(_in_arb_vals_3_T_1, in_arb_reqs[3].`0`[3])
node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`0`[4])
node _in_arb_vals_3_T_4 = or(_in_arb_vals_3_T_3, in_arb_reqs[3].`0`[5])
node _in_arb_vals_3_T_5 = or(_in_arb_vals_3_T_4, in_arb_reqs[3].`1`[0])
node _in_arb_vals_3_T_6 = or(_in_arb_vals_3_T_5, in_arb_reqs[3].`2`[0])
node _in_arb_vals_3_T_7 = or(_in_arb_vals_3_T_6, in_arb_reqs[3].`3`[0])
node _in_arb_vals_3_T_8 = and(io.req.`3`.valid, _in_arb_vals_3_T_7)
connect in_arb_vals[3], _in_arb_vals_3_T_8
connect io.req.`0`.ready, UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h0)
connect io.req.`2`.ready, UInt<1>(0h0)
connect io.req.`3`.ready, UInt<1>(0h0)
wire in_alloc : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
node _in_flow_T = bits(in_arb_sel, 0, 0)
node _in_flow_T_1 = bits(in_arb_sel, 1, 1)
node _in_flow_T_2 = bits(in_arb_sel, 2, 2)
node _in_flow_T_3 = bits(in_arb_sel, 3, 3)
wire in_flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _in_flow_T_4 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_5 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_6 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_7 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_8 = or(_in_flow_T_4, _in_flow_T_5)
node _in_flow_T_9 = or(_in_flow_T_8, _in_flow_T_6)
node _in_flow_T_10 = or(_in_flow_T_9, _in_flow_T_7)
wire _in_flow_WIRE : UInt<2>
connect _in_flow_WIRE, _in_flow_T_10
connect in_flow.egress_node_id, _in_flow_WIRE
node _in_flow_T_11 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_12 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_13 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_14 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_15 = or(_in_flow_T_11, _in_flow_T_12)
node _in_flow_T_16 = or(_in_flow_T_15, _in_flow_T_13)
node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_14)
wire _in_flow_WIRE_1 : UInt<4>
connect _in_flow_WIRE_1, _in_flow_T_17
connect in_flow.egress_node, _in_flow_WIRE_1
node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_21 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_22 = or(_in_flow_T_18, _in_flow_T_19)
node _in_flow_T_23 = or(_in_flow_T_22, _in_flow_T_20)
node _in_flow_T_24 = or(_in_flow_T_23, _in_flow_T_21)
wire _in_flow_WIRE_2 : UInt<2>
connect _in_flow_WIRE_2, _in_flow_T_24
connect in_flow.ingress_node_id, _in_flow_WIRE_2
node _in_flow_T_25 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_26 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_27 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_28 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_29 = or(_in_flow_T_25, _in_flow_T_26)
node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_27)
node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_28)
wire _in_flow_WIRE_3 : UInt<4>
connect _in_flow_WIRE_3, _in_flow_T_31
connect in_flow.ingress_node, _in_flow_WIRE_3
node _in_flow_T_32 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_33 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_34 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_35 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_36 = or(_in_flow_T_32, _in_flow_T_33)
node _in_flow_T_37 = or(_in_flow_T_36, _in_flow_T_34)
node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_35)
wire _in_flow_WIRE_4 : UInt<2>
connect _in_flow_WIRE_4, _in_flow_T_38
connect in_flow.vnet_id, _in_flow_WIRE_4
node _in_vc_T = bits(in_arb_sel, 0, 0)
node _in_vc_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_T_3 = bits(in_arb_sel, 3, 3)
node _in_vc_T_4 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_5 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_6 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_7 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_8 = or(_in_vc_T_4, _in_vc_T_5)
node _in_vc_T_9 = or(_in_vc_T_8, _in_vc_T_6)
node _in_vc_T_10 = or(_in_vc_T_9, _in_vc_T_7)
wire in_vc : UInt<3>
connect in_vc, _in_vc_T_10
node _in_vc_sel_T = bits(in_arb_sel, 0, 0)
node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3)
wire in_vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
wire _in_vc_sel_WIRE : UInt<1>[6]
node _in_vc_sel_T_4 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_5 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_6 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_7 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_8 = or(_in_vc_sel_T_4, _in_vc_sel_T_5)
node _in_vc_sel_T_9 = or(_in_vc_sel_T_8, _in_vc_sel_T_6)
node _in_vc_sel_T_10 = or(_in_vc_sel_T_9, _in_vc_sel_T_7)
wire _in_vc_sel_WIRE_1 : UInt<1>
connect _in_vc_sel_WIRE_1, _in_vc_sel_T_10
connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1
node _in_vc_sel_T_11 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_12 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_13 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_14 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_15 = or(_in_vc_sel_T_11, _in_vc_sel_T_12)
node _in_vc_sel_T_16 = or(_in_vc_sel_T_15, _in_vc_sel_T_13)
node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_14)
wire _in_vc_sel_WIRE_2 : UInt<1>
connect _in_vc_sel_WIRE_2, _in_vc_sel_T_17
connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2
node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_21 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_22 = or(_in_vc_sel_T_18, _in_vc_sel_T_19)
node _in_vc_sel_T_23 = or(_in_vc_sel_T_22, _in_vc_sel_T_20)
node _in_vc_sel_T_24 = or(_in_vc_sel_T_23, _in_vc_sel_T_21)
wire _in_vc_sel_WIRE_3 : UInt<1>
connect _in_vc_sel_WIRE_3, _in_vc_sel_T_24
connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3
node _in_vc_sel_T_25 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_26 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_27 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_28 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_29 = or(_in_vc_sel_T_25, _in_vc_sel_T_26)
node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_27)
node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_28)
wire _in_vc_sel_WIRE_4 : UInt<1>
connect _in_vc_sel_WIRE_4, _in_vc_sel_T_31
connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4
node _in_vc_sel_T_32 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_33 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_34 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_35 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_36 = or(_in_vc_sel_T_32, _in_vc_sel_T_33)
node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_34)
node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_35)
wire _in_vc_sel_WIRE_5 : UInt<1>
connect _in_vc_sel_WIRE_5, _in_vc_sel_T_38
connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5
node _in_vc_sel_T_39 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_40 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_41 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_42 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_43 = or(_in_vc_sel_T_39, _in_vc_sel_T_40)
node _in_vc_sel_T_44 = or(_in_vc_sel_T_43, _in_vc_sel_T_41)
node _in_vc_sel_T_45 = or(_in_vc_sel_T_44, _in_vc_sel_T_42)
wire _in_vc_sel_WIRE_6 : UInt<1>
connect _in_vc_sel_WIRE_6, _in_vc_sel_T_45
connect _in_vc_sel_WIRE[5], _in_vc_sel_WIRE_6
connect in_vc_sel.`0`, _in_vc_sel_WIRE
wire _in_vc_sel_WIRE_7 : UInt<1>[1]
node _in_vc_sel_T_46 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_47 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_48 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_49 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_50 = or(_in_vc_sel_T_46, _in_vc_sel_T_47)
node _in_vc_sel_T_51 = or(_in_vc_sel_T_50, _in_vc_sel_T_48)
node _in_vc_sel_T_52 = or(_in_vc_sel_T_51, _in_vc_sel_T_49)
wire _in_vc_sel_WIRE_8 : UInt<1>
connect _in_vc_sel_WIRE_8, _in_vc_sel_T_52
connect _in_vc_sel_WIRE_7[0], _in_vc_sel_WIRE_8
connect in_vc_sel.`1`, _in_vc_sel_WIRE_7
wire _in_vc_sel_WIRE_9 : UInt<1>[1]
node _in_vc_sel_T_53 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_54 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_55 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_56 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_57 = or(_in_vc_sel_T_53, _in_vc_sel_T_54)
node _in_vc_sel_T_58 = or(_in_vc_sel_T_57, _in_vc_sel_T_55)
node _in_vc_sel_T_59 = or(_in_vc_sel_T_58, _in_vc_sel_T_56)
wire _in_vc_sel_WIRE_10 : UInt<1>
connect _in_vc_sel_WIRE_10, _in_vc_sel_T_59
connect _in_vc_sel_WIRE_9[0], _in_vc_sel_WIRE_10
connect in_vc_sel.`2`, _in_vc_sel_WIRE_9
wire _in_vc_sel_WIRE_11 : UInt<1>[1]
node _in_vc_sel_T_60 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_61 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_62 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_63 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_64 = or(_in_vc_sel_T_60, _in_vc_sel_T_61)
node _in_vc_sel_T_65 = or(_in_vc_sel_T_64, _in_vc_sel_T_62)
node _in_vc_sel_T_66 = or(_in_vc_sel_T_65, _in_vc_sel_T_63)
wire _in_vc_sel_WIRE_12 : UInt<1>
connect _in_vc_sel_WIRE_12, _in_vc_sel_T_66
connect _in_vc_sel_WIRE_11[0], _in_vc_sel_WIRE_12
connect in_vc_sel.`3`, _in_vc_sel_WIRE_11
node _T_3 = or(in_arb_vals[0], in_arb_vals[1])
node _T_4 = or(_T_3, in_arb_vals[2])
node _T_5 = or(_T_4, in_arb_vals[3])
node hi = bits(in_arb_sel, 3, 2)
node lo = bits(in_arb_sel, 1, 0)
node _T_6 = orr(hi)
node _T_7 = or(hi, lo)
node _T_8 = bits(_T_7, 1, 1)
node _T_9 = cat(_T_6, _T_8)
node _T_10 = and(io.req.`0`.ready, io.req.`0`.valid)
node _T_11 = and(io.req.`1`.ready, io.req.`1`.valid)
node _T_12 = and(io.req.`2`.ready, io.req.`2`.valid)
node _T_13 = and(io.req.`3`.ready, io.req.`3`.valid)
node _T_14 = or(_T_10, _T_11)
node _T_15 = or(_T_14, _T_12)
node _T_16 = or(_T_15, _T_13)
node lo_hi = cat(in_vc_sel.`0`[2], in_vc_sel.`0`[1])
node lo_1 = cat(lo_hi, in_vc_sel.`0`[0])
node hi_hi = cat(in_vc_sel.`0`[5], in_vc_sel.`0`[4])
node hi_1 = cat(hi_hi, in_vc_sel.`0`[3])
node _T_17 = cat(hi_1, lo_1)
node lo_2 = cat(in_vc_sel.`1`[0], _T_17)
node hi_2 = cat(in_vc_sel.`3`[0], in_vc_sel.`2`[0])
node _T_18 = cat(hi_2, lo_2)
regreset mask_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _full_T = not(mask_1)
node _full_T_1 = and(_T_18, _full_T)
node full = cat(_T_18, _full_T_1)
node _oh_T = bits(full, 0, 0)
node _oh_T_1 = bits(full, 1, 1)
node _oh_T_2 = bits(full, 2, 2)
node _oh_T_3 = bits(full, 3, 3)
node _oh_T_4 = bits(full, 4, 4)
node _oh_T_5 = bits(full, 5, 5)
node _oh_T_6 = bits(full, 6, 6)
node _oh_T_7 = bits(full, 7, 7)
node _oh_T_8 = bits(full, 8, 8)
node _oh_T_9 = bits(full, 9, 9)
node _oh_T_10 = bits(full, 10, 10)
node _oh_T_11 = bits(full, 11, 11)
node _oh_T_12 = bits(full, 12, 12)
node _oh_T_13 = bits(full, 13, 13)
node _oh_T_14 = bits(full, 14, 14)
node _oh_T_15 = bits(full, 15, 15)
node _oh_T_16 = bits(full, 16, 16)
node _oh_T_17 = bits(full, 17, 17)
node _oh_T_18 = mux(_oh_T_17, UInt<18>(0h20000), UInt<18>(0h0))
node _oh_T_19 = mux(_oh_T_16, UInt<18>(0h10000), _oh_T_18)
node _oh_T_20 = mux(_oh_T_15, UInt<18>(0h8000), _oh_T_19)
node _oh_T_21 = mux(_oh_T_14, UInt<18>(0h4000), _oh_T_20)
node _oh_T_22 = mux(_oh_T_13, UInt<18>(0h2000), _oh_T_21)
node _oh_T_23 = mux(_oh_T_12, UInt<18>(0h1000), _oh_T_22)
node _oh_T_24 = mux(_oh_T_11, UInt<18>(0h800), _oh_T_23)
node _oh_T_25 = mux(_oh_T_10, UInt<18>(0h400), _oh_T_24)
node _oh_T_26 = mux(_oh_T_9, UInt<18>(0h200), _oh_T_25)
node _oh_T_27 = mux(_oh_T_8, UInt<18>(0h100), _oh_T_26)
node _oh_T_28 = mux(_oh_T_7, UInt<18>(0h80), _oh_T_27)
node _oh_T_29 = mux(_oh_T_6, UInt<18>(0h40), _oh_T_28)
node _oh_T_30 = mux(_oh_T_5, UInt<18>(0h20), _oh_T_29)
node _oh_T_31 = mux(_oh_T_4, UInt<18>(0h10), _oh_T_30)
node _oh_T_32 = mux(_oh_T_3, UInt<18>(0h8), _oh_T_31)
node _oh_T_33 = mux(_oh_T_2, UInt<18>(0h4), _oh_T_32)
node _oh_T_34 = mux(_oh_T_1, UInt<18>(0h2), _oh_T_33)
node oh = mux(_oh_T, UInt<18>(0h1), _oh_T_34)
node _sel_T = bits(oh, 8, 0)
node _sel_T_1 = shr(oh, 9)
node sel = or(_sel_T, _sel_T_1)
when _T_16 :
node _mask_T_15 = bits(sel, 0, 0)
node _mask_T_16 = not(UInt<1>(0h0))
node _mask_T_17 = bits(sel, 1, 1)
node _mask_T_18 = not(UInt<2>(0h0))
node _mask_T_19 = bits(sel, 2, 2)
node _mask_T_20 = not(UInt<3>(0h0))
node _mask_T_21 = bits(sel, 3, 3)
node _mask_T_22 = not(UInt<4>(0h0))
node _mask_T_23 = bits(sel, 4, 4)
node _mask_T_24 = not(UInt<5>(0h0))
node _mask_T_25 = bits(sel, 5, 5)
node _mask_T_26 = not(UInt<6>(0h0))
node _mask_T_27 = bits(sel, 6, 6)
node _mask_T_28 = not(UInt<7>(0h0))
node _mask_T_29 = bits(sel, 7, 7)
node _mask_T_30 = not(UInt<8>(0h0))
node _mask_T_31 = bits(sel, 8, 8)
node _mask_T_32 = not(UInt<9>(0h0))
node _mask_T_33 = mux(_mask_T_31, _mask_T_32, UInt<1>(0h0))
node _mask_T_34 = mux(_mask_T_29, _mask_T_30, _mask_T_33)
node _mask_T_35 = mux(_mask_T_27, _mask_T_28, _mask_T_34)
node _mask_T_36 = mux(_mask_T_25, _mask_T_26, _mask_T_35)
node _mask_T_37 = mux(_mask_T_23, _mask_T_24, _mask_T_36)
node _mask_T_38 = mux(_mask_T_21, _mask_T_22, _mask_T_37)
node _mask_T_39 = mux(_mask_T_19, _mask_T_20, _mask_T_38)
node _mask_T_40 = mux(_mask_T_17, _mask_T_18, _mask_T_39)
node _mask_T_41 = mux(_mask_T_15, _mask_T_16, _mask_T_40)
connect mask_1, _mask_T_41
wire _WIRE : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
wire _WIRE_1 : UInt<9>
connect _WIRE_1, sel
node _T_19 = bits(_WIRE_1, 0, 0)
connect _WIRE.`0`[0], _T_19
node _T_20 = bits(_WIRE_1, 1, 1)
connect _WIRE.`0`[1], _T_20
node _T_21 = bits(_WIRE_1, 2, 2)
connect _WIRE.`0`[2], _T_21
node _T_22 = bits(_WIRE_1, 3, 3)
connect _WIRE.`0`[3], _T_22
node _T_23 = bits(_WIRE_1, 4, 4)
connect _WIRE.`0`[4], _T_23
node _T_24 = bits(_WIRE_1, 5, 5)
connect _WIRE.`0`[5], _T_24
node _T_25 = bits(_WIRE_1, 6, 6)
connect _WIRE.`1`[0], _T_25
node _T_26 = bits(_WIRE_1, 7, 7)
connect _WIRE.`2`[0], _T_26
node _T_27 = bits(_WIRE_1, 8, 8)
connect _WIRE.`3`[0], _T_27
wire _WIRE_2 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
connect _WIRE_2.`0`[0], UInt<1>(0h0)
connect _WIRE_2.`0`[1], UInt<1>(0h0)
connect _WIRE_2.`0`[2], UInt<1>(0h0)
connect _WIRE_2.`0`[3], UInt<1>(0h0)
connect _WIRE_2.`0`[4], UInt<1>(0h0)
connect _WIRE_2.`0`[5], UInt<1>(0h0)
connect _WIRE_2.`1`[0], UInt<1>(0h0)
connect _WIRE_2.`2`[0], UInt<1>(0h0)
connect _WIRE_2.`3`[0], UInt<1>(0h0)
node _T_28 = mux(_T_5, _WIRE, _WIRE_2)
connect in_alloc.`0`, _T_28.`0`
connect in_alloc.`1`, _T_28.`1`
connect in_alloc.`2`, _T_28.`2`
connect in_alloc.`3`, _T_28.`3`
node _io_req_0_ready_T = bits(in_arb_sel, 0, 0)
connect io.req.`0`.ready, _io_req_0_ready_T
connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`0`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`0`.vc_sel.`3`[0], in_alloc.`3`[0]
node lo_hi_1 = cat(io.resp.`0`.vc_sel.`0`[2], io.resp.`0`.vc_sel.`0`[1])
node lo_3 = cat(lo_hi_1, io.resp.`0`.vc_sel.`0`[0])
node hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[5], io.resp.`0`.vc_sel.`0`[4])
node hi_3 = cat(hi_hi_1, io.resp.`0`.vc_sel.`0`[3])
node _T_29 = cat(hi_3, lo_3)
node lo_4 = cat(io.resp.`0`.vc_sel.`1`[0], _T_29)
node hi_4 = cat(io.resp.`0`.vc_sel.`3`[0], io.resp.`0`.vc_sel.`2`[0])
node _T_30 = cat(hi_4, lo_4)
node _T_31 = bits(_T_30, 0, 0)
node _T_32 = bits(_T_30, 1, 1)
node _T_33 = bits(_T_30, 2, 2)
node _T_34 = bits(_T_30, 3, 3)
node _T_35 = bits(_T_30, 4, 4)
node _T_36 = bits(_T_30, 5, 5)
node _T_37 = bits(_T_30, 6, 6)
node _T_38 = bits(_T_30, 7, 7)
node _T_39 = bits(_T_30, 8, 8)
node _T_40 = add(_T_31, _T_32)
node _T_41 = bits(_T_40, 1, 0)
node _T_42 = add(_T_33, _T_34)
node _T_43 = bits(_T_42, 1, 0)
node _T_44 = add(_T_41, _T_43)
node _T_45 = bits(_T_44, 2, 0)
node _T_46 = add(_T_35, _T_36)
node _T_47 = bits(_T_46, 1, 0)
node _T_48 = add(_T_38, _T_39)
node _T_49 = bits(_T_48, 1, 0)
node _T_50 = add(_T_37, _T_49)
node _T_51 = bits(_T_50, 1, 0)
node _T_52 = add(_T_47, _T_51)
node _T_53 = bits(_T_52, 2, 0)
node _T_54 = add(_T_45, _T_53)
node _T_55 = bits(_T_54, 3, 0)
node _T_56 = leq(_T_55, UInt<1>(0h1))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf
assert(clock, _T_56, UInt<1>(0h1), "") : assert
node _io_req_1_ready_T = bits(in_arb_sel, 1, 1)
connect io.req.`1`.ready, _io_req_1_ready_T
connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`1`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`1`.vc_sel.`3`[0], in_alloc.`3`[0]
node lo_hi_2 = cat(io.resp.`1`.vc_sel.`0`[2], io.resp.`1`.vc_sel.`0`[1])
node lo_5 = cat(lo_hi_2, io.resp.`1`.vc_sel.`0`[0])
node hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[5], io.resp.`1`.vc_sel.`0`[4])
node hi_5 = cat(hi_hi_2, io.resp.`1`.vc_sel.`0`[3])
node _T_60 = cat(hi_5, lo_5)
node lo_6 = cat(io.resp.`1`.vc_sel.`1`[0], _T_60)
node hi_6 = cat(io.resp.`1`.vc_sel.`3`[0], io.resp.`1`.vc_sel.`2`[0])
node _T_61 = cat(hi_6, lo_6)
node _T_62 = bits(_T_61, 0, 0)
node _T_63 = bits(_T_61, 1, 1)
node _T_64 = bits(_T_61, 2, 2)
node _T_65 = bits(_T_61, 3, 3)
node _T_66 = bits(_T_61, 4, 4)
node _T_67 = bits(_T_61, 5, 5)
node _T_68 = bits(_T_61, 6, 6)
node _T_69 = bits(_T_61, 7, 7)
node _T_70 = bits(_T_61, 8, 8)
node _T_71 = add(_T_62, _T_63)
node _T_72 = bits(_T_71, 1, 0)
node _T_73 = add(_T_64, _T_65)
node _T_74 = bits(_T_73, 1, 0)
node _T_75 = add(_T_72, _T_74)
node _T_76 = bits(_T_75, 2, 0)
node _T_77 = add(_T_66, _T_67)
node _T_78 = bits(_T_77, 1, 0)
node _T_79 = add(_T_69, _T_70)
node _T_80 = bits(_T_79, 1, 0)
node _T_81 = add(_T_68, _T_80)
node _T_82 = bits(_T_81, 1, 0)
node _T_83 = add(_T_78, _T_82)
node _T_84 = bits(_T_83, 2, 0)
node _T_85 = add(_T_76, _T_84)
node _T_86 = bits(_T_85, 3, 0)
node _T_87 = leq(_T_86, UInt<1>(0h1))
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1
assert(clock, _T_87, UInt<1>(0h1), "") : assert_1
node _io_req_2_ready_T = bits(in_arb_sel, 2, 2)
connect io.req.`2`.ready, _io_req_2_ready_T
connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`2`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`2`.vc_sel.`3`[0], in_alloc.`3`[0]
node lo_hi_3 = cat(io.resp.`2`.vc_sel.`0`[2], io.resp.`2`.vc_sel.`0`[1])
node lo_7 = cat(lo_hi_3, io.resp.`2`.vc_sel.`0`[0])
node hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[5], io.resp.`2`.vc_sel.`0`[4])
node hi_7 = cat(hi_hi_3, io.resp.`2`.vc_sel.`0`[3])
node _T_91 = cat(hi_7, lo_7)
node lo_8 = cat(io.resp.`2`.vc_sel.`1`[0], _T_91)
node hi_8 = cat(io.resp.`2`.vc_sel.`3`[0], io.resp.`2`.vc_sel.`2`[0])
node _T_92 = cat(hi_8, lo_8)
node _T_93 = bits(_T_92, 0, 0)
node _T_94 = bits(_T_92, 1, 1)
node _T_95 = bits(_T_92, 2, 2)
node _T_96 = bits(_T_92, 3, 3)
node _T_97 = bits(_T_92, 4, 4)
node _T_98 = bits(_T_92, 5, 5)
node _T_99 = bits(_T_92, 6, 6)
node _T_100 = bits(_T_92, 7, 7)
node _T_101 = bits(_T_92, 8, 8)
node _T_102 = add(_T_93, _T_94)
node _T_103 = bits(_T_102, 1, 0)
node _T_104 = add(_T_95, _T_96)
node _T_105 = bits(_T_104, 1, 0)
node _T_106 = add(_T_103, _T_105)
node _T_107 = bits(_T_106, 2, 0)
node _T_108 = add(_T_97, _T_98)
node _T_109 = bits(_T_108, 1, 0)
node _T_110 = add(_T_100, _T_101)
node _T_111 = bits(_T_110, 1, 0)
node _T_112 = add(_T_99, _T_111)
node _T_113 = bits(_T_112, 1, 0)
node _T_114 = add(_T_109, _T_113)
node _T_115 = bits(_T_114, 2, 0)
node _T_116 = add(_T_107, _T_115)
node _T_117 = bits(_T_116, 3, 0)
node _T_118 = leq(_T_117, UInt<1>(0h1))
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2
assert(clock, _T_118, UInt<1>(0h1), "") : assert_2
node _io_req_3_ready_T = bits(in_arb_sel, 3, 3)
connect io.req.`3`.ready, _io_req_3_ready_T
connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`3`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`3`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`3`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`3`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`3`.vc_sel.`3`[0], in_alloc.`3`[0]
node lo_hi_4 = cat(io.resp.`3`.vc_sel.`0`[2], io.resp.`3`.vc_sel.`0`[1])
node lo_9 = cat(lo_hi_4, io.resp.`3`.vc_sel.`0`[0])
node hi_hi_4 = cat(io.resp.`3`.vc_sel.`0`[5], io.resp.`3`.vc_sel.`0`[4])
node hi_9 = cat(hi_hi_4, io.resp.`3`.vc_sel.`0`[3])
node _T_122 = cat(hi_9, lo_9)
node lo_10 = cat(io.resp.`3`.vc_sel.`1`[0], _T_122)
node hi_10 = cat(io.resp.`3`.vc_sel.`3`[0], io.resp.`3`.vc_sel.`2`[0])
node _T_123 = cat(hi_10, lo_10)
node _T_124 = bits(_T_123, 0, 0)
node _T_125 = bits(_T_123, 1, 1)
node _T_126 = bits(_T_123, 2, 2)
node _T_127 = bits(_T_123, 3, 3)
node _T_128 = bits(_T_123, 4, 4)
node _T_129 = bits(_T_123, 5, 5)
node _T_130 = bits(_T_123, 6, 6)
node _T_131 = bits(_T_123, 7, 7)
node _T_132 = bits(_T_123, 8, 8)
node _T_133 = add(_T_124, _T_125)
node _T_134 = bits(_T_133, 1, 0)
node _T_135 = add(_T_126, _T_127)
node _T_136 = bits(_T_135, 1, 0)
node _T_137 = add(_T_134, _T_136)
node _T_138 = bits(_T_137, 2, 0)
node _T_139 = add(_T_128, _T_129)
node _T_140 = bits(_T_139, 1, 0)
node _T_141 = add(_T_131, _T_132)
node _T_142 = bits(_T_141, 1, 0)
node _T_143 = add(_T_130, _T_142)
node _T_144 = bits(_T_143, 1, 0)
node _T_145 = add(_T_140, _T_144)
node _T_146 = bits(_T_145, 2, 0)
node _T_147 = add(_T_138, _T_146)
node _T_148 = bits(_T_147, 3, 0)
node _T_149 = leq(_T_148, UInt<1>(0h1))
node _T_150 = asUInt(reset)
node _T_151 = eq(_T_150, UInt<1>(0h0))
when _T_151 :
node _T_152 = eq(_T_149, UInt<1>(0h0))
when _T_152 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3
assert(clock, _T_149, UInt<1>(0h1), "") : assert_3
connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0]
connect io.out_allocs.`0`[0].flow, in_flow
connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1]
connect io.out_allocs.`0`[1].flow, in_flow
connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2]
connect io.out_allocs.`0`[2].flow, in_flow
connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3]
connect io.out_allocs.`0`[3].flow, in_flow
connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4]
connect io.out_allocs.`0`[4].flow, in_flow
connect io.out_allocs.`0`[5].alloc, in_alloc.`0`[5]
connect io.out_allocs.`0`[5].flow, in_flow
connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0]
connect io.out_allocs.`1`[0].flow, in_flow
connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0]
connect io.out_allocs.`2`[0].flow, in_flow
connect io.out_allocs.`3`[0].alloc, in_alloc.`3`[0]
connect io.out_allocs.`3`[0].flow, in_flow | module RotatingSingleVCAllocator_8( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_3_ready, // @[VCAllocator.scala:49:14]
input io_req_3_valid, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_2_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_5_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [3:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [3:0] _in_arb_filter_T_3 = {in_arb_vals_3, 1'h0, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39]
wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : in_arb_vals_1 ? 8'h20 : {in_arb_vals_3, 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] in_arb_sel = in_arb_filter[3:0] | in_arb_filter[7:4]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_3; // @[package.scala:81:59]
wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_3 = io_req_0_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_4 = io_req_0_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_5 = io_req_0_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (io_req_0_bits_vc_sel_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_0_3 | in_arb_reqs_0_0_4 | in_arb_reqs_0_0_5 | in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0 | in_arb_reqs_0_3_0); // @[package.scala:81:59]
wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (io_req_1_bits_vc_sel_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_0_3 | in_arb_reqs_1_0_4 | in_arb_reqs_1_0_5 | in_arb_reqs_1_1_0 | in_arb_reqs_1_2_0 | in_arb_reqs_1_3_0); // @[package.scala:81:59]
wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_2 = io_req_3_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_3 = io_req_3_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_4 = io_req_3_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_5 = io_req_3_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_3_0 = io_req_3_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_3 = io_req_3_valid & (io_req_3_bits_vc_sel_0_0 | in_arb_reqs_3_0_1 | in_arb_reqs_3_0_2 | in_arb_reqs_3_0_3 | in_arb_reqs_3_0_4 | in_arb_reqs_3_0_5 | in_arb_reqs_3_1_0 | in_arb_reqs_3_2_0 | in_arb_reqs_3_3_0); // @[package.scala:81:59]
wire _in_vc_sel_T_10 = in_arb_sel[0] & io_req_0_bits_vc_sel_0_0 | in_arb_sel[1] & io_req_1_bits_vc_sel_0_0 | in_arb_sel[3] & io_req_3_bits_vc_sel_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_17 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[3] & in_arb_reqs_3_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_24 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2 | in_arb_sel[3] & in_arb_reqs_3_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_0_3 | in_arb_sel[1] & in_arb_reqs_1_0_3 | in_arb_sel[3] & in_arb_reqs_3_0_3; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_38 = in_arb_sel[0] & in_arb_reqs_0_0_4 | in_arb_sel[1] & in_arb_reqs_1_0_4 | in_arb_sel[3] & in_arb_reqs_3_0_4; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_45 = in_arb_sel[0] & in_arb_reqs_0_0_5 | in_arb_sel[1] & in_arb_reqs_1_0_5 | in_arb_sel[3] & in_arb_reqs_3_0_5; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_52 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[3] & in_arb_reqs_3_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_59 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_66 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[1] & in_arb_reqs_1_3_0 | in_arb_sel[3] & in_arb_reqs_3_3_0; // @[Mux.scala:30:73, :32:36]
reg [8:0] mask_1; // @[ISLIP.scala:17:25]
wire [8:0] _full_T_1 = {_in_vc_sel_T_66, _in_vc_sel_T_59, _in_vc_sel_T_52, _in_vc_sel_T_45, _in_vc_sel_T_38, _in_vc_sel_T_31, _in_vc_sel_T_24, _in_vc_sel_T_17, _in_vc_sel_T_10} & ~mask_1; // @[Mux.scala:30:73]
wire [17:0] oh = _full_T_1[0] ? 18'h1 : _full_T_1[1] ? 18'h2 : _full_T_1[2] ? 18'h4 : _full_T_1[3] ? 18'h8 : _full_T_1[4] ? 18'h10 : _full_T_1[5] ? 18'h20 : _full_T_1[6] ? 18'h40 : _full_T_1[7] ? 18'h80 : _full_T_1[8] ? 18'h100 : _in_vc_sel_T_10 ? 18'h200 : _in_vc_sel_T_17 ? 18'h400 : _in_vc_sel_T_24 ? 18'h800 : _in_vc_sel_T_31 ? 18'h1000 : _in_vc_sel_T_38 ? 18'h2000 : _in_vc_sel_T_45 ? 18'h4000 : _in_vc_sel_T_52 ? 18'h8000 : _in_vc_sel_T_59 ? 18'h10000 : {_in_vc_sel_T_66, 17'h0}; // @[OneHot.scala:85:71]
wire [8:0] sel = oh[8:0] | oh[17:9]; // @[Mux.scala:50:70]
wire in_alloc_3_0 = _GEN & sel[8]; // @[package.scala:81:59]
wire in_alloc_2_0 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]
wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59] |
Generate the Verilog code corresponding to this FIRRTL code module LCG16_5 :
input clock : Clock
input reset : Reset
output io : { out : UInt<16>, flip inc : UInt<1>}
reg state : UInt<32>, clock
when io.inc :
node _state_T = mul(state, UInt<32>(0h41c64e6d))
node _state_T_1 = add(_state_T, UInt<32>(0h3039))
node _state_T_2 = tail(_state_T_1, 1)
connect state, _state_T_2
node _io_out_T = bits(state, 30, 15)
connect io.out, _io_out_T | module LCG16_5( // @[LCG.scala:15:7]
input clock, // @[LCG.scala:15:7]
input reset, // @[LCG.scala:15:7]
output [15:0] io_out // @[LCG.scala:16:14]
);
wire io_inc = 1'h1; // @[LCG.scala:15:7, :16:14]
wire [15:0] _io_out_T; // @[LCG.scala:24:18]
wire [15:0] io_out_0; // @[LCG.scala:15:7]
reg [31:0] state; // @[LCG.scala:20:18]
wire [63:0] _state_T = {32'h0, state} * 64'h41C64E6D; // @[LCG.scala:20:18, :22:20]
wire [64:0] _state_T_1 = {1'h0, _state_T} + 65'h3039; // @[LCG.scala:22:{20,41}]
wire [63:0] _state_T_2 = _state_T_1[63:0]; // @[LCG.scala:22:41]
assign _io_out_T = state[30:15]; // @[LCG.scala:20:18, :24:18]
assign io_out_0 = _io_out_T; // @[LCG.scala:15:7, :24:18]
always @(posedge clock) // @[LCG.scala:15:7]
state <= _state_T_2[31:0]; // @[LCG.scala:20:18, :22:{11,41}]
assign io_out = io_out_0; // @[LCG.scala:15:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ConstellationSystemBus :
output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, coupler_to_bus_named_coh_widget_anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_9 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_8 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_7 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_6 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst sbus_clock_groups of ClockGroupAggregator_sbus
inst clockGroup of ClockGroup
inst fixedClockNode of FixedClockBroadcast_11
inst broadcast of BundleBridgeNexus_NoOutput
inst system_bus_noc of TLSplitACDxBENoC
connect system_bus_noc.clock, childClock
connect system_bus_noc.reset, childReset
inst fixer of TLFIFOFixer
connect fixer.clock, childClock
connect fixer.reset, childReset
inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus
connect coupler_to_bus_named_cbus.clock, childClock
connect coupler_to_bus_named_cbus.reset, childReset
inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus
connect coupler_from_bus_named_fbus.clock, childClock
connect coupler_from_bus_named_fbus.reset, childReset
inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh
connect coupler_to_bus_named_coh.clock, childClock
connect coupler_to_bus_named_coh.reset, childReset
inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile
connect coupler_from_rockettile.clock, childClock
connect coupler_from_rockettile.reset, childReset
inst coupler_from_rockettile_1 of TLInterconnectCoupler_sbus_from_rockettile_1
connect coupler_from_rockettile_1.clock, childClock
connect coupler_from_rockettile_1.reset, childReset
inst coupler_from_rockettile_2 of TLInterconnectCoupler_sbus_from_rockettile_2
connect coupler_from_rockettile_2.clock, childClock
connect coupler_from_rockettile_2.reset, childReset
inst coupler_from_rockettile_3 of TLInterconnectCoupler_sbus_from_rockettile_3
connect coupler_from_rockettile_3.clock, childClock
connect coupler_from_rockettile_3.reset, childReset
inst coupler_from_rockettile_4 of TLInterconnectCoupler_sbus_from_rockettile_4
connect coupler_from_rockettile_4.clock, childClock
connect coupler_from_rockettile_4.reset, childReset
inst coupler_from_rockettile_5 of TLInterconnectCoupler_sbus_from_rockettile_5
connect coupler_from_rockettile_5.clock, childClock
connect coupler_from_rockettile_5.reset, childReset
inst coupler_from_rockettile_6 of TLInterconnectCoupler_sbus_from_rockettile_6
connect coupler_from_rockettile_6.clock, childClock
connect coupler_from_rockettile_6.reset, childReset
inst coupler_from_rockettile_7 of TLInterconnectCoupler_sbus_from_rockettile_7
connect coupler_from_rockettile_7.clock, childClock
connect coupler_from_rockettile_7.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
connect clockGroup.auto.in, sbus_clock_groups.auto.out_0
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_noc.auto.out_0
connect coupler_to_bus_named_coh.auto.widget_anon_in_0, system_bus_noc.auto.out_1
connect coupler_to_bus_named_coh.auto.widget_anon_in_1, system_bus_noc.auto.out_2
connect coupler_to_bus_named_coh.auto.widget_anon_in_2, system_bus_noc.auto.out_3
connect coupler_to_bus_named_coh.auto.widget_anon_in_3, system_bus_noc.auto.out_4
connect system_bus_noc.auto.in_0, fixer.auto.anon_out_0
connect system_bus_noc.auto.in_1, fixer.auto.anon_out_1
connect system_bus_noc.auto.in_2, fixer.auto.anon_out_2
connect system_bus_noc.auto.in_3, fixer.auto.anon_out_3
connect system_bus_noc.auto.in_4, fixer.auto.anon_out_4
connect system_bus_noc.auto.in_5, fixer.auto.anon_out_5
connect system_bus_noc.auto.in_6, fixer.auto.anon_out_6
connect system_bus_noc.auto.in_7, fixer.auto.anon_out_7
connect system_bus_noc.auto.in_8, fixer.auto.anon_out_8
connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out
connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out
connect fixer.auto.anon_in_2, coupler_from_rockettile_1.auto.tl_out
connect fixer.auto.anon_in_3, coupler_from_rockettile_2.auto.tl_out
connect fixer.auto.anon_in_4, coupler_from_rockettile_3.auto.tl_out
connect fixer.auto.anon_in_5, coupler_from_rockettile_4.auto.tl_out
connect fixer.auto.anon_in_6, coupler_from_rockettile_5.auto.tl_out
connect fixer.auto.anon_in_7, coupler_from_rockettile_6.auto.tl_out
connect fixer.auto.anon_in_8, coupler_from_rockettile_7.auto.tl_out
connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1
connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3
connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4
connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5
connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6
connect auto.fixedClockNode_anon_out_6, fixedClockNode.auto.anon_out_7
connect auto.fixedClockNode_anon_out_7, fixedClockNode.auto.anon_out_8
connect auto.fixedClockNode_anon_out_8, fixedClockNode.auto.anon_out_9
connect auto.fixedClockNode_anon_out_9, fixedClockNode.auto.anon_out_10
connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready
connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.d, auto.coupler_to_bus_named_coh_widget_anon_out_0.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.b, auto.coupler_to_bus_named_coh_widget_anon_out_0.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_0.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_0.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_0.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_0.a.ready
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.d, auto.coupler_to_bus_named_coh_widget_anon_out_1.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.b, auto.coupler_to_bus_named_coh_widget_anon_out_1.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_1.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_1.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_1.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_1.a.ready
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.d, auto.coupler_to_bus_named_coh_widget_anon_out_2.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.b, auto.coupler_to_bus_named_coh_widget_anon_out_2.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_2.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_2.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_2.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_2.a.ready
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.d, auto.coupler_to_bus_named_coh_widget_anon_out_3.d
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.b, auto.coupler_to_bus_named_coh_widget_anon_out_3.b
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out_3.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out_3.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out_3.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out_3.a.ready
connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_0
connect coupler_from_rockettile_1.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_1
connect coupler_from_rockettile_2.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_2
connect coupler_from_rockettile_3.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_3
connect coupler_from_rockettile_4.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_4
connect coupler_from_rockettile_5.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_5
connect coupler_from_rockettile_6.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_6
connect coupler_from_rockettile_7.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_7
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module ConstellationSystemBus( // @[ClockDomain.scala:14:9]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_7_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_7_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_7_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_6_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_6_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_6_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_5_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_5_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_5_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_4_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_4_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_4_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_8_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_8_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_7_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_7_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_6_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_6_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114]
wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114]
FixedClockBroadcast_11 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (auto_sbus_clock_groups_in_member_sbus_0_clock),
.auto_anon_in_reset (auto_sbus_clock_groups_in_member_sbus_0_reset),
.auto_anon_out_9_clock (auto_fixedClockNode_anon_out_8_clock),
.auto_anon_out_9_reset (auto_fixedClockNode_anon_out_8_reset),
.auto_anon_out_8_clock (auto_fixedClockNode_anon_out_7_clock),
.auto_anon_out_8_reset (auto_fixedClockNode_anon_out_7_reset),
.auto_anon_out_7_clock (auto_fixedClockNode_anon_out_6_clock),
.auto_anon_out_7_reset (auto_fixedClockNode_anon_out_6_reset),
.auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock),
.auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset),
.auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock),
.auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset),
.auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock),
.auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset),
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset),
.auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock),
.auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset)
); // @[ClockGroup.scala:115:114]
TLSplitACDxBENoC system_bus_noc ( // @[Buses.scala:51:54]
.clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114]
.reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114]
.auto_in_8_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_ready),
.auto_in_8_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_valid),
.auto_in_8_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_opcode),
.auto_in_8_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_param),
.auto_in_8_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_size),
.auto_in_8_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_source),
.auto_in_8_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_address),
.auto_in_8_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_mask),
.auto_in_8_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_data),
.auto_in_8_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_corrupt),
.auto_in_8_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_ready),
.auto_in_8_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_valid),
.auto_in_8_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_opcode),
.auto_in_8_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_param),
.auto_in_8_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_size),
.auto_in_8_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_source),
.auto_in_8_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_address),
.auto_in_8_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_mask),
.auto_in_8_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_data),
.auto_in_8_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_corrupt),
.auto_in_8_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_ready),
.auto_in_8_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_valid),
.auto_in_8_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_opcode),
.auto_in_8_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_param),
.auto_in_8_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_size),
.auto_in_8_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_source),
.auto_in_8_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_address),
.auto_in_8_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_data),
.auto_in_8_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_bits_corrupt),
.auto_in_8_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_ready),
.auto_in_8_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_valid),
.auto_in_8_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_opcode),
.auto_in_8_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_param),
.auto_in_8_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_size),
.auto_in_8_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_source),
.auto_in_8_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_sink),
.auto_in_8_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_denied),
.auto_in_8_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_data),
.auto_in_8_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_corrupt),
.auto_in_8_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_e_ready),
.auto_in_8_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_e_valid),
.auto_in_8_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_7_e_bits_sink),
.auto_in_7_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_ready),
.auto_in_7_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_valid),
.auto_in_7_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_opcode),
.auto_in_7_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_param),
.auto_in_7_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_size),
.auto_in_7_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_source),
.auto_in_7_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_address),
.auto_in_7_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_mask),
.auto_in_7_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_data),
.auto_in_7_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_corrupt),
.auto_in_7_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_ready),
.auto_in_7_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_valid),
.auto_in_7_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_opcode),
.auto_in_7_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_param),
.auto_in_7_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_size),
.auto_in_7_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_source),
.auto_in_7_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_address),
.auto_in_7_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_mask),
.auto_in_7_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_data),
.auto_in_7_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_corrupt),
.auto_in_7_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_ready),
.auto_in_7_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_valid),
.auto_in_7_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_opcode),
.auto_in_7_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_param),
.auto_in_7_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_size),
.auto_in_7_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_source),
.auto_in_7_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_address),
.auto_in_7_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_data),
.auto_in_7_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_bits_corrupt),
.auto_in_7_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_ready),
.auto_in_7_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_valid),
.auto_in_7_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_opcode),
.auto_in_7_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_param),
.auto_in_7_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_size),
.auto_in_7_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_source),
.auto_in_7_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_sink),
.auto_in_7_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_denied),
.auto_in_7_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_data),
.auto_in_7_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_corrupt),
.auto_in_7_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_e_ready),
.auto_in_7_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_e_valid),
.auto_in_7_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_6_e_bits_sink),
.auto_in_6_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_ready),
.auto_in_6_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_valid),
.auto_in_6_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_opcode),
.auto_in_6_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_param),
.auto_in_6_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_size),
.auto_in_6_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_source),
.auto_in_6_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_address),
.auto_in_6_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_mask),
.auto_in_6_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_data),
.auto_in_6_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_corrupt),
.auto_in_6_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_ready),
.auto_in_6_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_valid),
.auto_in_6_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_opcode),
.auto_in_6_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_param),
.auto_in_6_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_size),
.auto_in_6_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_source),
.auto_in_6_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_address),
.auto_in_6_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_mask),
.auto_in_6_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_data),
.auto_in_6_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_corrupt),
.auto_in_6_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_ready),
.auto_in_6_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_valid),
.auto_in_6_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_opcode),
.auto_in_6_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_param),
.auto_in_6_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_size),
.auto_in_6_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_source),
.auto_in_6_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_address),
.auto_in_6_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_data),
.auto_in_6_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_bits_corrupt),
.auto_in_6_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_ready),
.auto_in_6_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_valid),
.auto_in_6_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_opcode),
.auto_in_6_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_param),
.auto_in_6_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_size),
.auto_in_6_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_source),
.auto_in_6_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_sink),
.auto_in_6_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_denied),
.auto_in_6_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_data),
.auto_in_6_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_corrupt),
.auto_in_6_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_e_ready),
.auto_in_6_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_e_valid),
.auto_in_6_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_5_e_bits_sink),
.auto_in_5_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_ready),
.auto_in_5_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_valid),
.auto_in_5_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_opcode),
.auto_in_5_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_param),
.auto_in_5_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_size),
.auto_in_5_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_source),
.auto_in_5_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_address),
.auto_in_5_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_mask),
.auto_in_5_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_data),
.auto_in_5_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_corrupt),
.auto_in_5_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_ready),
.auto_in_5_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_valid),
.auto_in_5_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_opcode),
.auto_in_5_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_param),
.auto_in_5_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_size),
.auto_in_5_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_source),
.auto_in_5_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_address),
.auto_in_5_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_mask),
.auto_in_5_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_data),
.auto_in_5_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_corrupt),
.auto_in_5_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_ready),
.auto_in_5_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_valid),
.auto_in_5_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_opcode),
.auto_in_5_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_param),
.auto_in_5_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_size),
.auto_in_5_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_source),
.auto_in_5_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_address),
.auto_in_5_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_data),
.auto_in_5_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_bits_corrupt),
.auto_in_5_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_ready),
.auto_in_5_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_valid),
.auto_in_5_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_opcode),
.auto_in_5_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_param),
.auto_in_5_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_size),
.auto_in_5_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_source),
.auto_in_5_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_sink),
.auto_in_5_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_denied),
.auto_in_5_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_data),
.auto_in_5_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_corrupt),
.auto_in_5_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_e_ready),
.auto_in_5_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_e_valid),
.auto_in_5_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_4_e_bits_sink),
.auto_in_4_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready),
.auto_in_4_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid),
.auto_in_4_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode),
.auto_in_4_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param),
.auto_in_4_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size),
.auto_in_4_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source),
.auto_in_4_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address),
.auto_in_4_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask),
.auto_in_4_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data),
.auto_in_4_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt),
.auto_in_4_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready),
.auto_in_4_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid),
.auto_in_4_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode),
.auto_in_4_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param),
.auto_in_4_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size),
.auto_in_4_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source),
.auto_in_4_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address),
.auto_in_4_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask),
.auto_in_4_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data),
.auto_in_4_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt),
.auto_in_4_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready),
.auto_in_4_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid),
.auto_in_4_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode),
.auto_in_4_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param),
.auto_in_4_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size),
.auto_in_4_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source),
.auto_in_4_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address),
.auto_in_4_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data),
.auto_in_4_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt),
.auto_in_4_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready),
.auto_in_4_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid),
.auto_in_4_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode),
.auto_in_4_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param),
.auto_in_4_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size),
.auto_in_4_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source),
.auto_in_4_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink),
.auto_in_4_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied),
.auto_in_4_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data),
.auto_in_4_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt),
.auto_in_4_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready),
.auto_in_4_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid),
.auto_in_4_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink),
.auto_in_3_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready),
.auto_in_3_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid),
.auto_in_3_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode),
.auto_in_3_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param),
.auto_in_3_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size),
.auto_in_3_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source),
.auto_in_3_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address),
.auto_in_3_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask),
.auto_in_3_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data),
.auto_in_3_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt),
.auto_in_3_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready),
.auto_in_3_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid),
.auto_in_3_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode),
.auto_in_3_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param),
.auto_in_3_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size),
.auto_in_3_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source),
.auto_in_3_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address),
.auto_in_3_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask),
.auto_in_3_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data),
.auto_in_3_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt),
.auto_in_3_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready),
.auto_in_3_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid),
.auto_in_3_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode),
.auto_in_3_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param),
.auto_in_3_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size),
.auto_in_3_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source),
.auto_in_3_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address),
.auto_in_3_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data),
.auto_in_3_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt),
.auto_in_3_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready),
.auto_in_3_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid),
.auto_in_3_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode),
.auto_in_3_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param),
.auto_in_3_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size),
.auto_in_3_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source),
.auto_in_3_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink),
.auto_in_3_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied),
.auto_in_3_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data),
.auto_in_3_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt),
.auto_in_3_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready),
.auto_in_3_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid),
.auto_in_3_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink),
.auto_in_2_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready),
.auto_in_2_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid),
.auto_in_2_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode),
.auto_in_2_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param),
.auto_in_2_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size),
.auto_in_2_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source),
.auto_in_2_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address),
.auto_in_2_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask),
.auto_in_2_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data),
.auto_in_2_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt),
.auto_in_2_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready),
.auto_in_2_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid),
.auto_in_2_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode),
.auto_in_2_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param),
.auto_in_2_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size),
.auto_in_2_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source),
.auto_in_2_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address),
.auto_in_2_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask),
.auto_in_2_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data),
.auto_in_2_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt),
.auto_in_2_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready),
.auto_in_2_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid),
.auto_in_2_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode),
.auto_in_2_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param),
.auto_in_2_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size),
.auto_in_2_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source),
.auto_in_2_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address),
.auto_in_2_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data),
.auto_in_2_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt),
.auto_in_2_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready),
.auto_in_2_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid),
.auto_in_2_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode),
.auto_in_2_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param),
.auto_in_2_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size),
.auto_in_2_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source),
.auto_in_2_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink),
.auto_in_2_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied),
.auto_in_2_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data),
.auto_in_2_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt),
.auto_in_2_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready),
.auto_in_2_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid),
.auto_in_2_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink),
.auto_in_1_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready),
.auto_in_1_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid),
.auto_in_1_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode),
.auto_in_1_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param),
.auto_in_1_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size),
.auto_in_1_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source),
.auto_in_1_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address),
.auto_in_1_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask),
.auto_in_1_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data),
.auto_in_1_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt),
.auto_in_1_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready),
.auto_in_1_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid),
.auto_in_1_b_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode),
.auto_in_1_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param),
.auto_in_1_b_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size),
.auto_in_1_b_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source),
.auto_in_1_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address),
.auto_in_1_b_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask),
.auto_in_1_b_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data),
.auto_in_1_b_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt),
.auto_in_1_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready),
.auto_in_1_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid),
.auto_in_1_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode),
.auto_in_1_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param),
.auto_in_1_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size),
.auto_in_1_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source),
.auto_in_1_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address),
.auto_in_1_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data),
.auto_in_1_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt),
.auto_in_1_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready),
.auto_in_1_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid),
.auto_in_1_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode),
.auto_in_1_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param),
.auto_in_1_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size),
.auto_in_1_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source),
.auto_in_1_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink),
.auto_in_1_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied),
.auto_in_1_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data),
.auto_in_1_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt),
.auto_in_1_e_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready),
.auto_in_1_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid),
.auto_in_1_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink),
.auto_in_0_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready),
.auto_in_0_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid),
.auto_in_0_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode),
.auto_in_0_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param),
.auto_in_0_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size),
.auto_in_0_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source),
.auto_in_0_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address),
.auto_in_0_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask),
.auto_in_0_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data),
.auto_in_0_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt),
.auto_in_0_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready),
.auto_in_0_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid),
.auto_in_0_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode),
.auto_in_0_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param),
.auto_in_0_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size),
.auto_in_0_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source),
.auto_in_0_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink),
.auto_in_0_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied),
.auto_in_0_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data),
.auto_in_0_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt),
.auto_out_4_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_ready),
.auto_out_4_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid),
.auto_out_4_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode),
.auto_out_4_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param),
.auto_out_4_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size),
.auto_out_4_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source),
.auto_out_4_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address),
.auto_out_4_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask),
.auto_out_4_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data),
.auto_out_4_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt),
.auto_out_4_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready),
.auto_out_4_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_valid),
.auto_out_4_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_param),
.auto_out_4_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_source),
.auto_out_4_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_b_bits_address),
.auto_out_4_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_ready),
.auto_out_4_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid),
.auto_out_4_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode),
.auto_out_4_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param),
.auto_out_4_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size),
.auto_out_4_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source),
.auto_out_4_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address),
.auto_out_4_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data),
.auto_out_4_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt),
.auto_out_4_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready),
.auto_out_4_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_valid),
.auto_out_4_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_opcode),
.auto_out_4_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_param),
.auto_out_4_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_size),
.auto_out_4_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_source),
.auto_out_4_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_sink),
.auto_out_4_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_denied),
.auto_out_4_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_data),
.auto_out_4_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_3_d_bits_corrupt),
.auto_out_4_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid),
.auto_out_4_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink),
.auto_out_3_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_ready),
.auto_out_3_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid),
.auto_out_3_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode),
.auto_out_3_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param),
.auto_out_3_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size),
.auto_out_3_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source),
.auto_out_3_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address),
.auto_out_3_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask),
.auto_out_3_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data),
.auto_out_3_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt),
.auto_out_3_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready),
.auto_out_3_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_valid),
.auto_out_3_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_param),
.auto_out_3_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_source),
.auto_out_3_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_b_bits_address),
.auto_out_3_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_ready),
.auto_out_3_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid),
.auto_out_3_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode),
.auto_out_3_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param),
.auto_out_3_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size),
.auto_out_3_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source),
.auto_out_3_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address),
.auto_out_3_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data),
.auto_out_3_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt),
.auto_out_3_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready),
.auto_out_3_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_valid),
.auto_out_3_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_opcode),
.auto_out_3_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_param),
.auto_out_3_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_size),
.auto_out_3_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_source),
.auto_out_3_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_sink),
.auto_out_3_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_denied),
.auto_out_3_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_data),
.auto_out_3_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_2_d_bits_corrupt),
.auto_out_3_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid),
.auto_out_3_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink),
.auto_out_2_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_ready),
.auto_out_2_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid),
.auto_out_2_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode),
.auto_out_2_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param),
.auto_out_2_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size),
.auto_out_2_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source),
.auto_out_2_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address),
.auto_out_2_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask),
.auto_out_2_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data),
.auto_out_2_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt),
.auto_out_2_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready),
.auto_out_2_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_valid),
.auto_out_2_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_param),
.auto_out_2_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_source),
.auto_out_2_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_b_bits_address),
.auto_out_2_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_ready),
.auto_out_2_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid),
.auto_out_2_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode),
.auto_out_2_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param),
.auto_out_2_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size),
.auto_out_2_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source),
.auto_out_2_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address),
.auto_out_2_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data),
.auto_out_2_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt),
.auto_out_2_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready),
.auto_out_2_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_valid),
.auto_out_2_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_opcode),
.auto_out_2_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_param),
.auto_out_2_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_size),
.auto_out_2_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_source),
.auto_out_2_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_sink),
.auto_out_2_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_denied),
.auto_out_2_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_data),
.auto_out_2_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_1_d_bits_corrupt),
.auto_out_2_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid),
.auto_out_2_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink),
.auto_out_1_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_ready),
.auto_out_1_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid),
.auto_out_1_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode),
.auto_out_1_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param),
.auto_out_1_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size),
.auto_out_1_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source),
.auto_out_1_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address),
.auto_out_1_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask),
.auto_out_1_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data),
.auto_out_1_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt),
.auto_out_1_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready),
.auto_out_1_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_valid),
.auto_out_1_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_param),
.auto_out_1_b_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_source),
.auto_out_1_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_b_bits_address),
.auto_out_1_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_ready),
.auto_out_1_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid),
.auto_out_1_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode),
.auto_out_1_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param),
.auto_out_1_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size),
.auto_out_1_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source),
.auto_out_1_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address),
.auto_out_1_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data),
.auto_out_1_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt),
.auto_out_1_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready),
.auto_out_1_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_valid),
.auto_out_1_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_opcode),
.auto_out_1_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_param),
.auto_out_1_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_size),
.auto_out_1_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_source),
.auto_out_1_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_sink),
.auto_out_1_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_denied),
.auto_out_1_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_data),
.auto_out_1_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_0_d_bits_corrupt),
.auto_out_1_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid),
.auto_out_1_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink),
.auto_out_0_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready),
.auto_out_0_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid),
.auto_out_0_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode),
.auto_out_0_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param),
.auto_out_0_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size),
.auto_out_0_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source),
.auto_out_0_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address),
.auto_out_0_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask),
.auto_out_0_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data),
.auto_out_0_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt),
.auto_out_0_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready),
.auto_out_0_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid),
.auto_out_0_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode),
.auto_out_0_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param),
.auto_out_0_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size),
.auto_out_0_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source),
.auto_out_0_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink),
.auto_out_0_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied),
.auto_out_0_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data),
.auto_out_0_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt)
); // @[Buses.scala:51:54]
assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_60 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_60
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_60( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_60 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_183 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_183( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PTW_1 :
input clock : Clock
input reset : Reset
output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}}
regreset state : UInt<3>, clock, reset, UInt<3>(0h0)
wire l2_refill_wire : UInt<1>
inst arb of Arbiter2_Valid_PTWReq_1
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], io.requestor[0].req
connect arb.io.in[1], io.requestor[1].req
node _arb_io_out_ready_T = eq(state, UInt<3>(0h0))
node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0))
node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1)
connect arb.io.out.ready, _arb_io_out_ready_T_2
wire _resp_valid_WIRE : UInt<1>[2]
connect _resp_valid_WIRE[0], UInt<1>(0h0)
connect _resp_valid_WIRE[1], UInt<1>(0h0)
reg resp_valid : UInt<1>[2], clock
connect resp_valid, _resp_valid_WIRE
node _clock_en_T = neq(state, UInt<3>(0h0))
node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire)
node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid)
node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid)
node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0)
node clock_en = or(_clock_en_T_3, _clock_en_T_4)
node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en)
connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T
reg invalidated : UInt<1>, clock
reg count : UInt<2>, clock
reg resp_ae_ptw : UInt<1>, clock
reg resp_ae_final : UInt<1>, clock
reg resp_pf : UInt<1>, clock
reg resp_gf : UInt<1>, clock
reg resp_hr : UInt<1>, clock
reg resp_hw : UInt<1>, clock
reg resp_hx : UInt<1>, clock
reg resp_fragmented_superpage : UInt<1>, clock
reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock
reg r_req_dest : UInt, clock
reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg aux_count : UInt<2>, clock
reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg gpa_pgoff : UInt<12>, clock
reg stage2 : UInt<1>, clock
reg stage2_final : UInt<1>, clock
node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1)
node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0))
node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1)
node do_both_stages = and(r_req.vstage1, r_req.stage2)
node _max_count_T = lt(count, aux_count)
node max_count = mux(_max_count_T, aux_count, count)
node _vpn_T = and(r_req.vstage1, stage2)
node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr)
reg mem_resp_valid : UInt<1>, clock
connect mem_resp_valid, io.mem.resp.valid
reg mem_resp_data : UInt, clock
connect mem_resp_data, io.mem.resp.bits.data
wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
wire _tmp_WIRE : UInt<64>
connect _tmp_WIRE, mem_resp_data
node _tmp_T = bits(_tmp_WIRE, 0, 0)
connect tmp.v, _tmp_T
node _tmp_T_1 = bits(_tmp_WIRE, 1, 1)
connect tmp.r, _tmp_T_1
node _tmp_T_2 = bits(_tmp_WIRE, 2, 2)
connect tmp.w, _tmp_T_2
node _tmp_T_3 = bits(_tmp_WIRE, 3, 3)
connect tmp.x, _tmp_T_3
node _tmp_T_4 = bits(_tmp_WIRE, 4, 4)
connect tmp.u, _tmp_T_4
node _tmp_T_5 = bits(_tmp_WIRE, 5, 5)
connect tmp.g, _tmp_T_5
node _tmp_T_6 = bits(_tmp_WIRE, 6, 6)
connect tmp.a, _tmp_T_6
node _tmp_T_7 = bits(_tmp_WIRE, 7, 7)
connect tmp.d, _tmp_T_7
node _tmp_T_8 = bits(_tmp_WIRE, 9, 8)
connect tmp.reserved_for_software, _tmp_T_8
node _tmp_T_9 = bits(_tmp_WIRE, 53, 10)
connect tmp.ppn, _tmp_T_9
node _tmp_T_10 = bits(_tmp_WIRE, 63, 54)
connect tmp.reserved_for_future, _tmp_T_10
wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect pte, tmp
node _res_ppn_T = eq(stage2, UInt<1>(0h0))
node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T)
node _res_ppn_T_2 = bits(tmp.ppn, 26, 0)
node _res_ppn_T_3 = bits(tmp.ppn, 19, 0)
node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3)
connect pte.ppn, _res_ppn_T_4
node _T = or(tmp.r, tmp.w)
node _T_1 = or(_T, tmp.x)
when _T_1 :
node _T_2 = leq(count, UInt<1>(0h0))
node _T_3 = bits(tmp.ppn, 17, 9)
node _T_4 = neq(_T_3, UInt<1>(0h0))
node _T_5 = and(_T_2, _T_4)
when _T_5 :
connect pte.v, UInt<1>(0h0)
node _T_6 = leq(count, UInt<1>(0h1))
node _T_7 = bits(tmp.ppn, 8, 0)
node _T_8 = neq(_T_7, UInt<1>(0h0))
node _T_9 = and(_T_6, _T_8)
when _T_9 :
connect pte.v, UInt<1>(0h0)
node _T_10 = eq(stage2, UInt<1>(0h0))
node _T_11 = and(do_both_stages, _T_10)
node _T_12 = shr(tmp.ppn, 27)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = shr(tmp.ppn, 20)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node invalid_paddr = mux(_T_11, _T_13, _T_15)
node _T_16 = eq(stage2, UInt<1>(0h0))
node _T_17 = and(do_both_stages, _T_16)
node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _count_T_1 = tail(_count_T, 1)
node _count_T_2 = sub(_count_T_1, UInt<1>(0h0))
node count_1 = tail(_count_T_2, 1)
node idxs_0 = shr(tmp.ppn, 29)
wire _WIRE : UInt<15>[1]
connect _WIRE[0], idxs_0
node _T_18 = or(count_1, UInt<0>(0h0))
node _T_19 = neq(_WIRE[0], UInt<1>(0h0))
node invalid_gpa = and(_T_17, _T_19)
node _traverse_T = eq(pte.r, UInt<1>(0h0))
node _traverse_T_1 = and(pte.v, _traverse_T)
node _traverse_T_2 = eq(pte.w, UInt<1>(0h0))
node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2)
node _traverse_T_4 = eq(pte.x, UInt<1>(0h0))
node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4)
node _traverse_T_6 = eq(pte.d, UInt<1>(0h0))
node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6)
node _traverse_T_8 = eq(pte.a, UInt<1>(0h0))
node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8)
node _traverse_T_10 = eq(pte.u, UInt<1>(0h0))
node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10)
node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12)
node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0))
node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14)
node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0))
node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16)
node _traverse_T_18 = lt(count, UInt<2>(0h2))
node traverse = and(_traverse_T_17, _traverse_T_18)
node _pte_addr_vpn_idxs_T = shr(vpn, 18)
node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0)
node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9)
node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0)
node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0)
node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0)
node _pte_addr_mask_T = eq(count, r_hgatp_initial_count)
node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T)
node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff))
node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1))
node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0)
node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2))
node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1)
node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3))
node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3)
node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask)
node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9)
node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx)
node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3)
node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags : UInt<32>[8], clock
reg data : UInt<20>[8], clock
node _can_hit_T = lt(count, UInt<2>(0h2))
node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0))
node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1)
node can_hit = and(_can_hit_T, _can_hit_T_2)
node tag = cat(r_req.vstage1, pte_addr)
node _hits_T = eq(tags[0], tag)
node _hits_T_1 = eq(tags[1], tag)
node _hits_T_2 = eq(tags[2], tag)
node _hits_T_3 = eq(tags[3], tag)
node _hits_T_4 = eq(tags[4], tag)
node _hits_T_5 = eq(tags[5], tag)
node _hits_T_6 = eq(tags[6], tag)
node _hits_T_7 = eq(tags[7], tag)
node hits_lo_lo = cat(_hits_T_1, _hits_T)
node hits_lo_hi = cat(_hits_T_3, _hits_T_2)
node hits_lo = cat(hits_lo_hi, hits_lo_lo)
node hits_hi_lo = cat(_hits_T_5, _hits_T_4)
node hits_hi_hi = cat(_hits_T_7, _hits_T_6)
node hits_hi = cat(hits_hi_hi, hits_hi_lo)
node _hits_T_8 = cat(hits_hi, hits_lo)
node hits = and(_hits_T_8, valid)
node _hit_T = orr(hits)
node pte_cache_hit = and(_hit_T, can_hit)
node _T_20 = and(mem_resp_valid, traverse)
node _T_21 = and(_T_20, can_hit)
node _T_22 = orr(hits)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = and(_T_21, _T_23)
node _T_25 = eq(invalidated, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
when _T_26 :
node _r_T = andr(valid)
node r_left_subtree_older = bits(state_reg, 6, 6)
node r_left_subtree_state = bits(state_reg, 5, 3)
node r_right_subtree_state = bits(state_reg, 2, 0)
node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2)
node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1)
node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0)
node _r_T_1 = bits(r_left_subtree_state_1, 0, 0)
node _r_T_2 = bits(r_right_subtree_state_1, 0, 0)
node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2)
node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3)
node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2)
node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1)
node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0)
node _r_T_5 = bits(r_left_subtree_state_2, 0, 0)
node _r_T_6 = bits(r_right_subtree_state_2, 0, 0)
node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6)
node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7)
node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8)
node _r_T_10 = cat(r_left_subtree_older, _r_T_9)
node _r_T_11 = not(valid)
node _r_T_12 = bits(_r_T_11, 0, 0)
node _r_T_13 = bits(_r_T_11, 1, 1)
node _r_T_14 = bits(_r_T_11, 2, 2)
node _r_T_15 = bits(_r_T_11, 3, 3)
node _r_T_16 = bits(_r_T_11, 4, 4)
node _r_T_17 = bits(_r_T_11, 5, 5)
node _r_T_18 = bits(_r_T_11, 6, 6)
node _r_T_19 = bits(_r_T_11, 7, 7)
node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20)
node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21)
node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22)
node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23)
node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24)
node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25)
node r = mux(_r_T, _r_T_10, _r_T_26)
node _valid_T = dshl(UInt<1>(0h1), r)
node _valid_T_1 = or(valid, _valid_T)
connect valid, _valid_T_1
connect tags[r], tag
connect data[r], pte.ppn
node state_reg_touch_way_sized = bits(r, 2, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg, 5, 3)
node state_reg_right_subtree_state = bits(state_reg, 2, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1)
node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0))
node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1)
node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0)
node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0))
node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3)
node _state_reg_T_5 = bits(_state_reg_T, 0, 0)
node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0)
node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0))
node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1)
node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4)
node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8)
node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9)
node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1)
node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0))
node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1)
node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0)
node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0)
node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0))
node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14)
node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0)
node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0))
node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2)
node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15)
node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19)
node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state)
node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10)
node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21)
connect state_reg, _state_reg_T_22
node _T_27 = eq(state, UInt<3>(0h1))
node _T_28 = and(pte_cache_hit, _T_27)
when _T_28 :
node hi = bits(hits, 7, 4)
node lo = bits(hits, 3, 0)
node _T_29 = orr(hi)
node _T_30 = or(hi, lo)
node hi_1 = bits(_T_30, 3, 2)
node lo_1 = bits(_T_30, 1, 0)
node _T_31 = orr(hi_1)
node _T_32 = or(hi_1, lo_1)
node _T_33 = bits(_T_32, 1, 1)
node _T_34 = cat(_T_31, _T_33)
node _T_35 = cat(_T_29, _T_34)
node state_reg_touch_way_sized_1 = bits(_T_35, 2, 0)
node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2)
node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0))
node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3)
node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0)
node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1)
node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0))
node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0)
node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0)
node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0))
node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26)
node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0)
node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0))
node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4)
node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27)
node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31)
node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32)
node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1)
node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0))
node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0)
node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0)
node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0))
node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37)
node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0)
node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0))
node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5)
node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38)
node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42)
node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3)
node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33)
node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44)
connect state_reg, _state_reg_T_45
node _T_36 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_37 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_38 = or(_T_36, _T_37)
node _T_39 = and(io.dpath.sfence.valid, _T_38)
when _T_39 :
connect valid, UInt<1>(0h0)
node _T_40 = eq(state, UInt<3>(0h1))
node _T_41 = and(pte_cache_hit, _T_40)
node _T_42 = eq(count, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(state, UInt<3>(0h1))
node _T_45 = and(pte_cache_hit, _T_44)
node _T_46 = eq(count, UInt<1>(0h1))
node _T_47 = and(_T_45, _T_46)
node _T_48 = bits(hits, 0, 0)
node _T_49 = bits(hits, 1, 1)
node _T_50 = bits(hits, 2, 2)
node _T_51 = bits(hits, 3, 3)
node _T_52 = bits(hits, 4, 4)
node _T_53 = bits(hits, 5, 5)
node _T_54 = bits(hits, 6, 6)
node _T_55 = bits(hits, 7, 7)
node _T_56 = mux(_T_48, data[0], UInt<1>(0h0))
node _T_57 = mux(_T_49, data[1], UInt<1>(0h0))
node _T_58 = mux(_T_50, data[2], UInt<1>(0h0))
node _T_59 = mux(_T_51, data[3], UInt<1>(0h0))
node _T_60 = mux(_T_52, data[4], UInt<1>(0h0))
node _T_61 = mux(_T_53, data[5], UInt<1>(0h0))
node _T_62 = mux(_T_54, data[6], UInt<1>(0h0))
node _T_63 = mux(_T_55, data[7], UInt<1>(0h0))
node _T_64 = or(_T_56, _T_57)
node _T_65 = or(_T_64, _T_58)
node _T_66 = or(_T_65, _T_59)
node _T_67 = or(_T_66, _T_60)
node _T_68 = or(_T_67, _T_61)
node _T_69 = or(_T_68, _T_62)
node _T_70 = or(_T_69, _T_63)
wire pte_cache_data : UInt<20>
connect pte_cache_data, _T_70
regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags_1 : UInt<32>[8], clock
reg data_1 : UInt<20>[8], clock
node _can_hit_T_3 = eq(count, r_hgatp_initial_count)
node _can_hit_T_4 = lt(aux_count, UInt<2>(0h2))
node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4)
node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1)
node _can_hit_T_7 = and(_can_hit_T_6, stage2)
node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0))
node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8)
node _can_refill_T = eq(stage2, UInt<1>(0h0))
node _can_refill_T_1 = and(do_both_stages, _can_refill_T)
node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0))
node can_refill = and(_can_refill_T_1, _can_refill_T_2)
node _tag_T = cat(UInt<38>(0h0), UInt<1>(0h0))
node tag_1 = cat(UInt<1>(0h1), _tag_T)
node _hits_T_9 = eq(tags_1[0], tag_1)
node _hits_T_10 = eq(tags_1[1], tag_1)
node _hits_T_11 = eq(tags_1[2], tag_1)
node _hits_T_12 = eq(tags_1[3], tag_1)
node _hits_T_13 = eq(tags_1[4], tag_1)
node _hits_T_14 = eq(tags_1[5], tag_1)
node _hits_T_15 = eq(tags_1[6], tag_1)
node _hits_T_16 = eq(tags_1[7], tag_1)
node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9)
node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11)
node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1)
node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13)
node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15)
node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1)
node _hits_T_17 = cat(hits_hi_1, hits_lo_1)
node hits_1 = and(_hits_T_17, valid_1)
node _hit_T_1 = orr(hits_1)
node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1)
node _T_71 = and(mem_resp_valid, traverse)
node _T_72 = and(_T_71, can_refill)
node _T_73 = orr(hits_1)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = and(_T_72, _T_74)
node _T_76 = eq(invalidated, UInt<1>(0h0))
node _T_77 = and(_T_75, _T_76)
when _T_77 :
node _r_T_27 = andr(valid_1)
node r_left_subtree_older_3 = bits(state_reg_1, 6, 6)
node r_left_subtree_state_3 = bits(state_reg_1, 5, 3)
node r_right_subtree_state_3 = bits(state_reg_1, 2, 0)
node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2)
node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1)
node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0)
node _r_T_28 = bits(r_left_subtree_state_4, 0, 0)
node _r_T_29 = bits(r_right_subtree_state_4, 0, 0)
node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29)
node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30)
node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2)
node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1)
node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0)
node _r_T_32 = bits(r_left_subtree_state_5, 0, 0)
node _r_T_33 = bits(r_right_subtree_state_5, 0, 0)
node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33)
node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34)
node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35)
node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36)
node _r_T_38 = not(valid_1)
node _r_T_39 = bits(_r_T_38, 0, 0)
node _r_T_40 = bits(_r_T_38, 1, 1)
node _r_T_41 = bits(_r_T_38, 2, 2)
node _r_T_42 = bits(_r_T_38, 3, 3)
node _r_T_43 = bits(_r_T_38, 4, 4)
node _r_T_44 = bits(_r_T_38, 5, 5)
node _r_T_45 = bits(_r_T_38, 6, 6)
node _r_T_46 = bits(_r_T_38, 7, 7)
node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47)
node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48)
node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49)
node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50)
node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51)
node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52)
node r_1 = mux(_r_T_27, _r_T_37, _r_T_53)
node _valid_T_2 = dshl(UInt<1>(0h1), r_1)
node _valid_T_3 = or(valid_1, _valid_T_2)
connect valid_1, _valid_T_3
connect tags_1[r_1], tag_1
connect data_1[r_1], pte.ppn
node state_reg_touch_way_sized_2 = bits(r_1, 2, 0)
node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2)
node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0))
node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0)
node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1)
node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0))
node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0)
node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0)
node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0))
node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49)
node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0)
node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0))
node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7)
node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50)
node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54)
node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55)
node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1)
node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0))
node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0)
node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0)
node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0))
node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60)
node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0)
node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0))
node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8)
node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61)
node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65)
node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6)
node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56)
node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67)
connect state_reg_1, _state_reg_T_68
node _T_78 = eq(state, UInt<3>(0h1))
node _T_79 = and(stage2_pte_cache_hit, _T_78)
when _T_79 :
node hi_2 = bits(hits_1, 7, 4)
node lo_2 = bits(hits_1, 3, 0)
node _T_80 = orr(hi_2)
node _T_81 = or(hi_2, lo_2)
node hi_3 = bits(_T_81, 3, 2)
node lo_3 = bits(_T_81, 1, 0)
node _T_82 = orr(hi_3)
node _T_83 = or(hi_3, lo_3)
node _T_84 = bits(_T_83, 1, 1)
node _T_85 = cat(_T_82, _T_84)
node _T_86 = cat(_T_80, _T_85)
node state_reg_touch_way_sized_3 = bits(_T_86, 2, 0)
node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2)
node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0))
node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0)
node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1)
node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0))
node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0)
node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0)
node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0))
node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72)
node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0)
node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0))
node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10)
node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73)
node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77)
node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78)
node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1)
node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0))
node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0)
node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0)
node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0))
node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83)
node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0)
node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0))
node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11)
node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84)
node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88)
node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9)
node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79)
node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90)
connect state_reg_1, _state_reg_T_91
node _T_87 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_88 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_89 = or(_T_87, _T_88)
node _T_90 = and(io.dpath.sfence.valid, _T_89)
when _T_90 :
connect valid_1, UInt<1>(0h0)
node _T_91 = eq(state, UInt<3>(0h1))
node _T_92 = and(stage2_pte_cache_hit, _T_91)
node _T_93 = eq(aux_count, UInt<1>(0h0))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(state, UInt<3>(0h1))
node _T_96 = and(stage2_pte_cache_hit, _T_95)
node _T_97 = eq(aux_count, UInt<1>(0h1))
node _T_98 = and(_T_96, _T_97)
node _T_99 = bits(hits_1, 0, 0)
node _T_100 = bits(hits_1, 1, 1)
node _T_101 = bits(hits_1, 2, 2)
node _T_102 = bits(hits_1, 3, 3)
node _T_103 = bits(hits_1, 4, 4)
node _T_104 = bits(hits_1, 5, 5)
node _T_105 = bits(hits_1, 6, 6)
node _T_106 = bits(hits_1, 7, 7)
node _T_107 = mux(_T_99, data_1[0], UInt<1>(0h0))
node _T_108 = mux(_T_100, data_1[1], UInt<1>(0h0))
node _T_109 = mux(_T_101, data_1[2], UInt<1>(0h0))
node _T_110 = mux(_T_102, data_1[3], UInt<1>(0h0))
node _T_111 = mux(_T_103, data_1[4], UInt<1>(0h0))
node _T_112 = mux(_T_104, data_1[5], UInt<1>(0h0))
node _T_113 = mux(_T_105, data_1[6], UInt<1>(0h0))
node _T_114 = mux(_T_106, data_1[7], UInt<1>(0h0))
node _T_115 = or(_T_107, _T_108)
node _T_116 = or(_T_115, _T_109)
node _T_117 = or(_T_116, _T_110)
node _T_118 = or(_T_117, _T_111)
node _T_119 = or(_T_118, _T_112)
node _T_120 = or(_T_119, _T_113)
node _T_121 = or(_T_120, _T_114)
wire stage2_pte_cache_data : UInt<20>
connect stage2_pte_cache_data, _T_121
reg pte_hit : UInt<1>, clock
connect pte_hit, UInt<1>(0h0)
connect io.dpath.perf.pte_miss, UInt<1>(0h0)
node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1))
node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T)
node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0))
node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2)
connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3
node _T_122 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit)
node _T_123 = and(io.dpath.perf.l2hit, _T_122)
node _T_124 = eq(_T_123, UInt<1>(0h0))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf
assert(clock, _T_124, UInt<1>(0h1), "") : assert
reg l2_refill : UInt<1>, clock
connect l2_refill, UInt<1>(0h0)
connect l2_refill_wire, l2_refill
connect io.dpath.perf.l2miss, UInt<1>(0h0)
connect io.dpath.perf.l2hit, UInt<1>(0h0)
wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect _WIRE_1.v, UInt<1>(0h0)
connect _WIRE_1.r, UInt<1>(0h0)
connect _WIRE_1.w, UInt<1>(0h0)
connect _WIRE_1.x, UInt<1>(0h0)
connect _WIRE_1.u, UInt<1>(0h0)
connect _WIRE_1.g, UInt<1>(0h0)
connect _WIRE_1.a, UInt<1>(0h0)
connect _WIRE_1.d, UInt<1>(0h0)
connect _WIRE_1.reserved_for_software, UInt<2>(0h0)
connect _WIRE_1.ppn, UInt<44>(0h0)
connect _WIRE_1.reserved_for_future, UInt<10>(0h0)
wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect l2_pte, _WIRE_1
node _invalidated_T = neq(state, UInt<3>(0h0))
node _invalidated_T_1 = and(invalidated, _invalidated_T)
node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1)
connect invalidated, _invalidated_T_2
connect io.mem.keep_clock_enabled, UInt<1>(0h0)
node _io_mem_req_valid_T = eq(state, UInt<3>(0h1))
node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3))
node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1)
connect io.mem.req.valid, _io_mem_req_valid_T_2
connect io.mem.req.bits.phys, UInt<1>(0h1)
connect io.mem.req.bits.cmd, UInt<1>(0h0)
connect io.mem.req.bits.size, UInt<2>(0h3)
connect io.mem.req.bits.signed, UInt<1>(0h0)
connect io.mem.req.bits.addr, pte_addr
connect io.mem.req.bits.dprv, UInt<1>(0h1)
node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0))
node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T)
connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1
invalidate io.mem.req.bits.tag
connect io.mem.req.bits.no_resp, UInt<1>(0h0)
invalidate io.mem.req.bits.no_alloc
invalidate io.mem.req.bits.no_xcpt
invalidate io.mem.req.bits.data
invalidate io.mem.req.bits.mask
node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2))
node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T)
node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf)
connect io.mem.s1_kill, _io_mem_s1_kill_T_2
invalidate io.mem.s1_data.mask
invalidate io.mem.s1_data.data
connect io.mem.s2_kill, UInt<1>(0h0)
node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8)
node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10)
node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13)
node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15)
node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12)
node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17)
node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21)
node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23)
node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25)
node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28)
node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30)
node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32)
node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38)
node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000)))
node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40)
node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43)
node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45)
node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48)
node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50)
node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000))
node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53)
node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<18>(0h2f000)))
node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55)
node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000))
node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58)
node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60)
node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000))
node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63)
node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65)
node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68)
node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70)
node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73)
node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75)
node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000))
node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78)
node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80)
node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83)
node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85)
node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_88 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42)
node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_47)
node _pmaPgLevelHomogeneous_T_90 = or(_pmaPgLevelHomogeneous_T_89, _pmaPgLevelHomogeneous_T_52)
node _pmaPgLevelHomogeneous_T_91 = or(_pmaPgLevelHomogeneous_T_90, _pmaPgLevelHomogeneous_T_57)
node _pmaPgLevelHomogeneous_T_92 = or(_pmaPgLevelHomogeneous_T_91, _pmaPgLevelHomogeneous_T_62)
node _pmaPgLevelHomogeneous_T_93 = or(_pmaPgLevelHomogeneous_T_92, _pmaPgLevelHomogeneous_T_67)
node _pmaPgLevelHomogeneous_T_94 = or(_pmaPgLevelHomogeneous_T_93, _pmaPgLevelHomogeneous_T_72)
node _pmaPgLevelHomogeneous_T_95 = or(_pmaPgLevelHomogeneous_T_94, _pmaPgLevelHomogeneous_T_77)
node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_82)
node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_87)
node _pmaPgLevelHomogeneous_T_97 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_98 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_99 = cvt(_pmaPgLevelHomogeneous_T_98)
node _pmaPgLevelHomogeneous_T_100 = and(_pmaPgLevelHomogeneous_T_99, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_101 = asSInt(_pmaPgLevelHomogeneous_T_100)
node _pmaPgLevelHomogeneous_T_102 = eq(_pmaPgLevelHomogeneous_T_101, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_103 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_102)
node _pmaPgLevelHomogeneous_T_104 = eq(_pmaPgLevelHomogeneous_T_103, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105)
node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h9e113000)))
node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107)
node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110)
node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h9e113000)))
node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112)
node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_115 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_116 = cvt(_pmaPgLevelHomogeneous_T_115)
node _pmaPgLevelHomogeneous_T_117 = and(_pmaPgLevelHomogeneous_T_116, asSInt(UInt<33>(0h9e110000)))
node _pmaPgLevelHomogeneous_T_118 = asSInt(_pmaPgLevelHomogeneous_T_117)
node _pmaPgLevelHomogeneous_T_119 = eq(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_120 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_121 = cvt(_pmaPgLevelHomogeneous_T_120)
node _pmaPgLevelHomogeneous_T_122 = and(_pmaPgLevelHomogeneous_T_121, asSInt(UInt<33>(0h9e110000)))
node _pmaPgLevelHomogeneous_T_123 = asSInt(_pmaPgLevelHomogeneous_T_122)
node _pmaPgLevelHomogeneous_T_124 = eq(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_125 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_126 = cvt(_pmaPgLevelHomogeneous_T_125)
node _pmaPgLevelHomogeneous_T_127 = and(_pmaPgLevelHomogeneous_T_126, asSInt(UInt<33>(0h90000000)))
node _pmaPgLevelHomogeneous_T_128 = asSInt(_pmaPgLevelHomogeneous_T_127)
node _pmaPgLevelHomogeneous_T_129 = eq(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_130 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109)
node _pmaPgLevelHomogeneous_T_131 = or(_pmaPgLevelHomogeneous_T_130, _pmaPgLevelHomogeneous_T_114)
node _pmaPgLevelHomogeneous_T_132 = or(_pmaPgLevelHomogeneous_T_131, _pmaPgLevelHomogeneous_T_119)
node _pmaPgLevelHomogeneous_T_133 = or(_pmaPgLevelHomogeneous_T_132, _pmaPgLevelHomogeneous_T_124)
node _pmaPgLevelHomogeneous_T_134 = or(_pmaPgLevelHomogeneous_T_133, _pmaPgLevelHomogeneous_T_129)
node _pmaPgLevelHomogeneous_T_135 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_136 = cvt(_pmaPgLevelHomogeneous_T_135)
node _pmaPgLevelHomogeneous_T_137 = and(_pmaPgLevelHomogeneous_T_136, asSInt(UInt<33>(0h8e000000)))
node _pmaPgLevelHomogeneous_T_138 = asSInt(_pmaPgLevelHomogeneous_T_137)
node _pmaPgLevelHomogeneous_T_139 = eq(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_140 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_141 = cvt(_pmaPgLevelHomogeneous_T_140)
node _pmaPgLevelHomogeneous_T_142 = and(_pmaPgLevelHomogeneous_T_141, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_143 = asSInt(_pmaPgLevelHomogeneous_T_142)
node _pmaPgLevelHomogeneous_T_144 = eq(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_145 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_139)
node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_144)
node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147)
node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149)
node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151)
node _pmaPgLevelHomogeneous_T_153 = eq(_pmaPgLevelHomogeneous_T_152, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154)
node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156)
node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158)
node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0))
node _pmaHomogeneous_T = eq(count, UInt<1>(0h1))
node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0))
node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2))
node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1)
node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3))
node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3)
node _pmpHomogeneous_T = shl(r_pte.ppn, 12)
wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0)
connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0)
connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0)
node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T)
node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_4)
node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6)
node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2)
node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3))
node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4)
node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5)
node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 30)
node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0))
node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9)
node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3))
node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11)
node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12)
node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 21)
node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0))
node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16)
node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3))
node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18)
node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19)
node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 12)
node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0))
node _pmpHomogeneous_T_23 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_24 = mux(_pmpHomogeneous_T_23, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8)
node _pmpHomogeneous_T_25 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_26 = mux(_pmpHomogeneous_T_25, _pmpHomogeneous_T_22, _pmpHomogeneous_T_24)
node _pmpHomogeneous_T_27 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_28 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_22, _pmpHomogeneous_T_26)
node _pmpHomogeneous_T_29 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_28)
node _pmpHomogeneous_T_30 = bits(io.dpath.pmp[0].cfg.a, 0, 0)
node _pmpHomogeneous_T_31 = eq(_pmpHomogeneous_T_30, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T)
node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2)
node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3)
node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T)
node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2)
node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3)
node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_1)
node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3)
node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1)
node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3)
node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5)
node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1)
node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3)
node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5)
node _pmpHomogeneous_T_32 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper)
node _pmpHomogeneous_T_33 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper)
node _pmpHomogeneous_T_34 = or(_pmpHomogeneous_T_32, _pmpHomogeneous_T_33)
node _pmpHomogeneous_T_35 = or(_pmpHomogeneous_T_31, _pmpHomogeneous_T_34)
node _pmpHomogeneous_T_36 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_29, _pmpHomogeneous_T_35)
node _pmpHomogeneous_T_37 = and(UInt<1>(0h1), _pmpHomogeneous_T_36)
node _pmpHomogeneous_T_38 = bits(io.dpath.pmp[1].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_8)
node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_12)
node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14)
node _pmpHomogeneous_T_39 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_40 = not(_pmpHomogeneous_T_39)
node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_40, UInt<2>(0h3))
node _pmpHomogeneous_T_42 = not(_pmpHomogeneous_T_41)
node _pmpHomogeneous_T_43 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_42)
node _pmpHomogeneous_T_44 = shr(_pmpHomogeneous_T_43, 30)
node _pmpHomogeneous_T_45 = neq(_pmpHomogeneous_T_44, UInt<1>(0h0))
node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46)
node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3))
node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48)
node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49)
node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 21)
node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0))
node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53)
node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3))
node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55)
node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56)
node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 12)
node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0))
node _pmpHomogeneous_T_60 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_61 = mux(_pmpHomogeneous_T_60, _pmpHomogeneous_T_52, _pmpHomogeneous_T_45)
node _pmpHomogeneous_T_62 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_63 = mux(_pmpHomogeneous_T_62, _pmpHomogeneous_T_59, _pmpHomogeneous_T_61)
node _pmpHomogeneous_T_64 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_65 = mux(_pmpHomogeneous_T_64, _pmpHomogeneous_T_59, _pmpHomogeneous_T_63)
node _pmpHomogeneous_T_66 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_65)
node _pmpHomogeneous_T_67 = bits(io.dpath.pmp[1].cfg.a, 0, 0)
node _pmpHomogeneous_T_68 = eq(_pmpHomogeneous_T_67, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5)
node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7)
node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8)
node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5)
node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7)
node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8)
node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_6)
node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8)
node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7)
node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9)
node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11)
node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7)
node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9)
node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11)
node _pmpHomogeneous_T_69 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1)
node _pmpHomogeneous_T_70 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1)
node _pmpHomogeneous_T_71 = or(_pmpHomogeneous_T_69, _pmpHomogeneous_T_70)
node _pmpHomogeneous_T_72 = or(_pmpHomogeneous_T_68, _pmpHomogeneous_T_71)
node _pmpHomogeneous_T_73 = mux(_pmpHomogeneous_T_38, _pmpHomogeneous_T_66, _pmpHomogeneous_T_72)
node _pmpHomogeneous_T_74 = and(_pmpHomogeneous_T_37, _pmpHomogeneous_T_73)
node _pmpHomogeneous_T_75 = bits(io.dpath.pmp[2].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16)
node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_20)
node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22)
node _pmpHomogeneous_T_76 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_77 = not(_pmpHomogeneous_T_76)
node _pmpHomogeneous_T_78 = or(_pmpHomogeneous_T_77, UInt<2>(0h3))
node _pmpHomogeneous_T_79 = not(_pmpHomogeneous_T_78)
node _pmpHomogeneous_T_80 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_79)
node _pmpHomogeneous_T_81 = shr(_pmpHomogeneous_T_80, 30)
node _pmpHomogeneous_T_82 = neq(_pmpHomogeneous_T_81, UInt<1>(0h0))
node _pmpHomogeneous_T_83 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_84 = not(_pmpHomogeneous_T_83)
node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_84, UInt<2>(0h3))
node _pmpHomogeneous_T_86 = not(_pmpHomogeneous_T_85)
node _pmpHomogeneous_T_87 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_86)
node _pmpHomogeneous_T_88 = shr(_pmpHomogeneous_T_87, 21)
node _pmpHomogeneous_T_89 = neq(_pmpHomogeneous_T_88, UInt<1>(0h0))
node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90)
node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3))
node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92)
node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93)
node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 12)
node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0))
node _pmpHomogeneous_T_97 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_98 = mux(_pmpHomogeneous_T_97, _pmpHomogeneous_T_89, _pmpHomogeneous_T_82)
node _pmpHomogeneous_T_99 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_100 = mux(_pmpHomogeneous_T_99, _pmpHomogeneous_T_96, _pmpHomogeneous_T_98)
node _pmpHomogeneous_T_101 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_102 = mux(_pmpHomogeneous_T_101, _pmpHomogeneous_T_96, _pmpHomogeneous_T_100)
node _pmpHomogeneous_T_103 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_102)
node _pmpHomogeneous_T_104 = bits(io.dpath.pmp[2].cfg.a, 0, 0)
node _pmpHomogeneous_T_105 = eq(_pmpHomogeneous_T_104, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10)
node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12)
node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13)
node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10)
node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12)
node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13)
node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_11)
node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13)
node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13)
node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15)
node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17)
node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13)
node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15)
node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17)
node _pmpHomogeneous_T_106 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2)
node _pmpHomogeneous_T_107 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2)
node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_106, _pmpHomogeneous_T_107)
node _pmpHomogeneous_T_109 = or(_pmpHomogeneous_T_105, _pmpHomogeneous_T_108)
node _pmpHomogeneous_T_110 = mux(_pmpHomogeneous_T_75, _pmpHomogeneous_T_103, _pmpHomogeneous_T_109)
node _pmpHomogeneous_T_111 = and(_pmpHomogeneous_T_74, _pmpHomogeneous_T_110)
node _pmpHomogeneous_T_112 = bits(io.dpath.pmp[3].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_24)
node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_28)
node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30)
node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113)
node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3))
node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115)
node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116)
node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 30)
node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0))
node _pmpHomogeneous_T_120 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_121 = not(_pmpHomogeneous_T_120)
node _pmpHomogeneous_T_122 = or(_pmpHomogeneous_T_121, UInt<2>(0h3))
node _pmpHomogeneous_T_123 = not(_pmpHomogeneous_T_122)
node _pmpHomogeneous_T_124 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_123)
node _pmpHomogeneous_T_125 = shr(_pmpHomogeneous_T_124, 21)
node _pmpHomogeneous_T_126 = neq(_pmpHomogeneous_T_125, UInt<1>(0h0))
node _pmpHomogeneous_T_127 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_128 = not(_pmpHomogeneous_T_127)
node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_128, UInt<2>(0h3))
node _pmpHomogeneous_T_130 = not(_pmpHomogeneous_T_129)
node _pmpHomogeneous_T_131 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_130)
node _pmpHomogeneous_T_132 = shr(_pmpHomogeneous_T_131, 12)
node _pmpHomogeneous_T_133 = neq(_pmpHomogeneous_T_132, UInt<1>(0h0))
node _pmpHomogeneous_T_134 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_135 = mux(_pmpHomogeneous_T_134, _pmpHomogeneous_T_126, _pmpHomogeneous_T_119)
node _pmpHomogeneous_T_136 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_137 = mux(_pmpHomogeneous_T_136, _pmpHomogeneous_T_133, _pmpHomogeneous_T_135)
node _pmpHomogeneous_T_138 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_139 = mux(_pmpHomogeneous_T_138, _pmpHomogeneous_T_133, _pmpHomogeneous_T_137)
node _pmpHomogeneous_T_140 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_139)
node _pmpHomogeneous_T_141 = bits(io.dpath.pmp[3].cfg.a, 0, 0)
node _pmpHomogeneous_T_142 = eq(_pmpHomogeneous_T_141, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15)
node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17)
node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18)
node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15)
node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17)
node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18)
node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_16)
node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18)
node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19)
node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21)
node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23)
node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19)
node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21)
node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23)
node _pmpHomogeneous_T_143 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3)
node _pmpHomogeneous_T_144 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3)
node _pmpHomogeneous_T_145 = or(_pmpHomogeneous_T_143, _pmpHomogeneous_T_144)
node _pmpHomogeneous_T_146 = or(_pmpHomogeneous_T_142, _pmpHomogeneous_T_145)
node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_112, _pmpHomogeneous_T_140, _pmpHomogeneous_T_146)
node _pmpHomogeneous_T_148 = and(_pmpHomogeneous_T_111, _pmpHomogeneous_T_147)
node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[4].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_32)
node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_36)
node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38)
node _pmpHomogeneous_T_150 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150)
node _pmpHomogeneous_T_152 = or(_pmpHomogeneous_T_151, UInt<2>(0h3))
node _pmpHomogeneous_T_153 = not(_pmpHomogeneous_T_152)
node _pmpHomogeneous_T_154 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_153)
node _pmpHomogeneous_T_155 = shr(_pmpHomogeneous_T_154, 30)
node _pmpHomogeneous_T_156 = neq(_pmpHomogeneous_T_155, UInt<1>(0h0))
node _pmpHomogeneous_T_157 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157)
node _pmpHomogeneous_T_159 = or(_pmpHomogeneous_T_158, UInt<2>(0h3))
node _pmpHomogeneous_T_160 = not(_pmpHomogeneous_T_159)
node _pmpHomogeneous_T_161 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_160)
node _pmpHomogeneous_T_162 = shr(_pmpHomogeneous_T_161, 21)
node _pmpHomogeneous_T_163 = neq(_pmpHomogeneous_T_162, UInt<1>(0h0))
node _pmpHomogeneous_T_164 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_165 = not(_pmpHomogeneous_T_164)
node _pmpHomogeneous_T_166 = or(_pmpHomogeneous_T_165, UInt<2>(0h3))
node _pmpHomogeneous_T_167 = not(_pmpHomogeneous_T_166)
node _pmpHomogeneous_T_168 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_167)
node _pmpHomogeneous_T_169 = shr(_pmpHomogeneous_T_168, 12)
node _pmpHomogeneous_T_170 = neq(_pmpHomogeneous_T_169, UInt<1>(0h0))
node _pmpHomogeneous_T_171 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_172 = mux(_pmpHomogeneous_T_171, _pmpHomogeneous_T_163, _pmpHomogeneous_T_156)
node _pmpHomogeneous_T_173 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_174 = mux(_pmpHomogeneous_T_173, _pmpHomogeneous_T_170, _pmpHomogeneous_T_172)
node _pmpHomogeneous_T_175 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_176 = mux(_pmpHomogeneous_T_175, _pmpHomogeneous_T_170, _pmpHomogeneous_T_174)
node _pmpHomogeneous_T_177 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_176)
node _pmpHomogeneous_T_178 = bits(io.dpath.pmp[4].cfg.a, 0, 0)
node _pmpHomogeneous_T_179 = eq(_pmpHomogeneous_T_178, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20)
node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22)
node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23)
node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20)
node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22)
node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23)
node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_21)
node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23)
node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25)
node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27)
node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29)
node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25)
node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27)
node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29)
node _pmpHomogeneous_T_180 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4)
node _pmpHomogeneous_T_181 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4)
node _pmpHomogeneous_T_182 = or(_pmpHomogeneous_T_180, _pmpHomogeneous_T_181)
node _pmpHomogeneous_T_183 = or(_pmpHomogeneous_T_179, _pmpHomogeneous_T_182)
node _pmpHomogeneous_T_184 = mux(_pmpHomogeneous_T_149, _pmpHomogeneous_T_177, _pmpHomogeneous_T_183)
node _pmpHomogeneous_T_185 = and(_pmpHomogeneous_T_148, _pmpHomogeneous_T_184)
node _pmpHomogeneous_T_186 = bits(io.dpath.pmp[5].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_40)
node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_44)
node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46)
node _pmpHomogeneous_T_187 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187)
node _pmpHomogeneous_T_189 = or(_pmpHomogeneous_T_188, UInt<2>(0h3))
node _pmpHomogeneous_T_190 = not(_pmpHomogeneous_T_189)
node _pmpHomogeneous_T_191 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_190)
node _pmpHomogeneous_T_192 = shr(_pmpHomogeneous_T_191, 30)
node _pmpHomogeneous_T_193 = neq(_pmpHomogeneous_T_192, UInt<1>(0h0))
node _pmpHomogeneous_T_194 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194)
node _pmpHomogeneous_T_196 = or(_pmpHomogeneous_T_195, UInt<2>(0h3))
node _pmpHomogeneous_T_197 = not(_pmpHomogeneous_T_196)
node _pmpHomogeneous_T_198 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_197)
node _pmpHomogeneous_T_199 = shr(_pmpHomogeneous_T_198, 21)
node _pmpHomogeneous_T_200 = neq(_pmpHomogeneous_T_199, UInt<1>(0h0))
node _pmpHomogeneous_T_201 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201)
node _pmpHomogeneous_T_203 = or(_pmpHomogeneous_T_202, UInt<2>(0h3))
node _pmpHomogeneous_T_204 = not(_pmpHomogeneous_T_203)
node _pmpHomogeneous_T_205 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_204)
node _pmpHomogeneous_T_206 = shr(_pmpHomogeneous_T_205, 12)
node _pmpHomogeneous_T_207 = neq(_pmpHomogeneous_T_206, UInt<1>(0h0))
node _pmpHomogeneous_T_208 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_200, _pmpHomogeneous_T_193)
node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_207, _pmpHomogeneous_T_209)
node _pmpHomogeneous_T_212 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_213 = mux(_pmpHomogeneous_T_212, _pmpHomogeneous_T_207, _pmpHomogeneous_T_211)
node _pmpHomogeneous_T_214 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_213)
node _pmpHomogeneous_T_215 = bits(io.dpath.pmp[5].cfg.a, 0, 0)
node _pmpHomogeneous_T_216 = eq(_pmpHomogeneous_T_215, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25)
node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27)
node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28)
node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25)
node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27)
node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28)
node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_26)
node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28)
node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31)
node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33)
node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35)
node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31)
node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33)
node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35)
node _pmpHomogeneous_T_217 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5)
node _pmpHomogeneous_T_218 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5)
node _pmpHomogeneous_T_219 = or(_pmpHomogeneous_T_217, _pmpHomogeneous_T_218)
node _pmpHomogeneous_T_220 = or(_pmpHomogeneous_T_216, _pmpHomogeneous_T_219)
node _pmpHomogeneous_T_221 = mux(_pmpHomogeneous_T_186, _pmpHomogeneous_T_214, _pmpHomogeneous_T_220)
node _pmpHomogeneous_T_222 = and(_pmpHomogeneous_T_185, _pmpHomogeneous_T_221)
node _pmpHomogeneous_T_223 = bits(io.dpath.pmp[6].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_48)
node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_52)
node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54)
node _pmpHomogeneous_T_224 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224)
node _pmpHomogeneous_T_226 = or(_pmpHomogeneous_T_225, UInt<2>(0h3))
node _pmpHomogeneous_T_227 = not(_pmpHomogeneous_T_226)
node _pmpHomogeneous_T_228 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_227)
node _pmpHomogeneous_T_229 = shr(_pmpHomogeneous_T_228, 30)
node _pmpHomogeneous_T_230 = neq(_pmpHomogeneous_T_229, UInt<1>(0h0))
node _pmpHomogeneous_T_231 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231)
node _pmpHomogeneous_T_233 = or(_pmpHomogeneous_T_232, UInt<2>(0h3))
node _pmpHomogeneous_T_234 = not(_pmpHomogeneous_T_233)
node _pmpHomogeneous_T_235 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_234)
node _pmpHomogeneous_T_236 = shr(_pmpHomogeneous_T_235, 21)
node _pmpHomogeneous_T_237 = neq(_pmpHomogeneous_T_236, UInt<1>(0h0))
node _pmpHomogeneous_T_238 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238)
node _pmpHomogeneous_T_240 = or(_pmpHomogeneous_T_239, UInt<2>(0h3))
node _pmpHomogeneous_T_241 = not(_pmpHomogeneous_T_240)
node _pmpHomogeneous_T_242 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_241)
node _pmpHomogeneous_T_243 = shr(_pmpHomogeneous_T_242, 12)
node _pmpHomogeneous_T_244 = neq(_pmpHomogeneous_T_243, UInt<1>(0h0))
node _pmpHomogeneous_T_245 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_246 = mux(_pmpHomogeneous_T_245, _pmpHomogeneous_T_237, _pmpHomogeneous_T_230)
node _pmpHomogeneous_T_247 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_248 = mux(_pmpHomogeneous_T_247, _pmpHomogeneous_T_244, _pmpHomogeneous_T_246)
node _pmpHomogeneous_T_249 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_250 = mux(_pmpHomogeneous_T_249, _pmpHomogeneous_T_244, _pmpHomogeneous_T_248)
node _pmpHomogeneous_T_251 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_250)
node _pmpHomogeneous_T_252 = bits(io.dpath.pmp[6].cfg.a, 0, 0)
node _pmpHomogeneous_T_253 = eq(_pmpHomogeneous_T_252, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30)
node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32)
node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33)
node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30)
node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32)
node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33)
node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_31)
node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33)
node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37)
node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39)
node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41)
node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37)
node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39)
node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41)
node _pmpHomogeneous_T_254 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6)
node _pmpHomogeneous_T_255 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6)
node _pmpHomogeneous_T_256 = or(_pmpHomogeneous_T_254, _pmpHomogeneous_T_255)
node _pmpHomogeneous_T_257 = or(_pmpHomogeneous_T_253, _pmpHomogeneous_T_256)
node _pmpHomogeneous_T_258 = mux(_pmpHomogeneous_T_223, _pmpHomogeneous_T_251, _pmpHomogeneous_T_257)
node _pmpHomogeneous_T_259 = and(_pmpHomogeneous_T_222, _pmpHomogeneous_T_258)
node _pmpHomogeneous_T_260 = bits(io.dpath.pmp[7].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_56)
node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_60)
node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62)
node _pmpHomogeneous_T_261 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_262 = not(_pmpHomogeneous_T_261)
node _pmpHomogeneous_T_263 = or(_pmpHomogeneous_T_262, UInt<2>(0h3))
node _pmpHomogeneous_T_264 = not(_pmpHomogeneous_T_263)
node _pmpHomogeneous_T_265 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_264)
node _pmpHomogeneous_T_266 = shr(_pmpHomogeneous_T_265, 30)
node _pmpHomogeneous_T_267 = neq(_pmpHomogeneous_T_266, UInt<1>(0h0))
node _pmpHomogeneous_T_268 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268)
node _pmpHomogeneous_T_270 = or(_pmpHomogeneous_T_269, UInt<2>(0h3))
node _pmpHomogeneous_T_271 = not(_pmpHomogeneous_T_270)
node _pmpHomogeneous_T_272 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_271)
node _pmpHomogeneous_T_273 = shr(_pmpHomogeneous_T_272, 21)
node _pmpHomogeneous_T_274 = neq(_pmpHomogeneous_T_273, UInt<1>(0h0))
node _pmpHomogeneous_T_275 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275)
node _pmpHomogeneous_T_277 = or(_pmpHomogeneous_T_276, UInt<2>(0h3))
node _pmpHomogeneous_T_278 = not(_pmpHomogeneous_T_277)
node _pmpHomogeneous_T_279 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_278)
node _pmpHomogeneous_T_280 = shr(_pmpHomogeneous_T_279, 12)
node _pmpHomogeneous_T_281 = neq(_pmpHomogeneous_T_280, UInt<1>(0h0))
node _pmpHomogeneous_T_282 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_283 = mux(_pmpHomogeneous_T_282, _pmpHomogeneous_T_274, _pmpHomogeneous_T_267)
node _pmpHomogeneous_T_284 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_285 = mux(_pmpHomogeneous_T_284, _pmpHomogeneous_T_281, _pmpHomogeneous_T_283)
node _pmpHomogeneous_T_286 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_287 = mux(_pmpHomogeneous_T_286, _pmpHomogeneous_T_281, _pmpHomogeneous_T_285)
node _pmpHomogeneous_T_288 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_287)
node _pmpHomogeneous_T_289 = bits(io.dpath.pmp[7].cfg.a, 0, 0)
node _pmpHomogeneous_T_290 = eq(_pmpHomogeneous_T_289, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35)
node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37)
node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38)
node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35)
node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37)
node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38)
node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_36)
node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38)
node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43)
node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45)
node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47)
node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43)
node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45)
node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47)
node _pmpHomogeneous_T_291 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7)
node _pmpHomogeneous_T_292 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7)
node _pmpHomogeneous_T_293 = or(_pmpHomogeneous_T_291, _pmpHomogeneous_T_292)
node _pmpHomogeneous_T_294 = or(_pmpHomogeneous_T_290, _pmpHomogeneous_T_293)
node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_260, _pmpHomogeneous_T_288, _pmpHomogeneous_T_294)
node pmpHomogeneous = and(_pmpHomogeneous_T_259, _pmpHomogeneous_T_295)
node homogeneous = and(pmaHomogeneous, pmpHomogeneous)
connect io.requestor[0].resp.valid, resp_valid[0]
connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[0].resp.bits.ae_final, resp_ae_final
connect io.requestor[0].resp.bits.pf, resp_pf
connect io.requestor[0].resp.bits.gf, resp_gf
connect io.requestor[0].resp.bits.hr, resp_hr
connect io.requestor[0].resp.bits.hw, resp_hw
connect io.requestor[0].resp.bits.hx, resp_hx
connect io.requestor[0].resp.bits.pte, r_pte
connect io.requestor[0].resp.bits.level, max_count
node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T
node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T
connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1)
node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2))
node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3)
node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18)
node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6)
node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9)
node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9)
node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0))
node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1))
node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7)
node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12)
node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff)
connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14
node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T
connect io.requestor[0].ptbr, io.dpath.ptbr
connect io.requestor[0].hgatp, io.dpath.hgatp
connect io.requestor[0].vsatp, io.dpath.vsatp
connect io.requestor[0].customCSRs, io.dpath.customCSRs
connect io.requestor[0].status, io.dpath.status
connect io.requestor[0].hstatus, io.dpath.hstatus
connect io.requestor[0].gstatus, io.dpath.gstatus
connect io.requestor[0].pmp, io.dpath.pmp
connect io.requestor[1].resp.valid, resp_valid[1]
connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[1].resp.bits.ae_final, resp_ae_final
connect io.requestor[1].resp.bits.pf, resp_pf
connect io.requestor[1].resp.bits.gf, resp_gf
connect io.requestor[1].resp.bits.hr, resp_hr
connect io.requestor[1].resp.bits.hw, resp_hw
connect io.requestor[1].resp.bits.hx, resp_hx
connect io.requestor[1].resp.bits.pte, r_pte
connect io.requestor[1].resp.bits.level, max_count
node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T
node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T
connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1)
node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2))
node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3)
node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18)
node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6)
node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9)
node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9)
node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0))
node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_11 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1))
node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7)
node _io_requestor_1_resp_bits_gpa_bits_T_13 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_12)
node _io_requestor_1_resp_bits_gpa_bits_T_14 = cat(_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff)
connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14
node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T
connect io.requestor[1].ptbr, io.dpath.ptbr
connect io.requestor[1].hgatp, io.dpath.hgatp
connect io.requestor[1].vsatp, io.dpath.vsatp
connect io.requestor[1].customCSRs, io.dpath.customCSRs
connect io.requestor[1].status, io.dpath.status
connect io.requestor[1].hstatus, io.dpath.hstatus
connect io.requestor[1].gstatus, io.dpath.gstatus
connect io.requestor[1].pmp, io.dpath.pmp
wire next_state : UInt
connect next_state, state
inst state_barrier of OptimizationBarrier_UInt_1
connect state_barrier.clock, clock
connect state_barrier.reset, reset
connect state_barrier.io.x, next_state
connect state, state_barrier.io.y
wire do_switch : UInt<1>
connect do_switch, UInt<1>(0h0)
node _T_128 = eq(UInt<3>(0h0), state)
when _T_128 :
node _T_129 = and(arb.io.out.ready, arb.io.out.valid)
when _T_129 :
node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1)
node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0))
node satp_initial_count = tail(_satp_initial_count_T_2, 1)
node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1)
node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0))
node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1)
node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1)
node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0))
node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1)
node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
connect r_req, arb.io.out.bits.bits
connect r_req_dest, arb.io.chosen
node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0))
connect next_state, _next_state_T
connect stage2, arb.io.out.bits.bits.stage2
node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0))
node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T)
connect stage2_final, _stage2_final_T_1
node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
connect count, _count_T_3
node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0))
connect aux_count, _aux_count_T
connect aux_pte.ppn, aux_ppn
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect resp_ae_ptw, UInt<1>(0h0)
connect resp_ae_final, UInt<1>(0h0)
connect resp_pf, UInt<1>(0h0)
node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1)
node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0))
node resp_gf_count = tail(_resp_gf_count_T_2, 1)
node resp_gf_idxs_0 = shr(aux_ppn, 29)
wire _resp_gf_WIRE : UInt<15>[1]
connect _resp_gf_WIRE[0], resp_gf_idxs_0
node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0))
node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0))
node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2)
connect resp_gf, _resp_gf_T_2
connect resp_hr, UInt<1>(0h1)
connect resp_hw, UInt<1>(0h1)
connect resp_hx, UInt<1>(0h1)
connect resp_fragmented_superpage, UInt<1>(0h0)
connect r_hgatp, io.dpath.hgatp
node _T_130 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0))
node _T_131 = or(_T_130, arb.io.out.bits.bits.stage2)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
else :
node _T_135 = eq(UInt<3>(0h1), state)
when _T_135 :
node _T_136 = eq(count, r_hgatp_initial_count)
node _T_137 = and(stage2, _T_136)
when _T_137 :
node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2))
node _gpa_pgoff_T_1 = shl(r_req.addr, 3)
node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0))
connect gpa_pgoff, _gpa_pgoff_T_2
when stage2_pte_cache_hit :
node _aux_count_T_1 = add(aux_count, UInt<1>(0h1))
node _aux_count_T_2 = tail(_aux_count_T_1, 1)
connect aux_count, _aux_count_T_2
connect aux_pte.ppn, stage2_pte_cache_data
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect pte_hit, UInt<1>(0h1)
else :
when pte_cache_hit :
node _count_T_4 = add(count, UInt<1>(0h1))
node _count_T_5 = tail(_count_T_4, 1)
connect count, _count_T_5
connect pte_hit, UInt<1>(0h1)
else :
node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1))
connect next_state, _next_state_T_1
when resp_gf :
connect next_state, UInt<3>(0h0)
node _T_138 = or(r_req_dest, UInt<1>(0h0))
node _T_139 = bits(_T_138, 0, 0)
connect resp_valid[_T_139], UInt<1>(0h1)
else :
node _T_140 = eq(UInt<3>(0h2), state)
when _T_140 :
node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4))
connect next_state, _next_state_T_2
else :
node _T_141 = eq(UInt<3>(0h4), state)
when _T_141 :
connect next_state, UInt<3>(0h5)
node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2))
connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T
when io.mem.s2_xcpt.ae.ld :
connect resp_ae_ptw, UInt<1>(0h1)
connect next_state, UInt<3>(0h0)
node _T_142 = or(r_req_dest, UInt<1>(0h0))
node _T_143 = bits(_T_142, 0, 0)
connect resp_valid[_T_143], UInt<1>(0h1)
else :
node _T_144 = eq(UInt<3>(0h7), state)
when _T_144 :
connect next_state, UInt<3>(0h0)
node _T_145 = or(r_req_dest, UInt<1>(0h0))
node _T_146 = bits(_T_145, 0, 0)
connect resp_valid[_T_146], UInt<1>(0h1)
node _T_147 = eq(homogeneous, UInt<1>(0h0))
when _T_147 :
connect count, UInt<2>(0h2)
connect resp_fragmented_superpage, UInt<1>(0h1)
when do_both_stages :
connect resp_fragmented_superpage, UInt<1>(0h1)
node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1))
node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000))
node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2)
node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3))
node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4)
node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18)
node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0)
node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1)
node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0)
node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3)
node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1))
node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0)
node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2))
node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1)
node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3))
node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3)
node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask)
wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect merged_pte, aux_pte
connect merged_pte.ppn, _merged_pte_T
node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T)
node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0))
node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2)
node _r_pte_T_4 = eq(state, UInt<3>(0h1))
node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit)
node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_1 = tail(_r_pte_count_T, 1)
node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0))
node r_pte_count = tail(_r_pte_count_T_2, 1)
node r_pte_idxs_0 = shr(stage2_pte_cache_data, 27)
wire r_pte_lsbs : UInt<2>
connect r_pte_lsbs, r_pte_idxs_0
wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte, l2_pte
node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs)
connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1
node _r_pte_T_6 = eq(state, UInt<3>(0h1))
node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit)
wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_1, l2_pte
connect r_pte_pte_1.ppn, pte_cache_data
node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1)
node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0))
node r_pte_count_1 = tail(_r_pte_count_T_5, 1)
node r_pte_idxs_0_1 = shr(pte.ppn, 27)
wire r_pte_lsbs_1 : UInt<2>
connect r_pte_lsbs_1, r_pte_idxs_0_1
wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_2, r_pte
node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1)
connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3
node _r_pte_T_8 = eq(traverse, UInt<1>(0h0))
node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1)
node _r_pte_T_10 = and(_r_pte_T_9, stage2)
node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte)
node _r_pte_T_12 = eq(state, UInt<3>(0h7))
node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0))
node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13)
node _r_pte_T_15 = neq(count, UInt<2>(0h2))
node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15)
node _r_pte_T_17 = shr(r_pte.ppn, 18)
node _r_pte_T_18 = bits(r_req.addr, 17, 0)
node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18)
node _r_pte_T_20 = shr(r_pte.ppn, 9)
node _r_pte_T_21 = bits(r_req.addr, 8, 0)
node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21)
node _r_pte_truncIdx_T = or(count, UInt<1>(0h0))
node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0)
node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1))
node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19)
wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_3, r_pte
connect r_pte_pte_3.ppn, _r_pte_T_24
node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid)
node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1)
node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0))
node r_pte_count_2 = tail(_r_pte_count_T_8, 1)
node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27)
wire r_pte_lsbs_2 : UInt<2>
connect r_pte_lsbs_2, r_pte_idxs_0_2
wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_4, r_pte
node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2)
node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2)
connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5
wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_5, r_pte
connect r_pte_pte_5.ppn, satp.ppn
node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5)
node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte)
node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27)
node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28)
node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29)
node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30)
node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31)
node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32)
inst r_pte_barrier of OptimizationBarrier_PTE_1
connect r_pte_barrier.clock, clock
connect r_pte_barrier.reset, reset
connect r_pte_barrier.io.x.v, _r_pte_T_33.v
connect r_pte_barrier.io.x.r, _r_pte_T_33.r
connect r_pte_barrier.io.x.w, _r_pte_T_33.w
connect r_pte_barrier.io.x.x, _r_pte_T_33.x
connect r_pte_barrier.io.x.u, _r_pte_T_33.u
connect r_pte_barrier.io.x.g, _r_pte_T_33.g
connect r_pte_barrier.io.x.a, _r_pte_T_33.a
connect r_pte_barrier.io.x.d, _r_pte_T_33.d
connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software
connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn
connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future
connect r_pte, r_pte_barrier.io.y
node _T_148 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_149 = and(UInt<1>(0h0), _T_148)
node _T_150 = eq(resp_gf, UInt<1>(0h0))
node _T_151 = and(_T_149, _T_150)
when _T_151 :
node _T_152 = eq(state, UInt<3>(0h1))
node _T_153 = eq(state, UInt<3>(0h2))
node _T_154 = or(_T_152, _T_153)
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_T_154, UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_2
assert(clock, _T_154, UInt<1>(0h1), "") : assert_2
connect next_state, UInt<3>(0h0)
node _T_158 = or(r_req_dest, UInt<1>(0h0))
node _T_159 = bits(_T_158, 0, 0)
connect resp_valid[_T_159], UInt<1>(0h1)
connect count, UInt<2>(0h2)
when mem_resp_valid :
node _T_160 = eq(state, UInt<3>(0h5))
node _T_161 = asUInt(reset)
node _T_162 = eq(_T_161, UInt<1>(0h0))
when _T_162 :
node _T_163 = eq(_T_160, UInt<1>(0h0))
when _T_163 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3
assert(clock, _T_160, UInt<1>(0h1), "") : assert_3
connect next_state, UInt<3>(0h1)
when traverse :
node _T_164 = eq(stage2, UInt<1>(0h0))
node _T_165 = and(do_both_stages, _T_164)
when _T_165 :
connect do_switch, UInt<1>(0h1)
node _count_T_6 = add(count, UInt<1>(0h1))
node _count_T_7 = tail(_count_T_6, 1)
connect count, _count_T_7
else :
node _gf_T = eq(stage2_final, UInt<1>(0h0))
node _gf_T_1 = and(stage2, _gf_T)
node _gf_T_2 = eq(pte.w, UInt<1>(0h0))
node _gf_T_3 = and(pte.x, _gf_T_2)
node _gf_T_4 = or(pte.r, _gf_T_3)
node _gf_T_5 = and(pte.v, _gf_T_4)
node _gf_T_6 = and(_gf_T_5, pte.a)
node _gf_T_7 = and(_gf_T_6, pte.r)
node _gf_T_8 = and(_gf_T_7, pte.u)
node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0))
node _gf_T_10 = and(_gf_T_1, _gf_T_9)
node _gf_T_11 = eq(pte.w, UInt<1>(0h0))
node _gf_T_12 = and(pte.x, _gf_T_11)
node _gf_T_13 = or(pte.r, _gf_T_12)
node _gf_T_14 = and(pte.v, _gf_T_13)
node _gf_T_15 = and(_gf_T_14, pte.a)
node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _gf_T_17 = and(_gf_T_15, _gf_T_16)
node _gf_T_18 = and(_gf_T_17, invalid_gpa)
node gf = or(_gf_T_10, _gf_T_18)
node ae = and(pte.v, invalid_paddr)
node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0))
node pf = and(pte.v, _pf_T)
node _success_T = eq(ae, UInt<1>(0h0))
node _success_T_1 = and(pte.v, _success_T)
node _success_T_2 = eq(pf, UInt<1>(0h0))
node _success_T_3 = and(_success_T_1, _success_T_2)
node _success_T_4 = eq(gf, UInt<1>(0h0))
node success = and(_success_T_3, _success_T_4)
node _T_166 = eq(stage2_final, UInt<1>(0h0))
node _T_167 = and(do_both_stages, _T_166)
node _T_168 = and(_T_167, success)
when _T_168 :
when stage2 :
connect stage2, UInt<1>(0h0)
connect count, aux_count
else :
connect stage2_final, UInt<1>(0h1)
connect do_switch, UInt<1>(0h1)
else :
node _l2_refill_T = eq(count, UInt<2>(0h2))
node _l2_refill_T_1 = and(success, _l2_refill_T)
node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0))
node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2)
node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0))
node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0))
node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5)
node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2))
node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7)
node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9)
node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10)
node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11)
node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a)
node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w)
node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d)
node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u)
node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17)
node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18)
node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19)
node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a)
node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x)
node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u)
node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23)
node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24)
node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25)
node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26)
connect l2_refill, _l2_refill_T_27
connect count, max_count
node _T_169 = eq(count, UInt<2>(0h2))
node _T_170 = eq(do_both_stages, UInt<1>(0h0))
node _T_171 = eq(aux_count, UInt<2>(0h2))
node _T_172 = or(_T_170, _T_171)
node _T_173 = and(_T_169, _T_172)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = and(UInt<1>(0h0), _T_174)
when _T_175 :
connect next_state, UInt<3>(0h7)
else :
connect next_state, UInt<3>(0h0)
node _T_176 = or(r_req_dest, UInt<1>(0h0))
node _T_177 = bits(_T_176, 0, 0)
connect resp_valid[_T_177], UInt<1>(0h1)
node _resp_ae_ptw_T = lt(count, UInt<2>(0h2))
node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T)
node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0))
node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2)
node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4)
node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0))
node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6)
node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0))
node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8)
node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0))
node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10)
node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0))
node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12)
node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14)
node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15)
connect resp_ae_ptw, _resp_ae_ptw_T_16
node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0))
node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T)
node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1)
node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2)
node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a)
node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4)
connect resp_ae_final, _resp_ae_final_T_5
node _resp_pf_T = eq(stage2, UInt<1>(0h0))
node _resp_pf_T_1 = and(pf, _resp_pf_T)
connect resp_pf, _resp_pf_T_1
node _resp_gf_T_3 = and(pf, stage2)
node _resp_gf_T_4 = or(gf, _resp_gf_T_3)
connect resp_gf, _resp_gf_T_4
node _resp_hr_T = eq(stage2, UInt<1>(0h0))
node _resp_hr_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hr_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2)
node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4)
node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5)
node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6)
node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a)
node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r)
node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u)
node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10)
node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11)
connect resp_hr, _resp_hr_T_12
node _resp_hw_T = eq(stage2, UInt<1>(0h0))
node _resp_hw_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hw_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2)
node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4)
node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5)
node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6)
node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a)
node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w)
node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d)
node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u)
node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11)
node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12)
connect resp_hw, _resp_hw_T_13
node _resp_hx_T = eq(stage2, UInt<1>(0h0))
node _resp_hx_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hx_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2)
node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4)
node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5)
node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6)
node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a)
node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x)
node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u)
node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10)
node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11)
connect resp_hx, _resp_hx_T_12
when io.mem.s2_nack :
node _T_178 = eq(state, UInt<3>(0h4))
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_T_178, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4
assert(clock, _T_178, UInt<1>(0h1), "") : assert_4
connect next_state, UInt<3>(0h1)
when do_switch :
node _aux_count_T_3 = add(count, UInt<1>(0h1))
node _aux_count_T_4 = tail(_aux_count_T_3, 1)
node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count)
connect aux_count, _aux_count_T_5
connect count, r_hgatp_initial_count
node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18)
node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0)
node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1)
node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0)
node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3)
node _aux_pte_T = eq(count, UInt<1>(0h1))
node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0)
node _aux_pte_T_2 = eq(count, UInt<2>(0h2))
node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1)
node _aux_pte_T_4 = eq(count, UInt<2>(0h3))
node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3)
wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect aux_pte_pte, pte
connect aux_pte_pte.ppn, _aux_pte_T_5
node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte)
connect aux_pte, _aux_pte_T_6
connect stage2, UInt<1>(0h1)
node _leaf_T = eq(traverse, UInt<1>(0h0))
node _leaf_T_1 = and(mem_resp_valid, _leaf_T)
node _leaf_T_2 = eq(count, UInt<1>(0h0))
node leaf = and(_leaf_T_1, _leaf_T_2)
node _T_182 = and(leaf, pte.v)
node _T_183 = eq(invalid_paddr, UInt<1>(0h0))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(invalid_gpa, UInt<1>(0h0))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = and(leaf, pte.v)
node _T_190 = and(_T_189, invalid_paddr)
node _T_191 = and(leaf, pte.v)
node _T_192 = and(_T_191, invalid_gpa)
node _T_193 = and(leaf, pte.v)
node _T_194 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_195 = and(_T_193, _T_194)
node _T_196 = bits(mem_resp_data, 0, 0)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = and(leaf, _T_197)
node _T_199 = eq(pte.v, UInt<1>(0h0))
node _T_200 = and(leaf, _T_199)
node _T_201 = bits(mem_resp_data, 0, 0)
node _T_202 = and(_T_200, _T_201)
node _leaf_T_3 = eq(traverse, UInt<1>(0h0))
node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3)
node _leaf_T_5 = eq(count, UInt<1>(0h1))
node leaf_1 = and(_leaf_T_4, _leaf_T_5)
node _T_203 = and(leaf_1, pte.v)
node _T_204 = eq(invalid_paddr, UInt<1>(0h0))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(invalid_gpa, UInt<1>(0h0))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_209 = and(_T_207, _T_208)
node _T_210 = and(leaf_1, pte.v)
node _T_211 = and(_T_210, invalid_paddr)
node _T_212 = and(leaf_1, pte.v)
node _T_213 = and(_T_212, invalid_gpa)
node _T_214 = and(leaf_1, pte.v)
node _T_215 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_216 = and(_T_214, _T_215)
node _T_217 = bits(mem_resp_data, 0, 0)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = and(leaf_1, _T_218)
node _T_220 = eq(pte.v, UInt<1>(0h0))
node _T_221 = and(leaf_1, _T_220)
node _T_222 = bits(mem_resp_data, 0, 0)
node _T_223 = and(_T_221, _T_222)
node _leaf_T_6 = eq(traverse, UInt<1>(0h0))
node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6)
node _leaf_T_8 = eq(count, UInt<2>(0h2))
node leaf_2 = and(_leaf_T_7, _leaf_T_8)
node _T_224 = and(leaf_2, pte.v)
node _T_225 = eq(invalid_paddr, UInt<1>(0h0))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(invalid_gpa, UInt<1>(0h0))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_230 = and(_T_228, _T_229)
node _T_231 = and(leaf_2, pte.v)
node _T_232 = and(_T_231, invalid_paddr)
node _T_233 = and(leaf_2, pte.v)
node _T_234 = and(_T_233, invalid_gpa)
node _T_235 = and(leaf_2, pte.v)
node _T_236 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_237 = and(_T_235, _T_236)
node _T_238 = bits(mem_resp_data, 0, 0)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = and(leaf_2, _T_239)
node _T_241 = eq(count, UInt<2>(0h2))
node _T_242 = and(mem_resp_valid, _T_241)
node _T_243 = eq(pte.r, UInt<1>(0h0))
node _T_244 = and(pte.v, _T_243)
node _T_245 = eq(pte.w, UInt<1>(0h0))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(pte.x, UInt<1>(0h0))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(pte.d, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(pte.a, UInt<1>(0h0))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(pte.u, UInt<1>(0h0))
node _T_254 = and(_T_252, _T_253)
node _T_255 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_256 = and(_T_254, _T_255)
node _T_257 = and(_T_242, _T_256)
node _T_258 = eq(state, UInt<3>(0h4))
node _T_259 = and(_T_258, io.mem.s2_xcpt.ae.ld) | module PTW_1( // @[PTW.scala:219:7]
input clock, // @[PTW.scala:219:7]
input reset, // @[PTW.scala:219:7]
output io_requestor_0_req_ready, // @[PTW.scala:220:14]
input io_requestor_0_req_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_0_resp_valid, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_0_status_debug, // @[PTW.scala:220:14]
output io_requestor_0_status_cease, // @[PTW.scala:220:14]
output io_requestor_0_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14]
output io_requestor_0_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14]
output io_requestor_0_status_v, // @[PTW.scala:220:14]
output io_requestor_0_status_sd, // @[PTW.scala:220:14]
output io_requestor_0_status_mpv, // @[PTW.scala:220:14]
output io_requestor_0_status_gva, // @[PTW.scala:220:14]
output io_requestor_0_status_tsr, // @[PTW.scala:220:14]
output io_requestor_0_status_tw, // @[PTW.scala:220:14]
output io_requestor_0_status_tvm, // @[PTW.scala:220:14]
output io_requestor_0_status_mxr, // @[PTW.scala:220:14]
output io_requestor_0_status_sum, // @[PTW.scala:220:14]
output io_requestor_0_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14]
output io_requestor_0_status_spp, // @[PTW.scala:220:14]
output io_requestor_0_status_mpie, // @[PTW.scala:220:14]
output io_requestor_0_status_spie, // @[PTW.scala:220:14]
output io_requestor_0_status_mie, // @[PTW.scala:220:14]
output io_requestor_0_status_sie, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14]
output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
output io_requestor_1_req_ready, // @[PTW.scala:220:14]
input io_requestor_1_req_valid, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_1_resp_valid, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14]
output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_1_status_debug, // @[PTW.scala:220:14]
output io_requestor_1_status_cease, // @[PTW.scala:220:14]
output io_requestor_1_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14]
output io_requestor_1_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14]
output io_requestor_1_status_v, // @[PTW.scala:220:14]
output io_requestor_1_status_sd, // @[PTW.scala:220:14]
output io_requestor_1_status_mpv, // @[PTW.scala:220:14]
output io_requestor_1_status_gva, // @[PTW.scala:220:14]
output io_requestor_1_status_tsr, // @[PTW.scala:220:14]
output io_requestor_1_status_tw, // @[PTW.scala:220:14]
output io_requestor_1_status_tvm, // @[PTW.scala:220:14]
output io_requestor_1_status_mxr, // @[PTW.scala:220:14]
output io_requestor_1_status_sum, // @[PTW.scala:220:14]
output io_requestor_1_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14]
output io_requestor_1_status_spp, // @[PTW.scala:220:14]
output io_requestor_1_status_mpie, // @[PTW.scala:220:14]
output io_requestor_1_status_spie, // @[PTW.scala:220:14]
output io_requestor_1_status_mie, // @[PTW.scala:220:14]
output io_requestor_1_status_sie, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14]
output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
input io_mem_req_ready, // @[PTW.scala:220:14]
output io_mem_req_valid, // @[PTW.scala:220:14]
output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14]
output io_mem_req_bits_dv, // @[PTW.scala:220:14]
output io_mem_s1_kill, // @[PTW.scala:220:14]
input io_mem_s2_nack, // @[PTW.scala:220:14]
input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14]
input io_mem_s2_uncached, // @[PTW.scala:220:14]
input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14]
input io_mem_resp_valid, // @[PTW.scala:220:14]
input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14]
input [6:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14]
input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14]
input io_mem_resp_bits_signed, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14]
input io_mem_resp_bits_dv, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14]
input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14]
input io_mem_resp_bits_replay, // @[PTW.scala:220:14]
input io_mem_resp_bits_has_data, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14]
input io_mem_replay_next, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14]
input [39:0] io_mem_s2_gpa, // @[PTW.scala:220:14]
input io_mem_ordered, // @[PTW.scala:220:14]
input io_mem_store_pending, // @[PTW.scala:220:14]
input io_mem_perf_acquire, // @[PTW.scala:220:14]
input io_mem_perf_release, // @[PTW.scala:220:14]
input io_mem_perf_grant, // @[PTW.scala:220:14]
input io_mem_perf_tlbMiss, // @[PTW.scala:220:14]
input io_mem_perf_blocked, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14]
input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14]
input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14]
input io_dpath_sfence_valid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14]
input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14]
input io_dpath_status_debug, // @[PTW.scala:220:14]
input io_dpath_status_cease, // @[PTW.scala:220:14]
input io_dpath_status_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14]
input io_dpath_status_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14]
input io_dpath_status_v, // @[PTW.scala:220:14]
input io_dpath_status_sd, // @[PTW.scala:220:14]
input io_dpath_status_mpv, // @[PTW.scala:220:14]
input io_dpath_status_gva, // @[PTW.scala:220:14]
input io_dpath_status_tsr, // @[PTW.scala:220:14]
input io_dpath_status_tw, // @[PTW.scala:220:14]
input io_dpath_status_tvm, // @[PTW.scala:220:14]
input io_dpath_status_mxr, // @[PTW.scala:220:14]
input io_dpath_status_sum, // @[PTW.scala:220:14]
input io_dpath_status_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14]
input io_dpath_status_spp, // @[PTW.scala:220:14]
input io_dpath_status_mpie, // @[PTW.scala:220:14]
input io_dpath_status_spie, // @[PTW.scala:220:14]
input io_dpath_status_mie, // @[PTW.scala:220:14]
input io_dpath_status_sie, // @[PTW.scala:220:14]
input io_dpath_hstatus_spvp, // @[PTW.scala:220:14]
input io_dpath_hstatus_spv, // @[PTW.scala:220:14]
input io_dpath_hstatus_gva, // @[PTW.scala:220:14]
input io_dpath_gstatus_debug, // @[PTW.scala:220:14]
input io_dpath_gstatus_cease, // @[PTW.scala:220:14]
input io_dpath_gstatus_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14]
input io_dpath_gstatus_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14]
input io_dpath_gstatus_v, // @[PTW.scala:220:14]
input io_dpath_gstatus_sd, // @[PTW.scala:220:14]
input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpv, // @[PTW.scala:220:14]
input io_dpath_gstatus_gva, // @[PTW.scala:220:14]
input io_dpath_gstatus_mbe, // @[PTW.scala:220:14]
input io_dpath_gstatus_sbe, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14]
input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14]
input io_dpath_gstatus_tsr, // @[PTW.scala:220:14]
input io_dpath_gstatus_tw, // @[PTW.scala:220:14]
input io_dpath_gstatus_tvm, // @[PTW.scala:220:14]
input io_dpath_gstatus_mxr, // @[PTW.scala:220:14]
input io_dpath_gstatus_sum, // @[PTW.scala:220:14]
input io_dpath_gstatus_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14]
input io_dpath_gstatus_spp, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpie, // @[PTW.scala:220:14]
input io_dpath_gstatus_ube, // @[PTW.scala:220:14]
input io_dpath_gstatus_spie, // @[PTW.scala:220:14]
input io_dpath_gstatus_upie, // @[PTW.scala:220:14]
input io_dpath_gstatus_mie, // @[PTW.scala:220:14]
input io_dpath_gstatus_hie, // @[PTW.scala:220:14]
input io_dpath_gstatus_sie, // @[PTW.scala:220:14]
input io_dpath_gstatus_uie, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14]
output io_dpath_perf_pte_miss, // @[PTW.scala:220:14]
output io_dpath_perf_pte_hit, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
output io_dpath_clock_enabled // @[PTW.scala:220:14]
);
wire tmp_r; // @[PTW.scala:304:37]
wire tmp_w; // @[PTW.scala:304:37]
wire tmp_x; // @[PTW.scala:304:37]
wire tmp_u; // @[PTW.scala:304:37]
wire tmp_g; // @[PTW.scala:304:37]
wire tmp_a; // @[PTW.scala:304:37]
wire tmp_d; // @[PTW.scala:304:37]
wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37]
wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37]
wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25]
wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25]
wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_d; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_a; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_g; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_u; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_x; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_w; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_r; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_v; // @[package.scala:267:25]
wire [2:0] _state_barrier_io_y; // @[package.scala:267:25]
wire _arb_io_out_valid; // @[PTW.scala:236:19]
wire _arb_io_out_bits_valid; // @[PTW.scala:236:19]
wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19]
wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19]
wire _arb_io_chosen; // @[PTW.scala:236:19]
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_valid_0 = io_requestor_1_req_bits_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7]
wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7]
wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7]
wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7]
wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7]
wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7]
wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7]
wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7]
wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7]
wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7]
wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7]
wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7]
wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7]
wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7]
wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7]
wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7]
wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7]
wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7]
wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7]
wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7]
wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7]
wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7]
wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7]
wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7]
wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7]
wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7]
wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7]
wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7]
wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7]
wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7]
wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7]
wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7]
wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7]
wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7]
wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7]
wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7]
wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7]
wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7]
wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7]
wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_0 = io_dpath_gstatus_sd; // @[PTW.scala:219:7]
wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7]
wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35]
wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35]
wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27]
wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20]
wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24]
wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17]
wire l2_pte_d = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_a = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_g = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_u = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_x = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_w = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_r = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_v = 1'h0; // @[PTW.scala:403:113]
wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32]
wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40]
wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53]
wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71]
wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16]
wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29]
wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25]
wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58]
wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26]
wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17]
wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18]
wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113]
wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19]
wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27]
wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43]
wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42]
wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58]
wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44]
wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13]
wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62]
wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113]
wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45]
wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61]
wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46]
wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62]
wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46]
wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62]
wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27]
wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27]
wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44]
wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40]
wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27]
wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26]
wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26]
wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27]
wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40]
wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7]
wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7]
wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7]
wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33]
wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16]
wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16]
wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60]
wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22]
wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28]
wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56]
wire _r_pte_T = 1'h1; // @[PTW.scala:670:19]
wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30]
wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58]
wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42]
wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58]
wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13]
wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45]
wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61]
wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46]
wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62]
wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46]
wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62]
wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44]
wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73]
wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58]
wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7]
wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113]
wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26]
wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26]
wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [39:0] tag_1 = 40'h8000000000; // @[PTW.scala:363:18]
wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23]
wire [38:0] _tag_T = 39'h0; // @[package.scala:138:15]
wire [1:0] max_count; // @[PTW.scala:289:25]
wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39]
wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40]
wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51]
wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17]
wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17]
wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57]
wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39]
wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7]
wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7]
wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7]
wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7]
wire io_mem_req_valid_0; // @[PTW.scala:219:7]
wire io_mem_s1_kill_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7]
wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7]
reg [2:0] state; // @[PTW.scala:233:22]
wire l2_refill_wire; // @[PTW.scala:234:28]
wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30]
wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46]
wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}]
reg resp_valid_0; // @[PTW.scala:242:27]
assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27]
reg resp_valid_1; // @[PTW.scala:242:27]
assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27]
wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24]
wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}]
wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}]
wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}]
wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61]
wire clock_en = _clock_en_T_3 | _clock_en_T_4; // @[CustomCSRs.scala:43:61]
assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39]
assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39]
reg invalidated; // @[PTW.scala:251:24]
reg [1:0] count; // @[PTW.scala:259:18]
wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21]
reg resp_ae_ptw; // @[PTW.scala:260:24]
assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
reg resp_ae_final; // @[PTW.scala:261:26]
assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
reg resp_pf; // @[PTW.scala:262:20]
assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
reg resp_gf; // @[PTW.scala:263:20]
assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
reg resp_hr; // @[PTW.scala:264:20]
assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
reg resp_hw; // @[PTW.scala:265:20]
assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
reg resp_hx; // @[PTW.scala:266:20]
assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
reg resp_fragmented_superpage; // @[PTW.scala:267:38]
reg [26:0] r_req_addr; // @[PTW.scala:270:18]
reg r_req_need_gpa; // @[PTW.scala:270:18]
assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
reg r_req_vstage1; // @[PTW.scala:270:18]
reg r_req_stage2; // @[PTW.scala:270:18]
reg r_req_dest; // @[PTW.scala:272:23]
reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
reg [43:0] r_pte_ppn; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
reg r_pte_d; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
reg r_pte_a; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
reg r_pte_g; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
reg r_pte_u; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
reg r_pte_x; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
reg r_pte_w; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
reg r_pte_r; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
reg r_pte_v; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20]
reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20]
reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20]
reg [1:0] aux_count; // @[PTW.scala:278:22]
wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20]
wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26]
reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20]
reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20]
wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26]
reg aux_pte_d; // @[PTW.scala:280:20]
wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26]
reg aux_pte_a; // @[PTW.scala:280:20]
wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26]
reg aux_pte_g; // @[PTW.scala:280:20]
wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26]
reg aux_pte_u; // @[PTW.scala:280:20]
wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26]
reg aux_pte_x; // @[PTW.scala:280:20]
wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26]
reg aux_pte_w; // @[PTW.scala:280:20]
wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26]
reg aux_pte_r; // @[PTW.scala:280:20]
wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26]
reg aux_pte_v; // @[PTW.scala:280:20]
wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26]
reg [11:0] gpa_pgoff; // @[PTW.scala:281:22]
reg stage2; // @[PTW.scala:282:19]
reg stage2_final; // @[PTW.scala:283:25]
wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26]
wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38]
wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25]
assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25]
assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31]
wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}]
wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12]
reg mem_resp_valid; // @[PTW.scala:292:31]
reg [63:0] mem_resp_data; // @[PTW.scala:293:30]
wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37]
wire [9:0] _tmp_T_10; // @[PTW.scala:304:37]
wire [43:0] _tmp_T_9; // @[PTW.scala:304:37]
wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26]
wire [1:0] _tmp_T_8; // @[PTW.scala:304:37]
wire _tmp_T_7; // @[PTW.scala:304:37]
wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_6; // @[PTW.scala:304:37]
wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_5; // @[PTW.scala:304:37]
wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_4; // @[PTW.scala:304:37]
wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_3; // @[PTW.scala:304:37]
wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_2; // @[PTW.scala:304:37]
wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_1; // @[PTW.scala:304:37]
wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26]
wire _tmp_T; // @[PTW.scala:304:37]
wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26]
wire [43:0] tmp_ppn; // @[PTW.scala:304:37]
wire tmp_v; // @[PTW.scala:304:37]
assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37]
assign tmp_v = _tmp_T; // @[PTW.scala:304:37]
assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37]
assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37]
assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37]
assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37]
assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37]
assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37]
assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37]
assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37]
assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37]
assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37]
assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37]
assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37]
assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37]
assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37]
assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37]
assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37]
assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37]
assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37]
assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37]
assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37]
wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26]
wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26]
wire [43:0] pte_ppn; // @[PTW.scala:305:26]
wire pte_v; // @[PTW.scala:305:26]
wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26]
wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38]
wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}]
wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54]
wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99]
wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}]
assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}]
assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}]
wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}]
wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58]
wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25]
wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26]
wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}]
wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}]
wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}]
wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}]
wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}]
wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}]
wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33]
wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}]
wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51]
wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}]
wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73]
wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}]
wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}]
wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}]
wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}]
wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40]
wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}]
wire _T_46 = count == 2'h1; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T = _T_46; // @[package.scala:39:86]
wire _pmaHomogeneous_T; // @[package.scala:39:86]
assign _pmaHomogeneous_T = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_23; // @[package.scala:39:86]
assign _pmpHomogeneous_T_23 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_60; // @[package.scala:39:86]
assign _pmpHomogeneous_T_60 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_5 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_97; // @[package.scala:39:86]
assign _pmpHomogeneous_T_97 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_10 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_134; // @[package.scala:39:86]
assign _pmpHomogeneous_T_134 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_15 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_171; // @[package.scala:39:86]
assign _pmpHomogeneous_T_171 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_20 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_208; // @[package.scala:39:86]
assign _pmpHomogeneous_T_208 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_25 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_245; // @[package.scala:39:86]
assign _pmpHomogeneous_T_245 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_30 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_282; // @[package.scala:39:86]
assign _pmpHomogeneous_T_282 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_35 = _T_46; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T = _T_46; // @[package.scala:39:86]
wire _aux_pte_T; // @[package.scala:39:86]
assign _aux_pte_T = _T_46; // @[package.scala:39:86]
wire _leaf_T_5; // @[PTW.scala:751:53]
assign _leaf_T_5 = _T_46; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}]
wire _T_241 = count == 2'h2; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T_2 = _T_241; // @[package.scala:39:86]
wire _pmaHomogeneous_T_2; // @[package.scala:39:86]
assign _pmaHomogeneous_T_2 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_25; // @[package.scala:39:86]
assign _pmpHomogeneous_T_25 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_2 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_62; // @[package.scala:39:86]
assign _pmpHomogeneous_T_62 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_7 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_99; // @[package.scala:39:86]
assign _pmpHomogeneous_T_99 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_12 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_136; // @[package.scala:39:86]
assign _pmpHomogeneous_T_136 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_17 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_173; // @[package.scala:39:86]
assign _pmpHomogeneous_T_173 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_22 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_210; // @[package.scala:39:86]
assign _pmpHomogeneous_T_210 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_27 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_247; // @[package.scala:39:86]
assign _pmpHomogeneous_T_247 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_32 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_284; // @[package.scala:39:86]
assign _pmpHomogeneous_T_284 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_37 = _T_241; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T_2 = _T_241; // @[package.scala:39:86]
wire _l2_refill_T; // @[PTW.scala:713:39]
assign _l2_refill_T = _T_241; // @[package.scala:39:86]
wire _aux_pte_T_2; // @[package.scala:39:86]
assign _aux_pte_T_2 = _T_241; // @[package.scala:39:86]
wire _leaf_T_8; // @[PTW.scala:751:53]
assign _leaf_T_8 = _T_241; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}]
wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}]
wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76]
wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36]
wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}]
wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}]
wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23]
reg [6:0] state_reg; // @[Replacement.scala:168:70]
reg [7:0] valid; // @[PTW.scala:352:24]
reg [31:0] tags_0; // @[PTW.scala:353:19]
reg [31:0] tags_1; // @[PTW.scala:353:19]
reg [31:0] tags_2; // @[PTW.scala:353:19]
reg [31:0] tags_3; // @[PTW.scala:353:19]
reg [31:0] tags_4; // @[PTW.scala:353:19]
reg [31:0] tags_5; // @[PTW.scala:353:19]
reg [31:0] tags_6; // @[PTW.scala:353:19]
reg [31:0] tags_7; // @[PTW.scala:353:19]
reg [19:0] data_0; // @[PTW.scala:355:19]
reg [19:0] data_1; // @[PTW.scala:355:19]
reg [19:0] data_2; // @[PTW.scala:355:19]
reg [19:0] data_3; // @[PTW.scala:355:19]
reg [19:0] data_4; // @[PTW.scala:355:19]
reg [19:0] data_5; // @[PTW.scala:355:19]
reg [19:0] data_6; // @[PTW.scala:355:19]
reg [19:0] data_7; // @[PTW.scala:355:19]
wire _can_hit_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :358:18]
wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65]
wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}]
wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}]
wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15]
wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27]
wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27]
wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27]
wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27]
wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27]
wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27]
wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27]
wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20]
wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}]
wire _r_T = &valid; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13]
wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13]
wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13]
wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57]
wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45]
wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45]
wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45]
wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45]
wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45]
wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45]
wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45]
wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45]
wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13]
wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13]
wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13]
wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13]
wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13]
wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16]
wire _T_152 = state == 3'h1; // @[PTW.scala:233:22, :377:24]
wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46]
assign _io_dpath_perf_pte_hit_T = _T_152; // @[PTW.scala:377:24, :394:46]
wire _io_mem_req_valid_T; // @[PTW.scala:515:29]
assign _io_mem_req_valid_T = _T_152; // @[PTW.scala:377:24, :515:29]
wire _r_pte_T_4; // @[PTW.scala:672:15]
assign _r_pte_T_4 = _T_152; // @[PTW.scala:377:24, :672:15]
wire _r_pte_T_6; // @[PTW.scala:674:15]
assign _r_pte_T_6 = _T_152; // @[PTW.scala:377:24, :674:15]
wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18]
wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18]
wire [3:0] _T_30 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_1 = _T_30[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_1 = _T_30[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13]
wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13]
wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13]
wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13]
wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16]
wire _leaf_T_2 = ~(|count); // @[PTW.scala:259:18, :324:40, :382:47, :751:53]
wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36]
reg [6:0] state_reg_1; // @[Replacement.scala:168:70]
reg [7:0] valid_1; // @[PTW.scala:352:24]
reg [19:0] data_1_0; // @[PTW.scala:355:19]
reg [19:0] data_1_1; // @[PTW.scala:355:19]
reg [19:0] data_1_2; // @[PTW.scala:355:19]
reg [19:0] data_1_3; // @[PTW.scala:355:19]
reg [19:0] data_1_4; // @[PTW.scala:355:19]
reg [19:0] data_1_5; // @[PTW.scala:355:19]
reg [19:0] data_1_6; // @[PTW.scala:355:19]
reg [19:0] data_1_7; // @[PTW.scala:355:19]
wire _can_hit_T_3 = ~(|count); // @[PTW.scala:259:18, :324:40, :357:21]
wire _can_hit_T_4 = ~(aux_count[1]); // @[PTW.scala:278:22, :357:60]
wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}]
wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}]
wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}]
wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107]
wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}]
wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33]
wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}]
wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44]
wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}]
wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13]
wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13]
wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12]
wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13]
wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38]
wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12]
wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57]
wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45]
wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45]
wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45]
wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45]
wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45]
wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45]
wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45]
wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45]
wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45]
wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45]
wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45]
wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45]
wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45]
wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13]
wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13]
wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13]
wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13]
wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13]
wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13]
wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13]
wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13]
wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13]
wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12]
wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13]
wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38]
wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12]
wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16]
wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16]
wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16]
reg pte_hit; // @[PTW.scala:392:24]
wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}]
assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}]
assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57]
reg l2_refill; // @[PTW.scala:398:26]
assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26]
wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65]
wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}]
wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}]
wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48]
assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}]
assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39]
assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24]
wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43]
assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}]
assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40]
wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38]
wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}]
assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}]
assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51]
wire [55:0] _GEN = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96]
wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_7 = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_37 = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80]
assign _pmpHomogeneous_T = _GEN; // @[PTW.scala:544:96, :548:80]
wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65]
wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}]
wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65]
wire [55:0] _GEN_0 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_43 = _GEN_0; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_110 = _GEN_0; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_48 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_98 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_115 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_147 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_154 = _GEN_1; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_68 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_120 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_135 = _GEN_2; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_83 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_125 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_140 = _GEN_3; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65]
wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 | _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 | _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 | _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 | _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}]
wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86]
wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_4 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_2 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_9 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_16 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_28; // @[package.scala:39:76]
wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}]
wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21]
wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_5 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T = _GEN_5; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_5; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62]
wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 | _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 | _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_6 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_39 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_46 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_53 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_45 = |_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_65; // @[package.scala:39:76]
wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_7; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_7; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 | _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 | _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_8 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_76 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_83 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_90 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_82 = |_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_89 = |_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_102; // @[package.scala:39:76]
wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_9; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_9; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 | _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 | _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_10 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_113 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_120 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_127 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_126 = |_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_133 = |_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_139; // @[package.scala:39:76]
wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_11; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_11; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 | _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 | _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_12 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_150 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_157 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_164 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_156 = |_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_163 = |_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_170 = |_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_176; // @[package.scala:39:76]
wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_13; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_13; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 | _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 | _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_14 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_187 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_194 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_201 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_193 = |_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_200 = |_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_207 = |_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_213; // @[package.scala:39:76]
wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_15; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_15; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 | _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 | _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_16 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_224 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_231 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_238 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_230 = |_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_237 = |_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_244 = |_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_250; // @[package.scala:39:76]
wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_17; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_17; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 | _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 | _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_18 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_261 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_268 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_275 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_267 = |_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_274 = |_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_281 = |_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_287; // @[package.scala:39:76]
wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_19; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_19; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 | _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 | _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10]
wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76]
assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _T_171 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60]
wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60]
wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60]
wire _gpa_pgoff_T; // @[PTW.scala:615:36]
assign _gpa_pgoff_T = _T_171; // @[PTW.scala:566:60, :615:36]
wire _l2_refill_T_7; // @[PTW.scala:715:40]
assign _l2_refill_T_7 = _T_171; // @[PTW.scala:566:60, :715:40]
wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
wire [2:0] next_state; // @[PTW.scala:579:31]
wire do_switch; // @[PTW.scala:581:30]
wire _T_129 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire _GEN_20 = ~(|state) & _T_129; // @[Decoupled.scala:51:35]
wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38]
wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26]
wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58]
wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40]
wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40]
wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67]
wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}]
wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32]
wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32]
wire [2:0] _GEN_21 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24]
wire [2:0] _count_T_4; // @[PTW.scala:624:24]
assign _count_T_4 = _GEN_21; // @[PTW.scala:624:24]
wire [2:0] _count_T_6; // @[PTW.scala:696:22]
assign _count_T_6 = _GEN_21; // @[PTW.scala:624:24, :696:22]
wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38]
assign _aux_count_T_3 = _GEN_21; // @[PTW.scala:624:24, :741:38]
wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24]
wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26]
wire _T_140 = state == 3'h2; // @[PTW.scala:233:22, :583:18]
wire _T_141 = state == 3'h4; // @[PTW.scala:233:22, :583:18]
wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39]
wire _GEN_22 = _T_152 | _T_140; // @[PTW.scala:377:24, :393:26, :583:18]
assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_22) & _T_141 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}]
wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45]
wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86]
wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}]
wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64]
wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}]
wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64]
wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}]
wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}]
wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86]
wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76]
wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26]
wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32]
wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26]
wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30]
wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30]
assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}]
assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}]
wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26]
assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73]
wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58]
wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27]
assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27]
wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26]
assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}]
assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29]
wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}]
wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}]
wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15]
wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43]
wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}]
wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65]
wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}]
wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}]
wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}]
wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76]
wire _r_pte_T_25 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26]
wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26]
wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26]
wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35]
wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35]
wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8]
wire [43:0] _r_pte_T_31_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_30_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26]
wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_d = ~_r_pte_T_7 & _r_pte_T_30_d; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_a = ~_r_pte_T_7 & _r_pte_T_30_a; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_g = ~_r_pte_T_7 & _r_pte_T_30_g; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_u = ~_r_pte_T_7 & _r_pte_T_30_u; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_x = ~_r_pte_T_7 & _r_pte_T_30_x; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_w = ~_r_pte_T_7 & _r_pte_T_30_w; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_r = ~_r_pte_T_7 & _r_pte_T_30_r; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_v = ~_r_pte_T_7 & _r_pte_T_30_v; // @[PTW.scala:674:{8,25}, :676:8]
wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8]
wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8]
wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8]
wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:8, :672:8]
wire [43:0] _r_pte_T_33_ppn = _r_pte_T_32_ppn; // @[PTW.scala:670:8, :672:8]
wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_d = _r_pte_T_32_d; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_a = _r_pte_T_32_a; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_g = _r_pte_T_32_g; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_u = _r_pte_T_32_u; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_x = _r_pte_T_32_x; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_w = _r_pte_T_32_w; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_r = _r_pte_T_32_r; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_v = _r_pte_T_32_v; // @[PTW.scala:670:8, :672:8]
wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22]
wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27]
wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}]
wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44]
wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}]
wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97]
wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}]
wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}]
wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}]
wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22]
wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49]
wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}]
wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30]
wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}]
wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37]
wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}]
wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44]
wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}]
wire _T_168 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}]
assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_168 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21]
wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}]
wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61]
wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}]
wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12]
wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30]
wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}]
wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}]
wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41]
wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}]
wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59]
wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44]
wire _GEN_23 = traverse | _T_168; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19]
wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36]
wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}]
wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26]
wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}]
wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}]
wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}]
wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}]
wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}]
wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}]
wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}]
wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29]
wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26]
wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}]
wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30]
wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}]
wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20]
wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32]
wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39]
wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}]
wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}]
wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}]
wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20]
wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32]
wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39]
wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}]
wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}]
wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}]
wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20]
wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32]
wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39]
wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}]
wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}]
wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}] |
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_4 :
input clock : Clock
input reset : Reset
output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}}
node _legal_address_T = xor(io.paddr, UInt<1>(0h0))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000))
node _legal_address_T_26 = cvt(_legal_address_T_25)
node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000)))
node _legal_address_T_28 = asSInt(_legal_address_T_27)
node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0)))
node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000))
node _legal_address_T_31 = cvt(_legal_address_T_30)
node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000)))
node _legal_address_T_33 = asSInt(_legal_address_T_32)
node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0)))
node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000))
node _legal_address_T_36 = cvt(_legal_address_T_35)
node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000)))
node _legal_address_T_38 = asSInt(_legal_address_T_37)
node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0)))
node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000))
node _legal_address_T_41 = cvt(_legal_address_T_40)
node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000)))
node _legal_address_T_43 = asSInt(_legal_address_T_42)
node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0)))
node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000))
node _legal_address_T_46 = cvt(_legal_address_T_45)
node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000)))
node _legal_address_T_48 = asSInt(_legal_address_T_47)
node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0)))
node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000))
node _legal_address_T_51 = cvt(_legal_address_T_50)
node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000)))
node _legal_address_T_53 = asSInt(_legal_address_T_52)
node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0)))
node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000))
node _legal_address_T_56 = cvt(_legal_address_T_55)
node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_58 = asSInt(_legal_address_T_57)
node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[12]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
connect _legal_address_WIRE[5], _legal_address_T_29
connect _legal_address_WIRE[6], _legal_address_T_34
connect _legal_address_WIRE[7], _legal_address_T_39
connect _legal_address_WIRE[8], _legal_address_T_44
connect _legal_address_WIRE[9], _legal_address_T_49
connect _legal_address_WIRE[10], _legal_address_T_54
connect _legal_address_WIRE[11], _legal_address_T_59
node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2])
node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3])
node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4])
node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5])
node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6])
node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7])
node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8])
node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9])
node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10])
node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11])
node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T)
node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2)
node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5)
node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7)
node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10)
node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12)
node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9)
node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14)
node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17)
node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000)))
node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19)
node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22)
node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000)))
node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24)
node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26)
node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29)
wire _io_resp_cacheable_WIRE : UInt<1>
connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30
node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE)
connect io.resp.cacheable, _io_resp_cacheable_T_31
node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_r_T_1 = cvt(_io_resp_r_T)
node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2)
node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1))
connect io.resp.r, _io_resp_r_T_5
node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_w_T_1 = cvt(_io_resp_w_T)
node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2)
node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_w_T_6 = cvt(_io_resp_w_T_5)
node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7)
node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_w_T_11 = cvt(_io_resp_w_T_10)
node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12)
node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_16 = cvt(_io_resp_w_T_15)
node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17)
node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_21 = cvt(_io_resp_w_T_20)
node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22)
node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_w_T_26 = cvt(_io_resp_w_T_25)
node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27)
node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_w_T_31 = cvt(_io_resp_w_T_30)
node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32)
node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9)
node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14)
node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19)
node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24)
node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29)
node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34)
node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_w_T_42 = cvt(_io_resp_w_T_41)
node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43)
node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47)
wire _io_resp_w_WIRE : UInt<1>
connect _io_resp_w_WIRE, _io_resp_w_T_48
node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE)
connect io.resp.w, _io_resp_w_T_49
node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_pp_T_1 = cvt(_io_resp_pp_T)
node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2)
node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5)
node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7)
node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10)
node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12)
node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15)
node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17)
node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20)
node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22)
node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25)
node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27)
node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30)
node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32)
node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9)
node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14)
node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19)
node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24)
node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29)
node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34)
node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41)
node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43)
node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47)
wire _io_resp_pp_WIRE : UInt<1>
connect _io_resp_pp_WIRE, _io_resp_pp_T_48
node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE)
connect io.resp.pp, _io_resp_pp_T_49
node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_al_T_1 = cvt(_io_resp_al_T)
node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2)
node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_al_T_6 = cvt(_io_resp_al_T_5)
node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7)
node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_al_T_11 = cvt(_io_resp_al_T_10)
node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12)
node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_16 = cvt(_io_resp_al_T_15)
node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17)
node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_21 = cvt(_io_resp_al_T_20)
node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22)
node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_al_T_26 = cvt(_io_resp_al_T_25)
node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27)
node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_al_T_31 = cvt(_io_resp_al_T_30)
node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32)
node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9)
node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14)
node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19)
node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24)
node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29)
node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34)
node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_al_T_42 = cvt(_io_resp_al_T_41)
node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43)
node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47)
wire _io_resp_al_WIRE : UInt<1>
connect _io_resp_al_WIRE, _io_resp_al_T_48
node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE)
connect io.resp.al, _io_resp_al_T_49
node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_aa_T_1 = cvt(_io_resp_aa_T)
node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2)
node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5)
node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7)
node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10)
node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12)
node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15)
node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17)
node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20)
node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22)
node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25)
node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27)
node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30)
node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32)
node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9)
node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14)
node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19)
node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24)
node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29)
node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34)
node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41)
node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43)
node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47)
wire _io_resp_aa_WIRE : UInt<1>
connect _io_resp_aa_WIRE, _io_resp_aa_T_48
node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE)
connect io.resp.aa, _io_resp_aa_T_49
node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_x_T_1 = cvt(_io_resp_x_T)
node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2)
node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_x_T_6 = cvt(_io_resp_x_T_5)
node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7)
node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_x_T_11 = cvt(_io_resp_x_T_10)
node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12)
node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_x_T_16 = cvt(_io_resp_x_T_15)
node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17)
node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_x_T_21 = cvt(_io_resp_x_T_20)
node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000)))
node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22)
node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9)
node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14)
node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19)
node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24)
node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000))
node _io_resp_x_T_30 = cvt(_io_resp_x_T_29)
node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31)
node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_x_T_35 = cvt(_io_resp_x_T_34)
node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000)))
node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36)
node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_x_T_40 = cvt(_io_resp_x_T_39)
node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41)
node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_x_T_45 = cvt(_io_resp_x_T_44)
node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46)
node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_x_T_50 = cvt(_io_resp_x_T_49)
node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000)))
node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51)
node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_x_T_55 = cvt(_io_resp_x_T_54)
node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56)
node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38)
node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43)
node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48)
node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53)
node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58)
node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65)
wire _io_resp_x_WIRE : UInt<1>
connect _io_resp_x_WIRE, _io_resp_x_T_66
node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE)
connect io.resp.x, _io_resp_x_T_67
node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_eff_T_1 = cvt(_io_resp_eff_T)
node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000)))
node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2)
node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5)
node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000)))
node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7)
node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10)
node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12)
node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15)
node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17)
node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20)
node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000)))
node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22)
node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25)
node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27)
node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9)
node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14)
node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19)
node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24)
node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29)
node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35)
node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37)
node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40)
node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42)
node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45)
node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47)
node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50)
node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000)))
node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52)
node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44)
node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49)
node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54)
node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59)
wire _io_resp_eff_WIRE : UInt<1>
connect _io_resp_eff_WIRE, _io_resp_eff_T_60
node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE)
connect io.resp.eff, _io_resp_eff_T_61 | module PMAChecker_4( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_49; // @[PMA.scala:39:19]
wire _io_resp_pp_T_49; // @[PMA.scala:39:19]
wire _io_resp_al_T_49; // @[PMA.scala:39:19]
wire _io_resp_aa_T_49; // @[PMA.scala:39:19]
wire _io_resp_x_T_67; // @[PMA.scala:39:19]
wire _io_resp_eff_T_61; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31]
assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31]
assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46]
wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73]
assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73]
assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46]
wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73]
assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73]
assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73]
assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73]
assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer :
input clock : Clock
input reset : Reset
output auto : { }
skip | module TLBuffer( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset // @[Buffer.scala:40:9]
);
endmodule |
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