Patent Number: 
Section: description

Referring to FIG. 1 is a schematic sectional view of one embodiment of an electron beam irradiating apparatus according to the present invention. The apparatus of the invention includes a chamber Cbin which a predetermined process takes place. The chamber CB has an opening at its top surface. A cathode plate CP, which in one embodiment is electrically insulated from the chamber CB, is installed over the opening. An insulating ring I is interposed between the cathode plate CP and the top of the chamber CB. The cathode plate CP may be a single cathode plate formed of a non-metal conductive material such as silicon, or a dual cathode plate having an upper cathode plate CP1 formed of a metal such as aluminum (Al) or an Al alloy, and a lower cathode plate CP2 formed of a non-metal conductive material such as silicon. The chamber CB is grounded. A grid plate GP is disposed beneath the cathode plate CP, and a gas injection ring GR is disposed below the grid plate GP. The gas injection ring GR has a doughnut shape as shown in FIG. 2. As shown in FIG. 2, the gas injection ring GR has a plurality of holes H along the inner circumference thereof, which allow a process gas, for example, an inert gas, to spray downwards and toward the center of the gas injection ring GR. In one embodiment, the grid plate GP is installed such that it is electrically insulated from the cathode plate CP and the chamber CB. The cathode plate CP is connected to a high voltage power source HVP while the grid plate GP is connected to a low voltage power source LVP. In particular, the positive terminal of the high voltage power source HVP is grounded and the negative terminal thereof is connected to the cathode plate CP. Thus, a high negative voltage, for example, a voltage of xe2x88x92500 to xe2x88x9230,000 volts, is applied to the cathode plate CP. Similarly, the positive terminal of the low voltage power source LVP is grounded while the negative terminal thereof is connected to the grid plate GP. Accordingly, a negative low voltage, for example, a voltage of 0 to xe2x88x92500 volts, is applied to the grid plate GP. A susceptor S is disposed on the bottom of the chamber CB, and a predetermined region of the bottom of the chamber CB is openeded to be connected to a vacuum pump P through a valve V interposed between the chamber CB and the vacuum pump P. The vacuum pump P maintains the pressure of the chamber CB at a lower pressure than the atmospheric pressure. In operation of the electron beam irradiating apparatus having the above structure, a wafer, on which a material layer such as a photoresist layer or an SOG layer has been deposited, is loaded onto the susceptor S. The inner pressure of the chamber CB is maintained at a predetermined pressure, for example, a low pressure of 1 to 200 mTorr, by the vacuum pump P and the valve V. Subsequently, a process gas, for example, an argon (Ar) or nitrogen (N2) gas, is injected into the chamber CB through the gas injection ring GR. At this time, a high negative voltage of about xe2x88x92500 to xe2x88x9230,000 volts is applied to the cathode plate CP by the high voltage power source HVP, while a low negative voltage of about 0 to xe2x88x92150 volts is applied to the grid plate CP by the low voltage power source LVP. Accordingly, the process gas injected into the chamber CB is ionized, so that positive and negative ions are produced, wherein the positive ions move toward the grid plate GP due to the electric field created by the low negative voltage applied to the grid plate GP. The positive ions that reach the grid plate GP are accelerated toward the cathode plate CP through the holes of the grid plate GP by the high negative voltage applied to the cathode plate CP. The accelerated positive ions hit the bottom surface of the cathode plate CP. As a consequence, secondary electrons are emitted from the cathode plate CP. Since the bottom surface of the cathode plate CP is formed of a non-metal conductive material, unlike a conventional case, emission of metal atoms from the cathode plate CP does not occur. The electrons emitted from the cathode plate CP are accelerated toward the wafer loaded onto the susceptor S by the electric field produced by the high and low negative voltages applied to the cathode plate CP and the grid plate GP, respectively. At this time, some electrons further ionize the process gas molecules which are present between the grid plate GP and the wafer, to thereby produce positive and negative ions. This allows continuous emission of the electrons from the cathode plate CP. With variations of the level of voltage applied to the grid and cathode plates, the number of electrons and the level of energy irradiated onto the wafer change. Thus, the wafer surface may be irradiated with an electron beam having a desired current density and energy by appropriate control of the grid voltage and cathode voltage. In the case where a photoresist layer is irradiated with the electron beam, the photoresist layer is cured by baking. When an SOG layer is irradiated with the electron beam, the SOG layer is also cured, wherein the cured SOG layer exhibits similar properties to those of a silicon oxide layer. For example, the dielectric constant and etch rate of the resulting cured SOG layer are similar to those of the silicon oxide layer. Also, by appropriately controlling an energy level of the electron beam irradiated onto the SOG layer, the thickness of the resulting cured SOG layer can be adjusted. For example, by appropriately controlling the electron beam irradiation conditions, a double-layered material film may be obtained. Each layer of the double-layered material film can be individually controlled and have different properties. For example, the double-layered film can include a non-cured SOG layer and a cured SOG layer. Since the electron beam irradiation is carried out at a low temperature of 200xc2x0 C. or less, diffusion of impurities that are implanted into the semiconductor wafer does not occur. Accordingly, a change in electrical properties of MOS transistors can be avoided. Also, when the wafer surface is irradiated with an electron beam by using the electron beam irradiating apparatus according to the present invention, the wafer can be prevented from contamination by metals, thus markedly improving the reliability of semiconductor devices. Thus, the electron beam irradiating apparatus according to the present invention is suitable for manufacturing highly integrated semiconductor devices with an increased requirement for low-temperature processing. FIGS. 3 through 6 are schematic sectional views illustrating a method of forming inter-metal dielectric (IMD) films of semiconductor devices by using the electron beam irradiating apparatus according to the present invention. For reference, the electron beam irradiating apparatus according to the present invention can be applied to forming general ILD films and baking photoresist layers, as well as to forming IMD films. By irradiating the wafer surface with an electron beam using the electron beam irradiating apparatus according to the present invention, the wafer surface can be protected from contamination by metal atoms. In addition, the electron beam irradiating apparatus according to the present invention permits low-temperature processes at a temperature of 200xc2x0 C. or less. In particular, referring to FIG. 3, an ILD film 3 is formed on a semiconductor substrate 1. Lower metal interconnections 5 are formed in predetermined regions of the ILD film 3. Then, a first capping insulation layer 7, for example, a plasma oxide layer, is formed on the metal interconnections 5 and the ILD films between the metal interconnections 5. A planarized SOG layer 9 is formed on the entire surface of the resultant structure having the first capping insulation layer 7. The planarized SOG layer 9 is formed by spinning a layer of liquid SOG on the first capping insulation layer 7. The planarized SOG layer 9 completely fills spaces between adjacent lower metal interconnections 5 and is in the form of a thin film on the top of each lower metal interconnection 5. Referring to FIG. 4, the surface of the planarized SOG layer 9 is irradiated with an electron beam E by using the electron beam irradiating apparatus of FIG. 1. At this time, the energy level is appropriately controlled to the extent that the thin SOG layer 9 on the top of the lower metal interconnections 5 is cured while the SOG layer 9 filling the spaces between the lower metal interconnections 5 is not cured. As a result, a cured SOG layer 9xe2x80x2 is formed to a predetermined thickness on the surface of the planarized SOG layer 9. The properties of the SOG layer 9 vary with a curing process. Thus, the cured SOG layer 9xe2x80x2 exhibits similar properties to those of silicon oxide layers. In particular, the initial SOG layer 9, which is not cured yet, has a low dielectric constant and a high etch rate, compared to those of the silicon oxide layers. Meanwhile, the dielectric constant and the etch rate of the cured SOG layer 9xe2x80x2 are nearly the same as those of the silicon oxide layers. In other words, it can be noted that as the SOG layer 9 is cured, the dielectric constant increases while the etch rate decreases. Referring to FIG. 5, a second capping insulation layer 11, for example, a plasma oxide layer, is formed on the cured SOG layer 9xe2x80x2. The second capping insulation layer 11, the cured SOG layer 9xe2x80x2 and the first capping insulation layer 7 are sequentially etched, to thereby form via holes 13 which expose a predetermined region of the lower metal interconnections 5. The etch rate of the cured SOG layer 9xe2x80x2 is nearly the same as that of the first and second capping insulation layers 7 and 11 formed of silicon oxide, such as plasma oxide, so that the vias 13 exhibit a normal sidewall profile. Also, since the uncured SOG layer 9 remains between the lower metal interconnections 5, parasitic capacitance between the lower metal interconnections 5 can be minimized. Referring to FIG. 6, a metal layer is deposited on the resultant structure having the vias 13, filling the vias 13. Then, the metal layer is patterned to form upper metal interconnections 15 which fill the vias 13. As described above, the electron beam irradiating apparatus according to the present invention can effectively suppress emission of metal atoms from the cathode plate. Thus, during electron beam irradiation onto the SOG layer or the photoresist layer, the semiconductor wafer can be protected from contamination by the metal atoms, thus producing semiconductor devices with stabilized electrical properties and reliability. While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.