Patent Number: 
Section: claims

1. A method of forming a pattern of elements for use on a semiconductor wafer, comprising:defining a perimeter geometry of a number of lithographic elements;selecting regions of the pattern where a distance between adjacent elements is within a selected range; andmodifying the perimeter geometry of at least one lithographic element, wherein the distance between adjacent elements is adjusted to a desired spacing. 2. The method of claim 1, wherein the selected range includes an upper limit, wherein above the upper limit, a supplemental lithographic element will fit between adjacent lithographic elements. 3. The method of claim 1, wherein the desired spacing is chosen from a plurality of desired spacings, wherein the desired spacing is determined by adjacent lithographic element geometry. 4. The method of claim 1, wherein the desired spacing includes a minimum lithographic feature size. 5. The method of claim 1, further including forming a reticle using the modified perimeter geometry. 6. The method of claim 5, further including patterning lithographic elements on a semiconductor substrate using the reticle. 7. The method of claim 1, wherein defining the perimeter geometry of the number of lithographic elements includes defining a perimeter geometry of a number of conductive traces. 8. A machine-readable medium with instructions stored thereon, the instructions when executed operable to cause:definition of a perimeter geometry for a number of lithographic elements;selection of regions in the pattern where a distance between adjacent elements is within a selected range; andmodification of the perimeter geometry of at least one lithographic element, wherein the distance between elements is adjusted to a desired spacing. 9. The machine-readable medium of claim 8, wherein definition of the perimeter geometry for the number of lithographic elements includes definition of a perimeter geometry for a number of conductive trace elements. 10. The machine-readable medium of claim 9, wherein definition of the perimeter geometry for the number of conductive trace elements includes definition of a perimeter geometry for a number of interconnect traces between memory cells in a memory device. 11. The machine-readable medium of claim 8, wherein the desired spacing is chosen from a plurality of desired spacings, wherein the desired spacing is determined by adjacent lithographic element geometry. 12. The machine-readable medium of claim 8, wherein the desired spacing includes a minimum lithographic feature size. 13. The machine-readable medium of claim 8, further including intructions for causing formation of a reticle with the modified perimeter geometry. 14. A memory device, comprising:a number of memory cells; andinterconnection circuitry between selected memory cells, wherein elements of the circuitry are formed by a method including:defining a perimeter geometry of a number of interconnect circuitry elements;selecting regions of the pattern where a distance between adjacent elements is within a selected range;modifying the perimeter geometry of at least one interconnect circuitry element, wherein the distance between adjacent elements is adjusted to a desired spacing; andlithographically forming the interconnect circuitry using the modified perimeter geometry. 15. The memory device of claim 14, wherein the memory cells include DRAM memory cells. 16. The memory device of claim 14, wherein the memory cells include flash memory cells. 17. The memory device of claim 14, wherein the selected range includes an upper limit, wherein above the upper limit, a supplemental lithographic element will fit between adjacent lithographic elements. 18. The memory device of claim 14, wherein the desired spacing is chosen from a plurality of desired spacings, wherein the desired spacing is determined by adjacent lithographic element geometry. 19. The memory device of claim 14, wherein the desired spacing includes a minimum lithographic feature size.