Patent Number: 
Section: claims

1. An automated method for repairing spacing of vertical conductive features in the fabrication of semiconductor integrated circuits, the method comprising:determining a minimum spacing;using a database, identifying vertical conductive feature patterns having a spacing less than the minimum spacing;for each identified vertical conductive feature pattern having a spacing less than the minimum spacing, determining a first direction to expand and a second direction to shrink to define a revised vertical conductive feature pattern;checking the revised vertical conductive feature pattern against design rules to see if the design rules are violated; andfor each identified vertical conductive feature pattern having a spacing less than the minimum spacing, replacing the identified vertical conductive feature pattern with the revised vertical conductive feature pattern when the design rules are not violated, wherein the revised vertical conductive feature pattern is expanded in the first direction and shrunk in the second direction. 2. The method of claim 1, wherein the vertical conductive feature patterns include via patterns. 3. The method of claim 1, wherein the vertical conductive feature patterns include contact patterns. 4. The method of claim 1 further comprising saving the revised vertical conductive feature pattern in the database. 5. The method of claim 1 further comprising forming a photo mask after the step of replacing the identified vertical conductive feature pattern with the revised vertical conductive feature pattern. 6. The method of claim 5 further comprising:forming a first lower-level conductive line and a second lower-level conductive line;forming a dielectric layer on the first and the second lower-level conductive lines;forming a photosensitive layer over the dielectric layer;placing the photo mask on the photosensitive layer;exposing the photosensitive layer;patterning the photosensitive layer;etching the dielectric layer and forming openings; andfilling the openings with a conductive material. 7. The method of claim 1, wherein the method is performed by a computer aided design utility tool. 8. The method of claim 1, wherein the revised vertical conductive feature pattern has a size substantially close to a size of the respective identified vertical conductive feature pattern. 9. The method of claim 1, wherein the revised vertical conductive feature pattern has a size substantially greater than a size of the respective identified vertical conductive feature pattern. 10. The method of claim 1, wherein the first direction is in a direction parallel to a longitudinal direction of a metal line connecting to the respective identified vertical conductive feature pattern. 11. A method of forming a photo mask used in integrated circuit fabrication processes, the method comprising:determining a minimum spacing;identifying patterns having a spacing less than the minimum spacing, wherein the patterns are for forming vertical conductive features;for each identified pattern, determining a first direction to expand and a second direction to shrink to define a revised pattern;checking against design rules to see if the design rules are violated if the respective identified pattern is expanded in the first direction and shrunk in the second direction;replacing each identified pattern with the respective revised pattern when the design rules are not violated, wherein the revised pattern is expanded in the first direction and shrunk in the second direction; andforming a photo mask using the revised pattern.