Patent Number: 
Section: claims

1. A method, comprising:determining at a processor device a first set of test measurements based on a first test structure;determining at the processor device a first device under test (DUT) measurement based on an open test structure, a short test structure, and a through test structure and based on the first set of test measurements;determining at the processor device a second DUT measurement based on the open test structure and the short test structure and based on the first set of test measurements;calculating at the processor device an imperfection error based on the first DUT measurement and the second DUT measurement;determining at the processor device a set of intrinsic electrical characteristics for a device under test based on the open test structure, the short test structure, the through test structure, a left test structure and a right test structure and based on the imperfection error; andstoring the set of intrinsic electrical characteristics. 2. The method of claim 1, wherein the first test structure includes the device under test. 3. The method of claim 1, wherein determining a set of intrinsic electrical characteristics comprises:determining a second set of test measurements based on a second test structure including the device under test; anddetermining the set of intrinsic electrical characteristics based on the second set of test measurements. 4. The method of claim 3, wherein the first set of test measurements is associated with a two-port test structure and the second set of test measurements is associated with a three-port device. 5. The method of claim 4, wherein the two-port test structure includes a resistive element. 6. The method of claim 1, wherein calculating an imperfection error comprises subtracting the second test measurement from the first test measurement to determine the imperfection error. 7. The method of claim 1, wherein determining the set of intrinsic electrical characteristics comprises subtracting the imperfection error from test measurements of the short test structure. 8. The method of claim 1, wherein determining the first DUT measurement comprises determining the first DUT measurement based on a three-step method. 9. The method of claim 1, wherein determining the second DUT measurement comprises determining the second DUT measurement based on a three-step method. 10. The method of claim 1, wherein determining the set of intrinsic electrical characteristics comprises determining the set of intrinsic electrical characteristics based on a four-port method. 11. The method of claim 1, wherein the first set of test parameters comprise scatter measurements. 12. The method of claim 1, wherein the device under test is a two terminal device. 13. The method of claim 1, further comprising designing an integrated circuit device based on the set of intrinsic electrical characteristics to produce an integrated circuit design. 14. The method of claim 13, further comprising forming an integrated circuit based on the integrated circuit design. 15. A method, comprising:determining at a processor device a first set of test measurements based on a first test structure including a device under test;determining at the processor device a first DUT measurement based on the first set of test measurements and a three-step de-embedding method;determining at the processor device a second DUT measurement based on the first set of test measurements and an open-short de-embedding method;determining at the processor device an imperfection error based on the first DUT measurement and the second DUT measurement;determining at the processor device a set of intrinsic electrical characteristics based on the imperfection error and a four-port de-embedding method; andstoring the set of intrinsic electrical characteristics. 16. The method of claim 15, wherein the imperfection error is a short imperfection error. 17. The method of claim 15, wherein determining the first set of test measurements comprises determining a set of scatter parameter measurements for the device under test. 18. A non-transitory computer readable medium containing a computer program, the computer program comprising instructions that, when executed by a processor, perform a method comprising:determining a first set of test measurements based on a first test structure;determining a first device under test (DUT) measurement based on an open test structure, a short test structure, and a through test structure and based on the first set of test measurements;determining a second DUT measurement based on the open test structure and the short test structure and based on the first set of test measurements;calculating an imperfection error based on the first DUT measurement and the second DUT measurement; anddetermining a set of intrinsic electrical characteristics for the device under test based on the open test structure, the short test structure, the through test structure, a left test structure and a right test structure and based on the imperfection error. 19. The non-transitory computer readable medium of claim 18, wherein the first test structure includes the device under test. 20. The non-transitory computer readable medium of claim 18, wherein the instructions to determine a set of intrinsic electrical characteristics comprise instructions, when executed by the processor, perform a method to:determining a second set of test measurements based on a second test structure including the device under test; anddetermining the set of intrinsic electrical characteristics based on the second set of test measurements.