Patent Number: 
Section: description

The invention is described below in the context of representative embodiments that are not intended to be limiting in any way. Since the respective figures accompanying the description of the embodiments are schematic, the figures do not provide actual or relative dimensions of the depicted components. As a result of a thorough investigation into the causes of deteriorated accuracy of projected pattern elements in peripheral regions of chips, as observed especially whenever charged-particle-beam (CPB) microlithography is performed with a high beam-acceleration voltage, it has been discovered that the actual cause is a xe2x80x9cproximity effectxe2x80x9d imparted by adjacent chips imprinted on the lithographic substrate (xe2x80x9cwaferxe2x80x9d). Normally, to perform CPB microlithography of a LSI pattern, for example, a first step involves defining the actual pattern. This step includes determining the manner in which the pattern is to be divided, on the reticle, into subfields and the manner in which individual pattern elements are to be configured in the respective subfields on the reticle. Determining how pattern elements are to be defined takes into consideration proximity effects expected to be imparted to the pattern elements when the elements are transfer-exposed onto the wafer. A xe2x80x9cproximity effectxe2x80x9d is a phenomenon that is manifest on the pattern as transfer-exposed onto the wafer, wherein unwanted regions (especially adjacent to pattern elements actually exposed) of the resist become exposed. The phenomenon is caused by: (1) backscattering, into adjacent areas of resist, of charged particles of the beam by atoms and molecules of the resist and by atoms of the substrate on which the beam is incident, and (2) secondary electrons emitted by the resist on which the beam is incident. The backscattered and secondary electrons penetrate into adjacent areas of resist, causing unwanted xe2x80x9cexposurexe2x80x9d of the adjacent areas. Defining individual pattern elements while taking into account proximity effects involves configuring the pattern elements, to be defined on the reticle, in a manner serving to offset the proximity effect. In other words, at least certain pattern elements are defined on the reticle with respective profiles that are different from actual designed profiles so that, when the pattern elements are projected onto the wafer, the resulting respective images as formed in the resist have profiles that more closely approximate the desired as-designed profiles. Hence, determining how pattern elements are to be defined on the reticle is performed with consideration given to a range over which respective proximity effects are significant, and to pattern elements that may be located within the range. Determining this range (termed the xe2x80x9cproximal rangexe2x80x9d) begins with a determination of the xe2x80x9cbackscattering radiusxe2x80x9d). The backscattering radius is the width of the Gaussian function corresponding to backscatter of electrons whenever the energy-intensity distribution of the incident beam is approximated by a linear combination of Gaussian functions. This radius is used to describe a distribution of energy intensity of cumulative exposure energy. The energy-intensity distribution is a function indicating the exposure energy received by surrounding points whenever an electron beam is incident at a point. The proximity effects imparted by pattern elements within the backscattering radius cannot be neglected. The proximal range (range over which proximity effects imparted by other pattern elements is significant) typically is wider than the backscattering radius, and is determined by a trade-off of accuracy versus calculation time (i.e., the greater the desired accuracy with which proximity effects are corrected, the longer the time required to calculate the proximity effects and their required corrections). Typically, by way of example, the proximal region extends more than three times the backscattering radius. The calculations result in determinations of the manner and extent to which individual pattern elements, as defined on the reticle, are to be reconfigured. Typically, these calculations are performed using a computer-simulation technique. Information relevant to performing these calculations and determining the width of the proximal region is set forth, for example, in U.S. patent application Ser. Nos. 09/704473 and 09/861210, incorporated herein by reference. At the relatively low beam-acceleration voltages conventionally used, backscattering radii tend to be small relative to the normal distance between adjacent (neighboring) chips on the wafer. As a result, adjacent chips on the wafer usually did not cause significant proximity effects on pattern elements projected onto peripheral regions of a chip. Hence, determining how pattern elements are to be defined on the reticle conventionally did not include a consideration of proximity effects caused by neighboring chips. However, with increases in beam-acceleration voltage, the backscattering radius and hence the proximal range is increased correspondingly. Hence, it has been discovered that a consideration must be given, when configuring pattern elements to be defined on the reticle, to proximity effects imparted to the elements by neighboring chips when the pattern is transfer-exposed from the reticle to the wafer. FIG. 1 schematically depicts, in plan view, an exemplary chip pattern 10 having outer dimensions of 2000 xcexcmxc3x972000 xcexcm. The chip pattern 10 comprises a large L-shaped pattern element 11, having arm widths of 100 xcexcm, extending along the left edge and bottom edge and a small line 12, having a width of 70 nm and a length of 50 xcexcm, situated in the upper right corner opposite the L-shaped element 11. FIG. 2 shows, in plan view, an exemplary arrangement of nine individual chips 13A-13I, each having a chip pattern as shown in FIG. 1, on the surface of a wafer. The chips 13A-13I are spaced 80 xcexcm apart in this example. Generally, the smaller the distance between chips on the wafer, the better in terms of production efficiency, because each wafer yields a correspondingly larger number of chips. Attention is directed, in FIG. 2, to the center chip 13E that is surrounded on all sides by neighboring (adjacent) chips. With respect to the element 12E extending along the upper right edge, investigations were made of a first situation in which backscatter from neighboring chips 13B, 13C, 13F was ignored, and a second situation in which backscatter from the neighboring chips was considered. Exemplary parameters in the investigations were: a silicon substrate, a beam-acceleration voltage of 125 kV, a backscatter radius of 47.2 xcexcm, a demagnification ratio of 1/4, and a backscatter coefficient of 0.7. In addition, the blur produced by the CPB optical system was 70 nm. In the investigation in which backscatter from adjacent chips is ignored, a sufficient distance was assumed to exist between the large L-shaped element 11E and the small element 12E in the chip 13E. Hence, it was assumed that transfer-exposure of the small element 12E was not influenced by any proximity effect from other pattern elements or chips. Under such conditions the corresponding pattern element as defined on the reticle (for a demagnification ratio of 1/4) had a width of 280 nm. The resulting pattern element 12E as transfer-exposed onto the chip 13E (FIG. 3(a)) was defined on the reticle as having a width of 70 nm. Exposure time was established so that the threshold exposure dose for the resist was exceeded in the element 12E. In actuality, in the chip 13E backscatter is received by the pattern element 12E from the respective large pattern elements 11B, 11C, 11F proximally located in the neighboring chips 13B, 13C, 13F, respectively. Taking this backscatter into account, the dosage received at the element 12E on the wafer is increased, as shown in FIG. 3(b). Consequently, the linewidth of the element 12E as formed on the wafer is increased by this proximity effect to 70.9 nm (FIG. 3(b)). Hence, in the investigation in which the contribution, to exposure of the pattern element 12E on the wafer, of backscatter from the large elements 11B, 11C, 11F is taken into account, calculations reveal that the width of the pattern element 12E as defined on the reticle should be changed slightly to offset this proximity effect. According to the calculations, the linewidth of the pattern element 12E as defined on the reticle is decreased to 276 nm. Exposure of this element onto the wafer yields a dosage, as received on the wafer, as shown in FIG. 3(c), in which the linewidth of the pattern element is restored to the desired width of 70 nm. With respect to the method described above, it is noted that a complete chip located peripherally (near an edge) of the wafer does not have a full complement of neighboring chips. As a result, whenever a pattern on the reticle is configured under the assumption in which a full set of neighboring chips exist, the reticle may not be configured optimally for exposure of certain chips (especially peripherally located chips). This situation is shown in FIG. 4, in which an edge 15 of the wafer 14 is depicted relative to the chips 13A-13I formed on the wafer. Each of the chips 13A-13I has a respective pattern such as that shown in FIG. 1. Note that the chips 13D-13E and 13G-13H can be made into finished microelectronic devices, but the chips 13A-13C, 13F and 13I cannot because each of these chips is missing at least a portion thereof (due to the chips extending partially or fully off the edge 15 of the wafer 14). The chips 13A, 13B, 13F, and 13I extending partially off the wafer edge 15 are said to be xe2x80x9cstraddlingxe2x80x9d the wafer edge. Conventionally, it is regarded as wasteful to expose any portions of chips such as 13A, 13B, 13C, 13F, and 13I. Consequently, exposure of these chips conventionally is not performed so as not to compromise throughput. Rather, exposure conventionally is performed only of the chips 13D-13E and 13G and 13H. In FIG. 4, features that conventionally are exposed are shaded more darkly than features that are not. However, whenever exposure of the chips 13A-13C, 13F, 13I is not performed, exposure of the chips 13D, 13E, and 13H is unaffected by backscatter from the neighboring chips 13A-13C, 13F, 13I. But, since the reticle (used to expose all the chips on the wafer) is configured to account for such backscatter, the chips 13D, 13E, 13H as transfer-exposed onto the wafer do not have optimally corrected pattern elements. To prevent this problem, exposure also is performed of portions of the chips 13A, 13B, 13F, and 13I that straddle the edge 15 of the wafer 14 but nevertheless will not become actual chips. (The chip 13C is not exposed at all because it is entirely off the wafer 14 where it cannot contribute any backscatter anyway.) By exposing the wafer in this manner, since all the chips actually formed on the wafer are affected substantially equally by backscatter by neighboring chips (or portions of chips). This allows a reticle configured to offset the resulting proximity effects to have an equally curative effect on all the chips. I.e., by exposing portions of the xe2x80x9cpartialxe2x80x9d chips 13A, 13B, 13F, and 13I, the full chips 13D, 13E, 13H will have patterns that are as design-mandated and as fully corrected as any other chip (e.g., chip 13G) on the wafer. Note that, with respect to the xe2x80x9cpartialxe2x80x9d chips (i.e., chips 13A, 13B, 13F, 13I), it is unnecessary to expose all the subfields of such chips. Rather, only those subfields of such chips capable of producing backscatter that can reach proximally situated xe2x80x9ccompletexe2x80x9d chips need be exposed. For example, as shown in FIG. 5, in the xe2x80x9cpartialxe2x80x9d chips 13A, 13B, 13F, and 13I, only subfields situated in the respective regions denoted 16A, 16B, 1F6, and 16I, respectively, are exposed. (In FIG. 5, exposed portions are shaded more darkly than portions that are not exposed.) FIG. 6 is a flow chart of a microelectronic-device manufacturing method that includes a microlithography step performed using a CPB-microlithography method as described herein. The depicted method generally comprises the main steps of wafer production (wafer preparation), reticle production (reticle preparation), wafer processing to form chips, chip dicing and assembly, and inspection of completed chips. Each step usually comprises several sub-steps. The wafer-preparation step results in production or preparation of a wafer suitable for use as a lithographic substrate. This step typically involves growth of a monocrystalline silicon ingot, cutting of the ingot into wafers, and polishing the wafers. The reticle-preparation step results in production or preparation of a reticle that defines a desired pattern to be transferred lithographically to the wafer. This step includes performing methods as described below. The wafer-processing step comprises multiple steps resulting in the formation of multiple layers of vertically and horizontally interconnected circuit elements, and is discussed below. The chip dicing and assembly step involves cutting out (dicing) of individual chips from the wafer after completing formation of all the constituent layers of the chips on the wafer, and assembling each individual chip into a respective package with connecting leads and the like. The inspection step involves qualification and reliability testing and inspection of completed devices. Among the main steps, wafer processing is key to achieving the smallest feature sizes (critical dimensions), best inter-layer registration, and device performance. In the wafer-processing step, multiple circuit patterns are layered successively atop one another in each die on the wafer, wherein the formation of each layer typically involves multiple sub-steps. Usually, many operative microelectronic devices (chips or dies) are produced on each wafer. Typical wafer-processing steps include: (1) Thin-film formation involving formation of a dielectric layer for electrical insulation or a metal layer for connecting wires. The films are produced by CVD, sputtering, or other suitable technique. (2) Oxidation of the thin-film layer or other portion of the wafer surface. (3) Microlithography to form a resist pattern, according to the reticle pattern, for selective processing of the thin film or the substrate itself. (4) Etching (e.g., dry etching) or analogous step to etch the thin film or substrate according to the resist pattern. (5) Doping as required for implantation of dopant ions or impurities into the thin film or substrate according to the resist pattern. Doping can include a thermal treatment to facilitate diffusion of the impurity. (6) Resist stripping to remove the resist from the wafer. (7) Wafer inspection. Wafer processing is repeated as required (typically many times) to fabricate the desired microelectronic devices on the wafer. FIG. 7 is a flow chart of typical steps performed in microlithography, which is a principal step in wafer processing. The microlithography step typically includes: (1) application of resist to the wafer, wherein a suitable resist is coated on the wafer substrate (which can include a circuit element formed in a previous wafer-processing step); (2) exposure step (using a CPB exposure method as described above), to expose the resist with the desired pattern and form a latent image; (3) development step, to develop the exposed resist and obtain an actual pattern in the resist; and (4) optional annealing step, to stabilize the developed pattern in the resist. Commonly known technology can be used for any of the steps summarized above, including the microelectronic-device manufacturing process, wafer-processing, and microlithography. Hence, detailed descriptions of these processes are not provided. Whereas the invention has been described in connection with multiple representative embodiments and examples, it will be understood that the invention is not limited to those examples. On the contrary, the invention is intended to encompass all modifications, alternatives, and equivalents as may be included within the spirit and scope of the invention, as defined by the appended claims.