Patent Number: 
Section: claims

1. A method for monitoring critical dimension (CD) variations of a reticle, comprising:providing a reticle layer over a reticle substrate, said reticle layer including each of:a patterned feature area corresponding to a desired circuitry pattern; anda test pattern area, wherein a portion of said test pattern area is within a step-distance of a portion of said patterned feature area;patterning a resist material by stepping said reticle, the patterning including each of the patterned feature area and test pattern area incorporated in said reticle layer;visually inspecting said resist material for light and dark regions within said test pattern area, said light and dark regions representing a corresponding variance in said patterned feature area of the resist material,using said resist material as patterned by said reticle to form the feature of a semiconductor device after said visually inspecting. 2. The method as recited in claim 1 wherein said portion of said test pattern area is a first portion of said test pattern area and said portion of said patterned feature area is a first portion of said patterned area and wherein said first portion of said test pattern area is within a step-distance of said first portion of said patterned feature area and a second portion of said test pattern area is within a step-distance of a second portion of said patterned feature area, a variance between said first and second portions of said test pattern area being indicative of a variance between said first and second portions of said patterned feature area. 3. The method as recited in claim 1 wherein said test pattern area creates a reflective grating in said patterned resist material, and said reflective grating is configured to provide said light and dark regions if said variance in said patterned feature area exists. 4. The method as recited in claim 3 wherein said reflective grating includes a reoccurring line/space structure. 5. The method as recited in claim 4 wherein said reoccurring line/space structure has a pitch of less than about 3/2 a wavelength used in said patterning step. 6. The method as recited in claim 1 wherein said test pattern area is located in a scribe region defined by said patterned feature area. 7. The method as recited in claim 1 wherein said variance is a systematic variance in critical dimension (CD) in said patterned feature area. 8. The method as recited in claim 1 wherein visually inspecting said material includes visually inspecting said material using an optical microscope. 9. The method as recited in claim 8, further including changing a focus on said optical microscope to cause said light and dark regions to become more or less pronounced. 10. A method for making a semiconductor device, comprising:patterning a resist material by stepping a reticle, wherein said reticle includes each of:a patterned feature area corresponding to a desired feature of a semiconductor device; anda test pattern area, wherein a portion of said test pattern area is within a step-distance of a portion of said patterned feature area; andvisually inspecting said patterned resist material for light and dark regions within a corresponding test pattern area, said light and dark regions representing a systematic variance in critical dimension (CD) in said patterned resist material;using said patterned resist material to form the feature of a semiconductor device after said visually inspecting. 11. The method as recited in claim 10 wherein said patterned resist material is used to form multiple features, and wherein said multiple features are electrically contacted to form an operational integrated circuit. 12. A method for making a semiconductor device, comprising:patterning a resist material using a reticle having a plurality of step areas within the reticle, wherein said reticle includes each of:a patterned feature area corresponding to a desired feature of a semiconductor device; anda test pattern area, wherein a portion of said test pattern area is within a step-area distance of a portion of said patterned feature area; andvisually inspecting said patterned resist material for light and dark regions, differences in said light and dark regions between said plurality of step areas representing a systematic variance in critical dimension (CD) in said patterned resist material;using said patterned resist material to form the feature of a semiconductor device after said visually inspecting.