Patent Number: 
Section: claims

1. A circuit comprising:a periodic Performance Monitor Counter (PMC), the periodic PMC being configured to count performance signals from a component of a computer system for a predetermined period of time; anda first count comparator hardware coupled to the periodic PMC, wherein in response to the first count comparator hardware determining that the number of performance signals stored in the periodic PMC is outside of a first predetermined range of numbers, the first count comparator hardware generates a first action signal to evoke a performance adjustment to a computer logic whose performance signals are being monitored by the periodic PMC. 2. The circuit of claim 1, further comprising:a PMC reset controller, wherein the PMC reset controller clears the periodic PMC after the predetermined period of time. 3. The circuit of claim 1, further comprising:a counter selector coupled to the first count comparator hardware;a first counter and a second counter coupled to the counter selector, wherein the counter selector is capable of selectively toggling between the first and second counters to store a current first action signal count stored in the periodic PMC, such that one of the first and second counters stores a previous period's first action signal count from the first count comparator hardware and the other of the first and second counters stores a current period's first action signal count from the first count comparator hardware; and a second count comparator coupled to the first and second counters, wherein the second count comparator issues an action signal in response to a difference between the performance signal counts in the first and second counters being outside of a second predetermined range of numbers. 4. The circuit of claim 1, wherein the computer system is a microprocessor. 5. The circuit of claim 1, wherein the action signal is an external trigger used to control an event capture by a logic analyzer that is external to the computer system. 6. The circuit of claim 1, wherein the action signal generates an internal trigger for use with an internal trace array. 7. The circuit of claim 1, wherein the action signal generates a new performance event that is stored in a performance event PMC, wherein the performance event PMC stores a total number of action signals that reflect the number of times that the performance signals exceed the first predetermined range of numbers. 8. A circuit comprising:a periodic Performance Monitor Counter (PMC), the periodic PMC being configured to count performance signals from a component of a computer system;a counter selector coupled to the periodic PMC;a first counter and a second counter coupled to the counter selector, wherein the counter selector is capable of selectively toggling between the first and second counters to store a current performance signal count stored in the periodic PMC, such that one of the first and second counters stores a previous period's performance signal count from the periodic PMC and the other of the first and second counters stores a current period's performance signal count from the periodic PMC; and a count comparator coupled to the first and second counters, wherein the count comparator issues an action signal in response to a difference between the performance signal counts in the first and second counters being outside of a predetermined range of numbers. 9. The circuit of claim 8, further comprising:a clock cycle counter coupled to the count comparator, wherein the clock cycle counter controls when the performance signal counts in the first and second counters are compared. 10. The circuit of claim 8, wherein the computer system is a microprocessor and wherein the action signal causes a chiplet in the microprocessor to perform a specific action. 11. The circuit of claim 8, wherein the action signal is an external trigger used to control an event capture by a logic analyzer that is external to the computer system. 12. The circuit of claim 8, wherein the action signal generates an internal trigger for use with an internal trace array. 13. The circuit of claim 8, wherein the action signal generates a new performance event that is stored in a performance event PMC, wherein the performance event PMC stores a total number of action signals that reflect the number of times that the performance signals exceed the predetermined range of numbers. 14. A method for capturing a change in performance in a computer logic using a Performance Monitoring Counter (PMC), the method comprising:storing in a first hardware counter a starting count of performance events captured by a PMC;storing in a second hardware counter an ending count of performance events captured by the PMC;comparing the counts of performance events in the first and second hardware counters; andgenerating an action signal if a first derivative of the performance event counts in the first and second hardware counters is outside a first predetermined range of values. 15. The method of claim 14, further comprising:storing the first derivative of the performance event counts in the first and second hardware registers in a third hardware counter;storing a subsequent first derivative of the performance event counts in the first and second hardware counters in a fourth hardware counter; andin response to a second derivative of the first derivative and the subsequent first derivative being outside of a second predetermined range of values, generating the action signal. 16. A method comprising:storing in a first hardware counter a starting count of performance events captured by a Performance Monitoring Counter (PMC);storing in a second hardware counter an ending count of performance events captured by the PMC;comparing the counts of performance events in the first and second hardware counters;using hardware to calculate a first derivative that reflects a rate of change in performance events;deriving the first derivative to obtain a second derivative that reflects a delta in the rate of change in performance events; andgenerating an action signal if the first derivative of the performance event counts in the first and second hardware counters is outside a first predetermined range of values. 17. The method of claim 16, further comprising: using the second derivative to prompt a configurable action. 18. The method of claim 17, wherein the configurable action is a chip inhibit. 19. The method of claim 17, wherein the configurable action is a trigger for a logic analyzer.