Patent Number: 063317117
Section: abstract

In scanning lithography as used in the semiconductor industry, systematic variations in critical dimension feature size which depend on the substrate coordinates are compensated for in a lithography tool. This is done by determining (experimentally or theoretically) low frequency variations in the critical dimensions on the target caused by imperfections in the lithography tool and/or the resist and/or the process steps. These low frequency spatial errors are compensated for, after the primary scanning exposure using the original pattern data, by a secondary scanning exposure of the target using a weaker intensity and relatively larger diameter exposure beam. The secondary exposure is also carried out at a larger address size (address grid) than is the primary exposure so it is relatively fast in terms of throughput. Since the secondary exposure is additive to the more intense primary exposure, relative critical dimension control is provided in fine increments but with relatively minor adverse impact on throughput and thus fabrication cost. Thus the detected systematic variation defects are compensated for without requiring the primary exposure to be performed at a smaller address size.