Patent Number: 
Section: claims

1. A method of patterning a substrate, comprising:providing a first set of patterned resist features on the substrate;exposing the first set of patterned resist features to a first exposure of ions extracted from a plasma sheath modifier operable to provide ions incident on the substrate over an angular range relative to the substrate; andperforming a lithographic patterning process on the substrate to form a second set of patterned resist features, wherein the plasma sheath modifier comprises a first insulator portion and a second insulator portion that define a gap therebetween, such that a shape of a boundary of the plasma proximate the gap is a convex shape relative to a plane of the substrate. 2. The method of claim 1, wherein the first and second set of patterned resist features are formed using a double patterning lithographic process. 3. The method of claim 1, wherein the first exposure is operable to harden the first set of patterned resist features which remain intact during the lithographic patterning process used to form the second set of patterned resist features. 4. The method of claim 1, wherein the first exposure comprises an exposure to inert gas ions. 5. The method of claim 1, wherein ion energy of the ions of the first exposure is less than about 20 keV. 6. The method of claim 1 wherein a linewidth roughness of the first set of patterned resist features is substantially reduced after the first exposure. 7. The method of claim 1, further comprising exposing the first set and second set of patterned resist features to a second exposure of ions extracted from the plasma sheath modifier operable to provide ions from the second exposure incident on the substrate over a wide angular range, wherein a linewidth roughness of the second set of patterned resist features is reduced after the second exposure. 8. The method of claim 1, wherein the angular range is between positive 60° and negative 60° centered about 0°. 9. The method of claim 1, wherein the first exposure is sufficient to produce a substantial decrease in low frequency linewidth roughness. 10. The method of claim 1, wherein the first and second sets of patterned resist features are silicon-based features.