Patent Number: 
Section: claims

1. A method of reticle field-wide hierarchy management, comprising:providing placement information of a hierarchical chip layout across a reticle field;generating templates and building a litho hierarchy tree for an entire reticle field in accordance with the placement information, the templates accounting for variation due to one or more of: positional environment within the reticle field, proximity environment, and structural functionality requirements;determining an exterior environment for each instance of a template candidate cell definition;generating a set of distinct environments for the exterior environments resulting from instances of the template candidate cell definition; andpartitioning instances of the template candidate cell definition to a corresponding one of the distinct environments to create one or more templates, in accordance with the respective exterior environments of the template candidate cells. 2. The method as claimed in claim 1, wherein the step of providing placement information comprises providing locations for instances of the chip layout as array references across the reticle field. 3. The method as claimed in claim 1, wherein the step of providing placement information comprises providing coordinates for instances of the chip layout across the reticle field to thereby enable arbitrary placement of the instances in the reticle field. 4. The method as claimed in claim 1, further comprising defining a reticle field-level cell encompassing at least one chip-level cell corresponding to the chip layout. 5. The method as claimed in claim 1, further comprising the step of defining primitive unit cells in the chip layout. 6. The method as claimed in claim 1, wherein the step of generating the templates in accordance with the placement information comprises generating the templates by assigning instances to distinct environments, wherein the environments are distinguished by cells in regions adjacent to each of the instances. 7. The method as claimed in claim 1, wherein the step of generating the templates in accordance with the placement information comprises generating the templates by assigning instances to different functional requirements pertaining to each of the instances. 8. The method as claimed in claim 1, wherein the step of generating the templates in accordance with the placement information comprises generating the templates by assigning instances to distinct environments, wherein the environments are distinguished by positional environment pertaining to each of the instances. 9. The method as claimed in claim 8, wherein the positional environment arises from at least one of lens aberration, optical flare, and/or pupil illumination non-uniformity. 10. The method as claimed in claim 1, wherein the, step of generating the templates in accordance with the placement information comprises:first grouping instances subject to common proximity perturbation effects; andthen further grouping the instances to address positional perturbation effects. 11. The method as claimed in claim 10, wherein the positional perturbation effects include at least one of lens aberration, optical flare, and/or pupil illumination non-uniformity. 12. The method as claimed in claim 1, further comprising distributing a computational task for an integrated circuit layout design on a reticle field wide basis among a collection of networked computation nodes, by carrying out the steps of:assigning the computation tasks for the templates to the networked computation nodes for concurrent execution; andassembling outputs from the computation nodes. 13. An integrated circuit manufactured according to the method of claim 12. 14. The method as claimed in claim 12, wherein the step of assembling outputs comprises creating a final processed circuit layout for the entire reticle field. 15. The method as claimed in claim 12, wherein the computational tasks are independent subtasks. 16. An integrated circuit manufactured according to the method of claim 1. 17. A method of reticle field-wide hierarchy management in an integrated circuit chip layout design, the method comprising the steps of:receiving a chip layout in hierarchical form;receiving placement information for the chip layout across a reticle field; and generating templates and building a litho hierarchy tree for an entire reticle field in accordance with the placement information; wherein the step of generating the templates and building the litho hierarchy tree comprises:for each instance of a template candidate cell definition, determining an exterior environment;for the exterior environments resulting from instances of the template candidate cell definition, generating a set of distinct environments; andpartitioning instances of the template candidate cell definition to a corresponding one of the distinct environments to create one or more templates, in accordance with the respective exterior enviromnents of the template candidate cells. 18. The method as claimed in claim 17, wherein the step of generating templates and building the litho hierarchy tree further comprises preprocessing steps of:identifying primary geometries of template candidate cells;generating primitive unit cells (PUC's) from the primary geometries of the template candidate cells; andassigning a unique identifier to each of the primitive unit cells. 19. The method as claimed in claim 17, wherein the step of determining the exterior environment for an instance comprises determining the said instance's proximity environment. 20. The method as claimed in claim 17, wherein the step of determining the exterior environment for an instance comprises determining the said instance's functional environment. 21. The method as claimed in claim 17, wherein the step of determining the exterior environment for an instance comprises determining the said instance's positional environment. 22. An integrated circuit manufactured according to the method of claim 17. 23. A method of partitioning a plurality of instances of a template candidate cell in a hierarchical chip layout design, the method comprising:identifying adjacent regions for each of the instances of the template candidate cell;generating an exterior environment for each of the instances of the template candidate cell, said exterior environment comprising one or more primitive unit cells (PUC's) overlapping or in contact with the adjacent regions of each of the instances;generating a set of unique environments for the exterior environments resulting from instances of template candidate cell definition; andassigning the instances of the template candidate cell to corresponding ones of the unique environments based on the PUC's. 24. The method as claimed in claim 23, wherein the adjacent regions correspond to regions within a range of influence for the instances. 25. The method as claimed in claim 24, wherein the range of influence is about 0.61.1 m. 26. The method as claimed in claim 23, wherein PUC identifiers are used to represent the primitive unit cells. 27. The method as claimed in claim 23, wherein the step of determining the set of unique environments comprises comparing identities and transforms for the PUC's. 28. The method as claimed in claim 23, further comprising defining templates for the instances based on the unique environments. 29. The method as claimed in claim 28, further comprising applying corrections for geometrical features within the templates. 30. The method as claimed in claim 29, wherein the corrections for geometrical features within the templates are computed by distributing respective templates for computation to respective ones of a collection of networked computation nodes. 31. The method as claimed in claim 30, wherein the computation nodes perform the intended computations for the templates concurrently. 32. The method as claimed in claim 30, wherein the computation nodes perform the intended computations for the templates on a reticle-wide basis. 33. The method as claimed in claim 28, further comprising determining optical proximity corrections for the templates. 34. The method as claimed in claim 28, further comprising determining corrections for the templates to address positional perturbations. 35. The method as claimed in claim 28, further comprising determining corrections for the templates to address functional requirements. 36. An integrated circuit manufactured according to the method of claim 23. 37. A computer program product comprising a computer useable medium having a computer readable program code functions embedded in the medium for causing a computer to manage for reticle field-wide hierarchy management in an integrated circuit chip layout design, the product comprising a computer-readable medium in which program instructions are stored, which instructions, when read by a computer, cause the computer to:receive the chip layout in hierarchical form;receive the placement information for the chip layout across the reticle field; and generating templates and building a litho hierarchy tree for an entire reticle filed in accordance with placement information, wherein said generating comprises:for each instance of a template candidate cell definition of the chip layout, determine an exterior environment;for the exterior environments resulting from instances of the template candidate cell definition, generate a set of unique distinct environments;partition the collection of instances of the template candidate cell definition to create one or more templates in accordance with their respective exterior environments; andgenerate the templates. 38. The product as claimed in claim 37, further comprising a third computer readable program code that causes the computer to determine if particular cell definitions are suitable candidates as templates. 39. The product as claimed in claim 37, further comprising fourth third computer readable program code that causes the computer to determine a proximity environment for each instance. 40. The product as claimed in claim 37, further comprising a fourth computer readable program code that causes the computer to determine a functional environment for each instance. 41. The product as claimed in claim 37 further comprising a fourth computer readable program code that causes the computer to determine a positional environment for each instance. 42. An integrated circuit manufactured with the computer program product of claim 37. 43. A computer program product for partitioning a plurality of instances of a template candidate cell in a hierarchical chip layout design the computer program product having a computer readable program instructions embedded in the medium for causing a computer to:identify adjacent regions for each of the instances of the template candidate cell;generate an exterior environment for each of the instances of the template candidate cell, said exterior environment comprising one or more primitive unit cells (PUC's) overlapping or in contact with the adjacent regions of each of the instances;generating a set of unique environments for the exterior environments resulting from instances of the template candidate cell definition; andassign the instances of the template candidate cell to corresponding ones of the unique environments based on the primitive unit cells. 44. The product as claimed in claim 43, wherein the adjacent regions correspond to regions within a range of influence for the instances. 45. The product as claimed in claim 43, wherein the instructions further cause the computer to compare identities and transforms for the PUC's. 46. The product as claimed in claim 43, wherein the instructions further cause the computer to define templates for the instances from unique environments. 47. The product as claimed in claim 46, wherein the instructions further cause the computer to distribute the templates among a collection of networked computation nodes. 48. The product as claimed in claim 47, wherein nodes are separate workstations. 49. The product as claimed in claim 47, wherein the instructions further cause the computer to perform intended computations for the templates. 50. The product as claimed in claim 47, wherein the instructions further cause the computer to perform the intended computations for the templates concurrently. 51. The product as claimed in claim 46, wherein the instructions further cause the computer to perform intended computations for the templates. 52. The product as claimed in claim 46, wherein the instructions further cause the computer to perform optical proximity corrections for the templates. 53. The product as claimed in claim 46, wherein the instructions further cause the computer to perform corrections for the templates to address positional perturbations. 54. The product as claimed in claim 46, wherein the instructions further cause the computer to perform corrections for the templates to address functional requirements. 55. An integrated circuit manufactured with the computer program product of claim 43. 56. A computer program product for distributing computational tasks for an integrated circuit layout design on a reticle field wide basis among a collection of networked computation nodes, the computer program product having a computer readable program instructions embedded in the medium for causing a computer to:generate a plurality of templates and building a litho hierarchy tree for an entire reticle field in accordance with a placement information of the integrated circuit layout across the reticle field;assign the computation tasks for the templates to the networked computation nodes for concurrent execution; andassemble outputs from the computation nodes, wherein generating the templates and building the litho hierarchy tree comprises:for each instance of a template candidate cell definition, determining an exterior environment;for the exterior environments resulting from instances of the template candidate cell definition, generating a set of distinct environments; andpartitioning instances of the template candidate cell definition to a corresponding one of the distinct enviromnents to create one or more templates, in accordance with the respective exterior environments of the template candidate cells. 57. The product as claimed in claim 56, wherein the computational tasks are independent subtasks. 58. The product as claimed in claim 56, wherein the instructions further cause the computer to create a final processed circuit layout for the entire reticle field.