Patent Number: 
Section: claims

1. A method comprising:receiving a target layout of an integrated circuit (IC);decomposing the target layout into a plurality of sub-layouts by a design system for a multiple patterning process, wherein the sub-layouts include a plurality of pattern edges, each of which is re-locatable within a respective region of freedom;relocating the pattern edges by the design system to improve manufacturability of the IC, resulting in modified sub-layouts, wherein the relocating of the pattern edges includes:choosing an evaluation index based on a target manufacturing process,moving one or more of the pattern edges in their respective regions of freedom, wherein the moving of the one or more of the pattern edges has an impact on a value of the evaluation index,calculating a score based on the evaluation index and the pattern edges, andrepeating the moving and the calculating until the score meets a threshold; andstoring the modified sub-layouts in a tangible computer-readable medium for use by a further IC process stage. 2. The method of claim 1, wherein the evaluation index includes one or more factors selected from the group consisting of: critical dimension (CD) variation budget, overlay budget, depth of focus, intensity log slope, mask error enhancement factor, data error enhancement factor, minimal area, minimal CD, and minimal spacing. 3. The method of claim 2, wherein the evaluation index is weighted. 4. The method of claim 1, wherein the score meets the threshold when the score reaches a local optimum. 5. The method of claim 1, wherein the score is calculated on the modified sub-layouts collectively and the threshold is defined for the modified sub-layouts collectively. 6. The method of claim 1, wherein the modified sub-layouts include a first modified sub-layout and a second modified sub-layout, further comprising:forming a first mask using the first modified sub-layout;forming a second mask using the second modified sub-layout;performing a first photolithography process to a wafer using the first mask; andperforming a second photolithography process to the wafer using the second mask. 7. The method of claim 6, wherein each of the first and second photolithography processes uses one of:an ultraviolet (UV) lithography process; andan extreme ultraviolet (EUV) lithography process. 8. The method of claim 1, wherein the modified sub-layouts include a first modified sub-layout and a second modified sub-layout, further comprising:performing a first maskless photolithography process to a wafer using the first modified sub-layout; andperforming a second maskless photolithography process to the wafer using the second modified sub-layout. 9. The method of claim 1, wherein the modified sub-layouts include a main layout and a cut layout. 10. The method of claim 1, further comprising:performing optical proximity correction (OPC) to the modified sub-layouts separately. 11. A method comprising:receiving a target layout of an integrated circuit (IC);decomposing the target layout into first and second sub-layouts, wherein polygon patterns of the first sub-layout overlap with polygon patterns of the second sub-layout, the first and second sub-layouts include first and second pluralities of re-locatable edges respectively, and each of the re-locatable edges is associated with a respective region of freedom where each of the re-locatable edges can be placed;performing an edge-relocation process to the first and second pluralities of re-locatable edges thereby resulting in first and second modified sub-layouts respectively, wherein the edge-relocation process includes:choosing an evaluation index based on a target manufacturing process,moving one or more of the re-locatable edges in their respective regions of freedom, wherein the moving of the one or more of the re-locatable edges has an impact on a value of the evaluation index,calculating a score of manufacturability based on the evaluation index and the re-locatable edges, andrepeating the moving and the calculating until the score of manufacturability meets a threshold;forming a first mask using the first modified sub-layout; andforming a second mask using the second modified sub-layout, wherein the first and second masks are to be used in first and second manufacturing processes to a wafer to collectively form the IC. 12. The method of claim 11, wherein the evaluation index includes edge placement errors for edges that are not re-locatable. 13. The method of claim 11, wherein the evaluation index includes one or more factors selected from the group consisting of: critical dimension (CD) variation budget, overlay budget, depth of focus, intensity log slope, mask error enhancement factor, minimal area, minimal CD, and minimal spacing. 14. The method of claim 11, wherein the moving of the one or more edges includes:fixing the first plurality of re-locatable edges in their respective initial locations; andmoving the second plurality of re-locatable edges in their respective regions of freedom. 15. The method of claim 11, wherein each of the polygon patterns of the first and second sub-layouts is a rectangle. 16. The method of claim 11, wherein each of the polygon patterns of the first and second sub-layouts includes at most one re-locatable edge. 17. The method of claim 11, further comprising:performing a first optical proximity correction (OPC) process to the first modified sub-layout before the forming of the first mask; andperforming a second optical proximity correction (OPC) process to the second modified sub-layout before the forming of the second mask. 18. A method comprising:receiving a target layout of an integrated circuit (IC);decomposing the target layout into a first sub-layout and a second sub-layout, wherein some patterns of the first sub-layout overlaps with some patterns of the second sub-layout;identifying a plurality of re-locatable edges in the first and second sub-layouts;associating each of the re-locatable edges with a respective region of freedom where each of the re-locatable edges can be placed;performing an edge-relocation process to the re-locatable edges thereby resulting in first and second modified sub-layouts respectively, wherein the edge-relocation process includes:choosing an evaluation index based on a target manufacturing process,moving one or more of the re-locatable edges in their respective regions of freedom, wherein the moving of the one or more of the re-locatable edges has an impact on a value of the evaluation index,calculating a score of manufacturability based on the evaluation index and the re-locatable edges, andrepeating the moving and the calculating until the score of manufacturability reaches a local optimum;performing a first target manufacturing process to a wafer using the first modified sub-layout; andperforming a second target manufacturing process to the wafer using the second modified sub-layout. 19. The method of claim 18, wherein the evaluation index includes one or more factors selected from the group consisting of: critical dimension (CD) variation budget, overlay budget, depth of focus, intensity log slope, mask error enhancement factor, data error enhancement factor, minimal area, minimal CD, and minimal spacing. 20. The method of claim 19, wherein the evaluation index is weighted.