Patent Number: 
Section: abstract

The present invention relates to a dimension measuring SEM system and a circuit pattern evaluating system capable of achieving accurate, minute OPC evaluation, the importance of which increase with the progressive miniaturization of design pattern of a circuit pattern for a semiconductor device, and a circuit pattern evaluating method. Design data and measured data on an image of a resist pattern formed by photolithography are superposed for the minute evaluation of differences between a design pattern defined by the design data and the image of the resist pattern, and one- or two-dimensional geometrical features representing differences between the design pattern and the resist pattern are calculated. In some cases, the shape of the resist pattern differs greatly from the design pattern due to OPE effect (optical proximity effect). To superpose the design data and the measured data on the resist pattern stably and accurately, an exposure simulator calculates a simulated pattern on the basis of photomask data on a photomask for an exposure process and exposure conditions and superposes the simulated pattern and the image of the resist pattern.