Patent Number: 
Section: claims

1. A method for use in a lithography process, comprising:providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid;converting the IC layout design GDS grid to a first exposure grid;applying a non-directional dither technique to the first exposure grid;applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid;applying non-directional dithers to the grid-shifted exposure grid; andafter applying the non-directional dither technique to the first exposure grid and after applying non-directional dithers to the grid-shifted exposure grid, adding, by a computer, the first exposure grid to the grid-shifted exposure grid to generate a second exposure grid. 2. The method of claim 1, wherein the first exposure grid is formed by a two-dimensional array of pixels, and wherein the pixel size is selected to be larger than the pixel size of the IC layout design grid. 3. The method of claim 1, wherein the non-directional dithers include dithering along a first direction. 4. The method of claim 1, wherein the non-directional dithers include dithering along a second direction. 5. The method of claim 1, wherein multiple non-directional dithers are applied to the first exposure grid. 6. The method of claim 1, wherein Floyd-Steinberg dithering is applied to the first exposure grid. 7. The method of claim 1, wherein multiple grid shifts are applied to the first exposure grid. 8. The method of claim 1, wherein the grid shift comprises shifting along a first direction. 9. The method of claim 1, wherein the grid shift comprises shifting along a second direction. 10. The method of claim 1, wherein the grid shift comprises shifting along two directions. 11. The method of claim 1, wherein a direction of the grid shift is independent of a direction of dithering. 12. A method for providing a modified exposure grid, comprising:providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid;converting the IC design layout GDS grid to a first exposure grid and using k bits for a grey level;dithering the first exposure grid and using less than k bits for grey level;applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and using less than k bits for grey level and applying a dither to the grid-shifted exposure grid; andafter dithering the first exposure grid and after applying the dither to the grid-shifted exposure grid, adding, by a computer, the first exposure grid to the grid-shifted exposure grid to generate a modified exposure grid. 13. The method of claim 12, wherein after dithering the first exposure grid the first exposure grid uses k−1 bits for a grey level. 14. The method of claim 12, wherein after dithering the first exposure grid the pixel size of the first exposure grid is not larger than the first exposure grid. 15. The method of claim 12, wherein after applying the dither to the grid-shifted exposure grid the grid-shifted exposure grid uses k−1 bits for a grey level. 16. The method of claim 12, wherein after applying the dither to the grid-shifted exposure grid the pixel size of the grid-shifted exposure grid is less than the first exposure grid. 17. The method of claim 12, wherein the pixel size of the modified exposure grid is less than the first exposure grid. 18. The method of claim 12, further comprising performing multiple non-directional dithers to the first exposure grid. 19. The method of claim 12, further comprising performing multiple grid shifts to the first exposure grid. 20. A method of providing a grid for use in a lithography process, comprising:providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid with a plurality of polygons in a two-dimensional array of pixels coordinate system;applying a proximity correction process to the IC layout design GDS grid;converting the IC layout design GDS grid to a first exposure grid with a plurality of polygons in a two-dimensional array of pixels coordinate system, using a pixel size larger than the IC layout design GDS grid, and using k bits for a grey level;applying dithering to the first exposure grid, wherein after applying dithering to the first exposure grid the first exposure grid uses less than k bits for a grey level;applying a grid shift to the first exposure grid, wherein the grid-shifted exposure grid uses less than k bits for a grey level and applying dither to the grid-shifted exposure grid; andafter applying the dithering to the first exposure grid and after applying the dither to the grid-shifted exposure grid, adding, by a computer, the first exposure grid to the grid-shifted exposure grid to generate a second exposure grid, wherein the second exposure grid contains a same or less data volume than the first exposure grid.