Patent Number: 
Section: description

FIG. 1A is a cross-sectional view of a first in-process structure 100 (transistor-precursor structure 100) that may occur during mass-production of integrated circuits. Precursor structure 100 may be arrived at as follows. A lightly-doped (e.g., Pxe2x88x92) semiconductor substrate 110 such as one formed of monocrystalline silicon or another suitable material is provided. A thin layer of gate-insulating oxide (GoX) or of another suitable material is thermally grown or otherwise formed on the substrate 110. A gate-forming material such as polycrystalline silicon or another suitable material is deposited by CVD process or by other means to define a gate-precursor layer 114 (e.g., poly-1 ) on top of the GoX layer 112. An anti-reflective coating (ARC) such as made of an oxynitride (ON) material 116 may be provided on the gate layer 114. Photoresist (PR) is deposited on the resulting precursor structure. Photo-lithographically or like feature-defining methods are used to pattern and develop PR features such as 119 to have initial dimensions such as the illustrated first length, L1. Because of limitations in photolithographic or other feature-defining processes, there is typically a constraint on how small the first dimension L1 may be. For example, in one process the desired or target value for L1 may be limited to being no smaller than about 200 nanometers (0.200xcexc). A first metrology step 121 may be carried out to measure the actual L1 dimension of plural production samples and to produce a corresponding DICD1 or ADICD1 (After-Development Inspection of Critical Dimension) measurement value. Isotropic etching of selected ones or all of the patterned PR layer features is typically employed to trim the anisotropically-etched photoresist 119 to sub-lithography dimensions. In FIG. 1A, the originally patterned photoresist is shown as dashed outline 119 with the corresponding first length dimension, L1, while the post-trim photoresist is shown as hatched block 118 with a corresponding second length dimension, L2 (where L2 less than L1). In one exemplary process the desired or target value for L2 may be about 140 nanometers (0.140xcexc). A second metrology step 122 may be used to measure the L2 dimension of plural production samples and to produce a corresponding DICD2 or ADICD2 measurement value. One or the other of metrology steps 121 and 122 may be bypassed if desired, or both may be carried out. Referring to FIG. 2, either or both of the pre-trim DICD1 measurement value and the post-trim DICD2 measurement value may be obtained as follows. After the respective formation of the pre-trim, anisotropically-etched photoresist feature 119 or the post-trim, isotropically-etched photoresist feature 118, samples of the dice, wafers or other mass-produced articles in which precursor structure 100 is repeatedly found are sent to a respective metrology station (schematically shown as 121 and 122 respectively) for measurement and determination of the average per-wafer and/or per wafer-lot values of the respective length dimension, L1 or L2, and of its statistical distribution at various points of the wafer (e.g., a 9-point star test) and across the respective production lot. Such measurement and calculation steps provide the corresponding DICD or ADICD measurement values. If the per-wafer, measured average value, LM of the pre/post-trim dimension, L1/L2 and its distribution closely match a respective target value, L1T or L2T, then the PR trim process is left as is and further batches of wafers are trimmed with the same PR-trim settings. For each wafer or other sample, there will typically be a manufacturing tolerance error that may be expressed as, eGatePR=LPRTxe2x88x92ADICD, where LPRT represents the desired or target value for the developed photoresist (either before or after PR trimming process respectively depending on whether ADICD represents measurement of the L1 or the L2 dimension). The group of fabrication personnel who are responsible for keeping the respective pre-trim or post-trim PR length (ADICD) close to the established ideal or target value (L1T or L2T), will typically define an allowed tolerance-range, e1xe2x80x2xe2x89xa6eGatePRxe2x89xa6e2xe2x80x2 (where e1xe2x80x2 is typically less than zero while e2xe2x80x2 is greater than zero). Nonconforming, post-trim wafers may have to be thrown away. In the above, exemplary process where L2 is about 0.140 xcexcm, e1xe2x80x2 may be xe2x88x920.015 xcexcm for example while e2xe2x80x2 may be +0.010 xcexcm. During mass-production, a situation may arise (as already alluded to above) where relatively large numbers of wafers begin to slip outside the predefined, allowed tolerance-range, e1xe2x80x2xe2x89xa6eGatePRxe2x89xa6e2xe2x80x2. In other words, the measured critical dimension values begin to slip away from closely matching the target, L1T or L2T, value. This could indicate that some parameter of the PR-development process might be slipping and that it may be desirable to fine-tune the PR-trimming process in order to compensate for the slippage. On the other hand, it could be a random statistical coincidence. The safest parameter to play with (if any process parameter is to be tuned at all) is the isotropic etch time which converts pre-trim feature 119 into post-trim feature 118. FIG. 2 illustrates a plot of trim-distance (etch depth) versus trim-time for a well-defined (well-characterized), first trim process 205. Under normal circumstances, with the PR etch time set at the nominal value, say t0, the average ADICD1 measurement of the pre-trim PR features 119 should come back with a measured feature length of LM being very close or equal to the target length, L1T (that is, LM=L1T) The corresponding, next PR trim time that will be used to convert a next, on-target, pre-trim feature 119 to an on-target, post-trim feature 118 having target length, L2Twill be the same PR trim time of t0 as is indicated in FIG. 2 by the notation, Next=t0. However, sometimes the measured feature length, L1M of metrology step 121 can be measurably, but not substantially, below the targeted etch length, L1T, such as indicated in the drawing by LMa=L1Txe2x88x92xcex94A where xcex94A is a relatively small, but still out of tolerance, positive perturbation. As one or more wafers begin to exhibit the new measured length, LMa, the PR trim process may be predictably fine-tuned by decreasing the PR trim time slightly as indicated on the time line by the notation Next=t0xe2x88x92xcex941. PR trim distance should then decrease slightly as predicted by the well-defined, distance versus time curve 205 and this should bring the post-trim feature length, L2 of such wafers back into the allowed tolerance-range, e1xe2x80x2xe2x89xa6eGatePRxe2x89xa6e2xe2x80x2. In other words, after such fine tuning, the average ADICD2 should again be very close to or exactly equal to the target length, L2T. It should be noted in passing that, although the immediately above and below discussions assume that the ADICD1 metrology step (121) is being used to control the PR trim time on a feed-forward basis, it is possible to alternatively or additionally use the ADICD2 metrology step (122) for controlling the PR trim time on a feed-back basis. An advantage of using the described, feed-forward approach (wherein the ADICD1 metrology step, 121 controls PR trim time of same product) is that over-etched product (samples where L1 is below target) do not have to be discarded. In counter to this, an advantage of using the feed-back approach (wherein the ADICD2 metrology step, 122 controls the PR trim time for subsequent product) is that a tighter control over dimensions may be obtained because actual results, after PR trim, are being measured instead of relying on pre-trim measurements. The feedforward control system (which relies on 121 for controlling PR trim time) is an open-loop and thus predictive approach. However, a disadvantage of using the feed-back approach (where ADICD2 controls PR trim time), at least in conventional processes, is that over-trimmed product (samples where L2 is below target value L2T) have to be discarded because one cannot un-do an excessive trim. One can only further trim, a still-undertrimmed feature. The present invention contemplates using either approach or a combination of both. Continuing with the explanation of FIG. 2, if the measured feature length, LM of a significant number of wafers begins to slip towards a new mean that is above the allowed tolerance-range, e1xe2x80x2xe2x89xa6eGatePRxe2x89xa6e2xe2x80x2, but not substantially above the target length, such as indicated by LMb=L1T+xcex94B, where xcex94B is a relatively small and positive perturbation, then the ensuing PR trim time may be automatically fine-tuned as indicated on the time line by Next=t0+xcex942, where xcex942 is positive. After such fine tuning, the post-trim, ADICD2 value (L2) should return to being again very close to or exactly equal to the target post-trim length, L2T. Let""s say, however, that at some point in time the measured, pre-trim length values, LM start coming in as being drastically larger than the target length, such as indicated by LMc=L1T+xcex94C, where xcex94C is a relatively much larger, positive deviation than are each of the fine-tunable deviations represented by xcex94A and xcex94B. In such a case, curve 205 may no longer provide an accurate prediction for what results are to be expected under the current state of the PR trimming equipment. If PR trim time is changed dramatically, the process can become highly nonlinear. In other words, if users begin to push the process outside the linearly predictive part of curve 205, the actual results may not conform with what the curve 205 predicts. There may be no well-defined amount of increase in trim time (e.g., Next=t0+xcex943; not shown) that can assuredly return production results back to the desired, mean target value, L2T when the LMc=L1T+xcex94C situation is encountered. Alternatively, the curve-dictated increase in trim time (e.g., Next=t0+xcex943) may be too large to be acceptable for meeting production schedules. Process technicians may elect in such a situation to switch to a different PR trim process such as second process 207. However, the second trim process 207 may be one that has not been well characterized. Its results may therefore not be accurately predictable. This may throw automated control out of a stable region of operation. Also, if the new process 207 is a more energetic one than the better-defined, process 205, fabrication uniformity may change drastically by shifting to the more energetic process 207. Nonetheless, this is something that is sometimes done in order to meet production schedules. Human technicians may well make correct, non-automated decisions in the short run. However, experience shows that over the long haul, process technicians will eventually make a human judgment error and choose a wrong one of a set of poorly-defined trim processes such as 207. Yields may then suffer drastically and thereby bring about an outcome that is the exact opposite of what the technicians wanted, namely to minimize process error. There is need for a better approach. Preferably this better approach is one that is automated so that human judgment error does not participate as a controlling factor. The above discussions concerning the tuning of PR trim time in response to ADICD measurements is just an introduction to a problem of bigger scope. That scope will be expanded on, shortly. However, before we continue along that path, it is worthwhile to understand the remainder of a transistor-forming process that conforms with the present invention. FIG. 1B shows a cross-sectional view of a subsequent, transistor-precursor structure 120 that is derived from structure 100 (FIG. 1A). In the time frame of FIG. 1B, the trimmed PR block 118 has been used as an initial mask for etching ARC layer 116 to thereby define a hard mask region 126. Subsequent anisotropic etching has produced the post-etch, polysilicon gate structure 124, as shown. This gate structure 124 has a length L2xe2x80x2 which should be equal to or relatively close to a corresponding and pre-defined, post-etch target length L2xe2x80x2T if the anisotropic etch has proceeded in a predicted manner. One way that the L2xe2x80x2 dimension can be made to statistically track the pre-defined, target length L2xe2x80x2T is by using the PR trim tuning method shown in FIG. 2 and by throwing away those nonconforming wafers that cannot be corrected with just the use of PR trim tuning. In other words, we discard those of the pre-trim or post-trim wafers whose respective ADICD1 or ADICD2 error is outside the fine-tunable range, e1xe2x80x2xe2x89xa6eGatePRxe2x89xa6e2xe2x80x2.  Similar to the way that samples of the first transistor-precursor structure 100 were sent to the first and/or second metrology stations (121 and 122 respectively); and similar to the way that nonconforming, unreworkable wafers were discarded; samples of the second transistor-precursor structure 120 are typically sent to a third metrology station 123. This third metrology station 123 may be dedicated to optically measuring the L2xe2x80x2 dimension of gate sub-structure 124. A determination is made of the average per-wafer and/or per wafer-lot values of the post-etch, length dimension, L2xe2x80x2 and of its statistical distribution at various points of the post-etch wafers (e.g., a 9-point star test) and across the respective production lot. Such measurement and calculation steps are sometimes referred to as FICD (Final Inspection measurement of Critical Dimension). As with the case of ADICD, an allowed tolerance-range, e3xe2x89xa6eGatexe2x89xa6e4 is defined for the FICD results. Nonconforming, post-etch wafers are thrown away. Variations in L2xe2x80x2 due to mask undercutting (if there is any) can be compensated for in a manner similar to that explained for FIG. 2. Feedback control from the FICD measurement step 123 can be used to further tweak the PR trim time (tNextxe2x80x2=tNextxc2x1xcex94=t0xc2x1xcex941/2xc2x1xcex943/4) of FIG. 2. FIG. 1C shows a cross-sectional view of a subsequent, third transistor-precursor structure 130 derived from in-process structure 120 (FIG. 1B). Here, a film has been deposited with a film thickness of Fw. The film may be composed of a spacer material such as an oxide or an oxynitride and it is typically, conformably deposited as layer 132 over the top and sides of the etched gate structure 124. Deposition thickness, Fw, is a controllable variable whose value is predictively set prior to the actual deposition. As with all mass-production operations, the actual deposition thickness may vary from the target thickness on a sample by sample basis. The total lateral length of gate structure 124 plus the sidewall portions of film 132 is denoted as L3. FIG. 1D shows a subsequent, fourth transistor-precursor structure (product-in-process form) 140 derived from in-process structure 130. Here, the initial spacer material film 132 has been anisotropically etched-down to remove its laterally-extending portions. The vertically-extending portions of the spacer material remain and thereby define, a set of trimmed spacer sidewalls 144 along the sides of gate sub-structure 124. The overall length of gate 124 and the trimmed spacers 144 is denoted as L3xe2x80x2. The post-trim width of each of the sidewall spacers is denoted as Sw. The term xe2x80x9ctrimmedxe2x80x9d as applied here to the spacer sidewalls 144 is understood to encompass a fine-tuning adjustment to one or both of the initially-set, deposition thickness, Fw (FIG. 1C) and to the anisotropic etch time (FIG. 1D). Fine-tuning of the spacer sidewall thickness is preferably controlled primarily with fine-tuning of the initial deposition thickness, Fw because this is easier and less costly to control than modifying the anisotropic etch that leaves behind the spacer sidewalls 144. However, it is within the contemplation of the present invention use either one or a combination of both the initial deposition thickness (Fw) and the side-wall trim as process variables that may be fine-tuned. After the spacer formation and trimming process is completed, samples of the fourth transistor-precursor structure 140 are sent to a fourth metrology station 125. This fourth metrology station 125 may be dedicated to optically measuring the thickness dimension, SwM of each of sidewalls 144. A determination is made of the average per-wafer and/or per wafer-lot values of the measured, post-etch, measured sidewall thickness dimension, SwM and of its statistical distribution at various points of the post-etch wafers (e.g., by way of a 9-point star test) and across the respective production lot. As with the case of the ADICD and/or FICD measurements, an allowed mass-production tolerance-range, e5xe2x89xa6eSidewallxe2x89xa6e6 is predefined for the SwM results, where eSidewall=SwMxe2x88x92SwT and SwT is a predefined target value about which the measurements should closely center and e5 is typically less than zero while e6 is greater than zero. Nonconforming, post-etch wafers may be thrown away if over-etched, or returned for further etching (re-work) if under-etched. Although the measured sidewall thickness dimension, SwM is preferably defined by measurements taken after deposition layer 132 is trimmed, it is within the contemplation of the invention to define the measured sidewall thickness dimension, SwM as being determined instead by measuring the pre-trim thickness FW of deposition layer 132 or as being determined by combining pre-trim and post trim measurements for the sidewalls 144 as may be appropriate. Variations over time in the returned values of SwM due to process slip (if there is any) can be compensated for in a manner similar to that explained for FIG. 2, but this time, preferably using the initial deposition thickness, Fw as a feedback, tuning control. Alternatively, or additionally, the post deposition trim time for the sidewalls may be tuned. FIG. 1E shows a next state 150 of the in-process structure wherein Tilted Channel Implant (TCI) is performed to thereby define a gradient (P, Pxe2x80x2,Pxe2x80x3) of channel doping density within regions where source and drain regions will abut into transistor channel regions. The PN junctions that will form between the channel and the source/drain regions, will be defined later. The characteristics of these PN junctions (including depth and lateral position) will be determined in part by the locus of the TCI-created, channel doping. More specifically, after thermal diffusion, there will be points inside the substrate where the TCI-created, density of P dopants balances equally against the source/drain doping density of implanted N dopants. In other words the points that satisfy N=P in terms of doping density will define the neutral center of the PN junction as shown at 157 in FIG. 1F). The Tilted Channel Implant (TCI) may be carried out by aiming implant beams at a tilted angle towards the combined gate structure 124 and trimmed sidewall spacers 144. The TCI process may also be masked by an added, photoresist mask 145. FIG. 1E shows a TCI doping source 152 applying tilted ion beams such as 153 and 154 to the structure. It is understood that the TCI implant operation will usually rotate either in steps or uniformly about the Z axis (vertical axis). In one embodiment, the rotations are in equal steps of between 45 degrees to 90 degrees thereby respectively providing between 8 to 4 equal rotations. The uniform or stepped rotations provide a generally uniform distribution of dopants in areas that are not shaded by features such as gate 124 and its sidewalls 144 (or mask 145). It is known in the art that a so-called xe2x80x98halo effectxe2x80x99 will develop in the shaded regions of the gate 124 and sidewalls 144. At a relatively large lateral distance out and away from the center of the spacer/gate/spacer structure 144/124/144, the dopant implant concentration will be relatively large (P) due to symmetrical contribution by unshaded beams such as 153 from all angles. At relatively smaller lateral distances from the center of structure 144/124/144, the implant concentration will be relatively moderate (Pxe2x80x2) due to some shadowing effect being provided by the upwardly projecting, gate/sidewalls structure 124/144. At yet a smaller lateral distance, the ion doping contribution will be relatively even smaller (Pxe2x80x3) and shallower because the only ion beams that manage to get to such under-the-gate locations are those tilted beams such as 154 which pass through a lower portion of sidewall 144. Sidewall 144 behaves as sort of a soft sponge that absorbs some of the ions and reduces the energy, and thus reduces the density and the depth of penetration of those ions (Pxe2x80x3) that get through. As for the channel doping that will develop under the center of gate/sidewalls structure 144/124/144, the gate structure 124 may act as a hard mask that blocks substantially all or part of the TCI doping beams 153-154 from getting through to the underlying, middle part of the channel region. Such a partial or full shading effect may leave the central part of the channel with essentially only the initial, Pxe2x88x92 density that was present in the initial substrate. (Of course, doping superposition variations on this basic approach are within the contemplation of the invention.) From the above it is seen that a halo-effect doping gradient may be produced in the channel. Under the very center of the gate/sidewalls structure 144/124/144, the ion doping contribution by the TCI operation will be essentially absent and the roughly middle part of the channel will thus retain the initial Pxe2x88x92 concentration that it had before the TCI operation (or a superposition of such with other doping processes). In one embodiment, the initial, Pxe2x88x92 density is about 1E15 (or 1015) doping atoms per cm3 while the heavier P density that is provided by the TCI operation is about 1E18/cm3. The heavier P density tapers down through successive intermediate levels, Pxe2x80x2 and Pxe2x80x3 down to the lower Pxe2x88x92 density as one moves laterally from outside and toward the center of the shadow cast by the spacer/gate/spacer structure 144/124/144. This halo-distributed, channel doping gradient is represented schematically at 155 in FIG. 1E. N-type dopants for forming the source/drain regions may be implanted before and/or after the Tilted Channel Implant 153/154. In one embodiment, a shallow, first N implant is performed before sidewalls 144 are formed to thereby define a shallow, inner part 156a of the source/drain regions 156/156xe2x80x2. In the same embodiment, a deeper, second N implant is performed after sidewalls 144 are formed to thereby define a deeper, outer part 156b of the source/drain regions. Typically, the gate structure 124 will acquire a heavy N+ doping from the ions it intercepts during the source/drain dopant implants. The top of the gate structure 124 may be masked (not shown) during the TCI operation. A schematic of the resulting source and/or drain profiles is shown at 156 and 156xe2x80x2 of FIG. 1F. The PN junction 157 that outlines the profile is understood to be the locus of points in which P-type doping balances out with N-type doping. The locations of such P=N balance points can be shifted inwardly (towards the center of spacer/gate/spacer structure 144/124/144) or outwardly depending on how the Pxe2x80x3Pxe2x80x2P gradient 155 is shaped and located and depending on how the N-type source/drain implants are carried out and how all dopants are diffused by thermal process. The illustrated source and drain regions 156 and 156xe2x80x2 in FIG. 1F provide an effective channel length, Leff therebetween. The dimension of this effective channel length, Leff is a function of both the TCI process and the N-type source/drain implants and a subsequent thermal annealing process that diffuses the implanted ions according to predefined diffusion characteristics. There may be a slight overlap Lov between the outer vertical walls of the gate 124 and the ends of the source and drain regions. This overlap defines an undesirable parasitic capacitance known as Cov. During rapid switching of gate-to-source voltage, VGS, the parasitic capacitance, Cov needs to be charged or discharged in order to bring the effective gate-to-source voltage above or below the transistor""s threshold level, VT. In general, large values for the parasitic capacitance, Cov are undesirable because they tend to slow down switching speed and/or increase power consumption. In summary, it is seen from the illustrated sequential process steps of FIGS. 1A-1E how certain critical dimensions such as, L2xe2x80x2+Sw=L3xe2x80x2, may determine the ultimate effective length Leff of the transistor. It is understood in the art that Leff is critical to defining many parameters of transistor behavior including switching speed and the transistor""s threshold voltage, VT. The profile and doping concentration gradients in regions 155 and 156a/b are also responsible for defining threshold voltage VT. The total amount of charge that may be stored in the surface region of the channel is determined by the net density of P-type doping atoms provided in this region and by the surface-length limiting effects of the source and drain regions 156/156xe2x80x2 which have a countering amount of net N-type doping atoms provided therein. FIG. 3 shows an automated fabrication system 300 in accordance with the invention. Fabrication system 300 includes one or more data collecting computers 301 that collect and thereafter optionally transform (via computational steps) process-related data, including metrology data that defines measured values, L2M and SwM or corresponding other measured values relating to gate length and sidewall thickness. Fabrication system 300 further includes one or more process flow control computers 302 that track in-process wafers and define the targeted process dimensions or other attributes that are to be imparted to the wafers during different parts of the fabrication flow sequence. The process flow control computer(s) 302 therefore generally define the target values, L2T and SwT or corresponding other target values relating to gate length and sidewall thickness. Fabrication system 300 yet further includes one or more implant control computers 303 that communicate with one or both of the process flow control computer(s) 302 and the data collecting/processing computer(s) 301. Computer(s) 301 and 302 are usually interlinked with one another as well as with implant control computer(s) 303 by way of a communications network. A fabrication control process 360, that will be shortly described, may be implemented by way of software and/or hardware either fully in one, or distributively among, computers 301, 302 and 303. It is within the contemplation of the invention to use general-purpose, and/or special-purpose computers that are re-configured or programmed with appropriate software to perform the herein-described functions. The re-configuring or programming of the computer(s) may be carried with use of one or both of computer-readable media (e.g., a CD-ROM or floppy diskette) 305 and network-downloaded signals 306, where the media 305 and/or signals 306 convey software instructions to respectively targeted computing machines for causing any one or more of such computer(s) 301-303 to become configured or programmed to perform part or all of the TCI feedforward control operations (360) described herein. As shown, fabrication system 300 comprises a variable TCI beam source 352 that is operatively and automatically controlled by implant control computer(s) 303. The variable TCI beam source 352 has at least one, and preferably both of variable energy and variable dosage capabilities. The variable energy and dosage controls of source 352 are denoted as Energya and Doseb and these are controllable by implant control computer(s) 303. Signals 362 and 364 that respectively represent manufacturing tolerance errors in gate length (eGate) and sidewall thickness (eSw) are fed forward from their respective calculating means (361, 363) to the TCI control computer(s) 303. In one embodiment, eGate is defined as target length L2T (which could be either the PR trim target length or the post-etch gate target length or a combination of both) minus the measured PR length L2M (which could be either DICD or FICD or a combination of both). In the same or an alternate embodiment, eSw is defined as measured sidewall thickness SwM minus target thickness SwT. The measured values can be directly measured ones or values that are derived as statistically fair representatives of what is happening in their respective PR-trimming, gate-etching or sidewall film-deposition or sidewall etching/trimming processes. The energy and/or dosage values used in the TCI process (352) are manually or automatically adjusted for each respective product in response to the received one or both of error signals 362 (eGate) and 364 (eSw). The preferred modality is for automatic (machine-implemented) adjustment because that removes the possibility of human error from the process. The energy and/or dosage values provide additional controllable variables which can be automatically tuned in accordance with the invention to counter manufacturing tolerance errors as will be explained shortly. Such feed forward means may be used in accordance with the invention for improving mass-production statistical distribution of critical parameters in semiconductor devices. Consider first the case where error signals 362 (eGate) and 364 (eSw) are both zero. For this case, there will be a specific and predefined set of default values (experimentally pre-established) for controllable variables, Energya and Doseb of source 352 as are to be applied for a respective product (e.g., a microprocessor chip or a memory chip). Let us call these, E0 and D0 respectively. Source/drain region 356 will have a corresponding, first doping distribution profile as represented by first junction outline 356a. It is understood that repeated electrical testing of final product statistics in the mass-production line has been performed beforehand to demonstrate that the default energy and dosage values, E0 and D0 are the essentially optimal ones for the given product in the case where the measured ADICD, FICD and sidewall thickness values are essentially on target. Consider next the case where error signal 364 (eSw) is positive while signal 362 (eGate) is zero. That implies that the measured sidewall thickness SwM is greater than the desired (target) thickness. If the TCI doping operation continues to use the default energy and dosage values, E0 and D0, the measurement-detected, excess thickness of the sidewall 144 will effectively pull the Pxe2x88x92Pxe2x80x2xe2x88x92Pxe2x80x3 outline 355 laterally outward, away from the center of the gate. Because of this, the outline of doping profile 356 will also shift laterally back from ideal position 356a to a further-back position 356b on each side of the gate. That works to undesirably increase Leff. Suppose, however that we now increase controllable variable Energya to a value greater than the default dosage value, E0. The amount of increase can be adjusted to push the Pxe2x88x92Pxe2x80x2xe2x88x92Pxe2x80x3 outline 355 deeper into the substrate so the outline 355 essentially returns to its ideal position. As a result, PN junction outline 356b is also pushed deeper into the substrate so the PN junction outline essentially returns to the ideal outline position 356a. Leff is then decreased back to its ideal value and mass-production may continue without suffering from the ill effects that the positive sidewall error (364) would have otherwise caused. In one embodiment, the amount of adjustment of fine tuning to the TCI energy value is automated and given by a linear or quasi-linear interpolation equation of the following form: Energya=E0*(1+xcex2*eSw/SwT)xe2x80x83xe2x80x83{Eq. 2}. In the above equation, Eq. 2, the multiplying factor, xcex2 may either be a constant or a function of a prespecified windowing range of the normalized error, eSw/SwT. In one embodiment, where P-channel devices (PNP FET""s) are being fabricated, the multiplying factor, xcex2 is defined as one or more constant values selected from the range, 0.02xe2x89xa6xcex2xe2x89xa60.20 where the selected value or values may depend on the sign and/or magnitude of eSw/SwT. In a second embodiment, where again P-channel devices are being fabricated, the multiplying factor, xcex2 is defined as one or more values selected from the range, 0.05xe2x89xa6xcex2xe2x89xa60.15 where the selected value depends on the sign of eSw/SwT. The multiplying factor, xcex2 may be derived from an empirical experience curve 450 such as shown in FIG. 4A which has one, two, or more empirically-obtained prediction points (e.g., EH, EL). Tests may be conducted to discover at least one, higher level of implant energy, EH which is statistically significant and useful for bringing electrical characteristics of manufactured devices back to the targeted characteristics in cases where the measured side wall thickness, SwM is larger than the desired or target thickness SwT by a given amount. For example, if the targeted thickness for the side walls is 400 xc3x85 in order to achieve the desired targeted electrical characteristics, a plurality of experiments may reveal that higher implant energy level, EH is useful for achieving the same electrical characteristics in cases where the side wall thickness is found by measurement to be the higher value of say SwMH=600 xc3x85. Such experiments and empirical findings may be carried out for a number of different points on experience curve 450. Then, one or more linear, or other kinds of interpolations may be used for calculating to an appropriately-close level of approximation, the desired higher energy levels for other amounts of positive thickness error, eSw. Straight line 451 in the magnified explosion, for example, shows how one such linear interpolation may be carried out for errors that lie between the experimentally-validated values for energy levels in the windowing range of E0 to EH or above. Returning to FIG. 3, suppose now that the sidewall error signal, eSw (364) is negative, thereby indicating that the measured sidewall thickness is less than the target or desired sidewall thickness. If this is so, the nominal implant energy E0 will be too high and will push the TCI doping implant Pxe2x88x92Pxe2x80x2xe2x88x92Pxe2x80x3 355 too deep into the substrate. As a consequence, the resulting PN junction profile 356c will be too deep. The solution, in accordance with the invention, is to reduce the implant energy level to a lower value such as, EL. Again, the experience curve 450 is used to validate with empirical measurements what one or more values of lower implant energy such as EL reproduce the electrical characteristics that are also found in devices whose sidewall thickness is at the nominal or targeted value of SwT. Straight line 452 in the magnification explosion shows how linear interpolation may be used to calculate a substantially close approximation of the correction values for the implant energy in cases where the error is other than those which are validated with corresponding experiments. Note that different slopes can appear for the linear interpolation lines, 451 and 452 that extend from the ideal or default point, (E0, SwT). Accordingly, the sign of the eSw error signal (364) may be used as a windowing parameter to determine which of interpolation lines, 451 and 452 is to be used. Other windowing determinants may be used additionally or alternatively as various situations may dictate. The multiplying factor, xcex2 of Eq. 2 may therefore be kept as a positive value whose magnitude changes in response to the sign of the eSw error signal. The sign of the eSw error signal determines automatically whether the TCI implant energy, Ea is to be increased or decreased in accordance with one embodiment of the above explanation. Referring again to FIG. 3, consider now a case where the measured gate length L2M is smaller than the desired or targeted length L2T even though the sidewall thickness is on target (eSw=0). The depth of the TCI process will be accurate relative to the sidewall edges of the gate 124. However, the effective gate length, Leff of the transistor will be too short. To counter this effect, the dosage Doseb of the Tilted Channel Implant should be increased to thereby effectively push the location of the Pxe2x88x92Pxe2x80x2xe2x88x92Pxe2x80x3 outline 355 laterally out and away from the center of the gate 124. The effect of this will be to also push the P=N junction 356a laterally outward so that the desired effective gate length, Leff is realized even though the gate dimension, L2M was below target (L2M less than L2T) In one embodiment, the following, interpolating correction formula (Eq. 3) is used: Dosea=Dose0*(1+xcex1(L2Txe2x88x92L2M)/L2T)xe2x80x83xe2x80x83{Eq. 3} Multiplying factor a is positive and causes the actual TCI dosage to increase above ideal value, Dose0 if L2M is found to be below target (L2M less than L2T). On the other hand, if L2M is found to be above its target value (L2M greater than L2T), then the action of a control mechanism acting according Eq. 3 will be to decrease the actual TCI dosage to a value less than the ideal value, Dose0. This will work to pull the P=N junction 356a laterally inward so that the desired effective gate length, Leff is realized even though the gate dimension, L2M was above target (L2M greater than L2T). In one embodiment, where P-channel devices (PNP FET""s) are being fabricated, the Eq. 3 multiplying factor, xcex1 is defined as one or more constant values selected from the range, 0.05xe2x89xa6xcex1xe2x89xa60.15 where the selected value or values may depend on the sign and/or windowed magnitude of eGate/L2T. In a second embodiment, where again P-channel devices are being fabricated, the Eq. 3 multiplying factor, xcex1 is defined as one or more values selected about the range of xcex1 being approximately 0.10, where the selected value depends on the sign and/or magnitude of eGate/L2T. The Eq. 3 multiplying factor, xcex1 may be derived from an experience curve 460 such as shown in FIG. 4B. Tests should be conducted to discover what higher or lower level of implant dosage, Dosea is statistically significant and useful for bringing electrical characteristics of manufactured devices back to the targeted characteristics in cases where the measured gate length dimension, L2M is different from the desired or target length, L2T by a respectively given amount. For example, if the targeted thickness for the gate 124 is L2T, a desired or targeted electrical characteristic of the transistor such as threshold voltage, VTT may be predefined, where the latter is associated with a corresponding channel surface charge QTT. A plurality of experiments may reveal that higher implant dose level, DH is useful for achieving the same electrical characteristics in cases where the gate length, L2Ma is found by measurement to be lower than the targeted length, L2T by a given amount. The comparatively higher TCI dosage, DH brings the net surface charge in the channel back to target level, QTT. Such experiments and empirical findings may be carried out for a number of different points on experience curve 460. Then, one or more linear interpolations may be used for calculating the desired higher energy levels for other amounts of positive gate length error, eGate=L2Txe2x88x92L2M. Straight lines such as 451 in the magnified explosion of earlier FIG. 4A may be used to provide interpolation for errors that lie between the experimentally-validated values for Dosage levels D0 and DH. Similarly, if the gate length error, eGate=L2Txe2x88x92L2M is instead negative, thereby indicating that the measured length is greater than the target length, lower TCI dosage such as DL may be found by way of experimental validation to be the amount that brings net channel charge (and thus VThresh) to the target value (QTT or VTT respectively). Again, straight lines such as 452 in the magnified explosion of earlier FIG. 4A may be used to provide interpolation for errors that lie between the experimentally-validated values for Dosage levels D0 and DL. The characterizing curve for the electrical characteristic that is being controlled (e.g., VThresh) does not have to be monotonically rising such as shown by exemplary curve 460. It may instead be hump-shaped such as shown by exemplary curve 470 or even more complex. The Eq. 3 multiplying factor, xcex1 should of course be selected according to the nature of the characterizing curve, 460 or 470 rather than just blindly according to whether the gate length error, eGate=L2Txe2x88x92L2M is positive or negative. Windowing determinators may be used to select the correct linear, or other interpolating equation for each respective section of an experience curve such as 460 or 470. FIGS. 5A-5B provide a process flow chart for a manually and/or machine-implemented process 500 that includes the carrying out of TCI feedforward correction in accordance with the invention. It is presumed that, without the presence of such TCI feedforward correction, that there will be certain, not-yet-expanded and respective, ranges of allowed error for one or more of the PR trim processes (see FIG. 1A), for the gate layer etch (see FIG. 1B), for the sidewall deposition process (see FIG. 1C), and for the sidewall etch/trim processes (see FIG. 1D). Embodiments in accordance with the invention do not necessarily carry out all of the steps or expansions of respective, ranges of allowed error as described in the following. It is illustrated by way of respective operations 510, 520, 530 and 540, that respective tolerable errors can be expanded somewhat for one or more of the PR trim processes (steps 512-514), for the gate layer etch processes (steps 522-524), for the sidewall deposition process (steps 532-534), and for the sidewall etch/trim processes (steps 542-544) because of the counter compensating adjustments that are made to TCI energy and/or dosage in the more downstream step 552. The respective expansions of tolerable error range for each of the out-of-range error tests in FIGS. 5A-5B, namely for tests 514, 524, 534 and 544, can mean that more wafers pass each such test and ultimate yield increases as compared to a like process that does not have feedforward compensation in the TCI step. It is therefore the feedforward compensation in TCI adjustment step 550 that allows the expansion of the error ranges and the increased yield of within-specification devices. More specifically, in the first and optional, error range expansion step 510, a comparatively expanded error range, e1xe2x80x3xe2x89xa6eGatePRxe2x89xa6e2xe2x80x3 is established where e1xe2x80x3 less than e1xe2x80x2 and/or e2xe2x80x3 greater than e2xe2x80x2 and where e1xe2x80x2 and e2xe2x80x2 are the error limits used (typically the first one being negative and the second positive) if TCI feedforward adjustment step 550 is bypassed. Next, in step 512, the photoresist (PR) patterning and trimming processes are performed and a corresponding DICD1 and/or DICD2 measurement is taken. See FIG. 1A. In test step 514, it is determined whether one or more of the ADICD errors is outside of its respective and allowed tolerance range. If the answer is YES, then the out-of-range wafer (or lot of wafers) may be discarded as indicated by step 517. Optional decision step 516 can be carried out for cases where it is economically and technically feasible to strip the out-of-specification PR layer (118 or 119) and form a new one in its place. In step 516, the reason for the out-of-range result of step 514 is analyzed and a decision is made whether to re-tune the PR patterning and/or trimming process and to thereafter or nonetheless strip and rework the nonconforming wafers. Path 515 is taken by wafers that are found to be in-range by test 514. In optional, error range expansion step 520, a comparatively expanded, second error range, e3xe2x80x3xe2x89xa6eGateEtched(Poly)xe2x89xa6e4xe2x80x3 is established for gate layer etching, where e3xe2x80x3 less than e3xe2x80x2 and/or e4xe2x80x3 greater than e4xe2x80x2 and where e3xe2x80x2 and e4xe2x80x2 are the error limits used (typically the first one being negative and the second positive) if TCI feedforward adjustment step 550 is bypassed. Next, in step 522, the gate layer etching processes are performed and a corresponding FICD measurement is taken. See FIG. 1B. In test step 524, it is determined whether one or more of the FICD errors is outside of its respective and allowed tolerance range. If the answer is YES, then the out-of-range wafer (or lot of wafers) may be discarded as indicated by step 527. Optional decision step 526 can be carried out for cases where it is economically and technically feasible to further etch wafers whose gate layer is not yet etched far enough (under-etched). In step 526, the reason for the out-of-range result of step 514 is analyzed and a decision is made whether to re-tune the PR patterning and/or trimming process and to thereafter or nonetheless further etch (528) those wafers or dice whose gate layer is under-etched. (It is generally not feasible or economical to strip and rework nonconforming wafers whose gate layer is over-etched such that gate length is too short.) Path 525 is taken by wafers that are found to be in-range by test 524. In optional, error range expansion step 530, a comparatively expanded, third error range, e5xe2x80x3xe2x89xa6eDepoxe2x89xa6e6xe2x80x3 is established for sidewall layer deposition, where e5xe2x80x3xe2x89xa6e5xe2x80x2 and/or e6xe2x80x3 greater than e6xe2x80x2 and where e5xe2x80x2 and e6xe2x80x2 are the error limits used (typically the first one being negative and the second positive) if TCI feedforward adjustment step 550 is bypassed. Next, in step 532, the depositing of the sidewall layer (132) is carried out and a corresponding deposition thickness measurement is taken. See FIG. 1C. In test step 534, it is determined whether one or more of the deposition thickness errors is outside of its respective and allowed tolerance range. If the answer is YES, then the out-of-range wafer (or lot of wafers) may be discarded as indicated by step 537. Optional decision step 536 can be carried out for cases where it is economically and technically feasible to further etch wafers whose sidewall deposition thickness is too large for correction simply with the sidewall etch/trim process 542. In step 536, the reason for the out-of-range result of step 534 is analyzed and a decision is made whether to re-tune the sidewall material deposition process and to thereafter or nonetheless further etch (538) those wafers whose sidewall layer 132 is too thick. (It is generally not feasible or economical to strip and rework nonconforming wafers whose sidewall deposition layer is too thin for counter compensation in the subsequent, sidewall etch/trim process 542.) Path 535 is taken by wafers that are found to be in-range by test 534. Additional wafers may reach next step 540 or 542 after being corrected in step 538. In optional, error range expansion step 540, a comparatively expanded, fourth error range, e7xe2x80x3xe2x89xa6eSWxe2x80x94trimxe2x89xa6e8xe2x80x3 is established for sidewall etching and trimming, where e7xe2x80x3 less than e7xe2x80x2 and/or e8xe2x80x3 greater than e8xe2x80x2 and where e7xe2x80x2 and e8xe2x80x2 are the error limits used (typically the first one being negative and the second positive) if TCI feedforward adjustment step 550 is bypassed. Next, in step 542, the anisotropic etching and/or subsequent isotropic trimming of the sidewall spacers (144) is carried out and a corresponding sidewall thickness measurement (SwM) is taken. See FIG. 1D. The trimming of the sidewall spacers (144) compensates partially for error in the sidewall deposition thickness. In test step 544, it is determined whether one or more of the sidewall thickness errors is outside of its respective and allowed tolerance range. If the answer is YES, then the out-of-range wafer (or lot of wafers) may be discarded as indicated by step 5437. Optional decision step 546 can be carried out for cases where it is economically and technically feasible to further etch wafers whose sidewall post-trim thickness is too large. In step 546, the reason for the out-of-range result of step 544 is analyzed and a decision is made whether to re-tune the sidewall trim process and to thereafter or nonetheless further etch (548) those wafers whose sidewall thickness is too large. (It is generally not feasible or economical to strip and rework nonconforming wafers whose sidewall spacers are too thin for counter compensation in the subsequent, TCI process 552.) Path 545 is taken by wafers that are found to be in-range by sidewall thickness test 544. In following step 550, the TCI energy and/or dosage values are adjusted in response to sidewall thickness error (Energya=f(eSw) . . . {Eq. 2a}) and in response to gate length error (Dosea=f(L2Txe2x88x92L2M) . . . {Eq. 3a}) per the above described considerations. In step 552 the TCI doping operation is carried out in accordance with the adjusted energy and/or dosage values of step 550. Continuation flow 555 represents the carrying out of further, downstream processes after the TCI operation 552. Sampled, electrical characterization of devices that are mass-produced by process flow 500 may be carried out as part of the downstream continuation 555. Table 1 demonstrates computer simulation results for electrical characterization of a given product device that is simulated to be mass-produced by different variations of process flow 500 and assumed to have Gaussian distributions of error in the various critical dimensions discussed above. In Table 1, the horizontal rows respectively represent the 3"sgr" mean values for power consumption in terms of transistor conductive-state current, leakage current and overlap capacitance. The vertical columns respectively represent, in left to right order, the statistical results for simulation with no Automatic Process Correction of any kind (sidewall trim or TCI), conventional Automatic Process Correction (no TCI adjust, but yes with respect to sidewall trim), TCI feedforward based on FICD measurements, and TCI feedforward based on DICD measurements. As can be seen, overlap capacitance (COV) is advantageously and significantly reduced by using one of the TCI feedforward correction schemes. This reduction helps to increase device switching speed. Also, power consumption figures in terms of Ioff-Leak and Ion are slightly better than what is achieved with conventional APC. As such it is seen from these simulation results that TCI feedforward correction can be expected to provide devices with significantly reduced average power consumption (represented by Ion in Table 1), significantly reduced average parasitic capacitance, and relatively small leakage current as compared to the No APC and Conventional APC results of Table 1. The above disclosure is to be taken as illustrative of the invention, not as limiting its scope or spirit. Numerous modifications and variations will become apparent to those skilled in the art after studying the above disclosure. By way of example, the drive-current improvement steps of Gardner U.S. Pat. No. 5,863,824 may be employed concurrently with use of one of the TCI feedforward correction schemes disclosed herein. The CD control steps of Toprac U.S. Pat. No. 5,926,690 may be additionally or alternatively employed concurrently with use of one of the TCI feedforward correction schemes disclosed herein. Given the above disclosure of general concepts and specific embodiments, the scope of protection sought is to be defined by the claims appended hereto.