Patent Number: 
Section: claims

1. A system that contains performance monitors (PMs) comprising:a memory for storing measured parameters for data transactions; anda multi-port memory controller enabling a plurality of data transactions, wherein the multi-port memory controller comprises:a plurality of ports for coupling devices to the multi-port memory controller, wherein a port of the plurality of ports comprises a configurable port implemented based upon the measured parameters; anda performance monitor associated with the port of the plurality of ports for measuring parameters of data transactions of the port, the performance monitor comprising:an address management circuit which qualifies an event for measurement;an event start circuit to determine the start of the qualified event;an event end circuit to determine the end of the qualified event; andan accumulation circuit to interpret the qualified event and provide results to the memory. 2. The system of claim 1, further comprising:a configuration circuit to programmably configure devices in the system based on the measured parameters. 3. The system of claim 1, wherein the measured parameters comprise at least one of measured data transaction execution time, transaction type, and transaction size. 4. The system of claim 1, wherein the measured parameters comprise a change of rate of time required to perform the plurality of data transactions. 5. The system of claim 1, wherein the performance monitor is further configured to store at least one of the plurality of data transactions, a time stamp for the at least one of the plurality of data transactions, an execution time of the at least one of the plurality of data transactions and a type of the at least one of the plurality of data transactions. 6. The system of claim 1, wherein the performance monitor is further configured to provide a histogram of the plurality of data transactions. 7. The system of claim 1, wherein the multi-port memory controller is programmably configured dynamically during operation of the system. 8. A method of monitoring the performance of a system comprising:configuring a plurality of ports associated with a multi-port memory controller for coupling devices to the multi-port memory controller;measuring values for at least one of size, execution time, time stamp and type of data transferred within the system;storing the measured values; andconfiguring a port of the plurality of ports associated with the multi-port memory controller based on the measured values. 9. The method of claim 8, wherein the system comprises a number of separate components operating together, and further comprising a step of adjusting hardware separately within at least some of the number of separate components. 10. The method of claim 8, further comprising providing a histogram of the measured values. 11. The method of claim 8, further comprising providing a time line diagram of the measured values indicating their relative order of occurrence. 12. The method of claim 11, wherein the stored values are organized by the time stamp and at least one of size, execution time, time stamp and type of data transferred within the system. 13. The method of claim 8, wherein the system comprises a multi-port memory controller is provided in a field programmable gate array (FPGA). 14. The method of claim 8, wherein the multi-port memory controller is programmably configured dynamically during operation of the system. 15. A multi-port memory controller (MPMC) comprising:a plurality of ports for coupling devices to the MPMC;a data path circuit configured to communicate data signals from the ports to a memory device;an address path circuit configured to communicate address signals from the ports to the memory device;a control path circuit configured to provide control signals to enable operation of the data path circuit and control path circuit; anda performance monitor (PM) connected to monitor transactions provided through at least one of the data path circuit, the address path circuit and the control path circuit, the PM configured to monitor parameters for at least one of operation execution time of a transaction, time stamp of a transaction, size of a transaction, and type of transaction performed by the at least one of the data path circuit, the address path circuit and the control path circuit. 16. The MPMC of claim 15, wherein arbitration algorithms are provided in the control path circuit, and wherein the arbitration algorithms are dynamically changed based on the monitored parameters determined by the PM. 17. The MPMC of claim 15, wherein the PM stores a histogram indicating at least one of the monitored parameters. 18. The MPMC of claim 17, wherein the transactions include read and write transactions. 19. The MPMC of claim 17, wherein the histogram provides a count of the number of clock cycles each of the transactions take to execute. 20. The MPMC of claim 15 further comprising:port interface modules (PIMs) connected to the ports, the PIMs including programmable logic to enable the port to be made compatible with a number of different components, wherein the PM is provided in a PIM of the PIMs.