Patent Number: 
Section: claims

1. A memory failure recovery analysis method that comprises:rending out plural bits of fail data from a failure analysis memory having stored therein the fail data for each bit of an addressible location in a memory under test;ORing two or more but less than all of the plural bits of the fail data read out of the failure analysis memory;performing recovery analysis processing based on the ORed result; andproviding memory failure recovery analysis for all of the plural bits of said fail data by one or more repetitions of ORing and performing the recovery analysis processing for other bits in the plural bits not processed;wherein the recovery analysis processing is performed bit by bit when the recovery analysis processing based on the result of ORing of the plural bits is decided impossible. 2. The memory failure recovery analysis method as recited in claim 1, wherein the two or more but less than all of the plural bits are selected according to failure statistics of the memory under test. 3. A memory testing apparatus comprising:a failure analysis memory that stores plural bits of fail data resulting from a bit-wise logical comparison between data read out of a memory under test and expected value data;an analysis data bit designating part that outputs bit designating data, which designates two or more but less than all of the plural bits in the fail data read out of the failure analysis memory;a bit designating register that outputs bit designating data for designating one bit in the fail data;a selector for selecting one of the output bit designating data from the bit designating register and the output designating data from the analysis data bit designating part;a logic circuit supplied with the bit designating data selected by the selector and said fail data that outputs the OR of designated plural bits in the fail data; andprocessing part supplied with the output from said logic circuit and an address by which said fail data was read out that performs recovery analysis processing for the memory under test. 4. The memory testing apparatus as recited in claim 3, wherein said analysis data bit designating part is formed by a memory which has the same bit width as said fail data, designates different bit numbers in the fail data, and stores plural pieces of bit designating data at least one of which designates plural bit numbers, and from which that one piece of bit designating data is read out and provided to said logic circuit. 5. The memory testing apparatus as recited in claim 4, wherein said plural pieces of bit designating data are produced so that all bits of the fail data are designated by these pieces of bit designating data. 6. The memory testing apparatus as recited in any one of claims 3 to 5, wherein:said analysis data bit designating part is said memory;said bit designating register is a decoder for outputting bit designating data for designating one bit in response to the input data; anda counter is provided which supplies count data as an address to said analysis data bit designating part and to said bit designating register. 7. A memory failure recovery analysis method which reads out fail data from a failure analysis memory having stored therein the fail data for each bit and performs failure recovery analysis processing, the method comprising:ORing plural bits of the fail data read out of the failure analysis memory;performing recovery analysis processing based on the ORed result; andif the recovery analysis processing based on the ORed result indicates recovery is not possible, performing the recovery analysis processing bit by bit for each of the plurality bits indicating a fail. 8. The memory failure recovery analysis method as recited in claim 7 that comprises:performing at least once the recovery analysis processing based on the result of ORing of the plural bits of the fail data; andperforming the recovery analysis processing for all bits of said fail data by at least one or more repetitions of the recovery analysis processing. 9. The memory failure recovery analysis method as recited in claim 7 or 8 that comprises:reading out fail data from the failure analysis memory at arbitrarily designated addresses; anddesignating an arbitrary bit in the read-out fail data and deciding whether the designated bit is fail data.