Patent Number: 
Section: claims

1. A method of detecting an over-etched defect in the formation of a semiconductor device using a scanning electron microscope comprising: applying an electrical field to at least one semiconductor device, each of the at least one semicondcutor devices comprising an exposed gate electrode and at least one of source and drain contacts, the source and drain contacts connecting respectively to source and drain diffusions, each of the diffusions forming a pn junction with one of a well or substrate region, wherein the electrical field is selected to forward bias the pn junction; and  detecting electrons emitted from the exposed gate electrode surface to determine the presence of a defect between the gate and one of the source and drain contacts. 2. The method as recited in  claim 1 , wherein the at least one semiconductor device comprises at least two devices and further comprising determining an intensity difference between the detected electrons emitted from the gate electrode surfaces of the first and the second of the at least two devices. claim 1 3. The method as recited in  claim 2  further comprising: claim 2 determining that a defect exists when the intensity difference exceeds a predetermined threshold. 4. The method as recited in  claim 2  wherein each of the at least two devices is an MOS device. claim 2 5. The method as recited in  claim 4  wherein the MOS device is a PMOS device and the electrical field applied is an extracting field. claim 4 6. The method as recited in  claim 5  wherein the pn junction is at least one of an interface between a source region and the N-well of the PMOS device and the interface between the drain region and the N-well of the PMOS device. claim 5 7. The method as recited in  claim 4  wherein the MOS device is an NMOS device and the electrical field applied is a retarding field. claim 4 8. The method as recited in  claim 7  wherein the pn junction is at least one of an interface between a source region and the P-well of the NMOS device and the interface between the drain region and the P-well of the NMOS device. claim 7 9. The method as recited in  claim 4  wherein the applying an electrical field and the determining the intensity difference occurs after contact holes connected to the gate and at least one of the source and drain regions have been filled with a conducting material. claim 4 10. The method as recited in  claim 4  wherein the applying an electrical field and the determining the intensity difference occurs after conducting material has been deposited in the contact holes connected to the gate and at least one of the source and drain regions and after chemical mechanical polishing of the deposited conducting materials. claim 4 11. The method as recited in  claim 4  wherein the applying an electrical field occurs after the semiconductor process steps of filling contact holes with a conductive material and before further fabrication steps are performed on the semiconductor. claim 4 12. The method as recited in  claim 4  wherein the applying an electrical field occurs after the semiconductor process steps of depositing a conductive material in the contact holes and performing a CMP step on the filled contacts and before further fabrication steps are performed on the semiconductor. claim 4 13. The method as recited in  claim 1  wherein a scanning electron microscope system applies the electrical field to the wafer. claim 1 14. The method as recited in  claim 1  wherein an electrode applies the electrical field to the wafer. claim 1