Patent Number: 
Section: claims

1. A method for exposing one or more areas on a semiconductor wafer to charged particles, comprising:aligning a wafer mask, having one or more mask patterns thereon, with the semiconductor wafer;bonding the semiconductor wafer with the wafer mask; andpassing the charged particle through then mask patterns to land on one or more selected areas on the semiconductor wafer. 2. The method of claim 1 wherein the charged particle transform semiconductor materials in the selected areas to have a higher resistivity than other areas not exposed to the charged particle. 3. The method of claim 2 wherein the selected areas become semi-insulating areas after receiving the charged particles with a collective energy level exceeding a predetermined threshold. 4. The method of claim 1 wherein the wafer mask has one or more alignment patterns thereon for aligning with the semiconductor wafer. 5. The method of claim 1 wherein the mask patterns are openings with their center portions unremoved. 6. The method of claim 5 wherein the openings are in rectangle shape. 7. The method of claim 1 wherein the wafer mask is made from a silicon wafer having a thickness between 100 um to 800 um. 8. The method of claim 1 wherein an angle between sidewalls of the mask patterns on the wafer mask and the surface of the wafer mask is between 80 to 100 degrees. 9. The method of claim 1 further comprising:determining the one or more selected areas on the semiconductor wafer for receiving the charged particles; andgenerating the wafer mask having the mask patterns containing thereon for passing the charged particles to land on the selected areas when the semiconductor wafer is aligned with the wafer mask. 10. The method of claim 1 wherein the charged particles are protons. 11. The method of claim 1 wherein the charged particles have an energy level between 0.5 to 5 MeV. 12. A method of exposing one or more areas on a semiconductor wafer to charged particles for making semi-insulating areas, comprising:aligning a wafer mask, having one or more mask patterns thereon, with the semiconductor wafer, with the mask being a predetermined proximity to the semiconductor wafer;bonding the semiconductor wafer with the wafer mask;generating the charged particles; anddirecting the charged particles through the mask patterns to land on one or more selected areas on the semiconductor wafer,wherein semiconductor materials in the selected areas of the semiconductor wafer are transformed to have a higher resistivity than those not exposed to the charged particles. 13. The method of claim 12 wherein the selected areas become semi-insulating areas. 14. The method of claim 12 further comprising:determining one or more selected areas on the semiconductor wafer for receiving the charged particles; andgenerating a wafer mask having one or more mask patterns contained thereon for passing the charged particles. 15. The method of claim 12 wherein the wafer mask has one or more alignment patterns thereon for aligning with the semiconductor wafer. 16. The method of claim 12 wherein the mask patterns are rectangular openings. 17. The method of claim 12 wherein the mask patterns are rectangular openings with their center portions of wafer material unremoved. 18. The method of claim 12 wherein the wafer mask has a thickness between 110 um to 800 um. 19. The method of claim 12 wherein an angle between sidewalls of the mask patterns on the wafer mask and the surface of the wafer mask is between 80 to 110 degrees. 20. The method of claim 12 wherein a fluence of the charge particles is between 1E14 ea/cm2 to 1E17 ea/cm2. 21. The method of claim 12 wherein the charged particles land substantially perpendicularly to the selected areas. 22. A system for exposing one or more areas on a semiconductor wafer to charged particles, comprising:means for aligning a wafer mask, having one or more mask patterns thereon with the semiconductor wafer;means for bonding the semiconductor wafer with the wafer mask:means for generating the charged particles; andmeans for directing the charged particles through the mask patterns to land on selected areas on the semiconductor wafer. 23. The system of claim 22 further comprising means for determining one or more selected areas on the semiconductor wafer for receiving the charged particles. 24. The system of claim 22 further comprising means for generating the mask patterns for passing the charged particles. 25. The system of claim 24 wherein the means for generating the mask further includes means for generating one or more alignment patterns thereon for aligning with the semiconductor wafer. 26. The system of claim 24 wherein the mask patterns are rectangular openings. 27. The system of claim 24 wherein the mask patterns are rectangular openings with their center portions of wafer material unremoved. 28. The system of claim 22 wherein the means for generating charged particles generates the charged particles with an energy level above 0.5 MeV. 29. The system of claim 22 wherein the means for generating charged particles generates the charged particles with an energy level below 5 MeV.