Patent Number: 
Section: claims

1. A circuit layout method of forming two masks for a plurality of patterns, said method comprising:receiving layout data representing the plurality of patterns, the layout data including a plurality of layers;identifying, by a processor of a computer system, spaces between adjacent patterns in at least one layer of the plurality of layers which violate a G0-rule;determining whether each identified space is a critical G0-space, by the processor, wherein the identified space is determined to be the critical G0-space if removal of a portion of at least one pattern merges two adjacent odd-loops of G0-spaces into a single even-loop of G0-spaces or converts one odd-loop of G0-spaces to a non-loop of G0-spaces;performing an adjustment, using the processor, of the at least one pattern based on a determination that at least one space is the critical G0-space based on received instructions; andoutputting an adjusted representation of the plurality of patterns, the adjusted representation including identified G0-rule violations and determined critical G0 spaces. 2. The circuit layout method of claim 1, further comprising updating a spacing of layer adjacent to the at least one layer and issuing a warning if the received adjustment causes at least one misalignment in the layer adjacent to the at least one layer. 3. The circuit layout method of claim 1, wherein identifying spaces which violate the G0-rule comprises determining whether a spacing between the adjacent patterns is between a minimum spacing and the minimum spacing multiplied by a parameter. 4. The circuit layout method of claim 3, wherein identifying spaces which violate the G0-rule further comprisessetting the parameter to a first value if the spacing is an end-end or an end-run spacing;setting the parameter to a second value if the spacing is a run-run spacing; andsetting the parameter to a third value if the spacing is a corner-corner spacing, wherein the first value is different from the second value and the third value. 5. The circuit layout method of claim 4, wherein the second value is equal to the third value. 6. The circuit layout method of claim 1, wherein updating a spacing of a layer of the plurality of layers adjacent to the at least one layer comprises re-shaping at least one pattern on the layer adjacent to the at least one layer. 7. The circuit layout method of claim 1, further comprising updating a position of an element in a layer adjacent to the at least one layer if the received adjustment causes at least one misalignment in the layer adjacent to the at least one layer. 8. A circuit layout method of forming two masks for a plurality of patterns, said method comprising:receiving layout data representing the plurality of patterns of at least one layer of the circuit layout;determining, by a processor of a computer system, whether a distance between a pair of adjacent patterns is a G0-space for each pair of adjacent patterns;determining, by the processor, whether a G0-rule violation exists for the G0-space;determining, by the processor, whether the G0-space violating the G0-rule is a critical G0-space based on whether the pair of adjacent patterns are separable into different masks;performing an adjustment, using the processor, of at least one pattern of the plurality of patterns based on the determined critical G0-space based on received instructions; andoutputting a representation comprising the G0-rule violation and the determined critical G0-space. 9. The circuit layout method of claim 8, further comprising:updating a spacing of a layer adjacent to the at least one layer based on the received adjustment, by the processor. 10. The circuit layout method of claim 9, wherein updating the spacing of the layer adjacent to the at least one layer comprises issuing a warning if the received adjustment causes at least one misalignment in the layer adjacent to the at least one layer. 11. The circuit layout method of claim 9, wherein updating the spacing of the layer adjacent to the at least one layer comprises re-shaping at least one pattern on the layer adjacent to the at least one layer. 12. The circuit layout method of claim 8, wherein determining whether the G0-rule violation exists comprises determining whether a spacing between the pair of adjacent patterns is between a minimum spacing and the minimum spacing multiplied by a parameter. 13. The circuit layout method of claim 12, wherein determining whether the G0-rule violation exists further comprises:setting the parameter to a first value if the spacing is an end-end or an end-run spacing;setting the parameter to a second value if the spacing is a run-run spacing; andsetting the parameter to a third value if the spacing is a corner-corner spacing, wherein the first value is different from the second value and the third value. 14. The circuit layout method of claim 13, wherein the second value is equal to the third value. 15. A non-transitory computer readable medium containing instructions, and the instructions comprise codes for execution by a processor for:receiving layout data representing the plurality of patterns, the layout data including a plurality of layers;identifying spaces between adjacent patterns in at least one layer of the plurality of layers which violate a G0-rule;determining whether each identified space is a critical G0-space, wherein the identified space is determined to be the critical G0-space if removal of a portion of at least one pattern merges two adjacent odd-loops of G0-spaces into a single even-loop of G0-spaces or converts one odd-loop of G0-spaces to a non-loop of G0-spaces;performing an adjustment, using the processor, of the at least one pattern based on the determination that at least one space is the critical G0-space based on received instructions; andupdating a spacing of a layer adjacent to the at least one layer based on the received adjustment. 16. The non-transitory computer readable medium of claim 15, wherein the instructions for execution by the processor are further for issuing a warning if the received adjustment causes at least one misalignment in the layer adjacent to the at least one layer. 17. The non-transitory computer readable medium of claim 15, wherein the instructions for execution by the processor are further for determining whether a spacing between the adjacent patterns is between a minimum spacing and the minimum spacing multiplied by a parameter. 18. The non-transitory computer readable medium of claim 17, wherein the instructions for execution by the processor are further forsetting the parameter to a first value if the spacing is an end-end or an end-run spacing;setting the parameter to a second value if the spacing is a run-run spacing; andsetting the parameter to a third value if the spacing is a corner-corner spacing, wherein the first value is different from the second value and the third value. 19. The non-transitory computer readable medium of claim 15, wherein the instructions for execution by the processor are further for outputting an adjusted representation of the plurality of patterns, the adjusted representation including identified G0-rule violations and determined critical G0 spaces. 20. The non-transitory computer readable medium of claim 15, wherein the instructions for execution by the processor are further for re-shaping at least one pattern on the layer adjacent to the at least one layer based on the received adjustment.