Patent Number: 
Section: claims

1. A method for distributing a process variable using statistically-correct spatial interpolation, the method comprising:configuring a circuit simulation tool to perform computerized modeling of a chip to be fabricated using the process variable in a process step;forming, using the circuit simulation tool, an array of equilateral triangles in a planar coordinate frame on a region of the chip;assigning, using the circuit simulation tool, a numerical value of the process variable at each vertex of the array of equilateral triangles;defining, using the circuit simulation tool, a plurality of test points at respective spatial locations in the planar coordinate frame that are bounded by the array of equilateral triangles;distributing, using the circuit simulation tool, a numerical value of the process variable at each of the test points by spatial interpolation from one or more of the numerical values of the process variable assigned at each vertex of the array of equilateral triangles; andadjusting, using the circuit simulation tool, the numerical value of the process variable distributed at each of the test points with a respective correction factor. 2. The method of claim 1 wherein forming, using the circuit simulation tool, the array of equilateral triangles further comprises:defining, using the circuit simulation tool, a local spatial correlation that equals zero at a minimum distance between test points; andassigning, using the circuit simulation tool, a length to each side of the equilateral triangles to be equal to the minimum distance for the local spatial correlation. 3. The method of claim 1 wherein assigning, using the circuit simulation tool, the numerical value of the process variable at each vertex of the equilateral triangles further comprises:providing, using the circuit simulation tool, a global distribution function for the process variable; andspecifying, using the circuit simulation tool, the numerical value at each vertex from the global distribution function. 4. The method of claim 3 wherein the global distribution function has an associated standard deviation, and each respective correction factor is selected to reduce a difference between a local standard deviation of the numerical values of the process variable at the test points and the standard deviation of the global distribution function. 5. The method of claim 1 wherein the numerical value at each vertex of the array of equilateral triangles is assigned from a global distribution function having a mean, and further comprising:randomly selecting, using the circuit simulation tool, a numerical value of the process variable chosen from the global distribution function with the mean set equal to zero;determining, using the circuit simulation tool, a respective multiplicative factor based upon the spatial location of each of the test points relative to respective spatial locations in the planar coordinate frame for one or more of the vertices of the array of equilateral triangles; andmultiplying, using the circuit simulation tool, the respective multiplicative factor and the randomly selected numerical value of the process variable to determine the respective correction factor used to adjust the numerical value of the process variable distributed at each of the test points. 6. The method of claim 1 further comprising:calculating, using the circuit simulation tool, the correction factor for the numerical value of the process variable at each of the test points with a mathematical algorithm. 7. The method of claim 1 wherein adjusting, using the circuit simulation tool, the numerical value of the process variable at each of the test points with the respective correction factor further comprises:adding, using the circuit simulation tool, a numerical offset as the respective correction factor to the numerical value of the process variable distributed by the spatial interpolation at each of the test points. 8. The method of claim 1 wherein the process variable is a height or a thickness for metallization in a wiring level of a multi-level interconnect of the chip.