Patent Number: 
Section: claims

1. An ion implanter comprising:an ion source adapted to direct charged ions having an initial mass and energy along a path;a mass analyzer downstream of the ion source for selecting ions based on the mass and energy of the ions;a multi-stage linear accelerator downstream of the mass analyzer comprising:a plurality of acceleration gaps; anda plurality of RF electrodes for accelerating the ions therebetween;wherein each stage of the multi-stage linear accelerator has at least one RF electrode and an acceleration gap adjacent to the electrode, and wherein each RF electrode is operatively associated with an accelerator energy source adapted to create an accelerating alternating electric field to accelerate the ions to a second energy;an end station adapted to position a workpiece so that the accelerated charged ions impact the workpiece; anda direct digital synthesis (DDS) controller coupled to the energy source and adapted to digitally synchronize a frequency and phase of the electric fields of each stage in the linear accelerator, the DDS controller comprising:a plurality of digital phase synthesis (DPS) circuits individually coupled to each of the plurality of RF electrodes to modulate the phase of the voltage applied to each RF electrode; anda digital frequency synthesis circuit (DFS) connected to each of the plurality of DPS circuits and adapted to digitally synthesize a master frequency and phase applied to each of the DPS circuits. 2. The ion implanter of claim 1, wherein the DDS controller further comprises a PLL connected between one of the plurality of DPS circuits and a corresponding one of the plurality of RF electrodes. 3. The ion implanter of claim 1, wherein the DDS controller further comprises a phase locked loop (PLL) connected between the master oscillator and one of the plurality of DPS circuits. 4. The ion implanter of claim 1, wherein each of the plurality of DPS circuits of the DDS controller further comprises a summation circuit adapted to receive a sample input and a phase offset value and connected to a digital storage register adapted to modulate the phase of the electric field applied to each RF electrode within a stage of the accelerator. 5. The ion implanter of claim 1, wherein the master oscillator (DFS) further comprises a digital accumulator and a look-up table adapted to digitally synthesize a master frequency and phase for each of the DPS circuits connected thereto, by reconstructing digitally calculated samples derived from the look-up table by correlating the phase of each sample to a corresponding voltage amplitude. 6. The ion implanter of claim 5, wherein the accumulator comprises a summation circuit adapted to receive a sample input and is connected to a digital storage register that is feedback connected to the summation circuit. 7. The ion implanter of claim 6, wherein the master oscillator (DFS) further comprises a plurality of phase shifter circuits adapted to digitally synthesize a master frequency and phase for each of the DPS circuits connected thereto comprising one of:a DFS circuit adapted to receive the master oscillator output frequency and a DPS circuit adapted to receive a phase offset value;a PLL circuit adapted to receive the master oscillator output frequency, a DFS circuit connected to the PLL circuit, and a first DPS phase offset circuit connected to the DFS circuit to produce a reference phase feedback connected to the PLL circuit, and a second DPS circuit connected to the DFS circuit and adapted to receive a phase offset input to produce a variable phase output to the RF electrode; anda summation circuit adapted to receive a phase offset value input and connected to a look-up table adapted to digitally synthesize a master frequency and phase for each of the DPS circuits connected thereto, by reconstructing digitally calculated samples derived from the look-up table by correlating the phase of each sample to a corresponding voltage amplitude. 8. The ion implanter of claim 1, wherein the DDS controller is configured such that the master oscillator and the DPS phase control circuits are centrally located within a single integrated circuit. 9. The ion implanter of claim 1, wherein the DDS controller is configured such that the DPS phase control circuits are centrally located within a single integrated circuit. 10. The ion implanter of claim 9, wherein the DPS phase control circuits are uniformly located for minimal delay variation at the perimeter of the integrated circuit. 11. The ion implanter of claim 10, wherein output registers of the DPS phase control circuits are uniformly located for minimal delay variation at the perimeter of the integrated circuit. 12. The ion implanter of claim 1, wherein the DDS controller is configured such that the DPS circuits are distributed locally to each stage of the accelerator, each stage comprising a PLL circuit adapted to receive the master oscillator output frequency, and a first DPS phase offset circuit connected to the PLL circuit to produce a reference phase feedback connected to the PLL circuit, and a second DPS circuit connected to the PLL circuit and adapted to produce a variable phase output to the RF electrode. 13. The ion implanter of claim 1, wherein the DDS controller is configured such that the DPS phase control circuits are centrally located within a single integrated circuit, and wherein the output signal terminals therefrom are uniformly spaced at the perimeter of the integrated circuit. 14. The ion implanter of claim 1, wherein the DDS controller is configured such that the DPS phase control circuits are centrally located within a single integrated circuit, and wherein the output signal terminals therefrom are uniformly spaced and are each located adjacent to a common ground or supply terminal at the perimeter of the integrated circuit. 15. The ion implanter of claim 1, wherein the DDS controller is configured such that the DPS phase control circuits are centrally located within a single integrated circuit, and wherein the DPS output signals comprise differential outputs from the integrated circuit.