system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | code for sm_80
Function : _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R7, R9.reuse, c[0x0][0x170], RZ ; /* 0x00005c0009077a24 */
/* 0x041fe400078e02ff */
/*0070*/ IMAD R9, R9, c[0x0][0x174], RZ ; /* 0x00005d0009097a24 */
/* 0x000fe400078e02ff */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x001fe40000011400 */
/*0090*/ IADD3 R2, P0, P1, R0, c[0x0][0x160], R7 ; /* 0x0000580000027a10 */
/* 0x000fc8000791e007 */
/*00a0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590005037a10 */
/* 0x000fcc00007e24ff */
/*00b0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ IADD3 R4, P0, P1, R0.reuse, c[0x0][0x168], R9 ; /* 0x00005a0000047a10 */
/* 0x040fe4000791e009 */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, P1 ; /* 0x00005b0005057a10 */
/* 0x000fe400007e24ff */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc60003f06270 */
/*0100*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f4000c101104 */
/*0110*/ @!P0 BRA 0x80 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | .file "tmpxft_00097a77_00000000-6_PadMatrixInLeadingDimensionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.type _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, @function
_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, .-_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii, @function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 8
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x14
s_load_b32 s0, s[0:1], 0x24
s_mul_i32 s3, s15, s2
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, s3
s_mul_i32 s15, s15, s8
s_addc_u32 s4, s5, 0
s_add_u32 s5, s6, s15
s_addc_u32 s6, s7, 0
s_and_b32 s7, s0, 0xffff
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v0
v_add_co_u32 v1, vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s4, v3, vcc_lo
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, s5, v0
v_add_nc_u32_e32 v0, s7, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s6, v3, vcc_lo
v_cmp_le_i32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33PadMatrixInLeadingDimensionKernelPKaPaii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | .text
.file "PadMatrixInLeadingDimensionKernel.hip"
.globl _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii # -- Begin function _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 4, 0x90
.type _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii: # @_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@object # @_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata,"a",@progbits
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 3, 0x0
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.quad _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R7, R9.reuse, c[0x0][0x170], RZ ; /* 0x00005c0009077a24 */
/* 0x041fe400078e02ff */
/*0070*/ IMAD R9, R9, c[0x0][0x174], RZ ; /* 0x00005d0009097a24 */
/* 0x000fe400078e02ff */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x001fe40000011400 */
/*0090*/ IADD3 R2, P0, P1, R0, c[0x0][0x160], R7 ; /* 0x0000580000027a10 */
/* 0x000fc8000791e007 */
/*00a0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590005037a10 */
/* 0x000fcc00007e24ff */
/*00b0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ IADD3 R4, P0, P1, R0.reuse, c[0x0][0x168], R9 ; /* 0x00005a0000047a10 */
/* 0x040fe4000791e009 */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, P1 ; /* 0x00005b0005057a10 */
/* 0x000fe400007e24ff */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc60003f06270 */
/*0100*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f4000c101104 */
/*0110*/ @!P0 BRA 0x80 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 8
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x14
s_load_b32 s0, s[0:1], 0x24
s_mul_i32 s3, s15, s2
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, s3
s_mul_i32 s15, s15, s8
s_addc_u32 s4, s5, 0
s_add_u32 s5, s6, s15
s_addc_u32 s6, s7, 0
s_and_b32 s7, s0, 0xffff
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v0
v_add_co_u32 v1, vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s4, v3, vcc_lo
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, s5, v0
v_add_nc_u32_e32 v0, s7, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s6, v3, vcc_lo
v_cmp_le_i32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33PadMatrixInLeadingDimensionKernelPKaPaii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00097a77_00000000-6_PadMatrixInLeadingDimensionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.type _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, @function
_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, .-_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii, @function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PadMatrixInLeadingDimensionKernel.hip"
.globl _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii # -- Begin function _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 4, 0x90
.type _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii: # @_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@object # @_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata,"a",@progbits
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 3, 0x0
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.quad _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
cudaMalloc((void**)&pA, (N*N)*sizeof(float));
cudaMalloc((void**)&pB, (N*N)*sizeof(float));
cudaMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
cudaMemcpy(pA, A, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pB, B, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pC, C, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
cudaMemcpy(C, pC, (N*N)*sizeof(float), cudaMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | code for sm_80
Function : _Z7MatMultPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R5, c[0x0][0x17c] ; /* 0x00005f0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e2a0000209400 */
/*0050*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IADD3 R4, RZ, -R3, RZ ; /* 0x80000003ff047210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00d0*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc60000000000 */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*00f0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fe200078e00ff */
/*0110*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e260000002200 */
/*0120*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f44070 */
/*0150*/ IMAD R4, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007047a24 */
/* 0x001fd800078e0202 */
/*0160*/ @!P2 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x800000050000a210 */
/* 0x080fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0190*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f45270 */
/*01a0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*01b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2c0000002100 */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fc800000001ff */
/*01f0*/ @!P1 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b9224 */
/* 0x000fe200078e0a0b */
/*0200*/ @!P2 LOP3.LUT R11, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0baa12 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD R5, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005057a24 */
/* 0x001fd800078e0200 */
/*0230*/ @!P0 BRA 0xaf0 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R3, R11.reuse, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x040fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R6, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b067812 */
/* 0x000fe400078ec0ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f46070 */
/*0280*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f06270 */
/*0290*/ SHF.L.U32 R9, R2, 0x3, RZ ; /* 0x0000000302097819 */
/* 0x000fe400000006ff */
/*02a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc40003f25270 */
/*02b0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*02c0*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x178], !P0 ; /* 0x00005e0005007a0c */
/* 0x000fe40004701270 */
/*02d0*/ LEA R8, R0, R9, 0x2 ; /* 0x0000000900087211 */
/* 0x000fe200078e10ff */
/*02e0*/ @!P2 BRA 0x910 ; /* 0x000006200000a947 */
/* 0x000fea0003800000 */
/*02f0*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0300*/ IMAD R18, R4, c[0x0][0x178], R0 ; /* 0x00005e0004127a24 */
/* 0x000fe200078e0200 */
/*0310*/ IADD3 R20, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002147a10 */
/* 0x000fe20007ffe0ff */
/*0320*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0330*/ LEA R16, R13.reuse, R2, 0x1 ; /* 0x000000020d107211 */
/* 0x040fe200078e08ff */
/*0340*/ IMAD R14, R13, 0x3, R2 ; /* 0x000000030d0e7824 */
/* 0x000fe200078e0202 */
/*0350*/ BSSY B0, 0x910 ; /* 0x000005b000007945 */
/* 0x000fe20003800000 */
/*0360*/ IADD3 R10, -R11, R6, RZ ; /* 0x000000060b0a7210 */
/* 0x000fe20007ffe1ff */
/*0370*/ IMAD R12, R13, c[0x0][0x178], RZ ; /* 0x00005e000d0c7a24 */
/* 0x000fc400078e02ff */
/*0380*/ IMAD R9, R13.reuse, 0x3, R18 ; /* 0x000000030d097824 */
/* 0x040fe200078e0212 */
/*0390*/ LEA R13, R13, R18, 0x1 ; /* 0x000000120d0d7211 */
/* 0x000fe200078e08ff */
/*03a0*/ IMAD R19, R2, c[0x0][0x178], R5.reuse ; /* 0x00005e0002137a24 */
/* 0x100fe400078e0205 */
/*03b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD R23, R20, c[0x0][0x178], R5.reuse ; /* 0x00005e0014177a24 */
/* 0x100fe400078e0205 */
/*03d0*/ IMAD R21, R14, c[0x0][0x178], R5.reuse ; /* 0x00005e000e157a24 */
/* 0x100fe400078e0205 */
/*03e0*/ IMAD R11, R16, c[0x0][0x178], R5 ; /* 0x00005e00100b7a24 */
/* 0x000fc400078e0205 */
/*03f0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff100424 */
/* 0x000fc800078e00ff */
/*0400*/ @P0 IMAD.WIDE.U32 R14, R18, R16, c[0x0][0x160] ; /* 0x00005800120e0625 */
/* 0x000fc800078e0010 */
/*0410*/ @P0 IMAD.WIDE.U32 R16, R19, R16, c[0x0][0x168] ; /* 0x00005a0013100625 */
/* 0x000fe200078e0010 */
/*0420*/ @P0 LDG.E R25, [R14.64] ; /* 0x000000040e190981 */
/* 0x0000a8000c1e1900 */
/*0430*/ @P0 LDG.E R27, [R16.64] ; /* 0x00000004101b0981 */
/* 0x0002e2000c1e1900 */
/*0440*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0450*/ @P0 IADD3 R20, R18, c[0x0][0x17c], RZ ; /* 0x00005f0012140a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ @P0 MOV R22, 0x4 ; /* 0x0000000400160802 */
/* 0x000fca0000000f00 */
/*0470*/ @P0 IMAD.WIDE.U32 R14, R20, R22, c[0x0][0x160] ; /* 0x00005800140e0625 */
/* 0x001fc800078e0016 */
/*0480*/ @P0 IMAD.WIDE.U32 R16, R23, R22, c[0x0][0x168] ; /* 0x00005a0017100625 */
/* 0x002fe200078e0016 */
/*0490*/ @P0 STS [R8], R25 ; /* 0x0000001908000388 */
/* 0x004fe80000000800 */
/*04a0*/ @P0 STS [R8+0x10], R27 ; /* 0x0000101b08000388 */
/* 0x0081e80000000800 */
/*04b0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04c0*/ @P0 LDS R26, [R0.X4+0x10] ; /* 0x00001000001a0984 */
/* 0x000fe80000004800 */
/*04d0*/ @P0 LDS R24, [R2.X8] ; /* 0x0000000002180984 */
/* 0x000e680000008800 */
/*04e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04f0*/ @P0 LDS R28, [R0.X4+0x18] ; /* 0x00001800001c0984 */
/* 0x000fe80000004800 */
/*0500*/ @P0 LDS R25, [R2.X8+0x4] ; /* 0x0000040002190984 */
/* 0x000ea80000008800 */
/*0510*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0520*/ @P0 LDG.E R27, [R14.64] ; /* 0x000000040e1b0981 */
/* 0x0010e8000c1e1900 */
/*0530*/ @P0 LDG.E R29, [R16.64] ; /* 0x00000004101d0981 */
/* 0x000962000c1e1900 */
/*0540*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0550*/ @P0 FFMA R24, R26, R24, R3 ; /* 0x000000181a180223 */
/* 0x002fc80000000003 */
/*0560*/ @P0 FFMA R3, R28, R25, R24 ; /* 0x000000191c030223 */
/* 0x004fe20000000018 */
/*0570*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0580*/ @P0 IMAD.WIDE.U32 R14, R13, R16, c[0x0][0x160] ; /* 0x000058000d0e0625 */
/* 0x001fc800078e0010 */
/*0590*/ @P0 IMAD.WIDE.U32 R16, R11, R16, c[0x0][0x168] ; /* 0x00005a000b100625 */
/* 0x000fe200078e0010 */
/*05a0*/ @P0 STS [R8], R27 ; /* 0x0000001b08000388 */
/* 0x008fe80000000800 */
/*05b0*/ @P0 STS [R8+0x10], R29 ; /* 0x0000101d08000388 */
/* 0x0201e80000000800 */
/*05c0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*05d0*/ @P0 LDS R20, [R0.X4+0x10] ; /* 0x0000100000140984 */
/* 0x000fe80000004800 */
/*05e0*/ @P0 LDS R22, [R2.X8] ; /* 0x0000000002160984 */
/* 0x000e680000008800 */
/*05f0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0600*/ @P0 LDS R27, [R0.X4+0x18] ; /* 0x00001800001b0984 */
/* 0x000fe80000004800 */
/*0610*/ @P0 LDS R26, [R2.X8+0x4] ; /* 0x00000400021a0984 */
/* 0x000ea80000008800 */
/*0620*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0630*/ @P0 LDG.E R29, [R14.64] ; /* 0x000000040e1d0981 */
/* 0x0010e8000c1e1900 */
/*0640*/ @P0 LDG.E R28, [R16.64] ; /* 0x00000004101c0981 */
/* 0x000962000c1e1900 */
/*0650*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0660*/ @P0 FFMA R20, R20, R22, R3 ; /* 0x0000001614140223 */
/* 0x002fc80000000003 */
/*0670*/ @P0 FFMA R3, R27, R26, R20 ; /* 0x0000001a1b030223 */
/* 0x004fe20000000014 */
/*0680*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0690*/ @P0 IMAD.WIDE.U32 R14, R9, R16, c[0x0][0x160] ; /* 0x00005800090e0625 */
/* 0x001fc800078e0010 */
/*06a0*/ @P0 IMAD.WIDE.U32 R16, R21, R16, c[0x0][0x168] ; /* 0x00005a0015100625 */
/* 0x000fe200078e0010 */
/*06b0*/ @P0 STS [R8], R29 ; /* 0x0000001d08000388 */
/* 0x008fe80000000800 */
/*06c0*/ @P0 STS [R8+0x10], R28 ; /* 0x0000101c08000388 */
/* 0x020fe80000000800 */
/*06d0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*06e0*/ @P0 LDS R24, [R0.X4+0x10] ; /* 0x0000100000180984 */
/* 0x000fe80000004800 */
/*06f0*/ @P0 LDS R25, [R2.X8] ; /* 0x0000000002190984 */
/* 0x000e280000008800 */
/*0700*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0710*/ @P0 LDS R20, [R0.X4+0x18] ; /* 0x0000180000140984 */
/* 0x000fe80000004800 */
/*0720*/ @P0 LDS R27, [R2.X8+0x4] ; /* 0x00000400021b0984 */
/* 0x000e680000008800 */
/*0730*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0740*/ @P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f0981 */
/* 0x0004e8000c1e1900 */
/*0750*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000410110981 */
/* 0x000962000c1e1900 */
/*0760*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0770*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0780*/ @P0 FFMA R24, R24, R25, R3 ; /* 0x0000001918180223 */
/* 0x001fe20000000003 */
/*0790*/ LEA R23, R12.reuse, R23, 0x2 ; /* 0x000000170c177211 */
/* 0x040fe200078e10ff */
/*07a0*/ IMAD R21, R12.reuse, 0x4, R21 ; /* 0x000000040c157824 */
/* 0x040fe200078e0215 */
/*07b0*/ LEA R19, R12, R19, 0x2 ; /* 0x000000130c137211 */
/* 0x000fe200078e10ff */
/*07c0*/ IMAD.IADD R14, R10, 0x1, R7 ; /* 0x000000010a0e7824 */
/* 0x004fe200078e0207 */
/*07d0*/ LEA R11, R12, R11, 0x2 ; /* 0x0000000b0c0b7211 */
/* 0x000fe200078e10ff */
/*07e0*/ @P0 FFMA R3, R20, R27, R24 ; /* 0x0000001b14030223 */
/* 0x002fe20000000018 */
/*07f0*/ MOV R16, c[0x0][0x17c] ; /* 0x00005f0000107a02 */
/* 0x010fc40000000f00 */
/*0800*/ ISETP.NE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f45270 */
/*0810*/ LEA R9, R16.reuse, R9, 0x2 ; /* 0x0000000910097211 */
/* 0x040fe200078e10ff */
/*0820*/ IMAD R18, R16.reuse, 0x4, R18 ; /* 0x0000000410127824 */
/* 0x040fe200078e0212 */
/*0830*/ LEA R13, R16, R13, 0x2 ; /* 0x0000000d100d7211 */
/* 0x000fe200078e10ff */
/*0840*/ @P0 STS [R8], R15 ; /* 0x0000000f08000388 */
/* 0x008fe80000000800 */
/*0850*/ @P0 STS [R8+0x10], R17 ; /* 0x0000101108000388 */
/* 0x020fe80000000800 */
/*0860*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0870*/ @P0 LDS R22, [R0.X4+0x10] ; /* 0x0000100000160984 */
/* 0x000fe80000004800 */
/*0880*/ @P0 LDS R26, [R2.X8] ; /* 0x00000000021a0984 */
/* 0x000e280000008800 */
/*0890*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08a0*/ @P0 LDS R29, [R0.X4+0x18] ; /* 0x00001800001d0984 */
/* 0x000fe80000004800 */
/*08b0*/ @P0 LDS R28, [R2.X8+0x4] ; /* 0x00000400021c0984 */
/* 0x000e620000008800 */
/*08c0*/ @P0 FFMA R22, R22, R26, R3 ; /* 0x0000001a16160223 */
/* 0x001fc80000000003 */
/*08d0*/ @P0 FFMA R3, R29, R28, R22 ; /* 0x0000001c1d030223 */
/* 0x002fe20000000016 */
/*08e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08f0*/ @P2 BRA 0x3f0 ; /* 0xfffffaf000002947 */
/* 0x000fea000383ffff */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ BSSY B0, 0xaf0 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0920*/ @!P1 BRA 0xae0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R10, R7.reuse, c[0x0][0x17c], R2 ; /* 0x00005f00070a7a24 */
/* 0x040fe400078e0202 */
/*0940*/ IMAD R7, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007077a24 */
/* 0x000fc400078e0200 */
/*0950*/ IMAD R9, R10, c[0x0][0x178], R5 ; /* 0x00005e000a097a24 */
/* 0x000fe400078e0205 */
/*0960*/ IMAD R7, R4, c[0x0][0x178], R7 ; /* 0x00005e0004077a24 */
/* 0x000fe400078e0207 */
/*0970*/ @P0 MOV R12, 0x4 ; /* 0x00000004000c0802 */
/* 0x000fca0000000f00 */
/*0980*/ @P0 IMAD.WIDE.U32 R10, R7, R12, c[0x0][0x160] ; /* 0x00005800070a0625 */
/* 0x000fc800078e000c */
/*0990*/ @P0 IMAD.WIDE.U32 R12, R9, R12, c[0x0][0x168] ; /* 0x00005a00090c0625 */
/* 0x000fe400078e000c */
/*09a0*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b0981 */
/* 0x0000a8000c1e1900 */
/*09b0*/ @P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d0981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*09d0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R7, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007077a10 */
/* 0x000fc40007ffe0ff */
/*09f0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0a00*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x001fca0000000f00 */
/*0a10*/ IMAD R9, R10, c[0x0][0x178], R9 ; /* 0x00005e000a097a24 */
/* 0x000fe200078e0209 */
/*0a20*/ @P0 STS [R8], R11 ; /* 0x0000000b08000388 */
/* 0x004fe80000000800 */
/*0a30*/ @P0 STS [R8+0x10], R13 ; /* 0x0000100d08000388 */
/* 0x008fe80000000800 */
/*0a40*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a50*/ @P0 LDS R14, [R0.X4+0x10] ; /* 0x00001000000e0984 */
/* 0x000fe80000004800 */
/*0a60*/ @P0 LDS R15, [R2.X8] ; /* 0x00000000020f0984 */
/* 0x000e280000008800 */
/*0a70*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a80*/ @P0 LDS R17, [R0.X4+0x18] ; /* 0x0000180000110984 */
/* 0x000fe80000004800 */
/*0a90*/ @P0 LDS R16, [R2.X8+0x4] ; /* 0x0000040002100984 */
/* 0x000e620000008800 */
/*0aa0*/ @P0 FFMA R14, R14, R15, R3 ; /* 0x0000000f0e0e0223 */
/* 0x001fc80000000003 */
/*0ab0*/ @P0 FFMA R3, R17, R16, R14 ; /* 0x0000001011030223 */
/* 0x002fe2000000000e */
/*0ac0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0ad0*/ @P1 BRA 0x970 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe20000000f00 */
/*0b00*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x000fc800078e0205 */
/*0b10*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0207 */
/*0b20*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
cudaMalloc((void**)&pA, (N*N)*sizeof(float));
cudaMalloc((void**)&pB, (N*N)*sizeof(float));
cudaMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
cudaMemcpy(pA, A, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pB, B, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pC, C, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
cudaMemcpy(C, pC, (N*N)*sizeof(float), cudaMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | .file "tmpxft_00139677_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4absff
.type _Z4absff, @function
_Z4absff:
.LFB2059:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L7
.L4:
ret
.L7:
xorps .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE2059:
.size _Z4absff, .-_Z4absff
.globl _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7MatMultPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.type _Z7MatMultPfS_S_ii, @function
_Z7MatMultPfS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7MatMultPfS_S_ii, .-_Z7MatMultPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Kernel matrix multiplication time: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "TEST PASSED\n"
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.type _Z12HostFunctionPA_fS0_S0_ii, @function
_Z12HostFunctionPA_fS0_S0_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 48(%rsp)
movl %ecx, %r15d
movl %r8d, 60(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
testl %ecx, %ecx
jle .L17
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movslq %ecx, %r14
salq $2, %r14
movl $0, 56(%rsp)
.L18:
movq 24(%rsp), %r13
movq 16(%rsp), %r12
movq 8(%rsp), %rbp
movl $0, %ebx
.L19:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
movl $0x00000000, 0(%r13)
movl %ebx, %eax
addl $1, %ebx
addq %r14, %rbp
addq %r14, %r12
addq %r14, %r13
cmpl %ebx, %r15d
jne .L19
movl 56(%rsp), %ebx
leal 1(%rbx), %edx
addq $4, 8(%rsp)
addq $4, 16(%rsp)
addq $4, 24(%rsp)
cmpl %eax, %ebx
je .L17
movl %edx, 56(%rsp)
jmp .L18
.L17:
movl %r15d, %ebx
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 68(%rsp)
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 60(%rsp), %eax
movl %eax, 112(%rsp)
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC9(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2sil %xmm3, %eax
movl %eax, 124(%rsp)
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl 120(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movq 124(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L21:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq dsize(%rip), %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
jle .L22
movq 32(%rsp), %r10
movslq %r15d, %rax
leaq 0(,%rax,4), %rsi
movq 40(%rsp), %r13
addq %rsi, %r13
negq %rax
leaq 0(,%rax,4), %r11
movl $0, %ebp
movl $0, %r12d
jmp .L23
.L35:
movl 60(%rsp), %r8d
movl %r15d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
jmp .L21
.L29:
movl %eax, %edi
.L25:
movq %r8, %r9
leaq (%rcx,%r11), %rax
movq %r10, %rdx
pxor %xmm1, %xmm1
.L24:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq %rsi, %rdx
addq $4, %rax
cmpq %rcx, %rax
jne .L24
movss %xmm1, (%r9)
leal 1(%rdi), %eax
addq %rsi, %r8
addq %rsi, %rcx
cmpl %eax, %r15d
jne .L29
leal 1(%rbp), %eax
addq $4, %r10
addq $4, %rbx
cmpl %edi, %ebp
je .L30
movl %eax, %ebp
.L23:
movq %r13, %rcx
movq %rbx, %r8
movl %r12d, %edi
jmp .L25
.L30:
movl $0, %ecx
.L26:
movl $0, %eax
.L27:
movl %eax, %edx
addl $1, %eax
cmpl %edx, %edi
jne .L27
leal 1(%rcx), %eax
cmpl %ecx, %edi
je .L22
movl %eax, %ecx
jmp .L26
.L22:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12HostFunctionPA_fS0_S0_ii, .-_Z12HostFunctionPA_fS0_S0_ii
.section .rodata.str1.1
.LC10:
.string "Tile Width = %d:\n"
.LC11:
.string "N = %d\n"
.LC12:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $2, 16(%rsp)
movl $4, 20(%rsp)
movl $10, 24(%rsp)
movl $20, 28(%rsp)
movl $25, 32(%rsp)
movl $100, 48(%rsp)
movl $200, 52(%rsp)
movl $500, 56(%rsp)
movl $1500, 60(%rsp)
movl $5000, 64(%rsp)
movl $2, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %r14
leaq 64(%rsp), %r15
.L38:
movl (%r14), %r13d
movl %r13d, %ebx
imull %r13d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, dsize(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %r8d
movl %r13d, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
addq $4, %r14
cmpq %r14, %r15
jne .L38
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %r13
leaq 36(%rsp), %rax
movq %rax, 8(%rsp)
leaq .LC12(%rip), %r15
.L39:
movl 0(%r13), %r14d
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $100000000, dsize(%rip)
movl $100000000, %edi
call malloc@PLT
movq %rax, %r12
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $5000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r8d
movl $5000, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r13, 8(%rsp)
jne .L39
movq stdin(%rip), %rdi
call getc@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7MatMultPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7MatMultPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dsize
.bss
.align 8
.type dsize, @object
.size dsize, 8
dsize:
.zero 8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC9:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
cudaMalloc((void**)&pA, (N*N)*sizeof(float));
cudaMalloc((void**)&pB, (N*N)*sizeof(float));
cudaMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
cudaMemcpy(pA, A, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pB, B, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pC, C, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
cudaMemcpy(C, pC, (N*N)*sizeof(float), cudaMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
hipMalloc((void**)&pA, (N*N)*sizeof(float));
hipMalloc((void**)&pB, (N*N)*sizeof(float));
hipMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
hipMemcpy(pA, A, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pB, B, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pC, C, (N*N)*sizeof(float), hipMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
hipMemcpy(C, pC, (N*N)*sizeof(float), hipMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
hipFree(pA);
hipFree(pB);
hipFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
hipMalloc((void**)&pA, (N*N)*sizeof(float));
hipMalloc((void**)&pB, (N*N)*sizeof(float));
hipMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
hipMemcpy(pA, A, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pB, B, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pC, C, (N*N)*sizeof(float), hipMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
hipMemcpy(C, pC, (N*N)*sizeof(float), hipMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
hipFree(pA);
hipFree(pB);
hipFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7MatMultPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.p2align 8
.type _Z7MatMultPfS_S_ii,@function
_Z7MatMultPfS_S_ii:
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s9, 31
s_ashr_i32 s6, s8, 31
s_add_i32 s3, s9, s2
s_add_i32 s7, s8, s6
s_xor_b32 s3, s3, s2
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s5, 0, s3
v_mad_u64_u32 v[4:5], null, s15, s9, v[2:3]
s_xor_b32 s2, s6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s4, v1
v_mad_u64_u32 v[0:1], null, s14, s9, v[3:4]
v_mul_lo_u32 v1, v4, s8
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s7, s4
s_mul_i32 s5, s4, s3
s_add_i32 s6, s4, 1
s_sub_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s3, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
s_sub_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v7, 2, v3
v_max_i32_e32 v6, v0, v4
v_lshlrev_b32_e32 v4, 3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 16, v7
v_cmp_gt_i32_e32 vcc_lo, s8, v6
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v6, v1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v4, v7
v_add_nc_u32_e32 v8, v5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s3
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_2
s_mul_i32 s2, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, s2, v2
v_add_nc_u32_e32 v9, s2, v6
v_mad_u64_u32 v[11:12], null, v13, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v12, v10
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s2, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s2, s5, v10, s2
v_add_co_u32 v11, s2, s6, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_mov_b32 s2, 0
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v5
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_5:
v_add_nc_u32_e32 v10, s2, v4
s_add_i32 s2, s2, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_eq_u32 s2, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v3, v10, v11
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
v_mov_b32_e32 v3, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7MatMultPfS_S_ii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7MatMultPfS_S_ii, .Lfunc_end0-_Z7MatMultPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7MatMultPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7MatMultPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
hipMalloc((void**)&pA, (N*N)*sizeof(float));
hipMalloc((void**)&pB, (N*N)*sizeof(float));
hipMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
hipMemcpy(pA, A, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pB, B, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pC, C, (N*N)*sizeof(float), hipMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
hipMemcpy(C, pC, (N*N)*sizeof(float), hipMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
hipFree(pA);
hipFree(pB);
hipFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | .text
.file "kernel.hip"
.globl _Z22__device_stub__MatMultPfS_S_ii # -- Begin function _Z22__device_stub__MatMultPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__MatMultPfS_S_ii,@function
_Z22__device_stub__MatMultPfS_S_ii: # @_Z22__device_stub__MatMultPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__MatMultPfS_S_ii, .Lfunc_end0-_Z22__device_stub__MatMultPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 2 # 0x2
.long 4 # 0x4
.long 10 # 0xa
.long 20 # 0x14
.LCPI1_1:
.long 100 # 0x64
.long 200 # 0xc8
.long 500 # 0x1f4
.long 1500 # 0x5dc
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2,4,10,20]
movaps %xmm0, 32(%rsp)
movl $25, 48(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [100,200,500,1500]
movaps %xmm0, (%rsp)
movl $5000, 16(%rsp) # imm = 0x1388
movl $.L.str, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rsp,%r13,4), %ebx
movl %ebx, %r14d
imull %r14d, %r14d
shlq $2, %r14
movq %r14, dsize(%rip)
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
movl %ebx, %ecx
movl $2, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r14, %rdi
callq free
incq %r13
cmpq $4, %r13
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.critedge
# =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r13,4), %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq $100000000, dsize(%rip) # imm = 0x5F5E100
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r14
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r15
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r12
movl $.L.str.1, %edi
movl $5000, %esi # imm = 0x1388
xorl %eax, %eax
callq printf
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $5000, %ecx # imm = 0x1388
movl %ebx, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movl $10, %edi
callq putchar@PLT
incq %r13
cmpq $5, %r13
jne .LBB1_3
# %bb.4:
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12HostFunctionPA_fS0_S0_ii
.LCPI2_0:
.long 0x41200000 # float 10
.LCPI2_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.p2align 4, 0x90
.type _Z12HostFunctionPA_fS0_S0_ii,@function
_Z12HostFunctionPA_fS0_S0_ii: # @_Z12HostFunctionPA_fS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 52(%rsp) # 4-byte Spill
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %ecx, (%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB2_5
# %bb.1: # %.preheader98.lr.ph
movl (%rsp), %r14d # 4-byte Reload
leaq (,%r14,4), %rbx
xorl %eax, %eax
movq 64(%rsp), %r13 # 8-byte Reload
movq 72(%rsp), %r12 # 8-byte Reload
movq 80(%rsp), %r15 # 8-byte Reload
movq %r14, 88(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.preheader98
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movq %rax, 96(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%r13,%rbp)
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp)
movl $0, (%r15,%rbp)
addq %rbx, %rbp
decq %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
incq %rax
addq $4, %r15
addq $4, %r12
addq $4, %r13
movq 88(%rsp), %r14 # 8-byte Reload
cmpq %r14, %rax
jne .LBB2_2
.LBB2_5: # %._crit_edge101
movl (%rsp), %r15d # 4-byte Reload
movl %r15d, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 52(%rsp), %ebp # 4-byte Reload
movl %ebp, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r15d, 60(%rsp)
movl %ebp, 56(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # %._crit_edge111
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12HostFunctionPA_fS0_S0_ii, .Lfunc_end2-_Z12HostFunctionPA_fS0_S0_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z4absff
.LCPI3_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z4absff
.p2align 4, 0x90
.type _Z4absff,@function
_Z4absff: # @_Z4absff
.cfi_startproc
# %bb.0:
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end3:
.size _Z4absff, .Lfunc_end3-_Z4absff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7MatMultPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7MatMultPfS_S_ii,@object # @_Z7MatMultPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z7MatMultPfS_S_ii
.p2align 3, 0x0
_Z7MatMultPfS_S_ii:
.quad _Z22__device_stub__MatMultPfS_S_ii
.size _Z7MatMultPfS_S_ii, 8
.type dsize,@object # @dsize
.bss
.globl dsize
.p2align 3, 0x0
dsize:
.quad 0 # 0x0
.size dsize, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tile Width = %d:\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "N = %d\n"
.size .L.str.1, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Kernel matrix multiplication time: %f\n"
.size .L.str.3, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7MatMultPfS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__MatMultPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7MatMultPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7MatMultPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R5, c[0x0][0x17c] ; /* 0x00005f0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e2a0000209400 */
/*0050*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IADD3 R4, RZ, -R3, RZ ; /* 0x80000003ff047210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00d0*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc60000000000 */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*00f0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fe200078e00ff */
/*0110*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e260000002200 */
/*0120*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f44070 */
/*0150*/ IMAD R4, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007047a24 */
/* 0x001fd800078e0202 */
/*0160*/ @!P2 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x800000050000a210 */
/* 0x080fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0190*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f45270 */
/*01a0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*01b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2c0000002100 */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fc800000001ff */
/*01f0*/ @!P1 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b9224 */
/* 0x000fe200078e0a0b */
/*0200*/ @!P2 LOP3.LUT R11, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0baa12 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD R5, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005057a24 */
/* 0x001fd800078e0200 */
/*0230*/ @!P0 BRA 0xaf0 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R3, R11.reuse, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x040fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R6, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b067812 */
/* 0x000fe400078ec0ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f46070 */
/*0280*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f06270 */
/*0290*/ SHF.L.U32 R9, R2, 0x3, RZ ; /* 0x0000000302097819 */
/* 0x000fe400000006ff */
/*02a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc40003f25270 */
/*02b0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*02c0*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x178], !P0 ; /* 0x00005e0005007a0c */
/* 0x000fe40004701270 */
/*02d0*/ LEA R8, R0, R9, 0x2 ; /* 0x0000000900087211 */
/* 0x000fe200078e10ff */
/*02e0*/ @!P2 BRA 0x910 ; /* 0x000006200000a947 */
/* 0x000fea0003800000 */
/*02f0*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0300*/ IMAD R18, R4, c[0x0][0x178], R0 ; /* 0x00005e0004127a24 */
/* 0x000fe200078e0200 */
/*0310*/ IADD3 R20, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002147a10 */
/* 0x000fe20007ffe0ff */
/*0320*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0330*/ LEA R16, R13.reuse, R2, 0x1 ; /* 0x000000020d107211 */
/* 0x040fe200078e08ff */
/*0340*/ IMAD R14, R13, 0x3, R2 ; /* 0x000000030d0e7824 */
/* 0x000fe200078e0202 */
/*0350*/ BSSY B0, 0x910 ; /* 0x000005b000007945 */
/* 0x000fe20003800000 */
/*0360*/ IADD3 R10, -R11, R6, RZ ; /* 0x000000060b0a7210 */
/* 0x000fe20007ffe1ff */
/*0370*/ IMAD R12, R13, c[0x0][0x178], RZ ; /* 0x00005e000d0c7a24 */
/* 0x000fc400078e02ff */
/*0380*/ IMAD R9, R13.reuse, 0x3, R18 ; /* 0x000000030d097824 */
/* 0x040fe200078e0212 */
/*0390*/ LEA R13, R13, R18, 0x1 ; /* 0x000000120d0d7211 */
/* 0x000fe200078e08ff */
/*03a0*/ IMAD R19, R2, c[0x0][0x178], R5.reuse ; /* 0x00005e0002137a24 */
/* 0x100fe400078e0205 */
/*03b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD R23, R20, c[0x0][0x178], R5.reuse ; /* 0x00005e0014177a24 */
/* 0x100fe400078e0205 */
/*03d0*/ IMAD R21, R14, c[0x0][0x178], R5.reuse ; /* 0x00005e000e157a24 */
/* 0x100fe400078e0205 */
/*03e0*/ IMAD R11, R16, c[0x0][0x178], R5 ; /* 0x00005e00100b7a24 */
/* 0x000fc400078e0205 */
/*03f0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff100424 */
/* 0x000fc800078e00ff */
/*0400*/ @P0 IMAD.WIDE.U32 R14, R18, R16, c[0x0][0x160] ; /* 0x00005800120e0625 */
/* 0x000fc800078e0010 */
/*0410*/ @P0 IMAD.WIDE.U32 R16, R19, R16, c[0x0][0x168] ; /* 0x00005a0013100625 */
/* 0x000fe200078e0010 */
/*0420*/ @P0 LDG.E R25, [R14.64] ; /* 0x000000040e190981 */
/* 0x0000a8000c1e1900 */
/*0430*/ @P0 LDG.E R27, [R16.64] ; /* 0x00000004101b0981 */
/* 0x0002e2000c1e1900 */
/*0440*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0450*/ @P0 IADD3 R20, R18, c[0x0][0x17c], RZ ; /* 0x00005f0012140a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ @P0 MOV R22, 0x4 ; /* 0x0000000400160802 */
/* 0x000fca0000000f00 */
/*0470*/ @P0 IMAD.WIDE.U32 R14, R20, R22, c[0x0][0x160] ; /* 0x00005800140e0625 */
/* 0x001fc800078e0016 */
/*0480*/ @P0 IMAD.WIDE.U32 R16, R23, R22, c[0x0][0x168] ; /* 0x00005a0017100625 */
/* 0x002fe200078e0016 */
/*0490*/ @P0 STS [R8], R25 ; /* 0x0000001908000388 */
/* 0x004fe80000000800 */
/*04a0*/ @P0 STS [R8+0x10], R27 ; /* 0x0000101b08000388 */
/* 0x0081e80000000800 */
/*04b0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04c0*/ @P0 LDS R26, [R0.X4+0x10] ; /* 0x00001000001a0984 */
/* 0x000fe80000004800 */
/*04d0*/ @P0 LDS R24, [R2.X8] ; /* 0x0000000002180984 */
/* 0x000e680000008800 */
/*04e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04f0*/ @P0 LDS R28, [R0.X4+0x18] ; /* 0x00001800001c0984 */
/* 0x000fe80000004800 */
/*0500*/ @P0 LDS R25, [R2.X8+0x4] ; /* 0x0000040002190984 */
/* 0x000ea80000008800 */
/*0510*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0520*/ @P0 LDG.E R27, [R14.64] ; /* 0x000000040e1b0981 */
/* 0x0010e8000c1e1900 */
/*0530*/ @P0 LDG.E R29, [R16.64] ; /* 0x00000004101d0981 */
/* 0x000962000c1e1900 */
/*0540*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0550*/ @P0 FFMA R24, R26, R24, R3 ; /* 0x000000181a180223 */
/* 0x002fc80000000003 */
/*0560*/ @P0 FFMA R3, R28, R25, R24 ; /* 0x000000191c030223 */
/* 0x004fe20000000018 */
/*0570*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0580*/ @P0 IMAD.WIDE.U32 R14, R13, R16, c[0x0][0x160] ; /* 0x000058000d0e0625 */
/* 0x001fc800078e0010 */
/*0590*/ @P0 IMAD.WIDE.U32 R16, R11, R16, c[0x0][0x168] ; /* 0x00005a000b100625 */
/* 0x000fe200078e0010 */
/*05a0*/ @P0 STS [R8], R27 ; /* 0x0000001b08000388 */
/* 0x008fe80000000800 */
/*05b0*/ @P0 STS [R8+0x10], R29 ; /* 0x0000101d08000388 */
/* 0x0201e80000000800 */
/*05c0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*05d0*/ @P0 LDS R20, [R0.X4+0x10] ; /* 0x0000100000140984 */
/* 0x000fe80000004800 */
/*05e0*/ @P0 LDS R22, [R2.X8] ; /* 0x0000000002160984 */
/* 0x000e680000008800 */
/*05f0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0600*/ @P0 LDS R27, [R0.X4+0x18] ; /* 0x00001800001b0984 */
/* 0x000fe80000004800 */
/*0610*/ @P0 LDS R26, [R2.X8+0x4] ; /* 0x00000400021a0984 */
/* 0x000ea80000008800 */
/*0620*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0630*/ @P0 LDG.E R29, [R14.64] ; /* 0x000000040e1d0981 */
/* 0x0010e8000c1e1900 */
/*0640*/ @P0 LDG.E R28, [R16.64] ; /* 0x00000004101c0981 */
/* 0x000962000c1e1900 */
/*0650*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0660*/ @P0 FFMA R20, R20, R22, R3 ; /* 0x0000001614140223 */
/* 0x002fc80000000003 */
/*0670*/ @P0 FFMA R3, R27, R26, R20 ; /* 0x0000001a1b030223 */
/* 0x004fe20000000014 */
/*0680*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0690*/ @P0 IMAD.WIDE.U32 R14, R9, R16, c[0x0][0x160] ; /* 0x00005800090e0625 */
/* 0x001fc800078e0010 */
/*06a0*/ @P0 IMAD.WIDE.U32 R16, R21, R16, c[0x0][0x168] ; /* 0x00005a0015100625 */
/* 0x000fe200078e0010 */
/*06b0*/ @P0 STS [R8], R29 ; /* 0x0000001d08000388 */
/* 0x008fe80000000800 */
/*06c0*/ @P0 STS [R8+0x10], R28 ; /* 0x0000101c08000388 */
/* 0x020fe80000000800 */
/*06d0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*06e0*/ @P0 LDS R24, [R0.X4+0x10] ; /* 0x0000100000180984 */
/* 0x000fe80000004800 */
/*06f0*/ @P0 LDS R25, [R2.X8] ; /* 0x0000000002190984 */
/* 0x000e280000008800 */
/*0700*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0710*/ @P0 LDS R20, [R0.X4+0x18] ; /* 0x0000180000140984 */
/* 0x000fe80000004800 */
/*0720*/ @P0 LDS R27, [R2.X8+0x4] ; /* 0x00000400021b0984 */
/* 0x000e680000008800 */
/*0730*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0740*/ @P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f0981 */
/* 0x0004e8000c1e1900 */
/*0750*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000410110981 */
/* 0x000962000c1e1900 */
/*0760*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0770*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0780*/ @P0 FFMA R24, R24, R25, R3 ; /* 0x0000001918180223 */
/* 0x001fe20000000003 */
/*0790*/ LEA R23, R12.reuse, R23, 0x2 ; /* 0x000000170c177211 */
/* 0x040fe200078e10ff */
/*07a0*/ IMAD R21, R12.reuse, 0x4, R21 ; /* 0x000000040c157824 */
/* 0x040fe200078e0215 */
/*07b0*/ LEA R19, R12, R19, 0x2 ; /* 0x000000130c137211 */
/* 0x000fe200078e10ff */
/*07c0*/ IMAD.IADD R14, R10, 0x1, R7 ; /* 0x000000010a0e7824 */
/* 0x004fe200078e0207 */
/*07d0*/ LEA R11, R12, R11, 0x2 ; /* 0x0000000b0c0b7211 */
/* 0x000fe200078e10ff */
/*07e0*/ @P0 FFMA R3, R20, R27, R24 ; /* 0x0000001b14030223 */
/* 0x002fe20000000018 */
/*07f0*/ MOV R16, c[0x0][0x17c] ; /* 0x00005f0000107a02 */
/* 0x010fc40000000f00 */
/*0800*/ ISETP.NE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f45270 */
/*0810*/ LEA R9, R16.reuse, R9, 0x2 ; /* 0x0000000910097211 */
/* 0x040fe200078e10ff */
/*0820*/ IMAD R18, R16.reuse, 0x4, R18 ; /* 0x0000000410127824 */
/* 0x040fe200078e0212 */
/*0830*/ LEA R13, R16, R13, 0x2 ; /* 0x0000000d100d7211 */
/* 0x000fe200078e10ff */
/*0840*/ @P0 STS [R8], R15 ; /* 0x0000000f08000388 */
/* 0x008fe80000000800 */
/*0850*/ @P0 STS [R8+0x10], R17 ; /* 0x0000101108000388 */
/* 0x020fe80000000800 */
/*0860*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0870*/ @P0 LDS R22, [R0.X4+0x10] ; /* 0x0000100000160984 */
/* 0x000fe80000004800 */
/*0880*/ @P0 LDS R26, [R2.X8] ; /* 0x00000000021a0984 */
/* 0x000e280000008800 */
/*0890*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08a0*/ @P0 LDS R29, [R0.X4+0x18] ; /* 0x00001800001d0984 */
/* 0x000fe80000004800 */
/*08b0*/ @P0 LDS R28, [R2.X8+0x4] ; /* 0x00000400021c0984 */
/* 0x000e620000008800 */
/*08c0*/ @P0 FFMA R22, R22, R26, R3 ; /* 0x0000001a16160223 */
/* 0x001fc80000000003 */
/*08d0*/ @P0 FFMA R3, R29, R28, R22 ; /* 0x0000001c1d030223 */
/* 0x002fe20000000016 */
/*08e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08f0*/ @P2 BRA 0x3f0 ; /* 0xfffffaf000002947 */
/* 0x000fea000383ffff */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ BSSY B0, 0xaf0 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0920*/ @!P1 BRA 0xae0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R10, R7.reuse, c[0x0][0x17c], R2 ; /* 0x00005f00070a7a24 */
/* 0x040fe400078e0202 */
/*0940*/ IMAD R7, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007077a24 */
/* 0x000fc400078e0200 */
/*0950*/ IMAD R9, R10, c[0x0][0x178], R5 ; /* 0x00005e000a097a24 */
/* 0x000fe400078e0205 */
/*0960*/ IMAD R7, R4, c[0x0][0x178], R7 ; /* 0x00005e0004077a24 */
/* 0x000fe400078e0207 */
/*0970*/ @P0 MOV R12, 0x4 ; /* 0x00000004000c0802 */
/* 0x000fca0000000f00 */
/*0980*/ @P0 IMAD.WIDE.U32 R10, R7, R12, c[0x0][0x160] ; /* 0x00005800070a0625 */
/* 0x000fc800078e000c */
/*0990*/ @P0 IMAD.WIDE.U32 R12, R9, R12, c[0x0][0x168] ; /* 0x00005a00090c0625 */
/* 0x000fe400078e000c */
/*09a0*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b0981 */
/* 0x0000a8000c1e1900 */
/*09b0*/ @P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d0981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*09d0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R7, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007077a10 */
/* 0x000fc40007ffe0ff */
/*09f0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0a00*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x001fca0000000f00 */
/*0a10*/ IMAD R9, R10, c[0x0][0x178], R9 ; /* 0x00005e000a097a24 */
/* 0x000fe200078e0209 */
/*0a20*/ @P0 STS [R8], R11 ; /* 0x0000000b08000388 */
/* 0x004fe80000000800 */
/*0a30*/ @P0 STS [R8+0x10], R13 ; /* 0x0000100d08000388 */
/* 0x008fe80000000800 */
/*0a40*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a50*/ @P0 LDS R14, [R0.X4+0x10] ; /* 0x00001000000e0984 */
/* 0x000fe80000004800 */
/*0a60*/ @P0 LDS R15, [R2.X8] ; /* 0x00000000020f0984 */
/* 0x000e280000008800 */
/*0a70*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a80*/ @P0 LDS R17, [R0.X4+0x18] ; /* 0x0000180000110984 */
/* 0x000fe80000004800 */
/*0a90*/ @P0 LDS R16, [R2.X8+0x4] ; /* 0x0000040002100984 */
/* 0x000e620000008800 */
/*0aa0*/ @P0 FFMA R14, R14, R15, R3 ; /* 0x0000000f0e0e0223 */
/* 0x001fc80000000003 */
/*0ab0*/ @P0 FFMA R3, R17, R16, R14 ; /* 0x0000001011030223 */
/* 0x002fe2000000000e */
/*0ac0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0ad0*/ @P1 BRA 0x970 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe20000000f00 */
/*0b00*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x000fc800078e0205 */
/*0b10*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0207 */
/*0b20*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7MatMultPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.p2align 8
.type _Z7MatMultPfS_S_ii,@function
_Z7MatMultPfS_S_ii:
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s9, 31
s_ashr_i32 s6, s8, 31
s_add_i32 s3, s9, s2
s_add_i32 s7, s8, s6
s_xor_b32 s3, s3, s2
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s5, 0, s3
v_mad_u64_u32 v[4:5], null, s15, s9, v[2:3]
s_xor_b32 s2, s6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s4, v1
v_mad_u64_u32 v[0:1], null, s14, s9, v[3:4]
v_mul_lo_u32 v1, v4, s8
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s7, s4
s_mul_i32 s5, s4, s3
s_add_i32 s6, s4, 1
s_sub_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s3, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
s_sub_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v7, 2, v3
v_max_i32_e32 v6, v0, v4
v_lshlrev_b32_e32 v4, 3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 16, v7
v_cmp_gt_i32_e32 vcc_lo, s8, v6
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v6, v1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v4, v7
v_add_nc_u32_e32 v8, v5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s3
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_2
s_mul_i32 s2, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, s2, v2
v_add_nc_u32_e32 v9, s2, v6
v_mad_u64_u32 v[11:12], null, v13, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v12, v10
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s2, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s2, s5, v10, s2
v_add_co_u32 v11, s2, s6, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_mov_b32 s2, 0
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v5
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_5:
v_add_nc_u32_e32 v10, s2, v4
s_add_i32 s2, s2, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_eq_u32 s2, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v3, v10, v11
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
v_mov_b32_e32 v3, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7MatMultPfS_S_ii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7MatMultPfS_S_ii, .Lfunc_end0-_Z7MatMultPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7MatMultPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7MatMultPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00139677_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4absff
.type _Z4absff, @function
_Z4absff:
.LFB2059:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L7
.L4:
ret
.L7:
xorps .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE2059:
.size _Z4absff, .-_Z4absff
.globl _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7MatMultPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.type _Z7MatMultPfS_S_ii, @function
_Z7MatMultPfS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7MatMultPfS_S_ii, .-_Z7MatMultPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Kernel matrix multiplication time: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "TEST PASSED\n"
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.type _Z12HostFunctionPA_fS0_S0_ii, @function
_Z12HostFunctionPA_fS0_S0_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 48(%rsp)
movl %ecx, %r15d
movl %r8d, 60(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
testl %ecx, %ecx
jle .L17
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movslq %ecx, %r14
salq $2, %r14
movl $0, 56(%rsp)
.L18:
movq 24(%rsp), %r13
movq 16(%rsp), %r12
movq 8(%rsp), %rbp
movl $0, %ebx
.L19:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
movl $0x00000000, 0(%r13)
movl %ebx, %eax
addl $1, %ebx
addq %r14, %rbp
addq %r14, %r12
addq %r14, %r13
cmpl %ebx, %r15d
jne .L19
movl 56(%rsp), %ebx
leal 1(%rbx), %edx
addq $4, 8(%rsp)
addq $4, 16(%rsp)
addq $4, 24(%rsp)
cmpl %eax, %ebx
je .L17
movl %edx, 56(%rsp)
jmp .L18
.L17:
movl %r15d, %ebx
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 68(%rsp)
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 60(%rsp), %eax
movl %eax, 112(%rsp)
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC9(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2sil %xmm3, %eax
movl %eax, 124(%rsp)
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl 120(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movq 124(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L21:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq dsize(%rip), %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
jle .L22
movq 32(%rsp), %r10
movslq %r15d, %rax
leaq 0(,%rax,4), %rsi
movq 40(%rsp), %r13
addq %rsi, %r13
negq %rax
leaq 0(,%rax,4), %r11
movl $0, %ebp
movl $0, %r12d
jmp .L23
.L35:
movl 60(%rsp), %r8d
movl %r15d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
jmp .L21
.L29:
movl %eax, %edi
.L25:
movq %r8, %r9
leaq (%rcx,%r11), %rax
movq %r10, %rdx
pxor %xmm1, %xmm1
.L24:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq %rsi, %rdx
addq $4, %rax
cmpq %rcx, %rax
jne .L24
movss %xmm1, (%r9)
leal 1(%rdi), %eax
addq %rsi, %r8
addq %rsi, %rcx
cmpl %eax, %r15d
jne .L29
leal 1(%rbp), %eax
addq $4, %r10
addq $4, %rbx
cmpl %edi, %ebp
je .L30
movl %eax, %ebp
.L23:
movq %r13, %rcx
movq %rbx, %r8
movl %r12d, %edi
jmp .L25
.L30:
movl $0, %ecx
.L26:
movl $0, %eax
.L27:
movl %eax, %edx
addl $1, %eax
cmpl %edx, %edi
jne .L27
leal 1(%rcx), %eax
cmpl %ecx, %edi
je .L22
movl %eax, %ecx
jmp .L26
.L22:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12HostFunctionPA_fS0_S0_ii, .-_Z12HostFunctionPA_fS0_S0_ii
.section .rodata.str1.1
.LC10:
.string "Tile Width = %d:\n"
.LC11:
.string "N = %d\n"
.LC12:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $2, 16(%rsp)
movl $4, 20(%rsp)
movl $10, 24(%rsp)
movl $20, 28(%rsp)
movl $25, 32(%rsp)
movl $100, 48(%rsp)
movl $200, 52(%rsp)
movl $500, 56(%rsp)
movl $1500, 60(%rsp)
movl $5000, 64(%rsp)
movl $2, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %r14
leaq 64(%rsp), %r15
.L38:
movl (%r14), %r13d
movl %r13d, %ebx
imull %r13d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, dsize(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %r8d
movl %r13d, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
addq $4, %r14
cmpq %r14, %r15
jne .L38
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %r13
leaq 36(%rsp), %rax
movq %rax, 8(%rsp)
leaq .LC12(%rip), %r15
.L39:
movl 0(%r13), %r14d
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $100000000, dsize(%rip)
movl $100000000, %edi
call malloc@PLT
movq %rax, %r12
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $5000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r8d
movl $5000, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r13, 8(%rsp)
jne .L39
movq stdin(%rip), %rdi
call getc@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7MatMultPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7MatMultPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dsize
.bss
.align 8
.type dsize, @object
.size dsize, 8
dsize:
.zero 8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC9:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z22__device_stub__MatMultPfS_S_ii # -- Begin function _Z22__device_stub__MatMultPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__MatMultPfS_S_ii,@function
_Z22__device_stub__MatMultPfS_S_ii: # @_Z22__device_stub__MatMultPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__MatMultPfS_S_ii, .Lfunc_end0-_Z22__device_stub__MatMultPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 2 # 0x2
.long 4 # 0x4
.long 10 # 0xa
.long 20 # 0x14
.LCPI1_1:
.long 100 # 0x64
.long 200 # 0xc8
.long 500 # 0x1f4
.long 1500 # 0x5dc
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2,4,10,20]
movaps %xmm0, 32(%rsp)
movl $25, 48(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [100,200,500,1500]
movaps %xmm0, (%rsp)
movl $5000, 16(%rsp) # imm = 0x1388
movl $.L.str, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rsp,%r13,4), %ebx
movl %ebx, %r14d
imull %r14d, %r14d
shlq $2, %r14
movq %r14, dsize(%rip)
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
movl %ebx, %ecx
movl $2, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r14, %rdi
callq free
incq %r13
cmpq $4, %r13
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.critedge
# =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r13,4), %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq $100000000, dsize(%rip) # imm = 0x5F5E100
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r14
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r15
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r12
movl $.L.str.1, %edi
movl $5000, %esi # imm = 0x1388
xorl %eax, %eax
callq printf
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $5000, %ecx # imm = 0x1388
movl %ebx, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movl $10, %edi
callq putchar@PLT
incq %r13
cmpq $5, %r13
jne .LBB1_3
# %bb.4:
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12HostFunctionPA_fS0_S0_ii
.LCPI2_0:
.long 0x41200000 # float 10
.LCPI2_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.p2align 4, 0x90
.type _Z12HostFunctionPA_fS0_S0_ii,@function
_Z12HostFunctionPA_fS0_S0_ii: # @_Z12HostFunctionPA_fS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 52(%rsp) # 4-byte Spill
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %ecx, (%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB2_5
# %bb.1: # %.preheader98.lr.ph
movl (%rsp), %r14d # 4-byte Reload
leaq (,%r14,4), %rbx
xorl %eax, %eax
movq 64(%rsp), %r13 # 8-byte Reload
movq 72(%rsp), %r12 # 8-byte Reload
movq 80(%rsp), %r15 # 8-byte Reload
movq %r14, 88(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.preheader98
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movq %rax, 96(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%r13,%rbp)
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp)
movl $0, (%r15,%rbp)
addq %rbx, %rbp
decq %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
incq %rax
addq $4, %r15
addq $4, %r12
addq $4, %r13
movq 88(%rsp), %r14 # 8-byte Reload
cmpq %r14, %rax
jne .LBB2_2
.LBB2_5: # %._crit_edge101
movl (%rsp), %r15d # 4-byte Reload
movl %r15d, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 52(%rsp), %ebp # 4-byte Reload
movl %ebp, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r15d, 60(%rsp)
movl %ebp, 56(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # %._crit_edge111
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12HostFunctionPA_fS0_S0_ii, .Lfunc_end2-_Z12HostFunctionPA_fS0_S0_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z4absff
.LCPI3_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z4absff
.p2align 4, 0x90
.type _Z4absff,@function
_Z4absff: # @_Z4absff
.cfi_startproc
# %bb.0:
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end3:
.size _Z4absff, .Lfunc_end3-_Z4absff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7MatMultPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7MatMultPfS_S_ii,@object # @_Z7MatMultPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z7MatMultPfS_S_ii
.p2align 3, 0x0
_Z7MatMultPfS_S_ii:
.quad _Z22__device_stub__MatMultPfS_S_ii
.size _Z7MatMultPfS_S_ii, 8
.type dsize,@object # @dsize
.bss
.globl dsize
.p2align 3, 0x0
dsize:
.quad 0 # 0x0
.size dsize, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tile Width = %d:\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "N = %d\n"
.size .L.str.1, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Kernel matrix multiplication time: %f\n"
.size .L.str.3, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7MatMultPfS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__MatMultPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7MatMultPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | code for sm_80
Function : _Z8vvlatbndiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R10 ; /* 0x0000010007077a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff087624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.NE.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe20003f05270 */
/*00c0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00d0*/ IADD3 R2, R7, -0x1, RZ ; /* 0xffffffff07027810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fe40007ffe0ff */
/*0100*/ SEL R3, R2, RZ, P0 ; /* 0x000000ff02037207 */
/* 0x000fe40000000000 */
/*0110*/ ISETP.NE.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fc60003f25270 */
/*0120*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fd400078e0200 */
/*0130*/ @P1 IADD3 R4, R7, 0x1, RZ ; /* 0x0000000107041810 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD R2, R4, c[0x0][0x160], R0 ; /* 0x0000580004027a24 */
/* 0x000fe400078e0200 */
/*0150*/ IMAD.WIDE.U32 R4, R3, R11, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e000b */
/*0160*/ IMAD.WIDE.U32 R2, R2, R11.reuse, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x080fe400078e000b */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R6, R7.reuse, c[0x0][0x160], R0 ; /* 0x0000580007067a24 */
/* 0x040fe200078e0200 */
/*01b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*01c0*/ IMAD R10, R9, 0x10, R10 ; /* 0x00000010090a7824 */
/* 0x000fe200078e020a */
/*01d0*/ ISETP.NE.AND P1, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe20003f25270 */
/*01e0*/ IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e000b */
/*01f0*/ STS [R10.X4+0x400], R5 ; /* 0x000400050a007388 */
/* 0x0041e80000004800 */
/*0200*/ STS [R10.X4], R3 ; /* 0x000000030a007388 */
/* 0x0081e80000004800 */
/*0210*/ @!P0 STG.E [R6.64], R3 ; /* 0x0000000306008986 */
/* 0x0001e2000c101904 */
/*0220*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0230*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | .file "tmpxft_0014341b_00000000-6_vvlatbnd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4signf
.type _Z4signf, @function
_Z4signf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4signf, .-_Z4signf
.globl _Z7mminus2ii
.type _Z7mminus2ii, @function
_Z7mminus2ii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z7mminus2ii, .-_Z7mminus2ii
.globl _Z5pplusii
.type _Z5pplusii, @function
_Z5pplusii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5pplusii, .-_Z5pplusii
.globl _Z6mminusii
.type _Z6mminusii, @function
_Z6mminusii:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z6mminusii, .-_Z6mminusii
.globl _Z29__device_stub__Z8vvlatbndiiPfiiPf
.type _Z29__device_stub__Z8vvlatbndiiPfiiPf, @function
_Z29__device_stub__Z8vvlatbndiiPfiiPf:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8vvlatbndiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z8vvlatbndiiPfiiPf, .-_Z29__device_stub__Z8vvlatbndiiPfiiPf
.globl _Z8vvlatbndiiPf
.type _Z8vvlatbndiiPf, @function
_Z8vvlatbndiiPf:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8vvlatbndiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z8vvlatbndiiPf, .-_Z8vvlatbndiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8vvlatbndiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vvlatbndiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl uuavg
.bss
.align 4
.type uuavg, @object
.size uuavg, 4
uuavg:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8vvlatbndiiPf
.globl _Z8vvlatbndiiPf
.p2align 8
.type _Z8vvlatbndiiPf,@function
_Z8vvlatbndiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_cmp_gt_u32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
v_sub_nc_u32_e64 v4, v0, 1 clamp
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s4, v[3:4]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s4, v[3:4]
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_add_i32 s3, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e64 v2, 1, s3, vcc_lo
v_mad_u64_u32 v[5:6], null, v2, s4, v[3:4]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[5:6]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v5, v[2:3], off
v_mov_b32_e32 v2, v6
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s5, -2
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vvlatbndiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8vvlatbndiiPf, .Lfunc_end0-_Z8vvlatbndiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vvlatbndiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8vvlatbndiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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