system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifdef _WIN32
# define NOMINMAX
#endif
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// includes, project
// includes, kernels
#include <hip/hip_runtime.h>
#define MAX_TILE_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
double* read_array(const char* filename, int len) {
double *x = (double*) malloc(len * sizeof(double));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%lf", &x[i]);
}
fclose(fp);
return x;
}
__global__ void computeOnDevice(double* dA,double* dB, double* dC, int nRows, int tileSize, float* incTime)
{
__shared__ float ds_M[MAX_TILE_SIZE];
__shared__ float ds_N[MAX_TILE_SIZE];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * tileSize + ty,
Col = bx * tileSize + tx;
double Pvalue = 0;
for (int m = 0; m < (nRows-1)/tileSize+1; ++m) {
if (Row < nRows && m*tileSize+tx < nRows)
ds_M[ty * tileSize + tx] = dA[Row*nRows + m*tileSize+tx];
else
ds_M[ty * tileSize + tx] = 0;
if (Col < nRows && m*tileSize+ty < nRows)
ds_N[ty * tileSize + tx] = dB[(m*tileSize+ty)*nRows+Col];
else
ds_N[ty * tileSize + tx] = 0;
__syncthreads();
for (int k = 0; k < tileSize; ++k)
Pvalue += ds_M[ty * tileSize + k] * ds_N[k * tileSize + tx];
__syncthreads();
}
if (Row < nRows && Col < nRows)
dC[Row*nRows+Col] = Pvalue;
return;//Placeholder
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
if(argc!=2)
{
printf("Usage: ./problem2 N\n");
return 0;
}
int nRows = 1024;
int num_elements = nRows*nRows;
int tileSize = atoi(argv[1]); //change this for scaling analysis
float incTime=0; // Time for GPU
double* hA = read_array("inputA.inp",num_elements);
double* hB = read_array("inputB.inp",num_elements);
double* hC = (double*) malloc(num_elements * sizeof(double));
dim3 dimGrid((nRows - 1) / tileSize + 1, (nRows - 1) / tileSize + 1, 1);
dim3 dimBlock(tileSize, tileSize, 1);
double * dA, *dB, *dC;
hipError_t error = hipMalloc((void**)&dA, sizeof(double)*num_elements);
error = hipMalloc((void**)&dB, sizeof(double)*num_elements);
error = hipMalloc((void**)&dC, sizeof(double)*num_elements);
hipMemcpy(dA, hA, sizeof(double)*num_elements, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, sizeof(double)*num_elements, hipMemcpyHostToDevice);
hipEvent_t startEvent_inc, stopEvent_inc;
hipEventCreate(&startEvent_inc);
hipEventCreate(&stopEvent_inc);
hipEventRecord(startEvent_inc,0); // starting timing for inclusive
// **===-------- Modify the body of this function -----------===**
computeOnDevice<<<dimGrid, dimBlock>>>(dA, dB, dC, nRows, tileSize, &incTime);
// **===-----------------------------------------------------------===**
hipDeviceSynchronize();
hipMemcpy(hC, dC, sizeof(double)*num_elements, hipMemcpyDeviceToHost);
hipEventRecord(stopEvent_inc,0); //ending timing for inclusive
hipEventSynchronize(stopEvent_inc);
hipEventElapsedTime(&incTime, startEvent_inc, stopEvent_inc);
printf("%lf\n%f\n%d\n",hC[num_elements - 1],incTime,tileSize);
// cleanup memory
free(hA);
free(hB);
free(hC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15computeOnDevicePdS_S_iiPf
.globl _Z15computeOnDevicePdS_S_iiPf
.p2align 8
.type _Z15computeOnDevicePdS_S_iiPf,@function
_Z15computeOnDevicePdS_S_iiPf:
s_load_b64 s[8:9], s[0:1], 0x18
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s9, 31
s_add_i32 s5, s8, -1
s_add_i32 s3, s9, s2
s_ashr_i32 s7, s5, 31
s_xor_b32 s3, s3, s2
s_add_i32 s5, s5, s7
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
s_xor_b32 s5, s5, s7
s_xor_b32 s2, s7, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s4, v1
v_mad_u64_u32 v[0:1], null, s15, s9, v[4:5]
v_mad_u64_u32 v[1:2], null, s14, s9, v[3:4]
s_mul_i32 s6, s6, s4
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_mul_hi_u32 s6, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s6
s_mul_hi_u32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s4, s3
s_sub_i32 s5, s5, s6
s_add_i32 s6, s4, 1
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s3, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
s_sub_i32 s10, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s10, 0
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v9, v4, s9
v_mad_u64_u32 v[7:8], null, v0, s8, v[3:4]
v_cmp_gt_i32_e64 s2, s8, v0
v_cmp_le_i32_e64 s12, s8, v0
v_cmp_gt_i32_e64 s3, s8, v1
v_cmp_le_i32_e64 s13, s8, v1
v_lshl_or_b32 v10, v3, 2, 0x1000
v_add_lshl_u32 v2, v9, v3, 2
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v11, 2, v9
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, 0x1000, v2
s_cmp_gt_i32 s9, 0
s_cselect_b32 s14, -1, 0
s_lshl_b32 s15, s9, 2
.LBB0_2:
s_mov_b32 s16, 0
s_mov_b32 s18, s12
s_and_saveexec_b32 s17, s2
s_mul_i32 s18, s11, s9
s_mov_b32 s16, exec_lo
v_dual_mov_b32 v14, s18 :: v_dual_add_nc_u32 v9, s18, v3
s_and_not1_b32 s18, s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v9
s_and_b32 s19, vcc_lo, exec_lo
s_or_b32 s18, s18, s19
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s17, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_6
s_and_not1_b32 s16, s16, exec_lo
ds_store_b32 v2, v13
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s17, s16
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v15, v7, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[15:16], 3, v[15:16]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
global_load_b64 v[15:16], v[15:16], off
s_waitcnt vmcnt(0)
v_cvt_f32_f64_e32 v9, v[15:16]
ds_store_b32 v2, v9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s17
s_mov_b32 s16, 0
s_mov_b32 s18, s13
s_and_saveexec_b32 s17, s3
v_mad_u64_u32 v[8:9], null, s11, s9, v[4:5]
s_and_not1_b32 s18, s13, exec_lo
s_mov_b32 s16, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v8
s_and_b32 s19, vcc_lo, exec_lo
s_or_b32 s18, s18, s19
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s17, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_12
s_and_not1_b32 s16, s16, exec_lo
ds_store_b32 v12, v13
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s17, s16
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[15:16], null, v8, s8, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[15:16], 3, v[15:16]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v15, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
global_load_b64 v[15:16], v[15:16], off
s_waitcnt vmcnt(0)
v_cvt_f32_f64_e32 v9, v[15:16]
ds_store_b32 v12, v9
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s17
v_mov_b32_e32 v9, v11
v_mov_b32_e32 v15, v10
s_and_not1_b32 vcc_lo, exec_lo, s14
s_mov_b32 s16, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_16
.LBB0_15:
ds_load_b32 v16, v9
ds_load_b32 v17, v15
v_add_nc_u32_e32 v9, 4, v9
s_add_i32 s16, s16, -1
v_add_nc_u32_e32 v15, s15, v15
s_cmp_eq_u32 s16, 0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v16, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[16:17], v16
v_add_f64 v[5:6], v[5:6], v[16:17]
s_cbranch_scc0 .LBB0_15
.LBB0_16:
s_add_i32 s16, s11, 1
s_cmp_eq_u32 s11, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s11, s16
s_branch .LBB0_2
.LBB0_18:
v_max_i32_e32 v2, v0, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s8, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[5:6], off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15computeOnDevicePdS_S_iiPf
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15computeOnDevicePdS_S_iiPf, .Lfunc_end0-_Z15computeOnDevicePdS_S_iiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15computeOnDevicePdS_S_iiPf
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z15computeOnDevicePdS_S_iiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifdef _WIN32
# define NOMINMAX
#endif
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// includes, project
// includes, kernels
#include <hip/hip_runtime.h>
#define MAX_TILE_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
double* read_array(const char* filename, int len) {
double *x = (double*) malloc(len * sizeof(double));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%lf", &x[i]);
}
fclose(fp);
return x;
}
__global__ void computeOnDevice(double* dA,double* dB, double* dC, int nRows, int tileSize, float* incTime)
{
__shared__ float ds_M[MAX_TILE_SIZE];
__shared__ float ds_N[MAX_TILE_SIZE];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * tileSize + ty,
Col = bx * tileSize + tx;
double Pvalue = 0;
for (int m = 0; m < (nRows-1)/tileSize+1; ++m) {
if (Row < nRows && m*tileSize+tx < nRows)
ds_M[ty * tileSize + tx] = dA[Row*nRows + m*tileSize+tx];
else
ds_M[ty * tileSize + tx] = 0;
if (Col < nRows && m*tileSize+ty < nRows)
ds_N[ty * tileSize + tx] = dB[(m*tileSize+ty)*nRows+Col];
else
ds_N[ty * tileSize + tx] = 0;
__syncthreads();
for (int k = 0; k < tileSize; ++k)
Pvalue += ds_M[ty * tileSize + k] * ds_N[k * tileSize + tx];
__syncthreads();
}
if (Row < nRows && Col < nRows)
dC[Row*nRows+Col] = Pvalue;
return;//Placeholder
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
if(argc!=2)
{
printf("Usage: ./problem2 N\n");
return 0;
}
int nRows = 1024;
int num_elements = nRows*nRows;
int tileSize = atoi(argv[1]); //change this for scaling analysis
float incTime=0; // Time for GPU
double* hA = read_array("inputA.inp",num_elements);
double* hB = read_array("inputB.inp",num_elements);
double* hC = (double*) malloc(num_elements * sizeof(double));
dim3 dimGrid((nRows - 1) / tileSize + 1, (nRows - 1) / tileSize + 1, 1);
dim3 dimBlock(tileSize, tileSize, 1);
double * dA, *dB, *dC;
hipError_t error = hipMalloc((void**)&dA, sizeof(double)*num_elements);
error = hipMalloc((void**)&dB, sizeof(double)*num_elements);
error = hipMalloc((void**)&dC, sizeof(double)*num_elements);
hipMemcpy(dA, hA, sizeof(double)*num_elements, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, sizeof(double)*num_elements, hipMemcpyHostToDevice);
hipEvent_t startEvent_inc, stopEvent_inc;
hipEventCreate(&startEvent_inc);
hipEventCreate(&stopEvent_inc);
hipEventRecord(startEvent_inc,0); // starting timing for inclusive
// **===-------- Modify the body of this function -----------===**
computeOnDevice<<<dimGrid, dimBlock>>>(dA, dB, dC, nRows, tileSize, &incTime);
// **===-----------------------------------------------------------===**
hipDeviceSynchronize();
hipMemcpy(hC, dC, sizeof(double)*num_elements, hipMemcpyDeviceToHost);
hipEventRecord(stopEvent_inc,0); //ending timing for inclusive
hipEventSynchronize(stopEvent_inc);
hipEventElapsedTime(&incTime, startEvent_inc, stopEvent_inc);
printf("%lf\n%f\n%d\n",hC[num_elements - 1],incTime,tileSize);
// cleanup memory
free(hA);
free(hB);
free(hC);
return 0;
} | .text
.file "problem2.hip"
.globl _Z10read_arrayPKci # -- Begin function _Z10read_arrayPKci
.p2align 4, 0x90
.type _Z10read_arrayPKci,@function
_Z10read_arrayPKci: # @_Z10read_arrayPKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %rbx
movl $.L.str, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
testl %r15d, %r15d
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
movq %rbx, %r15
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r15
decq %r12
jne .LBB0_2
.LBB0_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10read_arrayPKci, .Lfunc_end0-_Z10read_arrayPKci
.cfi_endproc
# -- End function
.globl _Z30__device_stub__computeOnDevicePdS_S_iiPf # -- Begin function _Z30__device_stub__computeOnDevicePdS_S_iiPf
.p2align 4, 0x90
.type _Z30__device_stub__computeOnDevicePdS_S_iiPf,@function
_Z30__device_stub__computeOnDevicePdS_S_iiPf: # @_Z30__device_stub__computeOnDevicePdS_S_iiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15computeOnDevicePdS_S_iiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__computeOnDevicePdS_S_iiPf, .Lfunc_end1-_Z30__device_stub__computeOnDevicePdS_S_iiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $0, 12(%rsp)
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
movl $.L.str.3, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq (%r14,%r12), %rdx
movl $.L.str.1, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
cmpq $8388608, %r12 # imm = 0x800000
jne .LBB2_3
# %bb.4: # %_Z10read_arrayPKci.exit
movq %r15, %rdi
callq fclose
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
movl $.L.str.4, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i37
# =>This Inner Loop Header: Depth=1
leaq (%r15,%r13), %rdx
movl $.L.str.1, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r13
cmpq $8388608, %r13 # imm = 0x800000
jne .LBB2_5
# %bb.6: # %_Z10read_arrayPKci.exit41
movq %r12, %rdi
callq fclose
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r12
movl $1023, %eax # imm = 0x3FF
xorl %edx, %edx
idivl %ebx
# kill: def $eax killed $eax def $rax
incl %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
movl %ebx, %eax
movq %rbx, %rbp
shlq $32, %rbp
orq %rax, %rbp
leaq 56(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq 56(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
movl %ebx, 24(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z15computeOnDevicePdS_S_iiPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movsd 8388600(%r12), %xmm0 # xmm0 = mem[0],zero
movss 12(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.5, %edi
movl %ebx, %esi
movb $2, %al
callq printf
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
jmp .LBB2_9
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_9:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15computeOnDevicePdS_S_iiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf"
.size .L.str.1, 4
.type _Z15computeOnDevicePdS_S_iiPf,@object # @_Z15computeOnDevicePdS_S_iiPf
.section .rodata,"a",@progbits
.globl _Z15computeOnDevicePdS_S_iiPf
.p2align 3, 0x0
_Z15computeOnDevicePdS_S_iiPf:
.quad _Z30__device_stub__computeOnDevicePdS_S_iiPf
.size _Z15computeOnDevicePdS_S_iiPf, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "inputA.inp"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "inputB.inp"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lf\n%f\n%d\n"
.size .L.str.5, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15computeOnDevicePdS_S_iiPf"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./problem2 N"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__computeOnDevicePdS_S_iiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15computeOnDevicePdS_S_iiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169e73_00000000-6_problem2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%lf"
.text
.globl _Z10read_arrayPKci
.type _Z10read_arrayPKci, @function
_Z10read_arrayPKci:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebx
movslq %esi, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L4
movq %r14, %rbx
addq %r14, %rbp
leaq .LC1(%rip), %r13
.L5:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
movq %r12, %rdi
call fclose@PLT
movq %r14, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10read_arrayPKci, .-_Z10read_arrayPKci
.globl _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
.type _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf, @function
_Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15computeOnDevicePdS_S_iiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf, .-_Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
.globl _Z15computeOnDevicePdS_S_iiPf
.type _Z15computeOnDevicePdS_S_iiPf, @function
_Z15computeOnDevicePdS_S_iiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15computeOnDevicePdS_S_iiPf, .-_Z15computeOnDevicePdS_S_iiPf
.section .rodata.str1.1
.LC2:
.string "Usage: ./problem2 N\n"
.LC4:
.string "inputA.inp"
.LC5:
.string "inputB.inp"
.LC6:
.string "%lf\n%f\n%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L17
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L18:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movl $0x00000000, 4(%rsp)
movl $1048576, %esi
leaq .LC4(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %r13
movl $1048576, %esi
leaq .LC5(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %r12
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbp
movl $1023, %eax
movl $0, %edx
idivl %ebx
addl $1, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl %ebx, 60(%rsp)
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movsd 8388600(%rbp), %xmm0
movl %r14d, %edx
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
jmp .L18
.L23:
leaq 4(%rsp), %r9
movl %ebx, %r8d
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
jmp .L19
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z15computeOnDevicePdS_S_iiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15computeOnDevicePdS_S_iiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "problem2.hip"
.globl _Z10read_arrayPKci # -- Begin function _Z10read_arrayPKci
.p2align 4, 0x90
.type _Z10read_arrayPKci,@function
_Z10read_arrayPKci: # @_Z10read_arrayPKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %rbx
movl $.L.str, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
testl %r15d, %r15d
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
movq %rbx, %r15
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r15
decq %r12
jne .LBB0_2
.LBB0_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10read_arrayPKci, .Lfunc_end0-_Z10read_arrayPKci
.cfi_endproc
# -- End function
.globl _Z30__device_stub__computeOnDevicePdS_S_iiPf # -- Begin function _Z30__device_stub__computeOnDevicePdS_S_iiPf
.p2align 4, 0x90
.type _Z30__device_stub__computeOnDevicePdS_S_iiPf,@function
_Z30__device_stub__computeOnDevicePdS_S_iiPf: # @_Z30__device_stub__computeOnDevicePdS_S_iiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15computeOnDevicePdS_S_iiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__computeOnDevicePdS_S_iiPf, .Lfunc_end1-_Z30__device_stub__computeOnDevicePdS_S_iiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $0, 12(%rsp)
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
movl $.L.str.3, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq (%r14,%r12), %rdx
movl $.L.str.1, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
cmpq $8388608, %r12 # imm = 0x800000
jne .LBB2_3
# %bb.4: # %_Z10read_arrayPKci.exit
movq %r15, %rdi
callq fclose
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
movl $.L.str.4, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i37
# =>This Inner Loop Header: Depth=1
leaq (%r15,%r13), %rdx
movl $.L.str.1, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r13
cmpq $8388608, %r13 # imm = 0x800000
jne .LBB2_5
# %bb.6: # %_Z10read_arrayPKci.exit41
movq %r12, %rdi
callq fclose
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r12
movl $1023, %eax # imm = 0x3FF
xorl %edx, %edx
idivl %ebx
# kill: def $eax killed $eax def $rax
incl %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
movl %ebx, %eax
movq %rbx, %rbp
shlq $32, %rbp
orq %rax, %rbp
leaq 56(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq 56(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
movl %ebx, 24(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z15computeOnDevicePdS_S_iiPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movsd 8388600(%r12), %xmm0 # xmm0 = mem[0],zero
movss 12(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.5, %edi
movl %ebx, %esi
movb $2, %al
callq printf
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
jmp .LBB2_9
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_9:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15computeOnDevicePdS_S_iiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf"
.size .L.str.1, 4
.type _Z15computeOnDevicePdS_S_iiPf,@object # @_Z15computeOnDevicePdS_S_iiPf
.section .rodata,"a",@progbits
.globl _Z15computeOnDevicePdS_S_iiPf
.p2align 3, 0x0
_Z15computeOnDevicePdS_S_iiPf:
.quad _Z30__device_stub__computeOnDevicePdS_S_iiPf
.size _Z15computeOnDevicePdS_S_iiPf, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "inputA.inp"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "inputB.inp"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lf\n%f\n%d\n"
.size .L.str.5, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15computeOnDevicePdS_S_iiPf"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./problem2 N"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__computeOnDevicePdS_S_iiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15computeOnDevicePdS_S_iiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <cstdlib>
#include <cmath>
#include <string>
#include <chrono>
#include <cooperative_groups.h>
using namespace std;
#include <cuda.h>
#include <curand_kernel.h>
#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__); \
return EXIT_FAILURE;}} while(0)
#define N_PROP 1100
#define THREADS_PER_BLOCK 256
#define N_BLOCKS 1 //Needed to be equal to 1 for the correct synchronization between threads
__device__ float dC = 0.0f;
__device__ int random_int(curandState &crstate, int min, int max){
float myrandf = curand_uniform(&crstate);
myrandf *= (max - min + 0.999999);
myrandf += min;
return (int)truncf(myrandf);
}
__global__ void trainBM(const float* weights, unsigned *net_state, const unsigned int net_size,
const float temp_init, const float final_temp, const float cooling_rate, int seed) {
// Handle to thread block group
__shared__ float shared_weights_array[THREADS_PER_BLOCK];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int nodes_per_thread = ceil((float)net_size/(float)THREADS_PER_BLOCK);
int unit_index = 0;
float temperature = temp_init;
curandState crstate;
curand_init(seed, 0, 0, &crstate);
if( i<net_size ){
net_state[i] = random_int(crstate, 0, 1);
}
do{
__syncthreads();
for(unsigned r=0; r<N_PROP; r++){
unit_index = random_int(crstate, 0, net_size-1);
if( i == 0 ){
dC = 0.0f;
}
//if(i<3 && j<3) printf("%d\n", unit_index);
for(int k=0; k<nodes_per_thread; k++){
int j = k*THREADS_PER_BLOCK + i;
shared_weights_array[tid] = ( j<net_size && j!=unit_index) ? weights[unit_index*net_size+j]*net_state[j] : 0;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
shared_weights_array[tid] += shared_weights_array[tid + s];
}
__syncthreads();
}
if (tid == 0){
dC += shared_weights_array[0];
}
__syncthreads();
}
if (i == 0){
float probability = 1 / (1 + expf(-dC / temperature));
//printf("dC--------->%f\nPROBABILITY--------->%f\n", dC, probability);
if( curand_uniform(&crstate)<probability ){
net_state[unit_index]=1;
}else{
net_state[unit_index]=0;
}
}else{
skipahead(1, &crstate);
}
}
temperature*=cooling_rate;
if(i==0) printf("%f\n", temperature);
}while( temperature > final_temp );
}
/*Params: 1. Number of nodes for the network
2. Initial Temperature
3. Final Temperature
4. Cooling Rate
5. Path to the file with the weights matrix
6. Seed
*/
int main(int narg, char** arg){
if(narg != 7){
perror("Wrong number of arguments.");
exit(1);
}
auto start = chrono::high_resolution_clock::now();
const unsigned int NET_SIZE = atoi(arg[1]);
const float INITIAL_TEMPERATURE = atof(arg[2]);
const float FINAL_TEMPERATURE = atof(arg[3]);
const float COOL_RATE = atof(arg[4]);
const unsigned SEED = atoi(arg[5]);
unsigned* net_states = new unsigned [NET_SIZE];
srand(SEED);
for(int i=0; i<NET_SIZE; i++){
net_states[i] = rand() % 2;
}
float* weights = new float [NET_SIZE*NET_SIZE];
ifstream matrix_file(arg[6], ifstream::in);
for(int i=0; i<NET_SIZE; i++){
for(int j=0; j<NET_SIZE; j++){
string x;
matrix_file>>x;
weights[i*NET_SIZE+j] = strtof( x.c_str(), NULL );
}
}
auto start_gpu = chrono::high_resolution_clock::now();
//Moving data to GPU
unsigned* g_net_states;
CUDA_CALL( cudaMalloc((void **)&g_net_states, NET_SIZE*sizeof(unsigned)) );
//CUDA_CALL( cudaMemcpy(g_net_states, net_states, NET_SIZE*sizeof(unsigned), cudaMemcpyHostToDevice) );
float* g_weights;
CUDA_CALL( cudaMalloc((float **)&g_weights, NET_SIZE*NET_SIZE*sizeof(float*)) );
CUDA_CALL( cudaMemcpy(g_weights, weights, NET_SIZE*NET_SIZE*sizeof(float), cudaMemcpyHostToDevice) );
//Running kernel
unsigned threadsPerBlock = THREADS_PER_BLOCK;
unsigned blocksPerGrid = N_BLOCKS;
trainBM<<<blocksPerGrid, threadsPerBlock>>>(g_weights, g_net_states, NET_SIZE,
INITIAL_TEMPERATURE, FINAL_TEMPERATURE, COOL_RATE, SEED);
/*std::string error = cudaGetErrorString(cudaPeekAtLastError());
printf("%s\n", error.c_str());
error = cudaGetErrorString(cudaThreadSynchronize());
printf("%s\n", error.c_str());*/
//Moving result to CPU
CUDA_CALL( cudaMemcpy(net_states, g_net_states, NET_SIZE*sizeof(float), cudaMemcpyDeviceToHost) );
//Freeing GPU memory
CUDA_CALL( cudaFree(g_net_states) );
CUDA_CALL( cudaFree(g_weights) );
auto end_gpu = chrono::high_resolution_clock::now();
float C = 0;
for(int i=0; i<NET_SIZE; i++){
for(int j=i+1; j<NET_SIZE; j++){
if( net_states[i] & net_states[j] ) C += weights[i*NET_SIZE+j];
}
}
delete [] net_states;
delete [] weights;
auto end = chrono::high_resolution_clock::now();
cout<<"Final cost function: "<<C<<endl;
cout<<"GPU time: "<<chrono::duration_cast<chrono::milliseconds>(end_gpu-start_gpu).count()/1000.0f<<" seconds."<<endl;
cout<<"Total time: "<<chrono::duration_cast<chrono::milliseconds>(end-start).count()/1000.0f<<" seconds."<<endl;
return 0;
} | .file "tmpxft_000d85cd_00000000-6_boltzmannGPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB7207:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7207:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10random_intR17curandStateXORWOWii
.type _Z10random_intR17curandStateXORWOWii, @function
_Z10random_intR17curandStateXORWOWii:
.LFB7200:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE7200:
.size _Z10random_intR17curandStateXORWOWii, .-_Z10random_intR17curandStateXORWOWii
.globl _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
.type _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi, @function
_Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi:
.LFB7229:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7trainBMPKfPjjfffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7229:
.size _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi, .-_Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
.globl _Z7trainBMPKfPjjfffi
.type _Z7trainBMPKfPjjfffi, @function
_Z7trainBMPKfPjjfffi:
.LFB7230:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7230:
.size _Z7trainBMPKfPjjfffi, .-_Z7trainBMPKfPjjfffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7trainBMPKfPjjfffi"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.LC10:
.string "dC"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_ZN40_INTERNAL_7eb18656_15_boltzmannGPU_cu_dC4cuda3std3__419piecewise_constructE"
.align 8
.LC12:
.string "_ZN40_INTERNAL_7eb18656_15_boltzmannGPU_cu_dC4cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC13:
.string "_ZN40_INTERNAL_7eb18656_15_boltzmannGPU_cu_dC4cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB7232:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7trainBMPKfPjjfffi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2dC(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7232:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC15:
.string "Wrong number of arguments."
.section .rodata.str1.8
.align 8
.LC16:
.string "/home/ubuntu/Datasets/stackv2/train-structured/aalonso99/CUDA-Classic-Boltzmann-Machine/master/boltzmannGPU.cu"
.section .rodata.str1.1
.LC17:
.string "Error at %s:%d\n"
.LC18:
.string "Final cost function: "
.LC19:
.string "GPU time: "
.LC21:
.string " seconds."
.LC22:
.string "Total time: "
.text
.globl main
.type main, @function
main:
.LFB7201:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA7201
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $712, %rsp
.cfi_def_cfa_offset 768
movq %fs:40, %rax
movq %rax, 696(%rsp)
xorl %eax, %eax
cmpl $7, %edi
jne .L61
movq %rsi, %rbx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 88(%rsp)
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movl %eax, %r15d
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq %rax, 56(%rsp)
movl %r14d, %eax
leaq 0(,%rax,4), %rcx
movq %rcx, 16(%rsp)
movq %rcx, %rdi
.LEHB0:
call _Znam@PLT
movq %rax, %rbp
movq %rax, 48(%rsp)
movl %r13d, %edi
call srand@PLT
testl %r14d, %r14d
je .L17
leal -1(%r14), %eax
leaq 4(%rbp,%rax,4), %r12
.L18:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L18
movq 24(%rsp), %r14
movl %r14d, %eax
imull %r14d, %eax
movq %rax, 32(%rsp)
salq $2, %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call _Znam@PLT
movq %rax, %r13
movq 48(%rbx), %rsi
leaq 176(%rsp), %rdi
movl $8, %edx
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
movl %r14d, 12(%rsp)
movl %r14d, %r12d
movl $0, 8(%rsp)
leaq 144(%rsp), %r14
jmp .L19
.L61:
leaq .LC15(%rip), %rdi
call perror@PLT
.LEHE0:
movl $1, %edi
call exit@PLT
.L63:
movl %ebx, %eax
leaq 0(%r13,%rax,4), %rbp
movl $0, %esi
movq 144(%rsp), %rdi
call strtof@PLT
movss %xmm0, 0(%rbp)
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L20
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L20:
addl $1, %ebx
cmpl %r12d, %ebx
je .L62
.L21:
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $0, 152(%rsp)
movb $0, 160(%rsp)
leaq 176(%rsp), %rdi
movq %r14, %rsi
.LEHB1:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE1:
jmp .L63
.L62:
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %r12d
movl 12(%rsp), %ecx
cmpl %ecx, %eax
je .L22
.L19:
movl %r12d, %ebx
subl %r15d, %ebx
jmp .L21
.L83:
testl %eax, %eax
jne .L64
movq 32(%rsp), %rsi
salq $3, %rsi
leaq 112(%rsp), %rdi
.LEHB2:
call cudaMalloc@PLT
jmp .L65
.L64:
movl $143, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L66
.L65:
testl %eax, %eax
jne .L67
movl $1, %ecx
movq 40(%rsp), %rdx
movq %r13, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L68
.L67:
movl $146, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L69
.L68:
testl %eax, %eax
jne .L70
movl $256, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
jmp .L71
.L70:
movl $147, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L72
.L71:
testl %eax, %eax
jne .L27
pxor %xmm0, %xmm0
cvtsd2ss 80(%rsp), %xmm0
movl 56(%rsp), %ecx
pxor %xmm2, %xmm2
cvtsd2ss 64(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movl %r15d, %edx
movq 104(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
.L27:
movl $2, %ecx
movq 16(%rsp), %rdx
movq 104(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L73
movq 104(%rsp), %rdi
call cudaFree@PLT
jmp .L74
.L73:
movl $161, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L75
.L74:
testl %eax, %eax
jne .L76
movq 112(%rsp), %rdi
call cudaFree@PLT
jmp .L77
.L76:
movl $164, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L78
.L77:
movl %eax, %ebp
testl %eax, %eax
jne .L79
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 24(%rsp), %rax
testl %eax, %eax
je .L45
movl %eax, %r8d
leal -1(%rax), %edi
addq $2, %rdi
movl $1, %esi
movl $0x00000000, 8(%rsp)
movq 48(%rsp), %rcx
jmp .L34
.L79:
movl $165, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L32:
addq $1, %rax
cmpl %r15d, %eax
jnb .L81
.L33:
movl %r9d, %edx
andl (%rcx,%rax,4), %edx
je .L32
leal 0(%rbp,%rax), %edx
movss 8(%rsp), %xmm3
addss 0(%r13,%rdx,4), %xmm3
movss %xmm3, 8(%rsp)
jmp .L32
.L81:
addq $1, %rsi
addl %r15d, %ebp
cmpq %rdi, %rsi
je .L31
.L34:
cmpq %r8, %rsi
je .L31
movl -4(%rcx,%rsi,4), %r9d
movq %rsi, %rax
jmp .L33
.L45:
movl $0x00000000, 8(%rsp)
.L31:
movq 48(%rsp), %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rax
subq %rbx, %rax
movl $1000000, %ecx
cqto
idivq %rcx
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rax
movq 88(%rsp), %rcx
subq %rcx, %rax
movl $1000000, %ecx
cqto
idivq %rcx
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
movl $0, %ebx
jmp .L24
.L66:
movl $1, %ebx
.L24:
leaq 176(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 696(%rsp), %rax
subq %fs:40, %rax
jne .L82
movl %ebx, %eax
addq $712, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
movl $1, %ebx
jmp .L24
.L72:
movl $1, %ebx
jmp .L24
.L75:
movl $1, %ebx
jmp .L24
.L78:
movl $1, %ebx
jmp .L24
.L80:
movl $1, %ebx
jmp .L24
.L46:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L36:
leaq 176(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 696(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L47:
endbr64
movq %rax, %rbx
jmp .L36
.L37:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.L17:
movl $0, %edi
call _Znam@PLT
movq %rax, %r13
movq 48(%rbx), %rsi
leaq 176(%rsp), %rdi
movl $8, %edx
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE3:
movq $0, 40(%rsp)
movq $0, 32(%rsp)
.L22:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq 104(%rsp), %rdi
movq 16(%rsp), %rsi
.LEHB4:
call cudaMalloc@PLT
.LEHE4:
jmp .L83
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7201:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA7201:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE7201-.LLSDACSB7201
.LLSDACSB7201:
.uleb128 .LEHB0-.LFB7201
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB7201
.uleb128 .LEHE1-.LEHB1
.uleb128 .L46-.LFB7201
.uleb128 0
.uleb128 .LEHB2-.LFB7201
.uleb128 .LEHE2-.LEHB2
.uleb128 .L47-.LFB7201
.uleb128 0
.uleb128 .LEHB3-.LFB7201
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB7201
.uleb128 .LEHE4-.LEHB4
.uleb128 .L47-.LFB7201
.uleb128 0
.LLSDACSE7201:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2dC
.comm _ZL2dC,4,4
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC20:
.long 1148846080
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <cstdlib>
#include <cmath>
#include <string>
#include <chrono>
#include <cooperative_groups.h>
using namespace std;
#include <cuda.h>
#include <curand_kernel.h>
#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__); \
return EXIT_FAILURE;}} while(0)
#define N_PROP 1100
#define THREADS_PER_BLOCK 256
#define N_BLOCKS 1 //Needed to be equal to 1 for the correct synchronization between threads
__device__ float dC = 0.0f;
__device__ int random_int(curandState &crstate, int min, int max){
float myrandf = curand_uniform(&crstate);
myrandf *= (max - min + 0.999999);
myrandf += min;
return (int)truncf(myrandf);
}
__global__ void trainBM(const float* weights, unsigned *net_state, const unsigned int net_size,
const float temp_init, const float final_temp, const float cooling_rate, int seed) {
// Handle to thread block group
__shared__ float shared_weights_array[THREADS_PER_BLOCK];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int nodes_per_thread = ceil((float)net_size/(float)THREADS_PER_BLOCK);
int unit_index = 0;
float temperature = temp_init;
curandState crstate;
curand_init(seed, 0, 0, &crstate);
if( i<net_size ){
net_state[i] = random_int(crstate, 0, 1);
}
do{
__syncthreads();
for(unsigned r=0; r<N_PROP; r++){
unit_index = random_int(crstate, 0, net_size-1);
if( i == 0 ){
dC = 0.0f;
}
//if(i<3 && j<3) printf("%d\n", unit_index);
for(int k=0; k<nodes_per_thread; k++){
int j = k*THREADS_PER_BLOCK + i;
shared_weights_array[tid] = ( j<net_size && j!=unit_index) ? weights[unit_index*net_size+j]*net_state[j] : 0;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
shared_weights_array[tid] += shared_weights_array[tid + s];
}
__syncthreads();
}
if (tid == 0){
dC += shared_weights_array[0];
}
__syncthreads();
}
if (i == 0){
float probability = 1 / (1 + expf(-dC / temperature));
//printf("dC--------->%f\nPROBABILITY--------->%f\n", dC, probability);
if( curand_uniform(&crstate)<probability ){
net_state[unit_index]=1;
}else{
net_state[unit_index]=0;
}
}else{
skipahead(1, &crstate);
}
}
temperature*=cooling_rate;
if(i==0) printf("%f\n", temperature);
}while( temperature > final_temp );
}
/*Params: 1. Number of nodes for the network
2. Initial Temperature
3. Final Temperature
4. Cooling Rate
5. Path to the file with the weights matrix
6. Seed
*/
int main(int narg, char** arg){
if(narg != 7){
perror("Wrong number of arguments.");
exit(1);
}
auto start = chrono::high_resolution_clock::now();
const unsigned int NET_SIZE = atoi(arg[1]);
const float INITIAL_TEMPERATURE = atof(arg[2]);
const float FINAL_TEMPERATURE = atof(arg[3]);
const float COOL_RATE = atof(arg[4]);
const unsigned SEED = atoi(arg[5]);
unsigned* net_states = new unsigned [NET_SIZE];
srand(SEED);
for(int i=0; i<NET_SIZE; i++){
net_states[i] = rand() % 2;
}
float* weights = new float [NET_SIZE*NET_SIZE];
ifstream matrix_file(arg[6], ifstream::in);
for(int i=0; i<NET_SIZE; i++){
for(int j=0; j<NET_SIZE; j++){
string x;
matrix_file>>x;
weights[i*NET_SIZE+j] = strtof( x.c_str(), NULL );
}
}
auto start_gpu = chrono::high_resolution_clock::now();
//Moving data to GPU
unsigned* g_net_states;
CUDA_CALL( cudaMalloc((void **)&g_net_states, NET_SIZE*sizeof(unsigned)) );
//CUDA_CALL( cudaMemcpy(g_net_states, net_states, NET_SIZE*sizeof(unsigned), cudaMemcpyHostToDevice) );
float* g_weights;
CUDA_CALL( cudaMalloc((float **)&g_weights, NET_SIZE*NET_SIZE*sizeof(float*)) );
CUDA_CALL( cudaMemcpy(g_weights, weights, NET_SIZE*NET_SIZE*sizeof(float), cudaMemcpyHostToDevice) );
//Running kernel
unsigned threadsPerBlock = THREADS_PER_BLOCK;
unsigned blocksPerGrid = N_BLOCKS;
trainBM<<<blocksPerGrid, threadsPerBlock>>>(g_weights, g_net_states, NET_SIZE,
INITIAL_TEMPERATURE, FINAL_TEMPERATURE, COOL_RATE, SEED);
/*std::string error = cudaGetErrorString(cudaPeekAtLastError());
printf("%s\n", error.c_str());
error = cudaGetErrorString(cudaThreadSynchronize());
printf("%s\n", error.c_str());*/
//Moving result to CPU
CUDA_CALL( cudaMemcpy(net_states, g_net_states, NET_SIZE*sizeof(float), cudaMemcpyDeviceToHost) );
//Freeing GPU memory
CUDA_CALL( cudaFree(g_net_states) );
CUDA_CALL( cudaFree(g_weights) );
auto end_gpu = chrono::high_resolution_clock::now();
float C = 0;
for(int i=0; i<NET_SIZE; i++){
for(int j=i+1; j<NET_SIZE; j++){
if( net_states[i] & net_states[j] ) C += weights[i*NET_SIZE+j];
}
}
delete [] net_states;
delete [] weights;
auto end = chrono::high_resolution_clock::now();
cout<<"Final cost function: "<<C<<endl;
cout<<"GPU time: "<<chrono::duration_cast<chrono::milliseconds>(end_gpu-start_gpu).count()/1000.0f<<" seconds."<<endl;
cout<<"Total time: "<<chrono::duration_cast<chrono::milliseconds>(end-start).count()/1000.0f<<" seconds."<<endl;
return 0;
} | #include <iostream>
#include <fstream>
#include <cstdlib>
#include <cmath>
#include <string>
#include <chrono>
#include <hip/hip_cooperative_groups.h>
using namespace std;
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__); \
return EXIT_FAILURE;}} while(0)
#define N_PROP 1100
#define THREADS_PER_BLOCK 256
#define N_BLOCKS 1 //Needed to be equal to 1 for the correct synchronization between threads
__device__ float dC = 0.0f;
__device__ int random_int(hiprandState &crstate, int min, int max){
float myrandf = hiprand_uniform(&crstate);
myrandf *= (max - min + 0.999999);
myrandf += min;
return (int)truncf(myrandf);
}
__global__ void trainBM(const float* weights, unsigned *net_state, const unsigned int net_size,
const float temp_init, const float final_temp, const float cooling_rate, int seed) {
// Handle to thread block group
__shared__ float shared_weights_array[THREADS_PER_BLOCK];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int nodes_per_thread = ceil((float)net_size/(float)THREADS_PER_BLOCK);
int unit_index = 0;
float temperature = temp_init;
hiprandState crstate;
hiprand_init(seed, 0, 0, &crstate);
if( i<net_size ){
net_state[i] = random_int(crstate, 0, 1);
}
do{
__syncthreads();
for(unsigned r=0; r<N_PROP; r++){
unit_index = random_int(crstate, 0, net_size-1);
if( i == 0 ){
dC = 0.0f;
}
//if(i<3 && j<3) printf("%d\n", unit_index);
for(int k=0; k<nodes_per_thread; k++){
int j = k*THREADS_PER_BLOCK + i;
shared_weights_array[tid] = ( j<net_size && j!=unit_index) ? weights[unit_index*net_size+j]*net_state[j] : 0;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
shared_weights_array[tid] += shared_weights_array[tid + s];
}
__syncthreads();
}
if (tid == 0){
dC += shared_weights_array[0];
}
__syncthreads();
}
if (i == 0){
float probability = 1 / (1 + expf(-dC / temperature));
//printf("dC--------->%f\nPROBABILITY--------->%f\n", dC, probability);
if( hiprand_uniform(&crstate)<probability ){
net_state[unit_index]=1;
}else{
net_state[unit_index]=0;
}
}else{
skipahead(1, &crstate);
}
}
temperature*=cooling_rate;
if(i==0) printf("%f\n", temperature);
}while( temperature > final_temp );
}
/*Params: 1. Number of nodes for the network
2. Initial Temperature
3. Final Temperature
4. Cooling Rate
5. Path to the file with the weights matrix
6. Seed
*/
int main(int narg, char** arg){
if(narg != 7){
perror("Wrong number of arguments.");
exit(1);
}
auto start = chrono::high_resolution_clock::now();
const unsigned int NET_SIZE = atoi(arg[1]);
const float INITIAL_TEMPERATURE = atof(arg[2]);
const float FINAL_TEMPERATURE = atof(arg[3]);
const float COOL_RATE = atof(arg[4]);
const unsigned SEED = atoi(arg[5]);
unsigned* net_states = new unsigned [NET_SIZE];
srand(SEED);
for(int i=0; i<NET_SIZE; i++){
net_states[i] = rand() % 2;
}
float* weights = new float [NET_SIZE*NET_SIZE];
ifstream matrix_file(arg[6], ifstream::in);
for(int i=0; i<NET_SIZE; i++){
for(int j=0; j<NET_SIZE; j++){
string x;
matrix_file>>x;
weights[i*NET_SIZE+j] = strtof( x.c_str(), NULL );
}
}
auto start_gpu = chrono::high_resolution_clock::now();
//Moving data to GPU
unsigned* g_net_states;
CUDA_CALL( hipMalloc((void **)&g_net_states, NET_SIZE*sizeof(unsigned)) );
//CUDA_CALL( cudaMemcpy(g_net_states, net_states, NET_SIZE*sizeof(unsigned), cudaMemcpyHostToDevice) );
float* g_weights;
CUDA_CALL( hipMalloc((float **)&g_weights, NET_SIZE*NET_SIZE*sizeof(float*)) );
CUDA_CALL( hipMemcpy(g_weights, weights, NET_SIZE*NET_SIZE*sizeof(float), hipMemcpyHostToDevice) );
//Running kernel
unsigned threadsPerBlock = THREADS_PER_BLOCK;
unsigned blocksPerGrid = N_BLOCKS;
trainBM<<<blocksPerGrid, threadsPerBlock>>>(g_weights, g_net_states, NET_SIZE,
INITIAL_TEMPERATURE, FINAL_TEMPERATURE, COOL_RATE, SEED);
/*std::string error = cudaGetErrorString(cudaPeekAtLastError());
printf("%s\n", error.c_str());
error = cudaGetErrorString(cudaThreadSynchronize());
printf("%s\n", error.c_str());*/
//Moving result to CPU
CUDA_CALL( hipMemcpy(net_states, g_net_states, NET_SIZE*sizeof(float), hipMemcpyDeviceToHost) );
//Freeing GPU memory
CUDA_CALL( hipFree(g_net_states) );
CUDA_CALL( hipFree(g_weights) );
auto end_gpu = chrono::high_resolution_clock::now();
float C = 0;
for(int i=0; i<NET_SIZE; i++){
for(int j=i+1; j<NET_SIZE; j++){
if( net_states[i] & net_states[j] ) C += weights[i*NET_SIZE+j];
}
}
delete [] net_states;
delete [] weights;
auto end = chrono::high_resolution_clock::now();
cout<<"Final cost function: "<<C<<endl;
cout<<"GPU time: "<<chrono::duration_cast<chrono::milliseconds>(end_gpu-start_gpu).count()/1000.0f<<" seconds."<<endl;
cout<<"Total time: "<<chrono::duration_cast<chrono::milliseconds>(end-start).count()/1000.0f<<" seconds."<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <fstream>
#include <cstdlib>
#include <cmath>
#include <string>
#include <chrono>
#include <hip/hip_cooperative_groups.h>
using namespace std;
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__); \
return EXIT_FAILURE;}} while(0)
#define N_PROP 1100
#define THREADS_PER_BLOCK 256
#define N_BLOCKS 1 //Needed to be equal to 1 for the correct synchronization between threads
__device__ float dC = 0.0f;
__device__ int random_int(hiprandState &crstate, int min, int max){
float myrandf = hiprand_uniform(&crstate);
myrandf *= (max - min + 0.999999);
myrandf += min;
return (int)truncf(myrandf);
}
__global__ void trainBM(const float* weights, unsigned *net_state, const unsigned int net_size,
const float temp_init, const float final_temp, const float cooling_rate, int seed) {
// Handle to thread block group
__shared__ float shared_weights_array[THREADS_PER_BLOCK];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int nodes_per_thread = ceil((float)net_size/(float)THREADS_PER_BLOCK);
int unit_index = 0;
float temperature = temp_init;
hiprandState crstate;
hiprand_init(seed, 0, 0, &crstate);
if( i<net_size ){
net_state[i] = random_int(crstate, 0, 1);
}
do{
__syncthreads();
for(unsigned r=0; r<N_PROP; r++){
unit_index = random_int(crstate, 0, net_size-1);
if( i == 0 ){
dC = 0.0f;
}
//if(i<3 && j<3) printf("%d\n", unit_index);
for(int k=0; k<nodes_per_thread; k++){
int j = k*THREADS_PER_BLOCK + i;
shared_weights_array[tid] = ( j<net_size && j!=unit_index) ? weights[unit_index*net_size+j]*net_state[j] : 0;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
shared_weights_array[tid] += shared_weights_array[tid + s];
}
__syncthreads();
}
if (tid == 0){
dC += shared_weights_array[0];
}
__syncthreads();
}
if (i == 0){
float probability = 1 / (1 + expf(-dC / temperature));
//printf("dC--------->%f\nPROBABILITY--------->%f\n", dC, probability);
if( hiprand_uniform(&crstate)<probability ){
net_state[unit_index]=1;
}else{
net_state[unit_index]=0;
}
}else{
skipahead(1, &crstate);
}
}
temperature*=cooling_rate;
if(i==0) printf("%f\n", temperature);
}while( temperature > final_temp );
}
/*Params: 1. Number of nodes for the network
2. Initial Temperature
3. Final Temperature
4. Cooling Rate
5. Path to the file with the weights matrix
6. Seed
*/
int main(int narg, char** arg){
if(narg != 7){
perror("Wrong number of arguments.");
exit(1);
}
auto start = chrono::high_resolution_clock::now();
const unsigned int NET_SIZE = atoi(arg[1]);
const float INITIAL_TEMPERATURE = atof(arg[2]);
const float FINAL_TEMPERATURE = atof(arg[3]);
const float COOL_RATE = atof(arg[4]);
const unsigned SEED = atoi(arg[5]);
unsigned* net_states = new unsigned [NET_SIZE];
srand(SEED);
for(int i=0; i<NET_SIZE; i++){
net_states[i] = rand() % 2;
}
float* weights = new float [NET_SIZE*NET_SIZE];
ifstream matrix_file(arg[6], ifstream::in);
for(int i=0; i<NET_SIZE; i++){
for(int j=0; j<NET_SIZE; j++){
string x;
matrix_file>>x;
weights[i*NET_SIZE+j] = strtof( x.c_str(), NULL );
}
}
auto start_gpu = chrono::high_resolution_clock::now();
//Moving data to GPU
unsigned* g_net_states;
CUDA_CALL( hipMalloc((void **)&g_net_states, NET_SIZE*sizeof(unsigned)) );
//CUDA_CALL( cudaMemcpy(g_net_states, net_states, NET_SIZE*sizeof(unsigned), cudaMemcpyHostToDevice) );
float* g_weights;
CUDA_CALL( hipMalloc((float **)&g_weights, NET_SIZE*NET_SIZE*sizeof(float*)) );
CUDA_CALL( hipMemcpy(g_weights, weights, NET_SIZE*NET_SIZE*sizeof(float), hipMemcpyHostToDevice) );
//Running kernel
unsigned threadsPerBlock = THREADS_PER_BLOCK;
unsigned blocksPerGrid = N_BLOCKS;
trainBM<<<blocksPerGrid, threadsPerBlock>>>(g_weights, g_net_states, NET_SIZE,
INITIAL_TEMPERATURE, FINAL_TEMPERATURE, COOL_RATE, SEED);
/*std::string error = cudaGetErrorString(cudaPeekAtLastError());
printf("%s\n", error.c_str());
error = cudaGetErrorString(cudaThreadSynchronize());
printf("%s\n", error.c_str());*/
//Moving result to CPU
CUDA_CALL( hipMemcpy(net_states, g_net_states, NET_SIZE*sizeof(float), hipMemcpyDeviceToHost) );
//Freeing GPU memory
CUDA_CALL( hipFree(g_net_states) );
CUDA_CALL( hipFree(g_weights) );
auto end_gpu = chrono::high_resolution_clock::now();
float C = 0;
for(int i=0; i<NET_SIZE; i++){
for(int j=i+1; j<NET_SIZE; j++){
if( net_states[i] & net_states[j] ) C += weights[i*NET_SIZE+j];
}
}
delete [] net_states;
delete [] weights;
auto end = chrono::high_resolution_clock::now();
cout<<"Final cost function: "<<C<<endl;
cout<<"GPU time: "<<chrono::duration_cast<chrono::milliseconds>(end_gpu-start_gpu).count()/1000.0f<<" seconds."<<endl;
cout<<"Total time: "<<chrono::duration_cast<chrono::milliseconds>(end-start).count()/1000.0f<<" seconds."<<endl;
return 0;
} | .text
.file "boltzmannGPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__trainBMPKfPjjfffi # -- Begin function _Z22__device_stub__trainBMPKfPjjfffi
.p2align 4, 0x90
.type _Z22__device_stub__trainBMPKfPjjfffi,@function
_Z22__device_stub__trainBMPKfPjjfffi: # @_Z22__device_stub__trainBMPKfPjjfffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7trainBMPKfPjjfffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__trainBMPKfPjjfffi, .Lfunc_end0-_Z22__device_stub__trainBMPKfPjjfffi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $664, %rsp # imm = 0x298
.cfi_def_cfa_offset 720
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jne .LBB1_60
# %bb.1:
movq %rsi, %r13
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 64(%rsp) # 8-byte Spill
movq 8(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 24(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 32(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 40(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %r15d, %edi
shlq $2, %rdi
movq %rdi, 120(%rsp) # 8-byte Spill
callq _Znam
movq %rax, %r12
movq %rbx, 80(%rsp) # 8-byte Spill
movl %ebx, %edi
callq srand
testl %r15d, %r15d
je .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r15d, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq %r12, (%rsp) # 8-byte Spill
movl %r15d, %eax
imull %eax, %eax
movq %rax, 112(%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
movq %rdi, 104(%rsp) # 8-byte Spill
callq _Znam
movq %rax, %r12
movq 48(%r13), %rsi
leaq 144(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
testl %r15d, %r15d
je .LBB1_12
# %bb.5: # %.preheader.lr.ph
leaq 48(%rsp), %rbx
movl %r15d, %eax
movq %rax, 136(%rsp) # 8-byte Spill
xorl %eax, %eax
leaq 144(%rsp), %r13
leaq 32(%rsp), %rbp
xorl %ecx, %ecx
movq %r15, 128(%rsp) # 8-byte Spill
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_6 Depth=1
movl 28(%rsp), %ecx # 4-byte Reload
incl %ecx
movq 128(%rsp), %r15 # 8-byte Reload
movq 8(%rsp), %rax # 8-byte Reload
addl %r15d, %eax
cmpl %r15d, %ecx
je .LBB1_12
.LBB1_6: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
movl %ecx, 28(%rsp) # 4-byte Spill
movq 136(%rsp), %r14 # 8-byte Reload
movq %rax, 8(%rsp) # 8-byte Spill
movl %eax, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB1_7 Depth=2
incl %r15d
decq %r14
je .LBB1_11
.LBB1_7: # Parent Loop BB1_6 Depth=1
# => This Inner Loop Header: Depth=2
movq %rbx, 32(%rsp)
movq $0, 40(%rsp)
movb $0, 48(%rsp)
.Ltmp0:
movq %r13, %rdi
movq %rbp, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp1:
# %bb.8: # in Loop: Header=BB1_7 Depth=2
movq 32(%rsp), %rdi
xorl %esi, %esi
callq strtof
movl %r15d, %eax
movss %xmm0, (%r12,%rax,4)
movq 32(%rsp), %rdi
cmpq %rbx, %rdi
je .LBB1_10
# %bb.9: # %.critedge.i.i
# in Loop: Header=BB1_7 Depth=2
callq _ZdlPv
jmp .LBB1_10
.LBB1_12: # %._crit_edge123
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
.Ltmp3:
leaq 32(%rsp), %rdi
movq 120(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
.Ltmp4:
# %bb.13:
testl %eax, %eax
je .LBB1_17
# %bb.14:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $143, %edx
jmp .LBB1_55
.LBB1_17:
movq 112(%rsp), %rsi # 8-byte Reload
shlq $3, %rsi
.Ltmp6:
leaq 16(%rsp), %rdi
callq hipMalloc
.Ltmp7:
# %bb.18: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
movl $146, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.19:
movq 16(%rsp), %rdi
.Ltmp8:
movq %r12, %rsi
movq 104(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
.Ltmp9:
# %bb.20:
movl $147, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.21:
.Ltmp11:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.22:
testl %eax, %eax
jne .LBB1_24
# %bb.23:
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 88(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
.Ltmp13:
movl %r15d, %edx
movq 80(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
callq _Z22__device_stub__trainBMPKfPjjfffi
.Ltmp14:
.LBB1_24:
movq 32(%rsp), %rsi
.Ltmp15:
movq (%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp16:
# %bb.25:
movl $161, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.26:
movq 32(%rsp), %rdi
.Ltmp17:
callq hipFree
.Ltmp18:
# %bb.27:
movl $164, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.28:
movq 16(%rsp), %rdi
.Ltmp19:
callq hipFree
.Ltmp20:
# %bb.29:
movl $165, %edx
testl %eax, %eax
je .LBB1_30
.LBB1_54: # %_ZNSolsEPFRSoS_E.exit107.sink.split
movl $.L.str.1, %edi
movl $.L.str.2, %esi
.LBB1_55:
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB1_56:
leaq 144(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 400(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movl %ebx, %eax
addq $664, %rsp # imm = 0x298
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_30:
.cfi_def_cfa_offset 720
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
testl %r15d, %r15d
je .LBB1_31
# %bb.32: # %.lr.ph131.preheader
movl %r15d, %eax
incq %r15
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movq %rax, %rdx
movq (%rsp), %rsi # 8-byte Reload
xorl %edi, %edi
jmp .LBB1_34
.LBB1_33: # %.loopexit
# in Loop: Header=BB1_34 Depth=1
addq %r15, %rcx
addq $4, %rsi
decq %rdx
cmpq %rax, %rdi
je .LBB1_39
.LBB1_34: # %.lr.ph131
# =>This Loop Header: Depth=1
# Child Loop BB1_36 Depth 2
movq %rdi, %r8
incq %rdi
cmpq %rax, %rdi
jae .LBB1_33
# %bb.35: # %.lr.ph127
# in Loop: Header=BB1_34 Depth=1
movq (%rsp), %r9 # 8-byte Reload
movl (%r9,%r8,4), %r8d
movl $1, %r9d
jmp .LBB1_36
.p2align 4, 0x90
.LBB1_38: # in Loop: Header=BB1_36 Depth=2
incq %r9
cmpq %r9, %rdx
je .LBB1_33
.LBB1_36: # Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
testl %r8d, (%rsi,%r9,4)
je .LBB1_38
# %bb.37: # in Loop: Header=BB1_36 Depth=2
leal (%rcx,%r9), %r10d
addss (%r12,%r10,4), %xmm0
jmp .LBB1_38
.LBB1_39: # %._crit_edge132.loopexit
cvtss2sd %xmm0, %xmm0
jmp .LBB1_40
.LBB1_31:
xorps %xmm0, %xmm0
.LBB1_40: # %._crit_edge132
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq (%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
.Ltmp22:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp24:
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp25:
# %bb.42: # %_ZNSolsEf.exit
.Ltmp26:
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp27:
# %bb.43: # %_ZNSolsEPFRSoS_E.exit
.Ltmp28:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp29:
# %bb.44: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit98
subq %r13, %rbx
movabsq $4835703278458516699, %r15 # imm = 0x431BDE82D7B634DB
movq %rbx, %rax
imulq %r15
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp30:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp31:
# %bb.45: # %_ZNSolsEf.exit99
.Ltmp32:
movq %rax, %rbx
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.46: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit100
.Ltmp34:
movq %rbx, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp35:
# %bb.47: # %_ZNSolsEPFRSoS_E.exit101
.Ltmp37:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.48: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit102
subq 64(%rsp), %r14 # 8-byte Folded Reload
movq %r14, %rax
imulq %r15
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp40:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp41:
# %bb.49: # %_ZNSolsEf.exit105
.Ltmp42:
movq %rax, %r14
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.50: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit106
xorl %ebx, %ebx
.Ltmp44:
movq %r14, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp45:
jmp .LBB1_56
.LBB1_60:
movl $.L.str, %edi
callq perror
movl $1, %edi
callq exit
.LBB1_53:
.Ltmp46:
jmp .LBB1_58
.LBB1_52:
.Ltmp36:
jmp .LBB1_58
.LBB1_51:
.Ltmp39:
jmp .LBB1_58
.LBB1_62:
.Ltmp21:
jmp .LBB1_58
.LBB1_61:
.Ltmp10:
jmp .LBB1_58
.LBB1_57:
.Ltmp5:
.LBB1_58:
movq %rax, %r14
jmp .LBB1_59
.LBB1_15:
.Ltmp2:
movq %rax, %r14
movq 32(%rsp), %rdi
cmpq %rbx, %rdi
je .LBB1_59
# %bb.16: # %.critedge.i.i95
callq _ZdlPv
.LBB1_59:
leaq 144(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 400(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp6 # Call between .Ltmp6 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp20-.Ltmp11 # Call between .Ltmp11 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp29-.Ltmp22 # Call between .Ltmp22 and .Ltmp29
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp45-.Ltmp40 # Call between .Ltmp40 and .Ltmp45
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end1-.Ltmp45 # Call between .Ltmp45 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7trainBMPKfPjjfffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $dC, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type dC,@object # @dC
.local dC
.comm dC,4,4
.type _Z7trainBMPKfPjjfffi,@object # @_Z7trainBMPKfPjjfffi
.section .rodata,"a",@progbits
.globl _Z7trainBMPKfPjjfffi
.p2align 3, 0x0
_Z7trainBMPKfPjjfffi:
.quad _Z22__device_stub__trainBMPKfPjjfffi
.size _Z7trainBMPKfPjjfffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Wrong number of arguments."
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error at %s:%d\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/aalonso99/CUDA-Classic-Boltzmann-Machine/master/boltzmannGPU.hip"
.size .L.str.2, 122
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Final cost function: "
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU time: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " seconds."
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total time: "
.size .L.str.6, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7trainBMPKfPjjfffi"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "dC"
.size .L__unnamed_2, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__trainBMPKfPjjfffi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym dC
.addrsig_sym _Z7trainBMPKfPjjfffi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d85cd_00000000-6_boltzmannGPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB7207:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7207:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10random_intR17curandStateXORWOWii
.type _Z10random_intR17curandStateXORWOWii, @function
_Z10random_intR17curandStateXORWOWii:
.LFB7200:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE7200:
.size _Z10random_intR17curandStateXORWOWii, .-_Z10random_intR17curandStateXORWOWii
.globl _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
.type _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi, @function
_Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi:
.LFB7229:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7trainBMPKfPjjfffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7229:
.size _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi, .-_Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
.globl _Z7trainBMPKfPjjfffi
.type _Z7trainBMPKfPjjfffi, @function
_Z7trainBMPKfPjjfffi:
.LFB7230:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7230:
.size _Z7trainBMPKfPjjfffi, .-_Z7trainBMPKfPjjfffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7trainBMPKfPjjfffi"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.LC10:
.string "dC"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_ZN40_INTERNAL_7eb18656_15_boltzmannGPU_cu_dC4cuda3std3__419piecewise_constructE"
.align 8
.LC12:
.string "_ZN40_INTERNAL_7eb18656_15_boltzmannGPU_cu_dC4cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC13:
.string "_ZN40_INTERNAL_7eb18656_15_boltzmannGPU_cu_dC4cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB7232:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7trainBMPKfPjjfffi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2dC(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7232:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC15:
.string "Wrong number of arguments."
.section .rodata.str1.8
.align 8
.LC16:
.string "/home/ubuntu/Datasets/stackv2/train-structured/aalonso99/CUDA-Classic-Boltzmann-Machine/master/boltzmannGPU.cu"
.section .rodata.str1.1
.LC17:
.string "Error at %s:%d\n"
.LC18:
.string "Final cost function: "
.LC19:
.string "GPU time: "
.LC21:
.string " seconds."
.LC22:
.string "Total time: "
.text
.globl main
.type main, @function
main:
.LFB7201:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA7201
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $712, %rsp
.cfi_def_cfa_offset 768
movq %fs:40, %rax
movq %rax, 696(%rsp)
xorl %eax, %eax
cmpl $7, %edi
jne .L61
movq %rsi, %rbx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 88(%rsp)
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movl %eax, %r15d
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq %rax, 56(%rsp)
movl %r14d, %eax
leaq 0(,%rax,4), %rcx
movq %rcx, 16(%rsp)
movq %rcx, %rdi
.LEHB0:
call _Znam@PLT
movq %rax, %rbp
movq %rax, 48(%rsp)
movl %r13d, %edi
call srand@PLT
testl %r14d, %r14d
je .L17
leal -1(%r14), %eax
leaq 4(%rbp,%rax,4), %r12
.L18:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L18
movq 24(%rsp), %r14
movl %r14d, %eax
imull %r14d, %eax
movq %rax, 32(%rsp)
salq $2, %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call _Znam@PLT
movq %rax, %r13
movq 48(%rbx), %rsi
leaq 176(%rsp), %rdi
movl $8, %edx
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
movl %r14d, 12(%rsp)
movl %r14d, %r12d
movl $0, 8(%rsp)
leaq 144(%rsp), %r14
jmp .L19
.L61:
leaq .LC15(%rip), %rdi
call perror@PLT
.LEHE0:
movl $1, %edi
call exit@PLT
.L63:
movl %ebx, %eax
leaq 0(%r13,%rax,4), %rbp
movl $0, %esi
movq 144(%rsp), %rdi
call strtof@PLT
movss %xmm0, 0(%rbp)
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L20
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L20:
addl $1, %ebx
cmpl %r12d, %ebx
je .L62
.L21:
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $0, 152(%rsp)
movb $0, 160(%rsp)
leaq 176(%rsp), %rdi
movq %r14, %rsi
.LEHB1:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE1:
jmp .L63
.L62:
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %r12d
movl 12(%rsp), %ecx
cmpl %ecx, %eax
je .L22
.L19:
movl %r12d, %ebx
subl %r15d, %ebx
jmp .L21
.L83:
testl %eax, %eax
jne .L64
movq 32(%rsp), %rsi
salq $3, %rsi
leaq 112(%rsp), %rdi
.LEHB2:
call cudaMalloc@PLT
jmp .L65
.L64:
movl $143, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L66
.L65:
testl %eax, %eax
jne .L67
movl $1, %ecx
movq 40(%rsp), %rdx
movq %r13, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L68
.L67:
movl $146, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L69
.L68:
testl %eax, %eax
jne .L70
movl $256, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
jmp .L71
.L70:
movl $147, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L72
.L71:
testl %eax, %eax
jne .L27
pxor %xmm0, %xmm0
cvtsd2ss 80(%rsp), %xmm0
movl 56(%rsp), %ecx
pxor %xmm2, %xmm2
cvtsd2ss 64(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movl %r15d, %edx
movq 104(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z34__device_stub__Z7trainBMPKfPjjfffiPKfPjjfffi
.L27:
movl $2, %ecx
movq 16(%rsp), %rdx
movq 104(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L73
movq 104(%rsp), %rdi
call cudaFree@PLT
jmp .L74
.L73:
movl $161, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L75
.L74:
testl %eax, %eax
jne .L76
movq 112(%rsp), %rdi
call cudaFree@PLT
jmp .L77
.L76:
movl $164, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L78
.L77:
movl %eax, %ebp
testl %eax, %eax
jne .L79
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 24(%rsp), %rax
testl %eax, %eax
je .L45
movl %eax, %r8d
leal -1(%rax), %edi
addq $2, %rdi
movl $1, %esi
movl $0x00000000, 8(%rsp)
movq 48(%rsp), %rcx
jmp .L34
.L79:
movl $165, %ecx
leaq .LC16(%rip), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L32:
addq $1, %rax
cmpl %r15d, %eax
jnb .L81
.L33:
movl %r9d, %edx
andl (%rcx,%rax,4), %edx
je .L32
leal 0(%rbp,%rax), %edx
movss 8(%rsp), %xmm3
addss 0(%r13,%rdx,4), %xmm3
movss %xmm3, 8(%rsp)
jmp .L32
.L81:
addq $1, %rsi
addl %r15d, %ebp
cmpq %rdi, %rsi
je .L31
.L34:
cmpq %r8, %rsi
je .L31
movl -4(%rcx,%rsi,4), %r9d
movq %rsi, %rax
jmp .L33
.L45:
movl $0x00000000, 8(%rsp)
.L31:
movq 48(%rsp), %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rax
subq %rbx, %rax
movl $1000000, %ecx
cqto
idivq %rcx
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rax
movq 88(%rsp), %rcx
subq %rcx, %rax
movl $1000000, %ecx
cqto
idivq %rcx
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
movl $0, %ebx
jmp .L24
.L66:
movl $1, %ebx
.L24:
leaq 176(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 696(%rsp), %rax
subq %fs:40, %rax
jne .L82
movl %ebx, %eax
addq $712, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
movl $1, %ebx
jmp .L24
.L72:
movl $1, %ebx
jmp .L24
.L75:
movl $1, %ebx
jmp .L24
.L78:
movl $1, %ebx
jmp .L24
.L80:
movl $1, %ebx
jmp .L24
.L46:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L36:
leaq 176(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 696(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L47:
endbr64
movq %rax, %rbx
jmp .L36
.L37:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.L17:
movl $0, %edi
call _Znam@PLT
movq %rax, %r13
movq 48(%rbx), %rsi
leaq 176(%rsp), %rdi
movl $8, %edx
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE3:
movq $0, 40(%rsp)
movq $0, 32(%rsp)
.L22:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq 104(%rsp), %rdi
movq 16(%rsp), %rsi
.LEHB4:
call cudaMalloc@PLT
.LEHE4:
jmp .L83
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7201:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA7201:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE7201-.LLSDACSB7201
.LLSDACSB7201:
.uleb128 .LEHB0-.LFB7201
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB7201
.uleb128 .LEHE1-.LEHB1
.uleb128 .L46-.LFB7201
.uleb128 0
.uleb128 .LEHB2-.LFB7201
.uleb128 .LEHE2-.LEHB2
.uleb128 .L47-.LFB7201
.uleb128 0
.uleb128 .LEHB3-.LFB7201
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB7201
.uleb128 .LEHE4-.LEHB4
.uleb128 .L47-.LFB7201
.uleb128 0
.LLSDACSE7201:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2dC
.comm _ZL2dC,4,4
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC20:
.long 1148846080
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "boltzmannGPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__trainBMPKfPjjfffi # -- Begin function _Z22__device_stub__trainBMPKfPjjfffi
.p2align 4, 0x90
.type _Z22__device_stub__trainBMPKfPjjfffi,@function
_Z22__device_stub__trainBMPKfPjjfffi: # @_Z22__device_stub__trainBMPKfPjjfffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7trainBMPKfPjjfffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__trainBMPKfPjjfffi, .Lfunc_end0-_Z22__device_stub__trainBMPKfPjjfffi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $664, %rsp # imm = 0x298
.cfi_def_cfa_offset 720
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jne .LBB1_60
# %bb.1:
movq %rsi, %r13
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 64(%rsp) # 8-byte Spill
movq 8(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 24(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 32(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 40(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %r15d, %edi
shlq $2, %rdi
movq %rdi, 120(%rsp) # 8-byte Spill
callq _Znam
movq %rax, %r12
movq %rbx, 80(%rsp) # 8-byte Spill
movl %ebx, %edi
callq srand
testl %r15d, %r15d
je .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r15d, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq %r12, (%rsp) # 8-byte Spill
movl %r15d, %eax
imull %eax, %eax
movq %rax, 112(%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
movq %rdi, 104(%rsp) # 8-byte Spill
callq _Znam
movq %rax, %r12
movq 48(%r13), %rsi
leaq 144(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
testl %r15d, %r15d
je .LBB1_12
# %bb.5: # %.preheader.lr.ph
leaq 48(%rsp), %rbx
movl %r15d, %eax
movq %rax, 136(%rsp) # 8-byte Spill
xorl %eax, %eax
leaq 144(%rsp), %r13
leaq 32(%rsp), %rbp
xorl %ecx, %ecx
movq %r15, 128(%rsp) # 8-byte Spill
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_6 Depth=1
movl 28(%rsp), %ecx # 4-byte Reload
incl %ecx
movq 128(%rsp), %r15 # 8-byte Reload
movq 8(%rsp), %rax # 8-byte Reload
addl %r15d, %eax
cmpl %r15d, %ecx
je .LBB1_12
.LBB1_6: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
movl %ecx, 28(%rsp) # 4-byte Spill
movq 136(%rsp), %r14 # 8-byte Reload
movq %rax, 8(%rsp) # 8-byte Spill
movl %eax, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB1_7 Depth=2
incl %r15d
decq %r14
je .LBB1_11
.LBB1_7: # Parent Loop BB1_6 Depth=1
# => This Inner Loop Header: Depth=2
movq %rbx, 32(%rsp)
movq $0, 40(%rsp)
movb $0, 48(%rsp)
.Ltmp0:
movq %r13, %rdi
movq %rbp, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp1:
# %bb.8: # in Loop: Header=BB1_7 Depth=2
movq 32(%rsp), %rdi
xorl %esi, %esi
callq strtof
movl %r15d, %eax
movss %xmm0, (%r12,%rax,4)
movq 32(%rsp), %rdi
cmpq %rbx, %rdi
je .LBB1_10
# %bb.9: # %.critedge.i.i
# in Loop: Header=BB1_7 Depth=2
callq _ZdlPv
jmp .LBB1_10
.LBB1_12: # %._crit_edge123
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
.Ltmp3:
leaq 32(%rsp), %rdi
movq 120(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
.Ltmp4:
# %bb.13:
testl %eax, %eax
je .LBB1_17
# %bb.14:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $143, %edx
jmp .LBB1_55
.LBB1_17:
movq 112(%rsp), %rsi # 8-byte Reload
shlq $3, %rsi
.Ltmp6:
leaq 16(%rsp), %rdi
callq hipMalloc
.Ltmp7:
# %bb.18: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
movl $146, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.19:
movq 16(%rsp), %rdi
.Ltmp8:
movq %r12, %rsi
movq 104(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
.Ltmp9:
# %bb.20:
movl $147, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.21:
.Ltmp11:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.22:
testl %eax, %eax
jne .LBB1_24
# %bb.23:
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 88(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
.Ltmp13:
movl %r15d, %edx
movq 80(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
callq _Z22__device_stub__trainBMPKfPjjfffi
.Ltmp14:
.LBB1_24:
movq 32(%rsp), %rsi
.Ltmp15:
movq (%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp16:
# %bb.25:
movl $161, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.26:
movq 32(%rsp), %rdi
.Ltmp17:
callq hipFree
.Ltmp18:
# %bb.27:
movl $164, %edx
testl %eax, %eax
jne .LBB1_54
# %bb.28:
movq 16(%rsp), %rdi
.Ltmp19:
callq hipFree
.Ltmp20:
# %bb.29:
movl $165, %edx
testl %eax, %eax
je .LBB1_30
.LBB1_54: # %_ZNSolsEPFRSoS_E.exit107.sink.split
movl $.L.str.1, %edi
movl $.L.str.2, %esi
.LBB1_55:
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB1_56:
leaq 144(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 400(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movl %ebx, %eax
addq $664, %rsp # imm = 0x298
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_30:
.cfi_def_cfa_offset 720
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
testl %r15d, %r15d
je .LBB1_31
# %bb.32: # %.lr.ph131.preheader
movl %r15d, %eax
incq %r15
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movq %rax, %rdx
movq (%rsp), %rsi # 8-byte Reload
xorl %edi, %edi
jmp .LBB1_34
.LBB1_33: # %.loopexit
# in Loop: Header=BB1_34 Depth=1
addq %r15, %rcx
addq $4, %rsi
decq %rdx
cmpq %rax, %rdi
je .LBB1_39
.LBB1_34: # %.lr.ph131
# =>This Loop Header: Depth=1
# Child Loop BB1_36 Depth 2
movq %rdi, %r8
incq %rdi
cmpq %rax, %rdi
jae .LBB1_33
# %bb.35: # %.lr.ph127
# in Loop: Header=BB1_34 Depth=1
movq (%rsp), %r9 # 8-byte Reload
movl (%r9,%r8,4), %r8d
movl $1, %r9d
jmp .LBB1_36
.p2align 4, 0x90
.LBB1_38: # in Loop: Header=BB1_36 Depth=2
incq %r9
cmpq %r9, %rdx
je .LBB1_33
.LBB1_36: # Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
testl %r8d, (%rsi,%r9,4)
je .LBB1_38
# %bb.37: # in Loop: Header=BB1_36 Depth=2
leal (%rcx,%r9), %r10d
addss (%r12,%r10,4), %xmm0
jmp .LBB1_38
.LBB1_39: # %._crit_edge132.loopexit
cvtss2sd %xmm0, %xmm0
jmp .LBB1_40
.LBB1_31:
xorps %xmm0, %xmm0
.LBB1_40: # %._crit_edge132
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq (%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
.Ltmp22:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp24:
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp25:
# %bb.42: # %_ZNSolsEf.exit
.Ltmp26:
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp27:
# %bb.43: # %_ZNSolsEPFRSoS_E.exit
.Ltmp28:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp29:
# %bb.44: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit98
subq %r13, %rbx
movabsq $4835703278458516699, %r15 # imm = 0x431BDE82D7B634DB
movq %rbx, %rax
imulq %r15
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp30:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp31:
# %bb.45: # %_ZNSolsEf.exit99
.Ltmp32:
movq %rax, %rbx
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.46: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit100
.Ltmp34:
movq %rbx, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp35:
# %bb.47: # %_ZNSolsEPFRSoS_E.exit101
.Ltmp37:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.48: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit102
subq 64(%rsp), %r14 # 8-byte Folded Reload
movq %r14, %rax
imulq %r15
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp40:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp41:
# %bb.49: # %_ZNSolsEf.exit105
.Ltmp42:
movq %rax, %r14
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.50: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit106
xorl %ebx, %ebx
.Ltmp44:
movq %r14, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp45:
jmp .LBB1_56
.LBB1_60:
movl $.L.str, %edi
callq perror
movl $1, %edi
callq exit
.LBB1_53:
.Ltmp46:
jmp .LBB1_58
.LBB1_52:
.Ltmp36:
jmp .LBB1_58
.LBB1_51:
.Ltmp39:
jmp .LBB1_58
.LBB1_62:
.Ltmp21:
jmp .LBB1_58
.LBB1_61:
.Ltmp10:
jmp .LBB1_58
.LBB1_57:
.Ltmp5:
.LBB1_58:
movq %rax, %r14
jmp .LBB1_59
.LBB1_15:
.Ltmp2:
movq %rax, %r14
movq 32(%rsp), %rdi
cmpq %rbx, %rdi
je .LBB1_59
# %bb.16: # %.critedge.i.i95
callq _ZdlPv
.LBB1_59:
leaq 144(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 400(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp6 # Call between .Ltmp6 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp20-.Ltmp11 # Call between .Ltmp11 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp29-.Ltmp22 # Call between .Ltmp22 and .Ltmp29
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp45-.Ltmp40 # Call between .Ltmp40 and .Ltmp45
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end1-.Ltmp45 # Call between .Ltmp45 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7trainBMPKfPjjfffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $dC, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type dC,@object # @dC
.local dC
.comm dC,4,4
.type _Z7trainBMPKfPjjfffi,@object # @_Z7trainBMPKfPjjfffi
.section .rodata,"a",@progbits
.globl _Z7trainBMPKfPjjfffi
.p2align 3, 0x0
_Z7trainBMPKfPjjfffi:
.quad _Z22__device_stub__trainBMPKfPjjfffi
.size _Z7trainBMPKfPjjfffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Wrong number of arguments."
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error at %s:%d\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/aalonso99/CUDA-Classic-Boltzmann-Machine/master/boltzmannGPU.hip"
.size .L.str.2, 122
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Final cost function: "
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU time: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " seconds."
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total time: "
.size .L.str.6, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7trainBMPKfPjjfffi"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "dC"
.size .L__unnamed_2, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__trainBMPKfPjjfffi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym dC
.addrsig_sym _Z7trainBMPKfPjjfffi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
#define DATA_SIZE 1048576
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++) {
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop, i) == cudaSuccess) {
if(prop.major >= 1) {
break;
}
}
}
if(i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
cudaSetDevice(i);
return true;
}
void GenerateNumbers(int *number, int size)
{
for(int i = 0; i < size; i++) {
number[i] = rand() % 10;
}
}
__global__ static void sumOfSquares(int *num, int* result, clock_t* time)
{
int sum = 0;
int i;
clock_t start = clock();
for(i = 0; i < DATA_SIZE; i++) {
sum += num[i] * num[i];
}
*result = sum;
*time = clock() - start;
}
int main()
{
if(!InitCUDA()) {
return 0;
}
printf("CUDA initialized.\n");
int data[DATA_SIZE];
GenerateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
clock_t start_g, stop_g;
start_g = clock();
cudaMalloc((void**) &gpudata, sizeof(int) * DATA_SIZE);
cudaMalloc((void**) &result, sizeof(int));
cudaMalloc((void**) &time, sizeof(clock_t));
cudaMemcpy(gpudata, data, sizeof(int) * DATA_SIZE, cudaMemcpyHostToDevice);
sumOfSquares<<<1, 1, 0>>>(gpudata, result, time);
int sum;
clock_t time_used;
cudaMemcpy(&sum, result, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&time_used, time, sizeof(clock_t), cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
cudaFree(time);
stop_g = (clock() - start_g);
printf("sum (GPU): %d time: %f timeg: %f \n", sum, (double)time_used / CLOCKS_PER_SEC, (double) stop_g / CLOCKS_PER_SEC);
clock_t start, stop;
start = clock();
sum = 0;
for(int i = 0; i < DATA_SIZE; i++) {
sum += data[i] * data[i];
}
stop = clock() - start;
printf("sum (CPU): %d time: %f \n", sum, (double)stop / CLOCKS_PER_SEC);
return 0;
} | code for sm_80
Function : _Z12sumOfSquaresPiS_Pl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fc60000000f00 */
/*0040*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fc80000015000 */
/*0050*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fe200000001ff */
/*0060*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*0070*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R26, [R2.64+0x4] ; /* 0x00000404021a7981 */
/* 0x000ee8000c1e1900 */
/*0090*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*00a0*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*00b0*/ LDG.E R22, [R2.64+0x10] ; /* 0x0000100402167981 */
/* 0x000f68000c1e1900 */
/*00c0*/ LDG.E R23, [R2.64+0x14] ; /* 0x0000140402177981 */
/* 0x000f68000c1e1900 */
/*00d0*/ LDG.E R24, [R2.64+0x18] ; /* 0x0000180402187981 */
/* 0x000f68000c1e1900 */
/*00e0*/ LDG.E R0, [R2.64+0x1c] ; /* 0x00001c0402007981 */
/* 0x000f68000c1e1900 */
/*00f0*/ LDG.E R6, [R2.64+0x20] ; /* 0x0000200402067981 */
/* 0x000f68000c1e1900 */
/*0100*/ LDG.E R7, [R2.64+0x24] ; /* 0x0000240402077981 */
/* 0x000f68000c1e1900 */
/*0110*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280402087981 */
/* 0x000f68000c1e1900 */
/*0120*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000f68000c1e1900 */
/*0130*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R11, [R2.64+0x34] ; /* 0x00003404020b7981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R12, [R2.64+0x38] ; /* 0x00003804020c7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c04020d7981 */
/* 0x000168000c1e1900 */
/*0170*/ LDG.E R14, [R2.64+0x40] ; /* 0x00004004020e7981 */
/* 0x000168000c1e1900 */
/*0180*/ LDG.E R15, [R2.64+0x44] ; /* 0x00004404020f7981 */
/* 0x000168000c1e1900 */
/*0190*/ LDG.E R16, [R2.64+0x48] ; /* 0x0000480402107981 */
/* 0x000168000c1e1900 */
/*01a0*/ LDG.E R17, [R2.64+0x4c] ; /* 0x00004c0402117981 */
/* 0x000162000c1e1900 */
/*01b0*/ IMAD R19, R19, R19, R18 ; /* 0x0000001313137224 */
/* 0x004fc600078e0212 */
/*01c0*/ LDG.E R18, [R2.64+0x50] ; /* 0x0000500402127981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ IMAD R27, R26, R26, R19 ; /* 0x0000001a1a1b7224 */
/* 0x008fc600078e0213 */
/*01e0*/ LDG.E R19, [R2.64+0x54] ; /* 0x0000540402137981 */
/* 0x0000e2000c1e1900 */
/*01f0*/ IMAD R26, R20, R20, R27 ; /* 0x00000014141a7224 */
/* 0x010fc600078e021b */
/*0200*/ LDG.E R20, [R2.64+0x58] ; /* 0x0000580402147981 */
/* 0x000122000c1e1900 */
/*0210*/ IMAD R27, R21, R21, R26 ; /* 0x00000015151b7224 */
/* 0x020fc600078e021a */
/*0220*/ LDG.E R21, [R2.64+0x5c] ; /* 0x00005c0402157981 */
/* 0x000162000c1e1900 */
/*0230*/ IMAD R26, R22, R22, R27 ; /* 0x00000016161a7224 */
/* 0x000fc600078e021b */
/*0240*/ LDG.E R22, [R2.64+0x60] ; /* 0x0000600402167981 */
/* 0x000162000c1e1900 */
/*0250*/ IMAD R27, R23, R23, R26 ; /* 0x00000017171b7224 */
/* 0x000fc600078e021a */
/*0260*/ LDG.E R23, [R2.64+0x64] ; /* 0x0000640402177981 */
/* 0x000162000c1e1900 */
/*0270*/ IMAD R27, R24, R24, R27 ; /* 0x00000018181b7224 */
/* 0x000fc600078e021b */
/*0280*/ LDG.E R24, [R2.64+0x68] ; /* 0x0000680402187981 */
/* 0x000162000c1e1900 */
/*0290*/ IMAD R27, R0, R0, R27 ; /* 0x00000000001b7224 */
/* 0x000fc600078e021b */
/*02a0*/ LDG.E R0, [R2.64+0x6c] ; /* 0x00006c0402007981 */
/* 0x000162000c1e1900 */
/*02b0*/ IMAD R26, R6, R6, R27 ; /* 0x00000006061a7224 */
/* 0x000fc600078e021b */
/*02c0*/ LDG.E R6, [R2.64+0x70] ; /* 0x0000700402067981 */
/* 0x000162000c1e1900 */
/*02d0*/ IMAD R27, R7, R7, R26 ; /* 0x00000007071b7224 */
/* 0x000fc600078e021a */
/*02e0*/ LDG.E R7, [R2.64+0x74] ; /* 0x0000740402077981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD R26, R8, R8, R27 ; /* 0x00000008081a7224 */
/* 0x000fc600078e021b */
/*0300*/ LDG.E R8, [R2.64+0x78] ; /* 0x0000780402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IMAD R27, R9, R9, R26 ; /* 0x00000009091b7224 */
/* 0x000fc600078e021a */
/*0320*/ LDG.E R9, [R2.64+0x7c] ; /* 0x00007c0402097981 */
/* 0x000162000c1e1900 */
/*0330*/ IADD3 R25, R25, 0x20, RZ ; /* 0x0000002019197810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R10, R10, R10, R27 ; /* 0x0000000a0a0a7224 */
/* 0x000fc600078e021b */
/*0350*/ ISETP.NE.AND P0, PT, R25, 0x100000, PT ; /* 0x001000001900780c */
/* 0x000fe20003f05270 */
/*0360*/ IMAD R11, R11, R11, R10 ; /* 0x0000000b0b0b7224 */
/* 0x000fc800078e020a */
/*0370*/ IMAD R12, R12, R12, R11 ; /* 0x0000000c0c0c7224 */
/* 0x000fe200078e020b */
/*0380*/ IADD3 R2, P1, R2, 0x80, RZ ; /* 0x0000008002027810 */
/* 0x001fc60007f3e0ff */
/*0390*/ IMAD R13, R13, R13, R12 ; /* 0x0000000d0d0d7224 */
/* 0x000fe200078e020c */
/*03a0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*03b0*/ IMAD R14, R14, R14, R13 ; /* 0x0000000e0e0e7224 */
/* 0x000fc800078e020d */
/*03c0*/ IMAD R15, R15, R15, R14 ; /* 0x0000000f0f0f7224 */
/* 0x000fc800078e020e */
/*03d0*/ IMAD R16, R16, R16, R15 ; /* 0x0000001010107224 */
/* 0x000fc800078e020f */
/*03e0*/ IMAD R17, R17, R17, R16 ; /* 0x0000001111117224 */
/* 0x000fc800078e0210 */
/*03f0*/ IMAD R18, R18, R18, R17 ; /* 0x0000001212127224 */
/* 0x004fc800078e0211 */
/*0400*/ IMAD R19, R19, R19, R18 ; /* 0x0000001313137224 */
/* 0x008fc800078e0212 */
/*0410*/ IMAD R20, R20, R20, R19 ; /* 0x0000001414147224 */
/* 0x010fc800078e0213 */
/*0420*/ IMAD R21, R21, R21, R20 ; /* 0x0000001515157224 */
/* 0x020fc800078e0214 */
/*0430*/ IMAD R22, R22, R22, R21 ; /* 0x0000001616167224 */
/* 0x000fc800078e0215 */
/*0440*/ IMAD R23, R23, R23, R22 ; /* 0x0000001717177224 */
/* 0x000fc800078e0216 */
/*0450*/ IMAD R23, R24, R24, R23 ; /* 0x0000001818177224 */
/* 0x000fc800078e0217 */
/*0460*/ IMAD R23, R0, R0, R23 ; /* 0x0000000000177224 */
/* 0x000fc800078e0217 */
/*0470*/ IMAD R6, R6, R6, R23 ; /* 0x0000000606067224 */
/* 0x000fc800078e0217 */
/*0480*/ IMAD R7, R7, R7, R6 ; /* 0x0000000707077224 */
/* 0x000fc800078e0206 */
/*0490*/ IMAD R8, R8, R8, R7 ; /* 0x0000000808087224 */
/* 0x000fc800078e0207 */
/*04a0*/ IMAD R18, R9, R9, R8 ; /* 0x0000000909127224 */
/* 0x000fe200078e0208 */
/*04b0*/ @P0 BRA 0x70 ; /* 0xfffffbb000000947 */
/* 0x000fea000383ffff */
/*04c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*04d0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*04e0*/ STG.E [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0001e4000c101904 */
/*04f0*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x001fcc0000015000 */
/*0500*/ IADD3 R4, P0, -R4, R2, RZ ; /* 0x0000000204047210 */
/* 0x000fe40007f1e1ff */
/*0510*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*0520*/ IADD3.X R5, ~R5, R3, RZ, P0, !PT ; /* 0x0000000305057210 */
/* 0x000fe400007fe5ff */
/*0530*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0540*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
#define DATA_SIZE 1048576
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++) {
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop, i) == cudaSuccess) {
if(prop.major >= 1) {
break;
}
}
}
if(i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
cudaSetDevice(i);
return true;
}
void GenerateNumbers(int *number, int size)
{
for(int i = 0; i < size; i++) {
number[i] = rand() % 10;
}
}
__global__ static void sumOfSquares(int *num, int* result, clock_t* time)
{
int sum = 0;
int i;
clock_t start = clock();
for(i = 0; i < DATA_SIZE; i++) {
sum += num[i] * num[i];
}
*result = sum;
*time = clock() - start;
}
int main()
{
if(!InitCUDA()) {
return 0;
}
printf("CUDA initialized.\n");
int data[DATA_SIZE];
GenerateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
clock_t start_g, stop_g;
start_g = clock();
cudaMalloc((void**) &gpudata, sizeof(int) * DATA_SIZE);
cudaMalloc((void**) &result, sizeof(int));
cudaMalloc((void**) &time, sizeof(clock_t));
cudaMemcpy(gpudata, data, sizeof(int) * DATA_SIZE, cudaMemcpyHostToDevice);
sumOfSquares<<<1, 1, 0>>>(gpudata, result, time);
int sum;
clock_t time_used;
cudaMemcpy(&sum, result, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&time_used, time, sizeof(clock_t), cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
cudaFree(time);
stop_g = (clock() - start_g);
printf("sum (GPU): %d time: %f timeg: %f \n", sum, (double)time_used / CLOCKS_PER_SEC, (double) stop_g / CLOCKS_PER_SEC);
clock_t start, stop;
start = clock();
sum = 0;
for(int i = 0; i < DATA_SIZE; i++) {
sum += data[i] * data[i];
}
stop = clock() - start;
printf("sum (CPU): %d time: %f \n", sum, (double)stop / CLOCKS_PER_SEC);
return 0;
} | .file "tmpxft_00106094_00000000-6_first_cuda_sq.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL12sumOfSquaresPiS_Pl, @function
_ZL12sumOfSquaresPiS_Pl:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL12sumOfSquaresPiS_Pl, .-_ZL12sumOfSquaresPiS_Pl
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "There is no device.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "There is no device supporting CUDA 1.x.\n"
.text
.globl _Z8InitCUDAv
.type _Z8InitCUDAv, @function
_Z8InitCUDAv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L22
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L14
jmp .L16
.L22:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %eax
jmp .L9
.L12:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L15
.L14:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L12
cmpl $0, 376(%rsp)
jle .L12
.L15:
cmpl %ebx, 12(%rsp)
je .L23
.L16:
movl %ebx, %edi
call cudaSetDevice@PLT
movl $1, %eax
.L9:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L24
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L9
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8InitCUDAv, .-_Z8InitCUDAv
.globl _Z15GenerateNumbersPii
.type _Z15GenerateNumbersPii, @function
_Z15GenerateNumbersPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L30
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L27:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L27
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z15GenerateNumbersPii, .-_Z15GenerateNumbersPii
.section .rodata.str1.1
.LC2:
.string "CUDA initialized.\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "sum (GPU): %d time: %f timeg: %f \n"
.section .rodata.str1.1
.LC5:
.string "sum (CPU): %d time: %f \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194328
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 4194416
movq %fs:40, %rax
movq %rax, 4194376(%rsp)
xorl %eax, %eax
call _Z8InitCUDAv
testb %al, %al
jne .L40
.L34:
movq 4194376(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $4194392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbp
movl $1048576, %esi
movq %rbp, %rdi
call _Z15GenerateNumbersPii
call clock@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L35:
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC3(%rip), %xmm2
pxor %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
divsd %xmm2, %xmm0
divsd %xmm2, %xmm1
movl 36(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
leaq 64(%rsp), %rdx
leaq 4194368(%rsp), %rsi
movl $0, %ecx
.L36:
movl (%rdx), %eax
imull %eax, %eax
addl %eax, %ecx
addq $4, %rdx
cmpq %rsi, %rdx
jne .L36
movl %ecx, 36(%rsp)
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movl 36(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L34
.L42:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _ZL12sumOfSquaresPiS_Pl
jmp .L35
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12sumOfSquaresPiS_Pl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
#define DATA_SIZE 1048576
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++) {
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop, i) == cudaSuccess) {
if(prop.major >= 1) {
break;
}
}
}
if(i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
cudaSetDevice(i);
return true;
}
void GenerateNumbers(int *number, int size)
{
for(int i = 0; i < size; i++) {
number[i] = rand() % 10;
}
}
__global__ static void sumOfSquares(int *num, int* result, clock_t* time)
{
int sum = 0;
int i;
clock_t start = clock();
for(i = 0; i < DATA_SIZE; i++) {
sum += num[i] * num[i];
}
*result = sum;
*time = clock() - start;
}
int main()
{
if(!InitCUDA()) {
return 0;
}
printf("CUDA initialized.\n");
int data[DATA_SIZE];
GenerateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
clock_t start_g, stop_g;
start_g = clock();
cudaMalloc((void**) &gpudata, sizeof(int) * DATA_SIZE);
cudaMalloc((void**) &result, sizeof(int));
cudaMalloc((void**) &time, sizeof(clock_t));
cudaMemcpy(gpudata, data, sizeof(int) * DATA_SIZE, cudaMemcpyHostToDevice);
sumOfSquares<<<1, 1, 0>>>(gpudata, result, time);
int sum;
clock_t time_used;
cudaMemcpy(&sum, result, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&time_used, time, sizeof(clock_t), cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
cudaFree(time);
stop_g = (clock() - start_g);
printf("sum (GPU): %d time: %f timeg: %f \n", sum, (double)time_used / CLOCKS_PER_SEC, (double) stop_g / CLOCKS_PER_SEC);
clock_t start, stop;
start = clock();
sum = 0;
for(int i = 0; i < DATA_SIZE; i++) {
sum += data[i] * data[i];
}
stop = clock() - start;
printf("sum (CPU): %d time: %f \n", sum, (double)stop / CLOCKS_PER_SEC);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define DATA_SIZE 1048576
bool InitCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++) {
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop, i) == hipSuccess) {
if(prop.major >= 1) {
break;
}
}
}
if(i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
hipSetDevice(i);
return true;
}
void GenerateNumbers(int *number, int size)
{
for(int i = 0; i < size; i++) {
number[i] = rand() % 10;
}
}
__global__ static void sumOfSquares(int *num, int* result, clock_t* time)
{
int sum = 0;
int i;
clock_t start = clock();
for(i = 0; i < DATA_SIZE; i++) {
sum += num[i] * num[i];
}
*result = sum;
*time = clock() - start;
}
int main()
{
if(!InitCUDA()) {
return 0;
}
printf("CUDA initialized.\n");
int data[DATA_SIZE];
GenerateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
clock_t start_g, stop_g;
start_g = clock();
hipMalloc((void**) &gpudata, sizeof(int) * DATA_SIZE);
hipMalloc((void**) &result, sizeof(int));
hipMalloc((void**) &time, sizeof(clock_t));
hipMemcpy(gpudata, data, sizeof(int) * DATA_SIZE, hipMemcpyHostToDevice);
sumOfSquares<<<1, 1, 0>>>(gpudata, result, time);
int sum;
clock_t time_used;
hipMemcpy(&sum, result, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&time_used, time, sizeof(clock_t), hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
hipFree(time);
stop_g = (clock() - start_g);
printf("sum (GPU): %d time: %f timeg: %f \n", sum, (double)time_used / CLOCKS_PER_SEC, (double) stop_g / CLOCKS_PER_SEC);
clock_t start, stop;
start = clock();
sum = 0;
for(int i = 0; i < DATA_SIZE; i++) {
sum += data[i] * data[i];
}
stop = clock() - start;
printf("sum (CPU): %d time: %f \n", sum, (double)stop / CLOCKS_PER_SEC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define DATA_SIZE 1048576
bool InitCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++) {
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop, i) == hipSuccess) {
if(prop.major >= 1) {
break;
}
}
}
if(i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
hipSetDevice(i);
return true;
}
void GenerateNumbers(int *number, int size)
{
for(int i = 0; i < size; i++) {
number[i] = rand() % 10;
}
}
__global__ static void sumOfSquares(int *num, int* result, clock_t* time)
{
int sum = 0;
int i;
clock_t start = clock();
for(i = 0; i < DATA_SIZE; i++) {
sum += num[i] * num[i];
}
*result = sum;
*time = clock() - start;
}
int main()
{
if(!InitCUDA()) {
return 0;
}
printf("CUDA initialized.\n");
int data[DATA_SIZE];
GenerateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
clock_t start_g, stop_g;
start_g = clock();
hipMalloc((void**) &gpudata, sizeof(int) * DATA_SIZE);
hipMalloc((void**) &result, sizeof(int));
hipMalloc((void**) &time, sizeof(clock_t));
hipMemcpy(gpudata, data, sizeof(int) * DATA_SIZE, hipMemcpyHostToDevice);
sumOfSquares<<<1, 1, 0>>>(gpudata, result, time);
int sum;
clock_t time_used;
hipMemcpy(&sum, result, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&time_used, time, sizeof(clock_t), hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
hipFree(time);
stop_g = (clock() - start_g);
printf("sum (GPU): %d time: %f timeg: %f \n", sum, (double)time_used / CLOCKS_PER_SEC, (double) stop_g / CLOCKS_PER_SEC);
clock_t start, stop;
start = clock();
sum = 0;
for(int i = 0; i < DATA_SIZE; i++) {
sum += data[i] * data[i];
}
stop = clock() - start;
printf("sum (CPU): %d time: %f \n", sum, (double)stop / CLOCKS_PER_SEC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.globl _ZL12sumOfSquaresPiS_Pl
.p2align 8
.type _ZL12sumOfSquaresPiS_Pl,@function
_ZL12sumOfSquaresPiS_Pl:
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
s_getreg_b32 s6, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s7, 0
s_mov_b64 s[4:5], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
s_add_u32 s4, s4, 4
global_load_b32 v2, v1, s[8:9]
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 0x400000
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v2, v0
s_cbranch_scc1 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v0, s[0:1]
s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_sub_u32 s0, s0, s6
s_subb_u32 s1, 0, s7
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL12sumOfSquaresPiS_Pl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.Lfunc_end0:
.size _ZL12sumOfSquaresPiS_Pl, .Lfunc_end0-_ZL12sumOfSquaresPiS_Pl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL12sumOfSquaresPiS_Pl
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _ZL12sumOfSquaresPiS_Pl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define DATA_SIZE 1048576
bool InitCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++) {
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop, i) == hipSuccess) {
if(prop.major >= 1) {
break;
}
}
}
if(i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
hipSetDevice(i);
return true;
}
void GenerateNumbers(int *number, int size)
{
for(int i = 0; i < size; i++) {
number[i] = rand() % 10;
}
}
__global__ static void sumOfSquares(int *num, int* result, clock_t* time)
{
int sum = 0;
int i;
clock_t start = clock();
for(i = 0; i < DATA_SIZE; i++) {
sum += num[i] * num[i];
}
*result = sum;
*time = clock() - start;
}
int main()
{
if(!InitCUDA()) {
return 0;
}
printf("CUDA initialized.\n");
int data[DATA_SIZE];
GenerateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
clock_t start_g, stop_g;
start_g = clock();
hipMalloc((void**) &gpudata, sizeof(int) * DATA_SIZE);
hipMalloc((void**) &result, sizeof(int));
hipMalloc((void**) &time, sizeof(clock_t));
hipMemcpy(gpudata, data, sizeof(int) * DATA_SIZE, hipMemcpyHostToDevice);
sumOfSquares<<<1, 1, 0>>>(gpudata, result, time);
int sum;
clock_t time_used;
hipMemcpy(&sum, result, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&time_used, time, sizeof(clock_t), hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
hipFree(time);
stop_g = (clock() - start_g);
printf("sum (GPU): %d time: %f timeg: %f \n", sum, (double)time_used / CLOCKS_PER_SEC, (double) stop_g / CLOCKS_PER_SEC);
clock_t start, stop;
start = clock();
sum = 0;
for(int i = 0; i < DATA_SIZE; i++) {
sum += data[i] * data[i];
}
stop = clock() - start;
printf("sum (CPU): %d time: %f \n", sum, (double)stop / CLOCKS_PER_SEC);
return 0;
} | .text
.file "first_cuda_sq.hip"
.globl _Z8InitCUDAv # -- Begin function _Z8InitCUDAv
.p2align 4, 0x90
.type _Z8InitCUDAv,@function
_Z8InitCUDAv: # @_Z8InitCUDAv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB0_3
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_2
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_8: # in Loop: Header=BB0_6 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_9
.LBB0_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.7: # in Loop: Header=BB0_6 Depth=1
cmpl $0, 368(%rsp)
jle .LBB0_8
jmp .LBB0_9
.LBB0_2:
xorl %ebx, %ebx
.LBB0_9: # %._crit_edge
cmpl 4(%rsp), %ebx
je .LBB0_10
# %bb.11:
movl %ebx, %edi
callq hipSetDevice
movb $1, %al
.LBB0_12:
# kill: def $al killed $al killed $eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $20, %esi
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $40, %esi
.LBB0_4:
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
jmp .LBB0_12
.Lfunc_end0:
.size _Z8InitCUDAv, .Lfunc_end0-_Z8InitCUDAv
.cfi_endproc
# -- End function
.globl _Z15GenerateNumbersPii # -- Begin function _Z15GenerateNumbersPii
.p2align 4, 0x90
.type _Z15GenerateNumbersPii,@function
_Z15GenerateNumbersPii: # @_Z15GenerateNumbersPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15GenerateNumbersPii, .Lfunc_end1-_Z15GenerateNumbersPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4194440, %rsp # imm = 0x400088
.cfi_def_cfa_offset 4194464
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq _Z8InitCUDAv
testb %al, %al
je .LBB2_8
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 128(%rsp,%rbx,4)
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB2_2
# %bb.3: # %_Z15GenerateNumbersPii.exit
callq clock
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 32(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
leaq 48(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
callq clock
subq %rbx, %rax
movl 8(%rsp), %esi
cvtsi2sdq 48(%rsp), %xmm0
movsd .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm0
cvtsi2sd %rax, %xmm1
divsd %xmm2, %xmm1
movl $.L.str.3, %edi
movb $2, %al
callq printf
callq clock
movq %rax, %rbx
movl $0, 8(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rax,4), %ecx
imull %ecx, %ecx
addl %ecx, %r14d
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_6
# %bb.7:
movl %r14d, 8(%rsp)
callq clock
subq %rbx, %rax
movl 8(%rsp), %esi
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
.LBB2_8:
xorl %eax, %eax
addq $4194440, %rsp # imm = 0x400088
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL27__device_stub__sumOfSquaresPiS_Pl
.type _ZL27__device_stub__sumOfSquaresPiS_Pl,@function
_ZL27__device_stub__sumOfSquaresPiS_Pl: # @_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _ZL27__device_stub__sumOfSquaresPiS_Pl, .Lfunc_end3-_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL12sumOfSquaresPiS_Pl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There is no device.\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There is no device supporting CUDA 1.x.\n"
.size .L.str.1, 41
.type _ZL12sumOfSquaresPiS_Pl,@object # @_ZL12sumOfSquaresPiS_Pl
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL12sumOfSquaresPiS_Pl:
.quad _ZL27__device_stub__sumOfSquaresPiS_Pl
.size _ZL12sumOfSquaresPiS_Pl, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "sum (GPU): %d time: %f timeg: %f \n"
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "sum (CPU): %d time: %f \n"
.size .L.str.4, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL12sumOfSquaresPiS_Pl"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA initialized."
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL27__device_stub__sumOfSquaresPiS_Pl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL12sumOfSquaresPiS_Pl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12sumOfSquaresPiS_Pl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fc60000000f00 */
/*0040*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fc80000015000 */
/*0050*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fe200000001ff */
/*0060*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*0070*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R26, [R2.64+0x4] ; /* 0x00000404021a7981 */
/* 0x000ee8000c1e1900 */
/*0090*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*00a0*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*00b0*/ LDG.E R22, [R2.64+0x10] ; /* 0x0000100402167981 */
/* 0x000f68000c1e1900 */
/*00c0*/ LDG.E R23, [R2.64+0x14] ; /* 0x0000140402177981 */
/* 0x000f68000c1e1900 */
/*00d0*/ LDG.E R24, [R2.64+0x18] ; /* 0x0000180402187981 */
/* 0x000f68000c1e1900 */
/*00e0*/ LDG.E R0, [R2.64+0x1c] ; /* 0x00001c0402007981 */
/* 0x000f68000c1e1900 */
/*00f0*/ LDG.E R6, [R2.64+0x20] ; /* 0x0000200402067981 */
/* 0x000f68000c1e1900 */
/*0100*/ LDG.E R7, [R2.64+0x24] ; /* 0x0000240402077981 */
/* 0x000f68000c1e1900 */
/*0110*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280402087981 */
/* 0x000f68000c1e1900 */
/*0120*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000f68000c1e1900 */
/*0130*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R11, [R2.64+0x34] ; /* 0x00003404020b7981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R12, [R2.64+0x38] ; /* 0x00003804020c7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c04020d7981 */
/* 0x000168000c1e1900 */
/*0170*/ LDG.E R14, [R2.64+0x40] ; /* 0x00004004020e7981 */
/* 0x000168000c1e1900 */
/*0180*/ LDG.E R15, [R2.64+0x44] ; /* 0x00004404020f7981 */
/* 0x000168000c1e1900 */
/*0190*/ LDG.E R16, [R2.64+0x48] ; /* 0x0000480402107981 */
/* 0x000168000c1e1900 */
/*01a0*/ LDG.E R17, [R2.64+0x4c] ; /* 0x00004c0402117981 */
/* 0x000162000c1e1900 */
/*01b0*/ IMAD R19, R19, R19, R18 ; /* 0x0000001313137224 */
/* 0x004fc600078e0212 */
/*01c0*/ LDG.E R18, [R2.64+0x50] ; /* 0x0000500402127981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ IMAD R27, R26, R26, R19 ; /* 0x0000001a1a1b7224 */
/* 0x008fc600078e0213 */
/*01e0*/ LDG.E R19, [R2.64+0x54] ; /* 0x0000540402137981 */
/* 0x0000e2000c1e1900 */
/*01f0*/ IMAD R26, R20, R20, R27 ; /* 0x00000014141a7224 */
/* 0x010fc600078e021b */
/*0200*/ LDG.E R20, [R2.64+0x58] ; /* 0x0000580402147981 */
/* 0x000122000c1e1900 */
/*0210*/ IMAD R27, R21, R21, R26 ; /* 0x00000015151b7224 */
/* 0x020fc600078e021a */
/*0220*/ LDG.E R21, [R2.64+0x5c] ; /* 0x00005c0402157981 */
/* 0x000162000c1e1900 */
/*0230*/ IMAD R26, R22, R22, R27 ; /* 0x00000016161a7224 */
/* 0x000fc600078e021b */
/*0240*/ LDG.E R22, [R2.64+0x60] ; /* 0x0000600402167981 */
/* 0x000162000c1e1900 */
/*0250*/ IMAD R27, R23, R23, R26 ; /* 0x00000017171b7224 */
/* 0x000fc600078e021a */
/*0260*/ LDG.E R23, [R2.64+0x64] ; /* 0x0000640402177981 */
/* 0x000162000c1e1900 */
/*0270*/ IMAD R27, R24, R24, R27 ; /* 0x00000018181b7224 */
/* 0x000fc600078e021b */
/*0280*/ LDG.E R24, [R2.64+0x68] ; /* 0x0000680402187981 */
/* 0x000162000c1e1900 */
/*0290*/ IMAD R27, R0, R0, R27 ; /* 0x00000000001b7224 */
/* 0x000fc600078e021b */
/*02a0*/ LDG.E R0, [R2.64+0x6c] ; /* 0x00006c0402007981 */
/* 0x000162000c1e1900 */
/*02b0*/ IMAD R26, R6, R6, R27 ; /* 0x00000006061a7224 */
/* 0x000fc600078e021b */
/*02c0*/ LDG.E R6, [R2.64+0x70] ; /* 0x0000700402067981 */
/* 0x000162000c1e1900 */
/*02d0*/ IMAD R27, R7, R7, R26 ; /* 0x00000007071b7224 */
/* 0x000fc600078e021a */
/*02e0*/ LDG.E R7, [R2.64+0x74] ; /* 0x0000740402077981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD R26, R8, R8, R27 ; /* 0x00000008081a7224 */
/* 0x000fc600078e021b */
/*0300*/ LDG.E R8, [R2.64+0x78] ; /* 0x0000780402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IMAD R27, R9, R9, R26 ; /* 0x00000009091b7224 */
/* 0x000fc600078e021a */
/*0320*/ LDG.E R9, [R2.64+0x7c] ; /* 0x00007c0402097981 */
/* 0x000162000c1e1900 */
/*0330*/ IADD3 R25, R25, 0x20, RZ ; /* 0x0000002019197810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R10, R10, R10, R27 ; /* 0x0000000a0a0a7224 */
/* 0x000fc600078e021b */
/*0350*/ ISETP.NE.AND P0, PT, R25, 0x100000, PT ; /* 0x001000001900780c */
/* 0x000fe20003f05270 */
/*0360*/ IMAD R11, R11, R11, R10 ; /* 0x0000000b0b0b7224 */
/* 0x000fc800078e020a */
/*0370*/ IMAD R12, R12, R12, R11 ; /* 0x0000000c0c0c7224 */
/* 0x000fe200078e020b */
/*0380*/ IADD3 R2, P1, R2, 0x80, RZ ; /* 0x0000008002027810 */
/* 0x001fc60007f3e0ff */
/*0390*/ IMAD R13, R13, R13, R12 ; /* 0x0000000d0d0d7224 */
/* 0x000fe200078e020c */
/*03a0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*03b0*/ IMAD R14, R14, R14, R13 ; /* 0x0000000e0e0e7224 */
/* 0x000fc800078e020d */
/*03c0*/ IMAD R15, R15, R15, R14 ; /* 0x0000000f0f0f7224 */
/* 0x000fc800078e020e */
/*03d0*/ IMAD R16, R16, R16, R15 ; /* 0x0000001010107224 */
/* 0x000fc800078e020f */
/*03e0*/ IMAD R17, R17, R17, R16 ; /* 0x0000001111117224 */
/* 0x000fc800078e0210 */
/*03f0*/ IMAD R18, R18, R18, R17 ; /* 0x0000001212127224 */
/* 0x004fc800078e0211 */
/*0400*/ IMAD R19, R19, R19, R18 ; /* 0x0000001313137224 */
/* 0x008fc800078e0212 */
/*0410*/ IMAD R20, R20, R20, R19 ; /* 0x0000001414147224 */
/* 0x010fc800078e0213 */
/*0420*/ IMAD R21, R21, R21, R20 ; /* 0x0000001515157224 */
/* 0x020fc800078e0214 */
/*0430*/ IMAD R22, R22, R22, R21 ; /* 0x0000001616167224 */
/* 0x000fc800078e0215 */
/*0440*/ IMAD R23, R23, R23, R22 ; /* 0x0000001717177224 */
/* 0x000fc800078e0216 */
/*0450*/ IMAD R23, R24, R24, R23 ; /* 0x0000001818177224 */
/* 0x000fc800078e0217 */
/*0460*/ IMAD R23, R0, R0, R23 ; /* 0x0000000000177224 */
/* 0x000fc800078e0217 */
/*0470*/ IMAD R6, R6, R6, R23 ; /* 0x0000000606067224 */
/* 0x000fc800078e0217 */
/*0480*/ IMAD R7, R7, R7, R6 ; /* 0x0000000707077224 */
/* 0x000fc800078e0206 */
/*0490*/ IMAD R8, R8, R8, R7 ; /* 0x0000000808087224 */
/* 0x000fc800078e0207 */
/*04a0*/ IMAD R18, R9, R9, R8 ; /* 0x0000000909127224 */
/* 0x000fe200078e0208 */
/*04b0*/ @P0 BRA 0x70 ; /* 0xfffffbb000000947 */
/* 0x000fea000383ffff */
/*04c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*04d0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*04e0*/ STG.E [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0001e4000c101904 */
/*04f0*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x001fcc0000015000 */
/*0500*/ IADD3 R4, P0, -R4, R2, RZ ; /* 0x0000000204047210 */
/* 0x000fe40007f1e1ff */
/*0510*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*0520*/ IADD3.X R5, ~R5, R3, RZ, P0, !PT ; /* 0x0000000305057210 */
/* 0x000fe400007fe5ff */
/*0530*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0540*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.globl _ZL12sumOfSquaresPiS_Pl
.p2align 8
.type _ZL12sumOfSquaresPiS_Pl,@function
_ZL12sumOfSquaresPiS_Pl:
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
s_getreg_b32 s6, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s7, 0
s_mov_b64 s[4:5], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
s_add_u32 s4, s4, 4
global_load_b32 v2, v1, s[8:9]
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 0x400000
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v2, v0
s_cbranch_scc1 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v0, s[0:1]
s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_sub_u32 s0, s0, s6
s_subb_u32 s1, 0, s7
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL12sumOfSquaresPiS_Pl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.Lfunc_end0:
.size _ZL12sumOfSquaresPiS_Pl, .Lfunc_end0-_ZL12sumOfSquaresPiS_Pl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL12sumOfSquaresPiS_Pl
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _ZL12sumOfSquaresPiS_Pl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00106094_00000000-6_first_cuda_sq.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL12sumOfSquaresPiS_Pl, @function
_ZL12sumOfSquaresPiS_Pl:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL12sumOfSquaresPiS_Pl, .-_ZL12sumOfSquaresPiS_Pl
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "There is no device.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "There is no device supporting CUDA 1.x.\n"
.text
.globl _Z8InitCUDAv
.type _Z8InitCUDAv, @function
_Z8InitCUDAv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L22
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L14
jmp .L16
.L22:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %eax
jmp .L9
.L12:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L15
.L14:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L12
cmpl $0, 376(%rsp)
jle .L12
.L15:
cmpl %ebx, 12(%rsp)
je .L23
.L16:
movl %ebx, %edi
call cudaSetDevice@PLT
movl $1, %eax
.L9:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L24
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L9
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8InitCUDAv, .-_Z8InitCUDAv
.globl _Z15GenerateNumbersPii
.type _Z15GenerateNumbersPii, @function
_Z15GenerateNumbersPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L30
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L27:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L27
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z15GenerateNumbersPii, .-_Z15GenerateNumbersPii
.section .rodata.str1.1
.LC2:
.string "CUDA initialized.\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "sum (GPU): %d time: %f timeg: %f \n"
.section .rodata.str1.1
.LC5:
.string "sum (CPU): %d time: %f \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194328
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 4194416
movq %fs:40, %rax
movq %rax, 4194376(%rsp)
xorl %eax, %eax
call _Z8InitCUDAv
testb %al, %al
jne .L40
.L34:
movq 4194376(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $4194392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbp
movl $1048576, %esi
movq %rbp, %rdi
call _Z15GenerateNumbersPii
call clock@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L35:
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC3(%rip), %xmm2
pxor %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
divsd %xmm2, %xmm0
divsd %xmm2, %xmm1
movl 36(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
leaq 64(%rsp), %rdx
leaq 4194368(%rsp), %rsi
movl $0, %ecx
.L36:
movl (%rdx), %eax
imull %eax, %eax
addl %eax, %ecx
addq $4, %rdx
cmpq %rsi, %rdx
jne .L36
movl %ecx, 36(%rsp)
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movl 36(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L34
.L42:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _ZL12sumOfSquaresPiS_Pl
jmp .L35
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12sumOfSquaresPiS_Pl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "first_cuda_sq.hip"
.globl _Z8InitCUDAv # -- Begin function _Z8InitCUDAv
.p2align 4, 0x90
.type _Z8InitCUDAv,@function
_Z8InitCUDAv: # @_Z8InitCUDAv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB0_3
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_2
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_8: # in Loop: Header=BB0_6 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_9
.LBB0_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.7: # in Loop: Header=BB0_6 Depth=1
cmpl $0, 368(%rsp)
jle .LBB0_8
jmp .LBB0_9
.LBB0_2:
xorl %ebx, %ebx
.LBB0_9: # %._crit_edge
cmpl 4(%rsp), %ebx
je .LBB0_10
# %bb.11:
movl %ebx, %edi
callq hipSetDevice
movb $1, %al
.LBB0_12:
# kill: def $al killed $al killed $eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $20, %esi
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $40, %esi
.LBB0_4:
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
jmp .LBB0_12
.Lfunc_end0:
.size _Z8InitCUDAv, .Lfunc_end0-_Z8InitCUDAv
.cfi_endproc
# -- End function
.globl _Z15GenerateNumbersPii # -- Begin function _Z15GenerateNumbersPii
.p2align 4, 0x90
.type _Z15GenerateNumbersPii,@function
_Z15GenerateNumbersPii: # @_Z15GenerateNumbersPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15GenerateNumbersPii, .Lfunc_end1-_Z15GenerateNumbersPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4194440, %rsp # imm = 0x400088
.cfi_def_cfa_offset 4194464
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq _Z8InitCUDAv
testb %al, %al
je .LBB2_8
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 128(%rsp,%rbx,4)
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB2_2
# %bb.3: # %_Z15GenerateNumbersPii.exit
callq clock
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 32(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
leaq 48(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
callq clock
subq %rbx, %rax
movl 8(%rsp), %esi
cvtsi2sdq 48(%rsp), %xmm0
movsd .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm0
cvtsi2sd %rax, %xmm1
divsd %xmm2, %xmm1
movl $.L.str.3, %edi
movb $2, %al
callq printf
callq clock
movq %rax, %rbx
movl $0, 8(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rax,4), %ecx
imull %ecx, %ecx
addl %ecx, %r14d
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_6
# %bb.7:
movl %r14d, 8(%rsp)
callq clock
subq %rbx, %rax
movl 8(%rsp), %esi
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
.LBB2_8:
xorl %eax, %eax
addq $4194440, %rsp # imm = 0x400088
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL27__device_stub__sumOfSquaresPiS_Pl
.type _ZL27__device_stub__sumOfSquaresPiS_Pl,@function
_ZL27__device_stub__sumOfSquaresPiS_Pl: # @_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _ZL27__device_stub__sumOfSquaresPiS_Pl, .Lfunc_end3-_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL12sumOfSquaresPiS_Pl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There is no device.\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There is no device supporting CUDA 1.x.\n"
.size .L.str.1, 41
.type _ZL12sumOfSquaresPiS_Pl,@object # @_ZL12sumOfSquaresPiS_Pl
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL12sumOfSquaresPiS_Pl:
.quad _ZL27__device_stub__sumOfSquaresPiS_Pl
.size _ZL12sumOfSquaresPiS_Pl, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "sum (GPU): %d time: %f timeg: %f \n"
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "sum (CPU): %d time: %f \n"
.size .L.str.4, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL12sumOfSquaresPiS_Pl"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA initialized."
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL27__device_stub__sumOfSquaresPiS_Pl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL12sumOfSquaresPiS_Pl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void InterpolateVectorKernel( int r, int q, int f, int inputSize, float *referenceVector )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
referenceVector[r * inputSize + threadId] = 0.50f * (referenceVector[q * inputSize + threadId] + referenceVector[f * inputSize + threadId]);
}
} | code for sm_80
Function : _Z23InterpolateVectorKerneliiiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IMAD R4, R7.reuse, c[0x0][0x168], R0.reuse ; /* 0x00005a0007047a24 */
/* 0x140fe400078e0200 */
/*00c0*/ IMAD R2, R7, c[0x0][0x164], R0 ; /* 0x0000590007027a24 */
/* 0x000fe400078e0200 */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe400078e0209 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD R6, R7, c[0x0][0x160], R0 ; /* 0x0000580007067a24 */
/* 0x000fc800078e0200 */
/*0120*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0209 */
/*0130*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */
/* 0x004fc80000000000 */
/*0140*/ FMUL R9, R0, 0.5 ; /* 0x3f00000000097820 */
/* 0x000fca0000400000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void InterpolateVectorKernel( int r, int q, int f, int inputSize, float *referenceVector )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
referenceVector[r * inputSize + threadId] = 0.50f * (referenceVector[q * inputSize + threadId] + referenceVector[f * inputSize + threadId]);
}
} | .file "tmpxft_000c8079_00000000-6_InterpolateVectorKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf
.type _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf, @function
_Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23InterpolateVectorKerneliiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf, .-_Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf
.globl _Z23InterpolateVectorKerneliiiiPf
.type _Z23InterpolateVectorKerneliiiiPf, @function
_Z23InterpolateVectorKerneliiiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23InterpolateVectorKerneliiiiPf, .-_Z23InterpolateVectorKerneliiiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23InterpolateVectorKerneliiiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23InterpolateVectorKerneliiiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void InterpolateVectorKernel( int r, int q, int f, int inputSize, float *referenceVector )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
referenceVector[r * inputSize + threadId] = 0.50f * (referenceVector[q * inputSize + threadId] + referenceVector[f * inputSize + threadId]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InterpolateVectorKernel( int r, int q, int f, int inputSize, float *referenceVector )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
referenceVector[r * inputSize + threadId] = 0.50f * (referenceVector[q * inputSize + threadId] + referenceVector[f * inputSize + threadId]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InterpolateVectorKernel( int r, int q, int f, int inputSize, float *referenceVector )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
referenceVector[r * inputSize + threadId] = 0.50f * (referenceVector[q * inputSize + threadId] + referenceVector[f * inputSize + threadId]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23InterpolateVectorKerneliiiiPf
.globl _Z23InterpolateVectorKerneliiiiPf
.p2align 8
.type _Z23InterpolateVectorKerneliiiiPf,@function
_Z23InterpolateVectorKerneliiiiPf:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s2, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v4, v[4:5], off
v_mad_u64_u32 v[2:3], null, s2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v4
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0.5, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23InterpolateVectorKerneliiiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23InterpolateVectorKerneliiiiPf, .Lfunc_end0-_Z23InterpolateVectorKerneliiiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23InterpolateVectorKerneliiiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23InterpolateVectorKerneliiiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InterpolateVectorKernel( int r, int q, int f, int inputSize, float *referenceVector )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < inputSize)
{
referenceVector[r * inputSize + threadId] = 0.50f * (referenceVector[q * inputSize + threadId] + referenceVector[f * inputSize + threadId]);
}
} | .text
.file "InterpolateVectorKernel.hip"
.globl _Z38__device_stub__InterpolateVectorKerneliiiiPf # -- Begin function _Z38__device_stub__InterpolateVectorKerneliiiiPf
.p2align 4, 0x90
.type _Z38__device_stub__InterpolateVectorKerneliiiiPf,@function
_Z38__device_stub__InterpolateVectorKerneliiiiPf: # @_Z38__device_stub__InterpolateVectorKerneliiiiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23InterpolateVectorKerneliiiiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__InterpolateVectorKerneliiiiPf, .Lfunc_end0-_Z38__device_stub__InterpolateVectorKerneliiiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23InterpolateVectorKerneliiiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23InterpolateVectorKerneliiiiPf,@object # @_Z23InterpolateVectorKerneliiiiPf
.section .rodata,"a",@progbits
.globl _Z23InterpolateVectorKerneliiiiPf
.p2align 3, 0x0
_Z23InterpolateVectorKerneliiiiPf:
.quad _Z38__device_stub__InterpolateVectorKerneliiiiPf
.size _Z23InterpolateVectorKerneliiiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23InterpolateVectorKerneliiiiPf"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__InterpolateVectorKerneliiiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23InterpolateVectorKerneliiiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23InterpolateVectorKerneliiiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IMAD R4, R7.reuse, c[0x0][0x168], R0.reuse ; /* 0x00005a0007047a24 */
/* 0x140fe400078e0200 */
/*00c0*/ IMAD R2, R7, c[0x0][0x164], R0 ; /* 0x0000590007027a24 */
/* 0x000fe400078e0200 */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe400078e0209 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD R6, R7, c[0x0][0x160], R0 ; /* 0x0000580007067a24 */
/* 0x000fc800078e0200 */
/*0120*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0209 */
/*0130*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */
/* 0x004fc80000000000 */
/*0140*/ FMUL R9, R0, 0.5 ; /* 0x3f00000000097820 */
/* 0x000fca0000400000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23InterpolateVectorKerneliiiiPf
.globl _Z23InterpolateVectorKerneliiiiPf
.p2align 8
.type _Z23InterpolateVectorKerneliiiiPf,@function
_Z23InterpolateVectorKerneliiiiPf:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s2, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v4, v[4:5], off
v_mad_u64_u32 v[2:3], null, s2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v4
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0.5, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23InterpolateVectorKerneliiiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23InterpolateVectorKerneliiiiPf, .Lfunc_end0-_Z23InterpolateVectorKerneliiiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23InterpolateVectorKerneliiiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23InterpolateVectorKerneliiiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c8079_00000000-6_InterpolateVectorKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf
.type _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf, @function
_Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23InterpolateVectorKerneliiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf, .-_Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf
.globl _Z23InterpolateVectorKerneliiiiPf
.type _Z23InterpolateVectorKerneliiiiPf, @function
_Z23InterpolateVectorKerneliiiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23InterpolateVectorKerneliiiiPfiiiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23InterpolateVectorKerneliiiiPf, .-_Z23InterpolateVectorKerneliiiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23InterpolateVectorKerneliiiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23InterpolateVectorKerneliiiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "InterpolateVectorKernel.hip"
.globl _Z38__device_stub__InterpolateVectorKerneliiiiPf # -- Begin function _Z38__device_stub__InterpolateVectorKerneliiiiPf
.p2align 4, 0x90
.type _Z38__device_stub__InterpolateVectorKerneliiiiPf,@function
_Z38__device_stub__InterpolateVectorKerneliiiiPf: # @_Z38__device_stub__InterpolateVectorKerneliiiiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23InterpolateVectorKerneliiiiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__InterpolateVectorKerneliiiiPf, .Lfunc_end0-_Z38__device_stub__InterpolateVectorKerneliiiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23InterpolateVectorKerneliiiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23InterpolateVectorKerneliiiiPf,@object # @_Z23InterpolateVectorKerneliiiiPf
.section .rodata,"a",@progbits
.globl _Z23InterpolateVectorKerneliiiiPf
.p2align 3, 0x0
_Z23InterpolateVectorKerneliiiiPf:
.quad _Z38__device_stub__InterpolateVectorKerneliiiiPf
.size _Z23InterpolateVectorKerneliiiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23InterpolateVectorKerneliiiiPf"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__InterpolateVectorKerneliiiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23InterpolateVectorKerneliiiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright (c) 2012 by Jörn Dinkla, www.dinkla.com, All rights reserved.
*/
#include <stdio.h>
// extern "C" ist notwendig, damit cuModuleGetFunction die Funktion findet
extern "C"
__global__ void hello()
{
int i = threadIdx.x;
int j = blockIdx.x;
printf("Hello World %i %i\n", i, j);
} | code for sm_80
Function : hello
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2012 by Jörn Dinkla, www.dinkla.com, All rights reserved.
*/
#include <stdio.h>
// extern "C" ist notwendig, damit cuModuleGetFunction die Funktion findet
extern "C"
__global__ void hello()
{
int i = threadIdx.x;
int j = blockIdx.x;
printf("Hello World %i %i\n", i, j);
} | .file "tmpxft_000d26db_00000000-6_helloWorld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq hello(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl hello
.type hello, @function
hello:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size hello, .-hello
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq hello(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2012 by Jörn Dinkla, www.dinkla.com, All rights reserved.
*/
#include <stdio.h>
// extern "C" ist notwendig, damit cuModuleGetFunction die Funktion findet
extern "C"
__global__ void hello()
{
int i = threadIdx.x;
int j = blockIdx.x;
printf("Hello World %i %i\n", i, j);
} | /*
* Copyright (c) 2012 by Jörn Dinkla, www.dinkla.com, All rights reserved.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
// extern "C" ist notwendig, damit cuModuleGetFunction die Funktion findet
extern "C"
__global__ void hello()
{
int i = threadIdx.x;
int j = blockIdx.x;
printf("Hello World %i %i\n", i, j);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright (c) 2012 by Jörn Dinkla, www.dinkla.com, All rights reserved.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
// extern "C" ist notwendig, damit cuModuleGetFunction die Funktion findet
extern "C"
__global__ void hello()
{
int i = threadIdx.x;
int j = blockIdx.x;
printf("Hello World %i %i\n", i, j);
} | .text
.file "helloWorld.hip"
.globl __device_stub__hello # -- Begin function __device_stub__hello
.p2align 4, 0x90
.type __device_stub__hello,@function
__device_stub__hello: # @__device_stub__hello
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $hello, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__hello, .Lfunc_end0-__device_stub__hello
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $hello, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type hello,@object # @hello
.section .rodata,"a",@progbits
.globl hello
.p2align 3, 0x0
hello:
.quad __device_stub__hello
.size hello, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "hello"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__hello
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym hello
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d26db_00000000-6_helloWorld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq hello(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl hello
.type hello, @function
hello:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size hello, .-hello
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq hello(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloWorld.hip"
.globl __device_stub__hello # -- Begin function __device_stub__hello
.p2align 4, 0x90
.type __device_stub__hello,@function
__device_stub__hello: # @__device_stub__hello
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $hello, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__hello, .Lfunc_end0-__device_stub__hello
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $hello, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type hello,@object # @hello
.section .rodata,"a",@progbits
.globl hello
.p2align 3, 0x0
hello:
.quad __device_stub__hello
.size hello, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "hello"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__hello
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym hello
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef __TILED_KERNEL__
#define __TILED_KERNEL__
#include<cuda_runtime.h>
__global__ void normal(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int sum=0;
if(bx*blockDim.x+tx<row && by*blockDim.y+ty<row){
for(int i=0;i<row;i++){
sum+=input1[ty*row+i]*input2[i*row+tx];
}
output[bx*blockDim.x+tx+(by*blockDim.y+ty)*row]=sum;
}
}
template <int blockSize>
__global__ void tile(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int targetx=bx*blockSize+tx;
int targety=by*blockSize+ty;
__shared__ float smemA[blockSize][blockSize];
__shared__ float smemB[blockSize][blockSize];
int totalPhase=(blockSize+row-1)/blockSize;
int startA=by*blockSize*row;
int startB=bx*blockSize;
int stepA=blockSize;
int stepB=blockSize*row;
float sum=0;
for(int i=0;i<totalPhase;i++){
//start phase,load share memory
if((i*blockSize+tx<row)&&(by*blockSize+ty<row))
smemA[ty][tx]=input1[startA+tx+row*ty];
else
{
smemA[ty][tx]=0;
}
if((bx*blockSize+tx<row)&&(i*blockSize+ty<row))
smemB[ty][tx]=input2[startB+tx+row*ty];
else
{
smemB[ty][tx]=0;
}
startA+=stepA;
startB+=stepB;
__syncthreads();
for(int j=0;j<blockSize;j++){
sum+=smemA[ty][j]*smemB[j][tx];
}
__syncthreads();
}
if(targetx<row&&targety<row){
output[targetx+targety*row]=sum;
}
}
#endif | code for sm_80
Function : _Z6normaliPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R4, R5, c[0x0][0x0], R2 ; /* 0x0000000005047a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R4, c[0x0][0x160], P0 ; /* 0x0000580004007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xfa0 ; /* 0x00000eb000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, R5.reuse, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x040fe40007ffe0ff */
/*0100*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe40000000f00 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0120*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fe400078ec0ff */
/*0130*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xe80 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R8, -R6, c[0x0][0x160], RZ ; /* 0x0000580006087a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R29, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1d7435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R9, R0, c[0x0][0x160], RZ ; /* 0x0000580000097a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R28, R2, R29, c[0x0][0x170] ; /* 0x00005c00021c7625 */
/* 0x000fcc00078e021d */
/*01d0*/ @!P0 BRA 0xc70 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x8b0 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x0010a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R18, R5, 0x4, R28 ; /* 0x0000000405127825 */
/* 0x000fc600078e021c */
/*0280*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0022e2000c1e1900 */
/*02a0*/ IMAD.WIDE R16, R5, 0x4, R18 ; /* 0x0000000405107825 */
/* 0x000fc600078e0212 */
/*02b0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x000b22000c1e1900 */
/*02d0*/ IMAD.WIDE R14, R5, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x000fc600078e0210 */
/*02e0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000ee8000c1e1900 */
/*02f0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x0002e2000c1e1900 */
/*0300*/ IMAD.WIDE R16, R5, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x020fc600078e020e */
/*0310*/ LDG.E R27, [R12.64+0x10] ; /* 0x000010040c1b7981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0010e2000c1e1900 */
/*0330*/ IMAD.WIDE R18, R5, 0x4, R16 ; /* 0x0000000405127825 */
/* 0x002fc600078e0210 */
/*0340*/ LDG.E R29, [R12.64+0x14] ; /* 0x000014040c1d7981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000322000c1e1900 */
/*0360*/ FFMA R20, R23, R22, R20 ; /* 0x0000001617147223 */
/* 0x004fe40000000014 */
/*0370*/ IMAD.WIDE R22, R5, 0x4, R18 ; /* 0x0000000405167825 */
/* 0x000fe400078e0212 */
/*0380*/ F2I.TRUNC.NTZ R18, R20 ; /* 0x0000001400127305 */
/* 0x0022a6000020f100 */
/*0390*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x002f62000c1e1900 */
/*03b0*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x004ee40000201400 */
/*03c0*/ FFMA R19, R10, R11, R18 ; /* 0x0000000b0a137223 */
/* 0x008fc40000000012 */
/*03d0*/ IMAD.WIDE R10, R5, 0x4, R22 ; /* 0x00000004050a7825 */
/* 0x000fc800078e0216 */
/*03e0*/ F2I.TRUNC.NTZ R16, R19 ; /* 0x0000001300107305 */
/* 0x001e22000020f100 */
/*03f0*/ LDG.E R23, [R12.64+0x1c] ; /* 0x00001c040c177981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x0002a6000c1e1900 */
/*0410*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x001f240000201400 */
/*0420*/ FFMA R18, R21, R24, R16 ; /* 0x0000001815127223 */
/* 0x010fc40000000010 */
/*0430*/ IMAD.WIDE R16, R5, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x000fe200078e020a */
/*0440*/ LDG.E R24, [R12.64+0x20] ; /* 0x000020040c187981 */
/* 0x000ee8000c1e1900 */
/*0450*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0000e2000c1e1900 */
/*0460*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000f30000020f100 */
/*0470*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x010f240000201400 */
/*0480*/ FFMA R25, R25, R26, R18 ; /* 0x0000001a19197223 */
/* 0x010fc40000000012 */
/*0490*/ IMAD.WIDE R18, R5, 0x4, R16 ; /* 0x0000000405127825 */
/* 0x000fc800078e0210 */
/*04a0*/ F2I.TRUNC.NTZ R10, R25 ; /* 0x00000019000a7305 */
/* 0x002322000020f100 */
/*04b0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x0000e8000c1e1900 */
/*04c0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002ee6000c1e1900 */
/*04d0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x010e640000201400 */
/*04e0*/ FFMA R27, R28, R27, R10 ; /* 0x0000001b1c1b7223 */
/* 0x002fc4000000000a */
/*04f0*/ IMAD.WIDE R10, R5, 0x4, R18 ; /* 0x00000004050a7825 */
/* 0x000fc800078e0212 */
/*0500*/ F2I.TRUNC.NTZ R16, R27 ; /* 0x0000001b00107305 */
/* 0x001062000020f100 */
/*0510*/ LDG.E R19, [R12.64+0x2c] ; /* 0x00002c040c137981 */
/* 0x000f28000c1e1900 */
/*0520*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000328000c1e1900 */
/*0530*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x001f22000c1e1900 */
/*0540*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x002e240000201400 */
/*0550*/ FFMA R14, R14, R29, R16 ; /* 0x0000001d0e0e7223 */
/* 0x001fc40000000010 */
/*0560*/ IMAD.WIDE R16, R5, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x000fc800078e020a */
/*0570*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e22000020f100 */
/*0580*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x00032e000c1e1900 */
/*0590*/ I2F R29, R14 ; /* 0x0000000e001d7306 */
/* 0x001f640000201400 */
/*05a0*/ FFMA R20, R15, R20, R29 ; /* 0x000000140f147223 */
/* 0x020fc4000000001d */
/*05b0*/ IMAD.WIDE R14, R5, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x000fe200078e0210 */
/*05c0*/ LDG.E R29, [R12.64+0x30] ; /* 0x000030040c1d7981 */
/* 0x000166000c1e1900 */
/*05d0*/ F2I.TRUNC.NTZ R10, R20 ; /* 0x00000014000a7305 */
/* 0x000064000020f100 */
/*05e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x00116c000c1e1900 */
/*05f0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x002ea40000201400 */
/*0600*/ FFMA R22, R22, R23, R10 ; /* 0x0000001716167223 */
/* 0x004fc4000000000a */
/*0610*/ IMAD.WIDE R10, R5, 0x4, R14 ; /* 0x00000004050a7825 */
/* 0x000fe200078e020e */
/*0620*/ LDG.E R23, [R12.64+0x34] ; /* 0x000034040c177981 */
/* 0x0002a6000c1e1900 */
/*0630*/ F2I.TRUNC.NTZ R15, R22 ; /* 0x00000016000f7305 */
/* 0x001064000020f100 */
/*0640*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x0010ac000c1e1900 */
/*0650*/ I2F R16, R15 ; /* 0x0000000f00107306 */
/* 0x002ee40000201400 */
/*0660*/ FFMA R21, R21, R24, R16 ; /* 0x0000001815157223 */
/* 0x008fc40000000010 */
/*0670*/ IMAD.WIDE R16, R5.reuse, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x040fe400078e020a */
/*0680*/ LDG.E R11, [R12.64+0x38] ; /* 0x000038040c0b7981 */
/* 0x0010e8000c1e1900 */
/*0690*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x0002e2000c1e1900 */
/*06a0*/ IMAD.WIDE R14, R5, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x000fca00078e0210 */
/*06b0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ LDG.E R17, [R12.64+0x3c] ; /* 0x00003c040c117981 */
/* 0x0020e2000c1e1900 */
/*06d0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e70000020f100 */
/*06e0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002e640000201400 */
/*06f0*/ FFMA R25, R26, R25, R21 ; /* 0x000000191a197223 */
/* 0x002fcc0000000015 */
/*0700*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000e70000020f100 */
/*0710*/ I2F R26, R25 ; /* 0x00000019001a7306 */
/* 0x002f240000201400 */
/*0720*/ FFMA R26, R28, R27, R26 ; /* 0x0000001b1c1a7223 */
/* 0x010fcc000000001a */
/*0730*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e70000020f100 */
/*0740*/ I2F R16, R26 ; /* 0x0000001a00107306 */
/* 0x002e640000201400 */
/*0750*/ FFMA R16, R18, R19, R16 ; /* 0x0000001312107223 */
/* 0x002fcc0000000010 */
/*0760*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0770*/ I2F R12, R16 ; /* 0x00000010000c7306 */
/* 0x001f640000201400 */
/*0780*/ FFMA R12, R20, R29, R12 ; /* 0x0000001d140c7223 */
/* 0x020fcc000000000c */
/*0790*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*07a0*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001ea40000201400 */
/*07b0*/ FFMA R13, R22, R23, R13 ; /* 0x00000017160d7223 */
/* 0x004fcc000000000d */
/*07c0*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*07d0*/ I2F R18, R13 ; /* 0x0000000d00127306 */
/* 0x001ee40000201400 */
/*07e0*/ FFMA R11, R24, R11, R18 ; /* 0x0000000b180b7223 */
/* 0x008fcc0000000012 */
/*07f0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0800*/ I2F R18, R11 ; /* 0x0000000b00127306 */
/* 0x001e220000201400 */
/*0810*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0820*/ FFMA R10, R10, R17, R18 ; /* 0x000000110a0a7223 */
/* 0x001fcc0000000012 */
/*0830*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*0840*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0850*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0860*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc60007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0880*/ I2F R20, R10 ; /* 0x0000000a00147306 */
/* 0x0010620000201400 */
/*0890*/ IMAD.WIDE R28, R5, 0x4, R14 ; /* 0x00000004051c7825 */
/* 0x000fca00078e020e */
/*08a0*/ @P1 BRA 0x220 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*08b0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xc50 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*08e0*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x0004e2000c1e1900 */
/*08f0*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0900*/ IMAD.WIDE R14, R9, 0x4, R14 ; /* 0x00000004090e7825 */
/* 0x000fca00078e020e */
/*0910*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IMAD.WIDE R18, R5, 0x4, R28 ; /* 0x0000000405127825 */
/* 0x000fc600078e021c */
/*0930*/ LDG.E R10, [R14.64+0x4] ; /* 0x000004040e0a7981 */
/* 0x001f28000c1e1900 */
/*0940*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x000128000c1e1900 */
/*0950*/ LDG.E R11, [R14.64+0x8] ; /* 0x000008040e0b7981 */
/* 0x000f68000c1e1900 */
/*0960*/ LDG.E R27, [R14.64+0xc] ; /* 0x00000c040e1b7981 */
/* 0x000f22000c1e1900 */
/*0970*/ IMAD.WIDE R18, R5, 0x4, R18 ; /* 0x0000000405127825 */
/* 0x001fc600078e0212 */
/*0980*/ LDG.E R25, [R14.64+0x10] ; /* 0x000010040e197981 */
/* 0x000128000c1e1900 */
/*0990*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000362000c1e1900 */
/*09a0*/ IMAD.WIDE R16, R5, 0x4, R18 ; /* 0x0000000405107825 */
/* 0x000fc600078e0212 */
/*09b0*/ LDG.E R28, [R14.64+0x14] ; /* 0x000014040e1c7981 */
/* 0x0040a8000c1e1900 */
/*09c0*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x0000a4000c1e1900 */
/*09d0*/ IMAD.WIDE R16, R5, 0x4, R16 ; /* 0x0000000405107825 */
/* 0x001fca00078e0210 */
/*09e0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0006a2000c1e1900 */
/*09f0*/ IMAD.WIDE R18, R5, 0x4, R16 ; /* 0x0000000405127825 */
/* 0x002fca00078e0210 */
/*0a00*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x0000a2000c1e1900 */
/*0a10*/ FFMA R16, R21, R22, R20 ; /* 0x0000001615107223 */
/* 0x008fe40000000014 */
/*0a20*/ IMAD.WIDE R20, R5.reuse, 0x4, R18 ; /* 0x0000000405147825 */
/* 0x040fe400078e0212 */
/*0a30*/ LDG.E R18, [R14.64+0x18] ; /* 0x000018040e127981 */
/* 0x0010e8000c1e1900 */
/*0a40*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0002e2000c1e1900 */
/*0a50*/ IMAD.WIDE R22, R5, 0x4, R20 ; /* 0x0000000405167825 */
/* 0x000fca00078e0214 */
/*0a60*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000ee8000c1e1900 */
/*0a70*/ LDG.E R20, [R14.64+0x1c] ; /* 0x00001c040e147981 */
/* 0x0020e2000c1e1900 */
/*0a80*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e70000020f100 */
/*0a90*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x002f240000201400 */
/*0aa0*/ FFMA R10, R13, R10, R16 ; /* 0x0000000a0d0a7223 */
/* 0x010fcc0000000010 */
/*0ab0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*0ac0*/ I2F R13, R10 ; /* 0x0000000a000d7306 */
/* 0x002f640000201400 */
/*0ad0*/ FFMA R11, R26, R11, R13 ; /* 0x0000000b1a0b7223 */
/* 0x020fcc000000000d */
/*0ae0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e70000020f100 */
/*0af0*/ I2F R13, R11 ; /* 0x0000000b000d7306 */
/* 0x002ea40000201400 */
/*0b00*/ FFMA R13, R24, R27, R13 ; /* 0x0000001b180d7223 */
/* 0x004fcc000000000d */
/*0b10*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0b20*/ I2F R14, R13 ; /* 0x0000000d000e7306 */
/* 0x001e240000201400 */
/*0b30*/ FFMA R12, R12, R25, R14 ; /* 0x000000190c0c7223 */
/* 0x001fcc000000000e */
/*0b40*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0b50*/ I2F R14, R12 ; /* 0x0000000c000e7306 */
/* 0x001e240000201400 */
/*0b60*/ FFMA R14, R29, R28, R14 ; /* 0x0000001c1d0e7223 */
/* 0x001fcc000000000e */
/*0b70*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0b80*/ I2F R10, R14 ; /* 0x0000000e000a7306 */
/* 0x001ee20000201400 */
/*0b90*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0ba0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0bb0*/ IMAD.WIDE R28, R5, 0x4, R22 ; /* 0x00000004051c7825 */
/* 0x000fe200078e0216 */
/*0bc0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fc40007ffe0ff */
/*0bd0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bf0*/ FFMA R10, R17, R18, R10 ; /* 0x00000012110a7223 */
/* 0x008fcc000000000a */
/*0c00*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*0c10*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e240000201400 */
/*0c20*/ FFMA R11, R19, R20, R11 ; /* 0x00000014130b7223 */
/* 0x001fcc000000000b */
/*0c30*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0c40*/ I2F R20, R11 ; /* 0x0000000b00147306 */
/* 0x0010640000201400 */
/*0c50*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0c60*/ @!P0 BRA 0xe80 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c70*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x001fe20008000f00 */
/*0c80*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x0000a2000c1e1900 */
/*0c90*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0ca0*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fca00078e020a */
/*0cb0*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea2000c1e1900 */
/*0cc0*/ IMAD.WIDE R16, R5, 0x4, R28 ; /* 0x0000000405107825 */
/* 0x000fc600078e021c */
/*0cd0*/ LDG.E R24, [R10.64+0x4] ; /* 0x000004040a187981 */
/* 0x000ee8000c1e1900 */
/*0ce0*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000ee2000c1e1900 */
/*0cf0*/ IMAD.WIDE R12, R5, 0x4, R16 ; /* 0x00000004050c7825 */
/* 0x000fc600078e0210 */
/*0d00*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f22000c1e1900 */
/*0d20*/ IMAD.WIDE R14, R5, 0x4, R12 ; /* 0x00000004050e7825 */
/* 0x000fc600078e020c */
/*0d30*/ LDG.E R26, [R10.64+0xc] ; /* 0x00000c040a1a7981 */
/* 0x000f68000c1e1900 */
/*0d40*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000f62000c1e1900 */
/*0d50*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0d70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d80*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc60007ffe0ff */
/*0d90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0da0*/ IMAD.WIDE R28, R5, 0x4, R14 ; /* 0x00000004051c7825 */
/* 0x001fc800078e020e */
/*0db0*/ FFMA R21, R21, R22, R20 ; /* 0x0000001615157223 */
/* 0x006fcc0000000014 */
/*0dc0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e30000020f100 */
/*0dd0*/ I2F R20, R21 ; /* 0x0000001500147306 */
/* 0x001ee40000201400 */
/*0de0*/ FFMA R23, R23, R24, R20 ; /* 0x0000001817177223 */
/* 0x008fcc0000000014 */
/*0df0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e30000020f100 */
/*0e00*/ I2F R16, R23 ; /* 0x0000001700107306 */
/* 0x001f240000201400 */
/*0e10*/ FFMA R16, R18, R19, R16 ; /* 0x0000001312107223 */
/* 0x010fcc0000000010 */
/*0e20*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0e30*/ I2F R12, R16 ; /* 0x00000010000c7306 */
/* 0x001f640000201400 */
/*0e40*/ FFMA R12, R25, R26, R12 ; /* 0x0000001a190c7223 */
/* 0x020fcc000000000c */
/*0e50*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0e60*/ I2F R20, R12 ; /* 0x0000000c00147306 */
/* 0x0010640000201400 */
/*0e70*/ @P0 BRA 0xc70 ; /* 0xfffffdf000000947 */
/* 0x003fea000383ffff */
/*0e80*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0e90*/ @!P0 BRA 0xfa0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x001fe200000001ff */
/*0eb0*/ IMAD R8, R0, c[0x0][0x160], R7 ; /* 0x0000580000087a24 */
/* 0x000fe400078e0207 */
/*0ec0*/ IMAD R2, R7, c[0x0][0x160], R2 ; /* 0x0000580007027a24 */
/* 0x000fce00078e0202 */
/*0ed0*/ IMAD.WIDE R8, R8, R11, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fc800078e020b */
/*0ee0*/ IMAD.WIDE R10, R2, R11, c[0x0][0x170] ; /* 0x00005c00020a7625 */
/* 0x000fca00078e020b */
/*0ef0*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0010a8000c1e1900 */
/*0f00*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0006a2000c1e1900 */
/*0f10*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0f20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0f30*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x001fe200078e020a */
/*0f40*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x008fc80007f3e0ff */
/*0f50*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*0f60*/ FFMA R0, R7, R0, R20 ; /* 0x0000000007007223 */
/* 0x006fcc0000000014 */
/*0f70*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e30000020f100 */
/*0f80*/ I2F R20, R0 ; /* 0x0000000000147306 */
/* 0x0010620000201400 */
/*0f90*/ @P0 BRA 0xef0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0fa0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0fb0*/ IMAD R3, R3, c[0x0][0x160], R4 ; /* 0x0000580003037a24 */
/* 0x000fc800078e0204 */
/*0fc0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0002 */
/*0fd0*/ STG.E [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101904 */
/*0fe0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0xff0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef __TILED_KERNEL__
#define __TILED_KERNEL__
#include<cuda_runtime.h>
__global__ void normal(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int sum=0;
if(bx*blockDim.x+tx<row && by*blockDim.y+ty<row){
for(int i=0;i<row;i++){
sum+=input1[ty*row+i]*input2[i*row+tx];
}
output[bx*blockDim.x+tx+(by*blockDim.y+ty)*row]=sum;
}
}
template <int blockSize>
__global__ void tile(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int targetx=bx*blockSize+tx;
int targety=by*blockSize+ty;
__shared__ float smemA[blockSize][blockSize];
__shared__ float smemB[blockSize][blockSize];
int totalPhase=(blockSize+row-1)/blockSize;
int startA=by*blockSize*row;
int startB=bx*blockSize;
int stepA=blockSize;
int stepB=blockSize*row;
float sum=0;
for(int i=0;i<totalPhase;i++){
//start phase,load share memory
if((i*blockSize+tx<row)&&(by*blockSize+ty<row))
smemA[ty][tx]=input1[startA+tx+row*ty];
else
{
smemA[ty][tx]=0;
}
if((bx*blockSize+tx<row)&&(i*blockSize+ty<row))
smemB[ty][tx]=input2[startB+tx+row*ty];
else
{
smemB[ty][tx]=0;
}
startA+=stepA;
startB+=stepB;
__syncthreads();
for(int j=0;j<blockSize;j++){
sum+=smemA[ty][j]*smemB[j][tx];
}
__syncthreads();
}
if(targetx<row&&targety<row){
output[targetx+targety*row]=sum;
}
}
#endif | .file "tmpxft_0017bf88_00000000-6_TiledMatrixMul_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6normaliPfS_S_iPfS_S_
.type _Z30__device_stub__Z6normaliPfS_S_iPfS_S_, @function
_Z30__device_stub__Z6normaliPfS_S_iPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6normaliPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z30__device_stub__Z6normaliPfS_S_iPfS_S_, .-_Z30__device_stub__Z6normaliPfS_S_iPfS_S_
.globl _Z6normaliPfS_S_
.type _Z6normaliPfS_S_, @function
_Z6normaliPfS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6normaliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6normaliPfS_S_, .-_Z6normaliPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6normaliPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6normaliPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef __TILED_KERNEL__
#define __TILED_KERNEL__
#include<cuda_runtime.h>
__global__ void normal(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int sum=0;
if(bx*blockDim.x+tx<row && by*blockDim.y+ty<row){
for(int i=0;i<row;i++){
sum+=input1[ty*row+i]*input2[i*row+tx];
}
output[bx*blockDim.x+tx+(by*blockDim.y+ty)*row]=sum;
}
}
template <int blockSize>
__global__ void tile(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int targetx=bx*blockSize+tx;
int targety=by*blockSize+ty;
__shared__ float smemA[blockSize][blockSize];
__shared__ float smemB[blockSize][blockSize];
int totalPhase=(blockSize+row-1)/blockSize;
int startA=by*blockSize*row;
int startB=bx*blockSize;
int stepA=blockSize;
int stepB=blockSize*row;
float sum=0;
for(int i=0;i<totalPhase;i++){
//start phase,load share memory
if((i*blockSize+tx<row)&&(by*blockSize+ty<row))
smemA[ty][tx]=input1[startA+tx+row*ty];
else
{
smemA[ty][tx]=0;
}
if((bx*blockSize+tx<row)&&(i*blockSize+ty<row))
smemB[ty][tx]=input2[startB+tx+row*ty];
else
{
smemB[ty][tx]=0;
}
startA+=stepA;
startB+=stepB;
__syncthreads();
for(int j=0;j<blockSize;j++){
sum+=smemA[ty][j]*smemB[j][tx];
}
__syncthreads();
}
if(targetx<row&&targety<row){
output[targetx+targety*row]=sum;
}
}
#endif | #ifndef __TILED_KERNEL__
#define __TILED_KERNEL__
#include<hip/hip_runtime.h>
__global__ void normal(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int sum=0;
if(bx*blockDim.x+tx<row && by*blockDim.y+ty<row){
for(int i=0;i<row;i++){
sum+=input1[ty*row+i]*input2[i*row+tx];
}
output[bx*blockDim.x+tx+(by*blockDim.y+ty)*row]=sum;
}
}
template <int blockSize>
__global__ void tile(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int targetx=bx*blockSize+tx;
int targety=by*blockSize+ty;
__shared__ float smemA[blockSize][blockSize];
__shared__ float smemB[blockSize][blockSize];
int totalPhase=(blockSize+row-1)/blockSize;
int startA=by*blockSize*row;
int startB=bx*blockSize;
int stepA=blockSize;
int stepB=blockSize*row;
float sum=0;
for(int i=0;i<totalPhase;i++){
//start phase,load share memory
if((i*blockSize+tx<row)&&(by*blockSize+ty<row))
smemA[ty][tx]=input1[startA+tx+row*ty];
else
{
smemA[ty][tx]=0;
}
if((bx*blockSize+tx<row)&&(i*blockSize+ty<row))
smemB[ty][tx]=input2[startB+tx+row*ty];
else
{
smemB[ty][tx]=0;
}
startA+=stepA;
startB+=stepB;
__syncthreads();
for(int j=0;j<blockSize;j++){
sum+=smemA[ty][j]*smemB[j][tx];
}
__syncthreads();
}
if(targetx<row&&targety<row){
output[targetx+targety*row]=sum;
}
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef __TILED_KERNEL__
#define __TILED_KERNEL__
#include<hip/hip_runtime.h>
__global__ void normal(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int sum=0;
if(bx*blockDim.x+tx<row && by*blockDim.y+ty<row){
for(int i=0;i<row;i++){
sum+=input1[ty*row+i]*input2[i*row+tx];
}
output[bx*blockDim.x+tx+(by*blockDim.y+ty)*row]=sum;
}
}
template <int blockSize>
__global__ void tile(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int targetx=bx*blockSize+tx;
int targety=by*blockSize+ty;
__shared__ float smemA[blockSize][blockSize];
__shared__ float smemB[blockSize][blockSize];
int totalPhase=(blockSize+row-1)/blockSize;
int startA=by*blockSize*row;
int startB=bx*blockSize;
int stepA=blockSize;
int stepB=blockSize*row;
float sum=0;
for(int i=0;i<totalPhase;i++){
//start phase,load share memory
if((i*blockSize+tx<row)&&(by*blockSize+ty<row))
smemA[ty][tx]=input1[startA+tx+row*ty];
else
{
smemA[ty][tx]=0;
}
if((bx*blockSize+tx<row)&&(i*blockSize+ty<row))
smemB[ty][tx]=input2[startB+tx+row*ty];
else
{
smemB[ty][tx]=0;
}
startA+=stepA;
startB+=stepB;
__syncthreads();
for(int j=0;j<blockSize;j++){
sum+=smemA[ty][j]*smemB[j][tx];
}
__syncthreads();
}
if(targetx<row&&targety<row){
output[targetx+targety*row]=sum;
}
}
#endif | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6normaliPfS_S_
.globl _Z6normaliPfS_S_
.p2align 8
.type _Z6normaliPfS_S_,@function
_Z6normaliPfS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_8
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s8, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v4, 0
v_mul_lo_u32 v6, v0, s8
s_mov_b32 s2, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v4
v_mov_b32_e32 v0, v4
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.p2align 6
.LBB0_4:
v_lshlrev_b64 v[8:9], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v0, v0
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_nc_u32_e32 v3, s8, v3
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v2, v8
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
s_cbranch_scc0 .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x18
v_mad_u64_u32 v[2:3], null, v5, s8, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6normaliPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6normaliPfS_S_, .Lfunc_end0-_Z6normaliPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6normaliPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6normaliPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __TILED_KERNEL__
#define __TILED_KERNEL__
#include<hip/hip_runtime.h>
__global__ void normal(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int sum=0;
if(bx*blockDim.x+tx<row && by*blockDim.y+ty<row){
for(int i=0;i<row;i++){
sum+=input1[ty*row+i]*input2[i*row+tx];
}
output[bx*blockDim.x+tx+(by*blockDim.y+ty)*row]=sum;
}
}
template <int blockSize>
__global__ void tile(int row,float* input1,float* input2,float *output){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int targetx=bx*blockSize+tx;
int targety=by*blockSize+ty;
__shared__ float smemA[blockSize][blockSize];
__shared__ float smemB[blockSize][blockSize];
int totalPhase=(blockSize+row-1)/blockSize;
int startA=by*blockSize*row;
int startB=bx*blockSize;
int stepA=blockSize;
int stepB=blockSize*row;
float sum=0;
for(int i=0;i<totalPhase;i++){
//start phase,load share memory
if((i*blockSize+tx<row)&&(by*blockSize+ty<row))
smemA[ty][tx]=input1[startA+tx+row*ty];
else
{
smemA[ty][tx]=0;
}
if((bx*blockSize+tx<row)&&(i*blockSize+ty<row))
smemB[ty][tx]=input2[startB+tx+row*ty];
else
{
smemB[ty][tx]=0;
}
startA+=stepA;
startB+=stepB;
__syncthreads();
for(int j=0;j<blockSize;j++){
sum+=smemA[ty][j]*smemB[j][tx];
}
__syncthreads();
}
if(targetx<row&&targety<row){
output[targetx+targety*row]=sum;
}
}
#endif | .text
.file "TiledMatrixMul_kernel.hip"
.globl _Z21__device_stub__normaliPfS_S_ # -- Begin function _Z21__device_stub__normaliPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__normaliPfS_S_,@function
_Z21__device_stub__normaliPfS_S_: # @_Z21__device_stub__normaliPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6normaliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__normaliPfS_S_, .Lfunc_end0-_Z21__device_stub__normaliPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6normaliPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6normaliPfS_S_,@object # @_Z6normaliPfS_S_
.section .rodata,"a",@progbits
.globl _Z6normaliPfS_S_
.p2align 3, 0x0
_Z6normaliPfS_S_:
.quad _Z21__device_stub__normaliPfS_S_
.size _Z6normaliPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6normaliPfS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__normaliPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6normaliPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6normaliPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R4, R5, c[0x0][0x0], R2 ; /* 0x0000000005047a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R4, c[0x0][0x160], P0 ; /* 0x0000580004007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xfa0 ; /* 0x00000eb000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, R5.reuse, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x040fe40007ffe0ff */
/*0100*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe40000000f00 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0120*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fe400078ec0ff */
/*0130*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xe80 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R8, -R6, c[0x0][0x160], RZ ; /* 0x0000580006087a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R29, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1d7435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R9, R0, c[0x0][0x160], RZ ; /* 0x0000580000097a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R28, R2, R29, c[0x0][0x170] ; /* 0x00005c00021c7625 */
/* 0x000fcc00078e021d */
/*01d0*/ @!P0 BRA 0xc70 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x8b0 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x0010a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R18, R5, 0x4, R28 ; /* 0x0000000405127825 */
/* 0x000fc600078e021c */
/*0280*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0022e2000c1e1900 */
/*02a0*/ IMAD.WIDE R16, R5, 0x4, R18 ; /* 0x0000000405107825 */
/* 0x000fc600078e0212 */
/*02b0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x000b22000c1e1900 */
/*02d0*/ IMAD.WIDE R14, R5, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x000fc600078e0210 */
/*02e0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000ee8000c1e1900 */
/*02f0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x0002e2000c1e1900 */
/*0300*/ IMAD.WIDE R16, R5, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x020fc600078e020e */
/*0310*/ LDG.E R27, [R12.64+0x10] ; /* 0x000010040c1b7981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0010e2000c1e1900 */
/*0330*/ IMAD.WIDE R18, R5, 0x4, R16 ; /* 0x0000000405127825 */
/* 0x002fc600078e0210 */
/*0340*/ LDG.E R29, [R12.64+0x14] ; /* 0x000014040c1d7981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000322000c1e1900 */
/*0360*/ FFMA R20, R23, R22, R20 ; /* 0x0000001617147223 */
/* 0x004fe40000000014 */
/*0370*/ IMAD.WIDE R22, R5, 0x4, R18 ; /* 0x0000000405167825 */
/* 0x000fe400078e0212 */
/*0380*/ F2I.TRUNC.NTZ R18, R20 ; /* 0x0000001400127305 */
/* 0x0022a6000020f100 */
/*0390*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x002f62000c1e1900 */
/*03b0*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x004ee40000201400 */
/*03c0*/ FFMA R19, R10, R11, R18 ; /* 0x0000000b0a137223 */
/* 0x008fc40000000012 */
/*03d0*/ IMAD.WIDE R10, R5, 0x4, R22 ; /* 0x00000004050a7825 */
/* 0x000fc800078e0216 */
/*03e0*/ F2I.TRUNC.NTZ R16, R19 ; /* 0x0000001300107305 */
/* 0x001e22000020f100 */
/*03f0*/ LDG.E R23, [R12.64+0x1c] ; /* 0x00001c040c177981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x0002a6000c1e1900 */
/*0410*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x001f240000201400 */
/*0420*/ FFMA R18, R21, R24, R16 ; /* 0x0000001815127223 */
/* 0x010fc40000000010 */
/*0430*/ IMAD.WIDE R16, R5, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x000fe200078e020a */
/*0440*/ LDG.E R24, [R12.64+0x20] ; /* 0x000020040c187981 */
/* 0x000ee8000c1e1900 */
/*0450*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0000e2000c1e1900 */
/*0460*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000f30000020f100 */
/*0470*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x010f240000201400 */
/*0480*/ FFMA R25, R25, R26, R18 ; /* 0x0000001a19197223 */
/* 0x010fc40000000012 */
/*0490*/ IMAD.WIDE R18, R5, 0x4, R16 ; /* 0x0000000405127825 */
/* 0x000fc800078e0210 */
/*04a0*/ F2I.TRUNC.NTZ R10, R25 ; /* 0x00000019000a7305 */
/* 0x002322000020f100 */
/*04b0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x0000e8000c1e1900 */
/*04c0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002ee6000c1e1900 */
/*04d0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x010e640000201400 */
/*04e0*/ FFMA R27, R28, R27, R10 ; /* 0x0000001b1c1b7223 */
/* 0x002fc4000000000a */
/*04f0*/ IMAD.WIDE R10, R5, 0x4, R18 ; /* 0x00000004050a7825 */
/* 0x000fc800078e0212 */
/*0500*/ F2I.TRUNC.NTZ R16, R27 ; /* 0x0000001b00107305 */
/* 0x001062000020f100 */
/*0510*/ LDG.E R19, [R12.64+0x2c] ; /* 0x00002c040c137981 */
/* 0x000f28000c1e1900 */
/*0520*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000328000c1e1900 */
/*0530*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x001f22000c1e1900 */
/*0540*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x002e240000201400 */
/*0550*/ FFMA R14, R14, R29, R16 ; /* 0x0000001d0e0e7223 */
/* 0x001fc40000000010 */
/*0560*/ IMAD.WIDE R16, R5, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x000fc800078e020a */
/*0570*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e22000020f100 */
/*0580*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x00032e000c1e1900 */
/*0590*/ I2F R29, R14 ; /* 0x0000000e001d7306 */
/* 0x001f640000201400 */
/*05a0*/ FFMA R20, R15, R20, R29 ; /* 0x000000140f147223 */
/* 0x020fc4000000001d */
/*05b0*/ IMAD.WIDE R14, R5, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x000fe200078e0210 */
/*05c0*/ LDG.E R29, [R12.64+0x30] ; /* 0x000030040c1d7981 */
/* 0x000166000c1e1900 */
/*05d0*/ F2I.TRUNC.NTZ R10, R20 ; /* 0x00000014000a7305 */
/* 0x000064000020f100 */
/*05e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x00116c000c1e1900 */
/*05f0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x002ea40000201400 */
/*0600*/ FFMA R22, R22, R23, R10 ; /* 0x0000001716167223 */
/* 0x004fc4000000000a */
/*0610*/ IMAD.WIDE R10, R5, 0x4, R14 ; /* 0x00000004050a7825 */
/* 0x000fe200078e020e */
/*0620*/ LDG.E R23, [R12.64+0x34] ; /* 0x000034040c177981 */
/* 0x0002a6000c1e1900 */
/*0630*/ F2I.TRUNC.NTZ R15, R22 ; /* 0x00000016000f7305 */
/* 0x001064000020f100 */
/*0640*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x0010ac000c1e1900 */
/*0650*/ I2F R16, R15 ; /* 0x0000000f00107306 */
/* 0x002ee40000201400 */
/*0660*/ FFMA R21, R21, R24, R16 ; /* 0x0000001815157223 */
/* 0x008fc40000000010 */
/*0670*/ IMAD.WIDE R16, R5.reuse, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x040fe400078e020a */
/*0680*/ LDG.E R11, [R12.64+0x38] ; /* 0x000038040c0b7981 */
/* 0x0010e8000c1e1900 */
/*0690*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x0002e2000c1e1900 */
/*06a0*/ IMAD.WIDE R14, R5, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x000fca00078e0210 */
/*06b0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ LDG.E R17, [R12.64+0x3c] ; /* 0x00003c040c117981 */
/* 0x0020e2000c1e1900 */
/*06d0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e70000020f100 */
/*06e0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x002e640000201400 */
/*06f0*/ FFMA R25, R26, R25, R21 ; /* 0x000000191a197223 */
/* 0x002fcc0000000015 */
/*0700*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000e70000020f100 */
/*0710*/ I2F R26, R25 ; /* 0x00000019001a7306 */
/* 0x002f240000201400 */
/*0720*/ FFMA R26, R28, R27, R26 ; /* 0x0000001b1c1a7223 */
/* 0x010fcc000000001a */
/*0730*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e70000020f100 */
/*0740*/ I2F R16, R26 ; /* 0x0000001a00107306 */
/* 0x002e640000201400 */
/*0750*/ FFMA R16, R18, R19, R16 ; /* 0x0000001312107223 */
/* 0x002fcc0000000010 */
/*0760*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0770*/ I2F R12, R16 ; /* 0x00000010000c7306 */
/* 0x001f640000201400 */
/*0780*/ FFMA R12, R20, R29, R12 ; /* 0x0000001d140c7223 */
/* 0x020fcc000000000c */
/*0790*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*07a0*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001ea40000201400 */
/*07b0*/ FFMA R13, R22, R23, R13 ; /* 0x00000017160d7223 */
/* 0x004fcc000000000d */
/*07c0*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*07d0*/ I2F R18, R13 ; /* 0x0000000d00127306 */
/* 0x001ee40000201400 */
/*07e0*/ FFMA R11, R24, R11, R18 ; /* 0x0000000b180b7223 */
/* 0x008fcc0000000012 */
/*07f0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0800*/ I2F R18, R11 ; /* 0x0000000b00127306 */
/* 0x001e220000201400 */
/*0810*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0820*/ FFMA R10, R10, R17, R18 ; /* 0x000000110a0a7223 */
/* 0x001fcc0000000012 */
/*0830*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*0840*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0850*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0860*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc60007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0880*/ I2F R20, R10 ; /* 0x0000000a00147306 */
/* 0x0010620000201400 */
/*0890*/ IMAD.WIDE R28, R5, 0x4, R14 ; /* 0x00000004051c7825 */
/* 0x000fca00078e020e */
/*08a0*/ @P1 BRA 0x220 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*08b0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xc50 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*08e0*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x0004e2000c1e1900 */
/*08f0*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0900*/ IMAD.WIDE R14, R9, 0x4, R14 ; /* 0x00000004090e7825 */
/* 0x000fca00078e020e */
/*0910*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IMAD.WIDE R18, R5, 0x4, R28 ; /* 0x0000000405127825 */
/* 0x000fc600078e021c */
/*0930*/ LDG.E R10, [R14.64+0x4] ; /* 0x000004040e0a7981 */
/* 0x001f28000c1e1900 */
/*0940*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x000128000c1e1900 */
/*0950*/ LDG.E R11, [R14.64+0x8] ; /* 0x000008040e0b7981 */
/* 0x000f68000c1e1900 */
/*0960*/ LDG.E R27, [R14.64+0xc] ; /* 0x00000c040e1b7981 */
/* 0x000f22000c1e1900 */
/*0970*/ IMAD.WIDE R18, R5, 0x4, R18 ; /* 0x0000000405127825 */
/* 0x001fc600078e0212 */
/*0980*/ LDG.E R25, [R14.64+0x10] ; /* 0x000010040e197981 */
/* 0x000128000c1e1900 */
/*0990*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000362000c1e1900 */
/*09a0*/ IMAD.WIDE R16, R5, 0x4, R18 ; /* 0x0000000405107825 */
/* 0x000fc600078e0212 */
/*09b0*/ LDG.E R28, [R14.64+0x14] ; /* 0x000014040e1c7981 */
/* 0x0040a8000c1e1900 */
/*09c0*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x0000a4000c1e1900 */
/*09d0*/ IMAD.WIDE R16, R5, 0x4, R16 ; /* 0x0000000405107825 */
/* 0x001fca00078e0210 */
/*09e0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0006a2000c1e1900 */
/*09f0*/ IMAD.WIDE R18, R5, 0x4, R16 ; /* 0x0000000405127825 */
/* 0x002fca00078e0210 */
/*0a00*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x0000a2000c1e1900 */
/*0a10*/ FFMA R16, R21, R22, R20 ; /* 0x0000001615107223 */
/* 0x008fe40000000014 */
/*0a20*/ IMAD.WIDE R20, R5.reuse, 0x4, R18 ; /* 0x0000000405147825 */
/* 0x040fe400078e0212 */
/*0a30*/ LDG.E R18, [R14.64+0x18] ; /* 0x000018040e127981 */
/* 0x0010e8000c1e1900 */
/*0a40*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0002e2000c1e1900 */
/*0a50*/ IMAD.WIDE R22, R5, 0x4, R20 ; /* 0x0000000405167825 */
/* 0x000fca00078e0214 */
/*0a60*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000ee8000c1e1900 */
/*0a70*/ LDG.E R20, [R14.64+0x1c] ; /* 0x00001c040e147981 */
/* 0x0020e2000c1e1900 */
/*0a80*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e70000020f100 */
/*0a90*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x002f240000201400 */
/*0aa0*/ FFMA R10, R13, R10, R16 ; /* 0x0000000a0d0a7223 */
/* 0x010fcc0000000010 */
/*0ab0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*0ac0*/ I2F R13, R10 ; /* 0x0000000a000d7306 */
/* 0x002f640000201400 */
/*0ad0*/ FFMA R11, R26, R11, R13 ; /* 0x0000000b1a0b7223 */
/* 0x020fcc000000000d */
/*0ae0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e70000020f100 */
/*0af0*/ I2F R13, R11 ; /* 0x0000000b000d7306 */
/* 0x002ea40000201400 */
/*0b00*/ FFMA R13, R24, R27, R13 ; /* 0x0000001b180d7223 */
/* 0x004fcc000000000d */
/*0b10*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0b20*/ I2F R14, R13 ; /* 0x0000000d000e7306 */
/* 0x001e240000201400 */
/*0b30*/ FFMA R12, R12, R25, R14 ; /* 0x000000190c0c7223 */
/* 0x001fcc000000000e */
/*0b40*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0b50*/ I2F R14, R12 ; /* 0x0000000c000e7306 */
/* 0x001e240000201400 */
/*0b60*/ FFMA R14, R29, R28, R14 ; /* 0x0000001c1d0e7223 */
/* 0x001fcc000000000e */
/*0b70*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0b80*/ I2F R10, R14 ; /* 0x0000000e000a7306 */
/* 0x001ee20000201400 */
/*0b90*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0ba0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0bb0*/ IMAD.WIDE R28, R5, 0x4, R22 ; /* 0x00000004051c7825 */
/* 0x000fe200078e0216 */
/*0bc0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fc40007ffe0ff */
/*0bd0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bf0*/ FFMA R10, R17, R18, R10 ; /* 0x00000012110a7223 */
/* 0x008fcc000000000a */
/*0c00*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*0c10*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e240000201400 */
/*0c20*/ FFMA R11, R19, R20, R11 ; /* 0x00000014130b7223 */
/* 0x001fcc000000000b */
/*0c30*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0c40*/ I2F R20, R11 ; /* 0x0000000b00147306 */
/* 0x0010640000201400 */
/*0c50*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0c60*/ @!P0 BRA 0xe80 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c70*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x001fe20008000f00 */
/*0c80*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x0000a2000c1e1900 */
/*0c90*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0ca0*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fca00078e020a */
/*0cb0*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea2000c1e1900 */
/*0cc0*/ IMAD.WIDE R16, R5, 0x4, R28 ; /* 0x0000000405107825 */
/* 0x000fc600078e021c */
/*0cd0*/ LDG.E R24, [R10.64+0x4] ; /* 0x000004040a187981 */
/* 0x000ee8000c1e1900 */
/*0ce0*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000ee2000c1e1900 */
/*0cf0*/ IMAD.WIDE R12, R5, 0x4, R16 ; /* 0x00000004050c7825 */
/* 0x000fc600078e0210 */
/*0d00*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f22000c1e1900 */
/*0d20*/ IMAD.WIDE R14, R5, 0x4, R12 ; /* 0x00000004050e7825 */
/* 0x000fc600078e020c */
/*0d30*/ LDG.E R26, [R10.64+0xc] ; /* 0x00000c040a1a7981 */
/* 0x000f68000c1e1900 */
/*0d40*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000f62000c1e1900 */
/*0d50*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0d70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d80*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc60007ffe0ff */
/*0d90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0da0*/ IMAD.WIDE R28, R5, 0x4, R14 ; /* 0x00000004051c7825 */
/* 0x001fc800078e020e */
/*0db0*/ FFMA R21, R21, R22, R20 ; /* 0x0000001615157223 */
/* 0x006fcc0000000014 */
/*0dc0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e30000020f100 */
/*0dd0*/ I2F R20, R21 ; /* 0x0000001500147306 */
/* 0x001ee40000201400 */
/*0de0*/ FFMA R23, R23, R24, R20 ; /* 0x0000001817177223 */
/* 0x008fcc0000000014 */
/*0df0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e30000020f100 */
/*0e00*/ I2F R16, R23 ; /* 0x0000001700107306 */
/* 0x001f240000201400 */
/*0e10*/ FFMA R16, R18, R19, R16 ; /* 0x0000001312107223 */
/* 0x010fcc0000000010 */
/*0e20*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0e30*/ I2F R12, R16 ; /* 0x00000010000c7306 */
/* 0x001f640000201400 */
/*0e40*/ FFMA R12, R25, R26, R12 ; /* 0x0000001a190c7223 */
/* 0x020fcc000000000c */
/*0e50*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0e60*/ I2F R20, R12 ; /* 0x0000000c00147306 */
/* 0x0010640000201400 */
/*0e70*/ @P0 BRA 0xc70 ; /* 0xfffffdf000000947 */
/* 0x003fea000383ffff */
/*0e80*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0e90*/ @!P0 BRA 0xfa0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x001fe200000001ff */
/*0eb0*/ IMAD R8, R0, c[0x0][0x160], R7 ; /* 0x0000580000087a24 */
/* 0x000fe400078e0207 */
/*0ec0*/ IMAD R2, R7, c[0x0][0x160], R2 ; /* 0x0000580007027a24 */
/* 0x000fce00078e0202 */
/*0ed0*/ IMAD.WIDE R8, R8, R11, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fc800078e020b */
/*0ee0*/ IMAD.WIDE R10, R2, R11, c[0x0][0x170] ; /* 0x00005c00020a7625 */
/* 0x000fca00078e020b */
/*0ef0*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0010a8000c1e1900 */
/*0f00*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0006a2000c1e1900 */
/*0f10*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0f20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0f30*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x001fe200078e020a */
/*0f40*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x008fc80007f3e0ff */
/*0f50*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*0f60*/ FFMA R0, R7, R0, R20 ; /* 0x0000000007007223 */
/* 0x006fcc0000000014 */
/*0f70*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e30000020f100 */
/*0f80*/ I2F R20, R0 ; /* 0x0000000000147306 */
/* 0x0010620000201400 */
/*0f90*/ @P0 BRA 0xef0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0fa0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0fb0*/ IMAD R3, R3, c[0x0][0x160], R4 ; /* 0x0000580003037a24 */
/* 0x000fc800078e0204 */
/*0fc0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0002 */
/*0fd0*/ STG.E [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101904 */
/*0fe0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0xff0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6normaliPfS_S_
.globl _Z6normaliPfS_S_
.p2align 8
.type _Z6normaliPfS_S_,@function
_Z6normaliPfS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_8
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s8, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v4, 0
v_mul_lo_u32 v6, v0, s8
s_mov_b32 s2, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v4
v_mov_b32_e32 v0, v4
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.p2align 6
.LBB0_4:
v_lshlrev_b64 v[8:9], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v0, v0
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_nc_u32_e32 v3, s8, v3
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v2, v8
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
s_cbranch_scc0 .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x18
v_mad_u64_u32 v[2:3], null, v5, s8, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6normaliPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6normaliPfS_S_, .Lfunc_end0-_Z6normaliPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6normaliPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6normaliPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017bf88_00000000-6_TiledMatrixMul_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6normaliPfS_S_iPfS_S_
.type _Z30__device_stub__Z6normaliPfS_S_iPfS_S_, @function
_Z30__device_stub__Z6normaliPfS_S_iPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6normaliPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z30__device_stub__Z6normaliPfS_S_iPfS_S_, .-_Z30__device_stub__Z6normaliPfS_S_iPfS_S_
.globl _Z6normaliPfS_S_
.type _Z6normaliPfS_S_, @function
_Z6normaliPfS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6normaliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6normaliPfS_S_, .-_Z6normaliPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6normaliPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6normaliPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "TiledMatrixMul_kernel.hip"
.globl _Z21__device_stub__normaliPfS_S_ # -- Begin function _Z21__device_stub__normaliPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__normaliPfS_S_,@function
_Z21__device_stub__normaliPfS_S_: # @_Z21__device_stub__normaliPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6normaliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__normaliPfS_S_, .Lfunc_end0-_Z21__device_stub__normaliPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6normaliPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6normaliPfS_S_,@object # @_Z6normaliPfS_S_
.section .rodata,"a",@progbits
.globl _Z6normaliPfS_S_
.p2align 3, 0x0
_Z6normaliPfS_S_:
.quad _Z21__device_stub__normaliPfS_S_
.size _Z6normaliPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6normaliPfS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__normaliPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6normaliPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <chrono>
using namespace std::chrono;
// comparison between insert vs copy vs resize
int main(){
// c1. larger vec to smaller vec -> in
int n = 1000000;
int reps = 8;
int init_size = n*reps/2;
thrust::host_vector<float> tmaster(0);
thrust::device_vector<float> temp(n, 1);
auto START = high_resolution_clock::now();
for(int i = 0; i < reps; i++){
tmaster.insert(tmaster.end(), temp.begin(), temp.end());
}
auto End = high_resolution_clock::now();
// for( int i = 0; i < tmaster.size(); i++)
// std::cout << tmaster[i] << " ";
auto red_duration = duration_cast<microseconds>(End - START);
std::cout << "insert time = "<< red_duration.count()/1e6 << std::endl;
std::cout << std::endl;
std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
return 0;
}
// int main(){
// // c1. larger vec to smaller vec -> in
// int n = 1000000;
// int reps = 8;
// int init_size = n*reps/2;
// thrust::host_vector<float> tmaster(2*n*reps);
// thrust::device_vector<float> temp(n, 1);
// auto START = high_resolution_clock::now();
// for(int i = 0; i < reps; i++){
// thrust::copy(temp.begin(), temp.end(), tmaster.begin() + i*n);
// }
// tmaster.resize(n*reps);
// auto End = high_resolution_clock::now();
// // for( int i = 0; i < tmaster.size(); i++)
// // std::cout << tmaster[i] << " ";
// auto red_duration = duration_cast<microseconds>(End - START);
// std::cout << "copy + resize time = "<< red_duration.count()/1e6 << std::endl;
// std::cout << std::endl;
// std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
// return 0;
// } | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <chrono>
using namespace std::chrono;
// comparison between insert vs copy vs resize
int main(){
// c1. larger vec to smaller vec -> in
int n = 1000000;
int reps = 8;
int init_size = n*reps/2;
thrust::host_vector<float> tmaster(0);
thrust::device_vector<float> temp(n, 1);
auto START = high_resolution_clock::now();
for(int i = 0; i < reps; i++){
tmaster.insert(tmaster.end(), temp.begin(), temp.end());
}
auto End = high_resolution_clock::now();
// for( int i = 0; i < tmaster.size(); i++)
// std::cout << tmaster[i] << " ";
auto red_duration = duration_cast<microseconds>(End - START);
std::cout << "insert time = "<< red_duration.count()/1e6 << std::endl;
std::cout << std::endl;
std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
return 0;
}
// int main(){
// // c1. larger vec to smaller vec -> in
// int n = 1000000;
// int reps = 8;
// int init_size = n*reps/2;
// thrust::host_vector<float> tmaster(2*n*reps);
// thrust::device_vector<float> temp(n, 1);
// auto START = high_resolution_clock::now();
// for(int i = 0; i < reps; i++){
// thrust::copy(temp.begin(), temp.end(), tmaster.begin() + i*n);
// }
// tmaster.resize(n*reps);
// auto End = high_resolution_clock::now();
// // for( int i = 0; i < tmaster.size(); i++)
// // std::cout << tmaster[i] << " ";
// auto red_duration = duration_cast<microseconds>(End - START);
// std::cout << "copy + resize time = "<< red_duration.count()/1e6 << std::endl;
// std::cout << std::endl;
// std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
// return 0;
// } | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <chrono>
using namespace std::chrono;
// comparison between insert vs copy vs resize
int main(){
// c1. larger vec to smaller vec -> in
int n = 1000000;
int reps = 8;
int init_size = n*reps/2;
thrust::host_vector<float> tmaster(0);
thrust::device_vector<float> temp(n, 1);
auto START = high_resolution_clock::now();
for(int i = 0; i < reps; i++){
tmaster.insert(tmaster.end(), temp.begin(), temp.end());
}
auto End = high_resolution_clock::now();
// for( int i = 0; i < tmaster.size(); i++)
// std::cout << tmaster[i] << " ";
auto red_duration = duration_cast<microseconds>(End - START);
std::cout << "insert time = "<< red_duration.count()/1e6 << std::endl;
std::cout << std::endl;
std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
return 0;
}
// int main(){
// // c1. larger vec to smaller vec -> in
// int n = 1000000;
// int reps = 8;
// int init_size = n*reps/2;
// thrust::host_vector<float> tmaster(2*n*reps);
// thrust::device_vector<float> temp(n, 1);
// auto START = high_resolution_clock::now();
// for(int i = 0; i < reps; i++){
// thrust::copy(temp.begin(), temp.end(), tmaster.begin() + i*n);
// }
// tmaster.resize(n*reps);
// auto End = high_resolution_clock::now();
// // for( int i = 0; i < tmaster.size(); i++)
// // std::cout << tmaster[i] << " ";
// auto red_duration = duration_cast<microseconds>(End - START);
// std::cout << "copy + resize time = "<< red_duration.count()/1e6 << std::endl;
// std::cout << std::endl;
// std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
// return 0;
// } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <chrono>
using namespace std::chrono;
// comparison between insert vs copy vs resize
int main(){
// c1. larger vec to smaller vec -> in
int n = 1000000;
int reps = 8;
int init_size = n*reps/2;
thrust::host_vector<float> tmaster(0);
thrust::device_vector<float> temp(n, 1);
auto START = high_resolution_clock::now();
for(int i = 0; i < reps; i++){
tmaster.insert(tmaster.end(), temp.begin(), temp.end());
}
auto End = high_resolution_clock::now();
// for( int i = 0; i < tmaster.size(); i++)
// std::cout << tmaster[i] << " ";
auto red_duration = duration_cast<microseconds>(End - START);
std::cout << "insert time = "<< red_duration.count()/1e6 << std::endl;
std::cout << std::endl;
std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
return 0;
}
// int main(){
// // c1. larger vec to smaller vec -> in
// int n = 1000000;
// int reps = 8;
// int init_size = n*reps/2;
// thrust::host_vector<float> tmaster(2*n*reps);
// thrust::device_vector<float> temp(n, 1);
// auto START = high_resolution_clock::now();
// for(int i = 0; i < reps; i++){
// thrust::copy(temp.begin(), temp.end(), tmaster.begin() + i*n);
// }
// tmaster.resize(n*reps);
// auto End = high_resolution_clock::now();
// // for( int i = 0; i < tmaster.size(); i++)
// // std::cout << tmaster[i] << " ";
// auto red_duration = duration_cast<microseconds>(End - START);
// std::cout << "copy + resize time = "<< red_duration.count()/1e6 << std::endl;
// std::cout << std::endl;
// std::cout << "tmaster.size()= " << tmaster.size() << std::endl;
// return 0;
// } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void dotProduct( float* matrixA, float* matrixB, float* matrixC, int n) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
float value = 0;
int k;
for (k = 0; k < n; k++) {
value += matrixA[i * n + k] * matrixB[k * n + j];
}
matrixC[i * n + j] = value;
}
int main() {
int size = 20;
//host
float *matrixA = (float*) malloc(size * size * sizeof(float));
float *matrixB = (float*) malloc(size * size * sizeof(float));
float *matrixC = (float*) malloc(size * size * sizeof(float));
//device
float *matrixA_d;
float *matrixB_d;
float *matrixC_d;
int i = 0;
while (i < size * size) {
matrixA[i] = rand()%100;
matrixB[i] = 1;
i++;
}
cudaMalloc((void**)&matrixA_d, size * size * sizeof(float));
cudaMalloc((void**)&matrixB_d, size * size * sizeof(float));
cudaMalloc((void**)&matrixC_d, size * size * sizeof(float));
dim3 dimBlock(size , size);
dim3 dimGrid(size / dimBlock.x , size / dimBlock.y);
cudaMemcpy(matrixA_d, matrixA, size * size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(matrixB_d, matrixB, size * size * sizeof(float), cudaMemcpyHostToDevice);
dotProduct<<<dimGrid,dimBlock>>>(matrixA_d,matrixB_d,matrixC_d,size);
cudaMemcpy(matrixC, matrixC_d, size * size * sizeof(float), cudaMemcpyDeviceToHost);
for (i = 0; i < size * size; i ++) {
if(i > 0 && i % size == 0)
printf("\n");
printf("%.2f ", matrixC[i]);
}
printf("\n");
} | code for sm_80
Function : _Z10dotProductPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void dotProduct( float* matrixA, float* matrixB, float* matrixC, int n) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
float value = 0;
int k;
for (k = 0; k < n; k++) {
value += matrixA[i * n + k] * matrixB[k * n + j];
}
matrixC[i * n + j] = value;
}
int main() {
int size = 20;
//host
float *matrixA = (float*) malloc(size * size * sizeof(float));
float *matrixB = (float*) malloc(size * size * sizeof(float));
float *matrixC = (float*) malloc(size * size * sizeof(float));
//device
float *matrixA_d;
float *matrixB_d;
float *matrixC_d;
int i = 0;
while (i < size * size) {
matrixA[i] = rand()%100;
matrixB[i] = 1;
i++;
}
cudaMalloc((void**)&matrixA_d, size * size * sizeof(float));
cudaMalloc((void**)&matrixB_d, size * size * sizeof(float));
cudaMalloc((void**)&matrixC_d, size * size * sizeof(float));
dim3 dimBlock(size , size);
dim3 dimGrid(size / dimBlock.x , size / dimBlock.y);
cudaMemcpy(matrixA_d, matrixA, size * size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(matrixB_d, matrixB, size * size * sizeof(float), cudaMemcpyHostToDevice);
dotProduct<<<dimGrid,dimBlock>>>(matrixA_d,matrixB_d,matrixC_d,size);
cudaMemcpy(matrixC, matrixC_d, size * size * sizeof(float), cudaMemcpyDeviceToHost);
for (i = 0; i < size * size; i ++) {
if(i > 0 && i % size == 0)
printf("\n");
printf("%.2f ", matrixC[i]);
}
printf("\n");
} | .file "tmpxft_00097890_00000000-6_matrixDotProduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10dotProductPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.globl _Z10dotProductPfS_S_i
.type _Z10dotProductPfS_S_i, @function
_Z10dotProductPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10dotProductPfS_S_i, .-_Z10dotProductPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n"
.LC2:
.string "%.2f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1600, %edi
call malloc@PLT
movq %rax, %r12
movl $1600, %edi
call malloc@PLT
movq %rax, %rbp
movl $1600, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %ebx
movl .LC0(%rip), %r14d
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx)
movl %r14d, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $1600, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, %ecx
movl $1600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1600, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 32(%rsp)
movl $20, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movl $1600, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
leaq .LC1(%rip), %r12
jmp .L17
.L23:
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
jmp .L13
.L15:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $400, %rbx
je .L24
.L17:
testl %ebx, %ebx
jle .L14
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
sall $2, %eax
cmpl %ebx, %eax
jne .L15
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L24:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
jmp .L17
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10dotProductPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dotProductPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void dotProduct( float* matrixA, float* matrixB, float* matrixC, int n) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
float value = 0;
int k;
for (k = 0; k < n; k++) {
value += matrixA[i * n + k] * matrixB[k * n + j];
}
matrixC[i * n + j] = value;
}
int main() {
int size = 20;
//host
float *matrixA = (float*) malloc(size * size * sizeof(float));
float *matrixB = (float*) malloc(size * size * sizeof(float));
float *matrixC = (float*) malloc(size * size * sizeof(float));
//device
float *matrixA_d;
float *matrixB_d;
float *matrixC_d;
int i = 0;
while (i < size * size) {
matrixA[i] = rand()%100;
matrixB[i] = 1;
i++;
}
cudaMalloc((void**)&matrixA_d, size * size * sizeof(float));
cudaMalloc((void**)&matrixB_d, size * size * sizeof(float));
cudaMalloc((void**)&matrixC_d, size * size * sizeof(float));
dim3 dimBlock(size , size);
dim3 dimGrid(size / dimBlock.x , size / dimBlock.y);
cudaMemcpy(matrixA_d, matrixA, size * size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(matrixB_d, matrixB, size * size * sizeof(float), cudaMemcpyHostToDevice);
dotProduct<<<dimGrid,dimBlock>>>(matrixA_d,matrixB_d,matrixC_d,size);
cudaMemcpy(matrixC, matrixC_d, size * size * sizeof(float), cudaMemcpyDeviceToHost);
for (i = 0; i < size * size; i ++) {
if(i > 0 && i % size == 0)
printf("\n");
printf("%.2f ", matrixC[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void dotProduct( float* matrixA, float* matrixB, float* matrixC, int n) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
float value = 0;
int k;
for (k = 0; k < n; k++) {
value += matrixA[i * n + k] * matrixB[k * n + j];
}
matrixC[i * n + j] = value;
}
int main() {
int size = 20;
//host
float *matrixA = (float*) malloc(size * size * sizeof(float));
float *matrixB = (float*) malloc(size * size * sizeof(float));
float *matrixC = (float*) malloc(size * size * sizeof(float));
//device
float *matrixA_d;
float *matrixB_d;
float *matrixC_d;
int i = 0;
while (i < size * size) {
matrixA[i] = rand()%100;
matrixB[i] = 1;
i++;
}
hipMalloc((void**)&matrixA_d, size * size * sizeof(float));
hipMalloc((void**)&matrixB_d, size * size * sizeof(float));
hipMalloc((void**)&matrixC_d, size * size * sizeof(float));
dim3 dimBlock(size , size);
dim3 dimGrid(size / dimBlock.x , size / dimBlock.y);
hipMemcpy(matrixA_d, matrixA, size * size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(matrixB_d, matrixB, size * size * sizeof(float), hipMemcpyHostToDevice);
dotProduct<<<dimGrid,dimBlock>>>(matrixA_d,matrixB_d,matrixC_d,size);
hipMemcpy(matrixC, matrixC_d, size * size * sizeof(float), hipMemcpyDeviceToHost);
for (i = 0; i < size * size; i ++) {
if(i > 0 && i % size == 0)
printf("\n");
printf("%.2f ", matrixC[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void dotProduct( float* matrixA, float* matrixB, float* matrixC, int n) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
float value = 0;
int k;
for (k = 0; k < n; k++) {
value += matrixA[i * n + k] * matrixB[k * n + j];
}
matrixC[i * n + j] = value;
}
int main() {
int size = 20;
//host
float *matrixA = (float*) malloc(size * size * sizeof(float));
float *matrixB = (float*) malloc(size * size * sizeof(float));
float *matrixC = (float*) malloc(size * size * sizeof(float));
//device
float *matrixA_d;
float *matrixB_d;
float *matrixC_d;
int i = 0;
while (i < size * size) {
matrixA[i] = rand()%100;
matrixB[i] = 1;
i++;
}
hipMalloc((void**)&matrixA_d, size * size * sizeof(float));
hipMalloc((void**)&matrixB_d, size * size * sizeof(float));
hipMalloc((void**)&matrixC_d, size * size * sizeof(float));
dim3 dimBlock(size , size);
dim3 dimGrid(size / dimBlock.x , size / dimBlock.y);
hipMemcpy(matrixA_d, matrixA, size * size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(matrixB_d, matrixB, size * size * sizeof(float), hipMemcpyHostToDevice);
dotProduct<<<dimGrid,dimBlock>>>(matrixA_d,matrixB_d,matrixC_d,size);
hipMemcpy(matrixC, matrixC_d, size * size * sizeof(float), hipMemcpyDeviceToHost);
for (i = 0; i < size * size; i ++) {
if(i > 0 && i % size == 0)
printf("\n");
printf("%.2f ", matrixC[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10dotProductPfS_S_i
.globl _Z10dotProductPfS_S_i
.p2align 8
.type _Z10dotProductPfS_S_i,@function
_Z10dotProductPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dotProductPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10dotProductPfS_S_i, .Lfunc_end0-_Z10dotProductPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dotProductPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10dotProductPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void dotProduct( float* matrixA, float* matrixB, float* matrixC, int n) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
float value = 0;
int k;
for (k = 0; k < n; k++) {
value += matrixA[i * n + k] * matrixB[k * n + j];
}
matrixC[i * n + j] = value;
}
int main() {
int size = 20;
//host
float *matrixA = (float*) malloc(size * size * sizeof(float));
float *matrixB = (float*) malloc(size * size * sizeof(float));
float *matrixC = (float*) malloc(size * size * sizeof(float));
//device
float *matrixA_d;
float *matrixB_d;
float *matrixC_d;
int i = 0;
while (i < size * size) {
matrixA[i] = rand()%100;
matrixB[i] = 1;
i++;
}
hipMalloc((void**)&matrixA_d, size * size * sizeof(float));
hipMalloc((void**)&matrixB_d, size * size * sizeof(float));
hipMalloc((void**)&matrixC_d, size * size * sizeof(float));
dim3 dimBlock(size , size);
dim3 dimGrid(size / dimBlock.x , size / dimBlock.y);
hipMemcpy(matrixA_d, matrixA, size * size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(matrixB_d, matrixB, size * size * sizeof(float), hipMemcpyHostToDevice);
dotProduct<<<dimGrid,dimBlock>>>(matrixA_d,matrixB_d,matrixC_d,size);
hipMemcpy(matrixC, matrixC_d, size * size * sizeof(float), hipMemcpyDeviceToHost);
for (i = 0; i < size * size; i ++) {
if(i > 0 && i % size == 0)
printf("\n");
printf("%.2f ", matrixC[i]);
}
printf("\n");
} | .text
.file "matrixDotProduct.hip"
.globl _Z25__device_stub__dotProductPfS_S_i # -- Begin function _Z25__device_stub__dotProductPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__dotProductPfS_S_i,@function
_Z25__device_stub__dotProductPfS_S_i: # @_Z25__device_stub__dotProductPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__dotProductPfS_S_i, .Lfunc_end0-_Z25__device_stub__dotProductPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r15
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r14
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
movl $1065353216, (%r14,%r12,4) # imm = 0x3F800000
incq %r12
cmpq $400, %r12 # imm = 0x190
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
movq 32(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $85899345940, %rdx # imm = 0x1400000014
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $1600, %edx # imm = 0x640
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq $-1600, %r15 # imm = 0xF9C0
movl $3435973837, %r12d # imm = 0xCCCCCCCD
xorl %r13d, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movss 1600(%rbx,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
decl %r13d
incl %r14d
addq $4, %r15
je .LBB1_9
.LBB1_5: # =>This Inner Loop Header: Depth=1
cmpq $-1600, %r15 # imm = 0xF9C0
je .LBB1_8
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl %r14d, %eax
imulq %r12, %rax
shrq $36, %rax
leal (%rax,%rax,4), %eax
leal (%r13,%rax,4), %eax
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_8
.LBB1_9:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dotProductPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10dotProductPfS_S_i,@object # @_Z10dotProductPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10dotProductPfS_S_i
.p2align 3, 0x0
_Z10dotProductPfS_S_i:
.quad _Z25__device_stub__dotProductPfS_S_i
.size _Z10dotProductPfS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.2f "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10dotProductPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__dotProductPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10dotProductPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10dotProductPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10dotProductPfS_S_i
.globl _Z10dotProductPfS_S_i
.p2align 8
.type _Z10dotProductPfS_S_i,@function
_Z10dotProductPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dotProductPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10dotProductPfS_S_i, .Lfunc_end0-_Z10dotProductPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dotProductPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10dotProductPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00097890_00000000-6_matrixDotProduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10dotProductPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.globl _Z10dotProductPfS_S_i
.type _Z10dotProductPfS_S_i, @function
_Z10dotProductPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10dotProductPfS_S_i, .-_Z10dotProductPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n"
.LC2:
.string "%.2f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1600, %edi
call malloc@PLT
movq %rax, %r12
movl $1600, %edi
call malloc@PLT
movq %rax, %rbp
movl $1600, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %ebx
movl .LC0(%rip), %r14d
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx)
movl %r14d, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $1600, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, %ecx
movl $1600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1600, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 32(%rsp)
movl $20, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movl $1600, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
leaq .LC1(%rip), %r12
jmp .L17
.L23:
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
jmp .L13
.L15:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $400, %rbx
je .L24
.L17:
testl %ebx, %ebx
jle .L14
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
sall $2, %eax
cmpl %ebx, %eax
jne .L15
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L24:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
jmp .L17
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10dotProductPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dotProductPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixDotProduct.hip"
.globl _Z25__device_stub__dotProductPfS_S_i # -- Begin function _Z25__device_stub__dotProductPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__dotProductPfS_S_i,@function
_Z25__device_stub__dotProductPfS_S_i: # @_Z25__device_stub__dotProductPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__dotProductPfS_S_i, .Lfunc_end0-_Z25__device_stub__dotProductPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r15
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r14
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
movl $1065353216, (%r14,%r12,4) # imm = 0x3F800000
incq %r12
cmpq $400, %r12 # imm = 0x190
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
movq 32(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $85899345940, %rdx # imm = 0x1400000014
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $1600, %edx # imm = 0x640
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq $-1600, %r15 # imm = 0xF9C0
movl $3435973837, %r12d # imm = 0xCCCCCCCD
xorl %r13d, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movss 1600(%rbx,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
decl %r13d
incl %r14d
addq $4, %r15
je .LBB1_9
.LBB1_5: # =>This Inner Loop Header: Depth=1
cmpq $-1600, %r15 # imm = 0xF9C0
je .LBB1_8
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl %r14d, %eax
imulq %r12, %rax
shrq $36, %rax
leal (%rax,%rax,4), %eax
leal (%r13,%rax,4), %eax
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_8
.LBB1_9:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dotProductPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10dotProductPfS_S_i,@object # @_Z10dotProductPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10dotProductPfS_S_i
.p2align 3, 0x0
_Z10dotProductPfS_S_i:
.quad _Z25__device_stub__dotProductPfS_S_i
.size _Z10dotProductPfS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.2f "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10dotProductPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__dotProductPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10dotProductPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void FindMinSample(float* DistanceBuffer, short2* IndexBuffer, int spread, int mapSizeX, int mapSizeY)
{
int kOffset = CUDASTDOFFSET;
float distance1 = DistanceBuffer[kOffset];
float distance2 = DistanceBuffer[kOffset + spread];
short2 index1 = IndexBuffer[kOffset];
short2 index2 = IndexBuffer[kOffset + spread];
if (kOffset + spread < mapSizeX * mapSizeY)
{
DistanceBuffer[kOffset] = (distance1 < distance2) ? distance1 : distance2;
IndexBuffer[kOffset] = (distance1 < distance2) ? index1 : index2;
}
} | code for sm_80
Function : _Z13FindMinSamplePfP6short2iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0070*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*00b0*/ IADD3 R2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000027a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*0120*/ LEA.HI.X R5, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1403 */
/*0130*/ IMAD.WIDE R6, R9.reuse, c[0x0][0x170], R4 ; /* 0x00005c0009067a25 */
/* 0x040fe200078e0204 */
/*0140*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea6000c1e1900 */
/*0150*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe400078e0209 */
/*0160*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ IMAD.WIDE R8, R9, c[0x0][0x170], R2 ; /* 0x00005c0009087a25 */
/* 0x000fe200078e0202 */
/*0180*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x00016a000c1e1900 */
/*0190*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee2000c1e1900 */
/*01a0*/ FSETP.GEU.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x004fc80003f0e000 */
/*01b0*/ FSEL R13, R10, R7, !P0 ; /* 0x000000070a0d7208 */
/* 0x000fca0004000000 */
/*01c0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e8000c101904 */
/*01d0*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0081e2000c101904 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x020fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void FindMinSample(float* DistanceBuffer, short2* IndexBuffer, int spread, int mapSizeX, int mapSizeY)
{
int kOffset = CUDASTDOFFSET;
float distance1 = DistanceBuffer[kOffset];
float distance2 = DistanceBuffer[kOffset + spread];
short2 index1 = IndexBuffer[kOffset];
short2 index2 = IndexBuffer[kOffset + spread];
if (kOffset + spread < mapSizeX * mapSizeY)
{
DistanceBuffer[kOffset] = (distance1 < distance2) ? distance1 : distance2;
IndexBuffer[kOffset] = (distance1 < distance2) ? index1 : index2;
}
} | .file "tmpxft_0005b0b4_00000000-6_FindMinSample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii
.type _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii, @function
_Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13FindMinSamplePfP6short2iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii, .-_Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii
.globl _Z13FindMinSamplePfP6short2iii
.type _Z13FindMinSamplePfP6short2iii, @function
_Z13FindMinSamplePfP6short2iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13FindMinSamplePfP6short2iii, .-_Z13FindMinSamplePfP6short2iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13FindMinSamplePfP6short2iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13FindMinSamplePfP6short2iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void FindMinSample(float* DistanceBuffer, short2* IndexBuffer, int spread, int mapSizeX, int mapSizeY)
{
int kOffset = CUDASTDOFFSET;
float distance1 = DistanceBuffer[kOffset];
float distance2 = DistanceBuffer[kOffset + spread];
short2 index1 = IndexBuffer[kOffset];
short2 index2 = IndexBuffer[kOffset + spread];
if (kOffset + spread < mapSizeX * mapSizeY)
{
DistanceBuffer[kOffset] = (distance1 < distance2) ? distance1 : distance2;
IndexBuffer[kOffset] = (distance1 < distance2) ? index1 : index2;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FindMinSample(float* DistanceBuffer, short2* IndexBuffer, int spread, int mapSizeX, int mapSizeY)
{
int kOffset = CUDASTDOFFSET;
float distance1 = DistanceBuffer[kOffset];
float distance2 = DistanceBuffer[kOffset + spread];
short2 index1 = IndexBuffer[kOffset];
short2 index2 = IndexBuffer[kOffset + spread];
if (kOffset + spread < mapSizeX * mapSizeY)
{
DistanceBuffer[kOffset] = (distance1 < distance2) ? distance1 : distance2;
IndexBuffer[kOffset] = (distance1 < distance2) ? index1 : index2;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FindMinSample(float* DistanceBuffer, short2* IndexBuffer, int spread, int mapSizeX, int mapSizeY)
{
int kOffset = CUDASTDOFFSET;
float distance1 = DistanceBuffer[kOffset];
float distance2 = DistanceBuffer[kOffset + spread];
short2 index1 = IndexBuffer[kOffset];
short2 index2 = IndexBuffer[kOffset + spread];
if (kOffset + spread < mapSizeX * mapSizeY)
{
DistanceBuffer[kOffset] = (distance1 < distance2) ? distance1 : distance2;
IndexBuffer[kOffset] = (distance1 < distance2) ? index1 : index2;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.globl _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.p2align 8
.type _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii,@function
_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii:
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s7, s7, s5
s_mul_i32 s2, s3, s2
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s13
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s4, v1
v_cmpx_gt_i32_e64 s7, v3
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[7:8], off
s_clause 0x1
global_load_b32 v4, v[5:6], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(2)
v_cmp_lt_f32_e32 vcc_lo, v3, v2
s_waitcnt vmcnt(0)
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v3, v4, v5
global_store_b32 v[7:8], v2, off
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, .Lfunc_end0-_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FindMinSample(float* DistanceBuffer, short2* IndexBuffer, int spread, int mapSizeX, int mapSizeY)
{
int kOffset = CUDASTDOFFSET;
float distance1 = DistanceBuffer[kOffset];
float distance2 = DistanceBuffer[kOffset + spread];
short2 index1 = IndexBuffer[kOffset];
short2 index2 = IndexBuffer[kOffset + spread];
if (kOffset + spread < mapSizeX * mapSizeY)
{
DistanceBuffer[kOffset] = (distance1 < distance2) ? distance1 : distance2;
IndexBuffer[kOffset] = (distance1 < distance2) ? index1 : index2;
}
} | .text
.file "FindMinSample.hip"
.globl _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii # -- Begin function _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.p2align 4, 0x90
.type _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii,@function
_Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii: # @_Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, .Lfunc_end0-_Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii,@object # @_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.section .rodata,"a",@progbits
.globl _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.p2align 3, 0x0
_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii:
.quad _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.size _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13FindMinSamplePfP6short2iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0070*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*00b0*/ IADD3 R2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000027a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*0120*/ LEA.HI.X R5, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1403 */
/*0130*/ IMAD.WIDE R6, R9.reuse, c[0x0][0x170], R4 ; /* 0x00005c0009067a25 */
/* 0x040fe200078e0204 */
/*0140*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea6000c1e1900 */
/*0150*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe400078e0209 */
/*0160*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ IMAD.WIDE R8, R9, c[0x0][0x170], R2 ; /* 0x00005c0009087a25 */
/* 0x000fe200078e0202 */
/*0180*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x00016a000c1e1900 */
/*0190*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee2000c1e1900 */
/*01a0*/ FSETP.GEU.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x004fc80003f0e000 */
/*01b0*/ FSEL R13, R10, R7, !P0 ; /* 0x000000070a0d7208 */
/* 0x000fca0004000000 */
/*01c0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e8000c101904 */
/*01d0*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0081e2000c101904 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x020fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.globl _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.p2align 8
.type _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii,@function
_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii:
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s7, s7, s5
s_mul_i32 s2, s3, s2
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s13
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s4, v1
v_cmpx_gt_i32_e64 s7, v3
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[7:8], off
s_clause 0x1
global_load_b32 v4, v[5:6], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(2)
v_cmp_lt_f32_e32 vcc_lo, v3, v2
s_waitcnt vmcnt(0)
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v3, v4, v5
global_store_b32 v[7:8], v2, off
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, .Lfunc_end0-_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005b0b4_00000000-6_FindMinSample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii
.type _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii, @function
_Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13FindMinSamplePfP6short2iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii, .-_Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii
.globl _Z13FindMinSamplePfP6short2iii
.type _Z13FindMinSamplePfP6short2iii, @function
_Z13FindMinSamplePfP6short2iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z13FindMinSamplePfP6short2iiiPfP6short2iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13FindMinSamplePfP6short2iii, .-_Z13FindMinSamplePfP6short2iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13FindMinSamplePfP6short2iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13FindMinSamplePfP6short2iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FindMinSample.hip"
.globl _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii # -- Begin function _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.p2align 4, 0x90
.type _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii,@function
_Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii: # @_Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, .Lfunc_end0-_Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii,@object # @_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.section .rodata,"a",@progbits
.globl _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.p2align 3, 0x0
_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii:
.quad _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.size _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13FindMinSamplePfP15HIP_vector_typeIsLj2EEiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdlib.h>
using namespace std;
__global__ void add(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
}
int main(int argc, char *argv[]){
cout<<"****** Array Addition ******\n"<<endl;
int *a, *b, *c;
int size = 10;
a = (int*) malloc(size*sizeof(int));
b = (int*) malloc(size*sizeof(int));
c = (int*) malloc(size*sizeof(int));
int *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<1,10>>>(d_a, d_b, d_c, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(a);
free(b);
free(c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdlib.h>
using namespace std;
__global__ void add(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
}
int main(int argc, char *argv[]){
cout<<"****** Array Addition ******\n"<<endl;
int *a, *b, *c;
int size = 10;
a = (int*) malloc(size*sizeof(int));
b = (int*) malloc(size*sizeof(int));
c = (int*) malloc(size*sizeof(int));
int *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<1,10>>>(d_a, d_b, d_c, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(a);
free(b);
free(c);
return 0;
} | .file "tmpxft_001150b6_00000000-6_h.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "****** Array Addition ******\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $10, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $10, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdlib.h>
using namespace std;
__global__ void add(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
}
int main(int argc, char *argv[]){
cout<<"****** Array Addition ******\n"<<endl;
int *a, *b, *c;
int size = 10;
a = (int*) malloc(size*sizeof(int));
b = (int*) malloc(size*sizeof(int));
c = (int*) malloc(size*sizeof(int));
int *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<1,10>>>(d_a, d_b, d_c, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(a);
free(b);
free(c);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
using namespace std;
__global__ void add(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
}
int main(int argc, char *argv[]){
cout<<"****** Array Addition ******\n"<<endl;
int *a, *b, *c;
int size = 10;
a = (int*) malloc(size*sizeof(int));
b = (int*) malloc(size*sizeof(int));
c = (int*) malloc(size*sizeof(int));
int *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<1,10>>>(d_a, d_b, d_c, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(a);
free(b);
free(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
using namespace std;
__global__ void add(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
}
int main(int argc, char *argv[]){
cout<<"****** Array Addition ******\n"<<endl;
int *a, *b, *c;
int size = 10;
a = (int*) malloc(size*sizeof(int));
b = (int*) malloc(size*sizeof(int));
c = (int*) malloc(size*sizeof(int));
int *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<1,10>>>(d_a, d_b, d_c, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(a);
free(b);
free(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
using namespace std;
__global__ void add(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
}
int main(int argc, char *argv[]){
cout<<"****** Array Addition ******\n"<<endl;
int *a, *b, *c;
int size = 10;
a = (int*) malloc(size*sizeof(int));
b = (int*) malloc(size*sizeof(int));
c = (int*) malloc(size*sizeof(int));
int *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<1,10>>>(d_a, d_b, d_c, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(a);
free(b);
free(c);
return 0;
} | .text
.file "h.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $10, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $10, %esi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $10, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $10, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $10, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "****** Array Addition ******\n"
.size .L.str, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001150b6_00000000-6_h.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "****** Array Addition ******\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $10, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $10, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "h.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $10, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $10, %esi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $10, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $10, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $10, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "****** Array Addition ******\n"
.size .L.str, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <chrono>
#include <cmath>
__global__ void vectors_add(float arr1[], float arr2[]) {
arr1[threadIdx.x + blockDim.x * blockIdx.x] += arr2[threadIdx.x + blockDim.x * blockIdx.x];
}
int main(int argc, char *argv[]) {
float *arr1, *arr2, *res, *devarr1, *devarr2;
for (int N = pow(2, 28), i = 0; i < 19; N /= 2, i++) {
int threads_per_block = std::stoi(argv[1]);
int num_of_blocks = N / threads_per_block;
arr1 = new float[N];
arr2 = new float[N];
res = new float[N];
for (int i = 0; i < N; i++) {
arr1[i] = (float) rand() / RAND_MAX;
arr2[i] = (float) rand() / RAND_MAX;
}
cudaError_t errcode = cudaMalloc((void **) &devarr1, N * sizeof(float));
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMalloc((void **) &devarr2, N * sizeof(float));
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMemcpy(devarr1, arr1, N * sizeof(float), cudaMemcpyHostToDevice);
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMemcpy(devarr2, arr2, N * sizeof(float), cudaMemcpyHostToDevice);
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
auto start = std::chrono::high_resolution_clock::now();
vectors_add<<<dim3(num_of_blocks), dim3(threads_per_block)>>>(devarr1, devarr2);
cudaDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << std::endl;
cudaMemcpy(res, devarr1, N * sizeof(float), cudaMemcpyDeviceToHost);
//for(int i = 0; i < 100; i++)
// std::cout << res[i] << '\n';
for (int i = 0; i < N; i++) {
if (res[i] != arr1[i] + arr2[i]) {
std::cout << "Error" << std::endl;
return 0;
}
}
cudaFree(devarr1);
cudaFree(devarr2);
delete[] arr1;
delete[] arr2;
delete[] res;
}
} | code for sm_80
Function : _Z11vectors_addPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0005 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <chrono>
#include <cmath>
__global__ void vectors_add(float arr1[], float arr2[]) {
arr1[threadIdx.x + blockDim.x * blockIdx.x] += arr2[threadIdx.x + blockDim.x * blockIdx.x];
}
int main(int argc, char *argv[]) {
float *arr1, *arr2, *res, *devarr1, *devarr2;
for (int N = pow(2, 28), i = 0; i < 19; N /= 2, i++) {
int threads_per_block = std::stoi(argv[1]);
int num_of_blocks = N / threads_per_block;
arr1 = new float[N];
arr2 = new float[N];
res = new float[N];
for (int i = 0; i < N; i++) {
arr1[i] = (float) rand() / RAND_MAX;
arr2[i] = (float) rand() / RAND_MAX;
}
cudaError_t errcode = cudaMalloc((void **) &devarr1, N * sizeof(float));
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMalloc((void **) &devarr2, N * sizeof(float));
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMemcpy(devarr1, arr1, N * sizeof(float), cudaMemcpyHostToDevice);
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMemcpy(devarr2, arr2, N * sizeof(float), cudaMemcpyHostToDevice);
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
auto start = std::chrono::high_resolution_clock::now();
vectors_add<<<dim3(num_of_blocks), dim3(threads_per_block)>>>(devarr1, devarr2);
cudaDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << std::endl;
cudaMemcpy(res, devarr1, N * sizeof(float), cudaMemcpyDeviceToHost);
//for(int i = 0; i < 100; i++)
// std::cout << res[i] << '\n';
for (int i = 0; i < N; i++) {
if (res[i] != arr1[i] + arr2[i]) {
std::cout << "Error" << std::endl;
return 0;
}
}
cudaFree(devarr1);
cudaFree(devarr2);
delete[] arr1;
delete[] arr2;
delete[] res;
}
} | .file "tmpxft_001924af_00000000-6_lab01.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11vectors_addPfS_PfS_
.type _Z33__device_stub__Z11vectors_addPfS_PfS_, @function
_Z33__device_stub__Z11vectors_addPfS_PfS_:
.LFB3797:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11vectors_addPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z33__device_stub__Z11vectors_addPfS_PfS_, .-_Z33__device_stub__Z11vectors_addPfS_PfS_
.globl _Z11vectors_addPfS_
.type _Z11vectors_addPfS_, @function
_Z11vectors_addPfS_:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11vectors_addPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z11vectors_addPfS_, .-_Z11vectors_addPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "stoi"
.LC3:
.string "Error"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3768
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, 32(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $19, 44(%rsp)
movl $268435456, 12(%rsp)
.L45:
movq 32(%rsp), %rax
movq 8(%rax), %rbp
leaq 112(%rsp), %rax
movq %rax, 96(%rsp)
testq %rbp, %rbp
je .L55
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 80(%rsp)
cmpq $15, %rax
ja .L56
cmpq $1, %rax
jne .L16
movzbl 0(%rbp), %eax
movb %al, 112(%rsp)
.L17:
movq 80(%rsp), %rax
movq %rax, 104(%rsp)
movq 96(%rsp), %rdx
movb $0, (%rdx,%rax)
movq 96(%rsp), %rbp
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r12d
movl $0, (%rax)
leaq 80(%rsp), %rsi
movl $10, %edx
movq %rbp, %rdi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
cmpq 80(%rsp), %rbp
je .L57
movl (%rbx), %eax
cmpl $34, %eax
je .L20
movq 16(%rsp), %rcx
movl $2147483648, %edx
addq %rcx, %rdx
movl $4294967295, %ecx
cmpq %rdx, %rcx
jb .L20
movl 16(%rsp), %ebp
testl %eax, %eax
jne .L23
movl %r12d, (%rbx)
.L23:
movq 96(%rsp), %rdi
leaq 112(%rsp), %rax
cmpq %rax, %rdi
je .L24
movq 112(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L24:
movl 12(%rsp), %eax
cltd
idivl %ebp
movl %eax, 40(%rsp)
movl 12(%rsp), %ebx
movslq %ebx, %r13
salq $2, %r13
movq %r13, %rdi
.LEHB0:
call _Znam@PLT
movq %rax, %r14
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r15
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L29
movq %r14, %rbx
movq %r15, %rbp
leaq 0(%r13,%r14), %rax
movq %r13, 24(%rsp)
movq %rax, %r13
.L30:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r13, %rbx
jne .L30
movq 24(%rsp), %r13
.L29:
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L59
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L60
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl 16(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl 40(%rsp), %eax
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L36:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rax
imulq %rcx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L63
cmpb $0, 56(%rbp)
je .L39
movzbl 67(%rbp), %esi
.L40:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $0, 12(%rsp)
jle .L41
movl $0, %eax
.L44:
movss (%r14,%rax), %xmm0
addss (%r15,%rax), %xmm0
ucomiss (%r12,%rax), %xmm0
jp .L49
jne .L49
addq $4, %rax
cmpq %rax, %r13
jne .L44
.L41:
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movl 12(%rsp), %ecx
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
movl %eax, 12(%rsp)
subl $1, 44(%rsp)
jne .L45
jmp .L46
.L55:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
leaq .LC0(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L64:
call __stack_chk_fail@PLT
.L56:
leaq 80(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE0:
movq %rax, %rdi
movq %rax, 96(%rsp)
movq 80(%rsp), %rax
movq %rax, 112(%rsp)
.L15:
movq %rbx, %rdx
movq %rbp, %rsi
call memcpy@PLT
jmp .L17
.L16:
testq %rax, %rax
je .L17
leaq 112(%rsp), %rdi
jmp .L15
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L65
leaq .LC1(%rip), %rdi
.LEHB1:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L65:
call __stack_chk_fail@PLT
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
leaq .LC1(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE1:
.L48:
endbr64
movq %rax, %rbp
cmpl $0, (%rbx)
jne .L27
movl %r12d, (%rbx)
.L27:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L66:
call __stack_chk_fail@PLT
.L28:
movq %rbp, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.L58:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L59:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L60:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L61:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L62:
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z33__device_stub__Z11vectors_addPfS_PfS_
jmp .L36
.L63:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L67
call _ZSt16__throw_bad_castv@PLT
.L67:
call __stack_chk_fail@PLT
.L39:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L49:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
.L46:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3768:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3768-.LLSDACSB3768
.LLSDACSB3768:
.uleb128 .LEHB0-.LFB3768
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3768
.uleb128 .LEHE1-.LEHB1
.uleb128 .L48-.LFB3768
.uleb128 0
.uleb128 .LEHB2-.LFB3768
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3768:
.text
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11vectors_addPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vectors_addPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <chrono>
#include <cmath>
__global__ void vectors_add(float arr1[], float arr2[]) {
arr1[threadIdx.x + blockDim.x * blockIdx.x] += arr2[threadIdx.x + blockDim.x * blockIdx.x];
}
int main(int argc, char *argv[]) {
float *arr1, *arr2, *res, *devarr1, *devarr2;
for (int N = pow(2, 28), i = 0; i < 19; N /= 2, i++) {
int threads_per_block = std::stoi(argv[1]);
int num_of_blocks = N / threads_per_block;
arr1 = new float[N];
arr2 = new float[N];
res = new float[N];
for (int i = 0; i < N; i++) {
arr1[i] = (float) rand() / RAND_MAX;
arr2[i] = (float) rand() / RAND_MAX;
}
cudaError_t errcode = cudaMalloc((void **) &devarr1, N * sizeof(float));
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMalloc((void **) &devarr2, N * sizeof(float));
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMemcpy(devarr1, arr1, N * sizeof(float), cudaMemcpyHostToDevice);
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = cudaMemcpy(devarr2, arr2, N * sizeof(float), cudaMemcpyHostToDevice);
if (errcode != cudaSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
auto start = std::chrono::high_resolution_clock::now();
vectors_add<<<dim3(num_of_blocks), dim3(threads_per_block)>>>(devarr1, devarr2);
cudaDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << std::endl;
cudaMemcpy(res, devarr1, N * sizeof(float), cudaMemcpyDeviceToHost);
//for(int i = 0; i < 100; i++)
// std::cout << res[i] << '\n';
for (int i = 0; i < N; i++) {
if (res[i] != arr1[i] + arr2[i]) {
std::cout << "Error" << std::endl;
return 0;
}
}
cudaFree(devarr1);
cudaFree(devarr2);
delete[] arr1;
delete[] arr2;
delete[] res;
}
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
#include <cmath>
__global__ void vectors_add(float arr1[], float arr2[]) {
arr1[threadIdx.x + blockDim.x * blockIdx.x] += arr2[threadIdx.x + blockDim.x * blockIdx.x];
}
int main(int argc, char *argv[]) {
float *arr1, *arr2, *res, *devarr1, *devarr2;
for (int N = pow(2, 28), i = 0; i < 19; N /= 2, i++) {
int threads_per_block = std::stoi(argv[1]);
int num_of_blocks = N / threads_per_block;
arr1 = new float[N];
arr2 = new float[N];
res = new float[N];
for (int i = 0; i < N; i++) {
arr1[i] = (float) rand() / RAND_MAX;
arr2[i] = (float) rand() / RAND_MAX;
}
hipError_t errcode = hipMalloc((void **) &devarr1, N * sizeof(float));
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMalloc((void **) &devarr2, N * sizeof(float));
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMemcpy(devarr1, arr1, N * sizeof(float), hipMemcpyHostToDevice);
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMemcpy(devarr2, arr2, N * sizeof(float), hipMemcpyHostToDevice);
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
auto start = std::chrono::high_resolution_clock::now();
vectors_add<<<dim3(num_of_blocks), dim3(threads_per_block)>>>(devarr1, devarr2);
hipDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << std::endl;
hipMemcpy(res, devarr1, N * sizeof(float), hipMemcpyDeviceToHost);
//for(int i = 0; i < 100; i++)
// std::cout << res[i] << '\n';
for (int i = 0; i < N; i++) {
if (res[i] != arr1[i] + arr2[i]) {
std::cout << "Error" << std::endl;
return 0;
}
}
hipFree(devarr1);
hipFree(devarr2);
delete[] arr1;
delete[] arr2;
delete[] res;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
#include <cmath>
__global__ void vectors_add(float arr1[], float arr2[]) {
arr1[threadIdx.x + blockDim.x * blockIdx.x] += arr2[threadIdx.x + blockDim.x * blockIdx.x];
}
int main(int argc, char *argv[]) {
float *arr1, *arr2, *res, *devarr1, *devarr2;
for (int N = pow(2, 28), i = 0; i < 19; N /= 2, i++) {
int threads_per_block = std::stoi(argv[1]);
int num_of_blocks = N / threads_per_block;
arr1 = new float[N];
arr2 = new float[N];
res = new float[N];
for (int i = 0; i < N; i++) {
arr1[i] = (float) rand() / RAND_MAX;
arr2[i] = (float) rand() / RAND_MAX;
}
hipError_t errcode = hipMalloc((void **) &devarr1, N * sizeof(float));
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMalloc((void **) &devarr2, N * sizeof(float));
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMemcpy(devarr1, arr1, N * sizeof(float), hipMemcpyHostToDevice);
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMemcpy(devarr2, arr2, N * sizeof(float), hipMemcpyHostToDevice);
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
auto start = std::chrono::high_resolution_clock::now();
vectors_add<<<dim3(num_of_blocks), dim3(threads_per_block)>>>(devarr1, devarr2);
hipDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << std::endl;
hipMemcpy(res, devarr1, N * sizeof(float), hipMemcpyDeviceToHost);
//for(int i = 0; i < 100; i++)
// std::cout << res[i] << '\n';
for (int i = 0; i < N; i++) {
if (res[i] != arr1[i] + arr2[i]) {
std::cout << "Error" << std::endl;
return 0;
}
}
hipFree(devarr1);
hipFree(devarr2);
delete[] arr1;
delete[] arr2;
delete[] res;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11vectors_addPfS_
.globl _Z11vectors_addPfS_
.p2align 8
.type _Z11vectors_addPfS_,@function
_Z11vectors_addPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11vectors_addPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11vectors_addPfS_, .Lfunc_end0-_Z11vectors_addPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11vectors_addPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11vectors_addPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
#include <cmath>
__global__ void vectors_add(float arr1[], float arr2[]) {
arr1[threadIdx.x + blockDim.x * blockIdx.x] += arr2[threadIdx.x + blockDim.x * blockIdx.x];
}
int main(int argc, char *argv[]) {
float *arr1, *arr2, *res, *devarr1, *devarr2;
for (int N = pow(2, 28), i = 0; i < 19; N /= 2, i++) {
int threads_per_block = std::stoi(argv[1]);
int num_of_blocks = N / threads_per_block;
arr1 = new float[N];
arr2 = new float[N];
res = new float[N];
for (int i = 0; i < N; i++) {
arr1[i] = (float) rand() / RAND_MAX;
arr2[i] = (float) rand() / RAND_MAX;
}
hipError_t errcode = hipMalloc((void **) &devarr1, N * sizeof(float));
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMalloc((void **) &devarr2, N * sizeof(float));
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMemcpy(devarr1, arr1, N * sizeof(float), hipMemcpyHostToDevice);
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
errcode = hipMemcpy(devarr2, arr2, N * sizeof(float), hipMemcpyHostToDevice);
if (errcode != hipSuccess) {
std::cout << "Error" << std::endl;
return 0;
}
auto start = std::chrono::high_resolution_clock::now();
vectors_add<<<dim3(num_of_blocks), dim3(threads_per_block)>>>(devarr1, devarr2);
hipDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << std::endl;
hipMemcpy(res, devarr1, N * sizeof(float), hipMemcpyDeviceToHost);
//for(int i = 0; i < 100; i++)
// std::cout << res[i] << '\n';
for (int i = 0; i < N; i++) {
if (res[i] != arr1[i] + arr2[i]) {
std::cout << "Error" << std::endl;
return 0;
}
}
hipFree(devarr1);
hipFree(devarr2);
delete[] arr1;
delete[] arr2;
delete[] res;
}
} | .text
.file "lab01.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__vectors_addPfS_ # -- Begin function _Z26__device_stub__vectors_addPfS_
.p2align 4, 0x90
.type _Z26__device_stub__vectors_addPfS_,@function
_Z26__device_stub__vectors_addPfS_: # @_Z26__device_stub__vectors_addPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11vectors_addPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__vectors_addPfS_, .Lfunc_end0-_Z26__device_stub__vectors_addPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 96(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movl $268435456, 4(%rsp) # 4-byte Folded Spill
# imm = 0x10000000
jmp .LBB1_1
.LBB1_63: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_64: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
testb %bpl, %bpl
movq 88(%rsp), %rbx # 8-byte Reload
jne .LBB1_66
.LBB1_65: # %.critedge
# in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
movl 4(%rsp), %ecx # 4-byte Reload
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
incl %r14d
movl %eax, 4(%rsp) # 4-byte Spill
cmpl $19, %r14d
je .LBB1_66
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_28 Depth 2
# Child Loop BB1_57 Depth 2
movq %r14, 104(%rsp) # 8-byte Spill
movq 96(%rsp), %rax # 8-byte Reload
movq 8(%rax), %rbx
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
testq %rbx, %rbx
je .LBB1_67
# %bb.2: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB1_6
# %bb.3: # in Loop: Header=BB1_1 Depth=1
testq %r14, %r14
js .LBB1_68
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movq %r14, %rdi
incq %rdi
js .LBB1_69
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, 32(%rsp)
movq %r14, 48(%rsp)
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
testq %r14, %r14
je .LBB1_10
# %bb.7: # in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rdi
cmpq $1, %r14
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_1 Depth=1
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB1_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
# in Loop: Header=BB1_1 Depth=1
movq %r14, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax,%r14)
movq 32(%rsp), %r15
.cfi_escape 0x2e, 0x00
callq __errno_location
movq %rax, %r14
movl (%rax), %ebp
movl $0, (%rax)
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
leaq 72(%rsp), %rsi
movl $10, %edx
callq __isoc23_strtol
cmpq %r15, 72(%rsp)
je .LBB1_11
# %bb.18: # in Loop: Header=BB1_1 Depth=1
movq %rax, %rbx
movslq %ebx, %rax
cmpq %rbx, %rax
jne .LBB1_20
# %bb.19: # in Loop: Header=BB1_1 Depth=1
movl (%r14), %eax
cmpl $34, %eax
je .LBB1_20
# %bb.22: # in Loop: Header=BB1_1 Depth=1
testl %eax, %eax
jne .LBB1_24
# %bb.23: # in Loop: Header=BB1_1 Depth=1
movl %ebp, (%r14)
.LBB1_24: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
# in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_26
# %bb.25: # %.critedge.i.i70
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB1_1 Depth=1
movl 4(%rsp), %r14d # 4-byte Reload
movl %r14d, %eax
cltd
idivl %ebx
movl %eax, 28(%rsp) # 4-byte Spill
movslq %r14d, %rbp
leaq (,%rbp,4), %r15
testl %ebp, %ebp
movq %r15, 112(%rsp) # 8-byte Spill
movq $-1, %rax
cmovsq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Znam
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Znam
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Znam
movq %rax, 88(%rsp) # 8-byte Spill
movl %r14d, %r15d
testl %ebp, %ebp
jle .LBB1_29
# %bb.27: # %.lr.ph.preheader
# in Loop: Header=BB1_1 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_28: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r13,%rbp,4)
.cfi_escape 0x2e, 0x00
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq %rbp, %r15
jne .LBB1_28
.LBB1_29: # %._crit_edge
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movq 112(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_30
# %bb.36: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_37
# %bb.40: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_41
# %bb.44: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_45
# %bb.48: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
movl 28(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %ebx, %edx
orq %rax, %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_50
# %bb.49: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 152(%rsp), %rax
movq %rax, 40(%rsp)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
.cfi_escape 0x2e, 0x10
movl $_Z11vectors_addPfS_, %edi
leaq 32(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_50: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbp, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_74
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i90
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_53
# %bb.52: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%rbx), %ecx
jmp .LBB1_54
.p2align 4, 0x90
.LBB1_53: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB1_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit93
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp) # 4-byte Folded Reload
setg %bpl
movq 104(%rsp), %r14 # 8-byte Reload
jle .LBB1_65
# %bb.55: # %.lr.ph148.preheader
# in Loop: Header=BB1_1 Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss (%r12), %xmm1
ucomiss %xmm1, %xmm0
jne .LBB1_60
jp .LBB1_60
# %bb.56: # %.lr.ph194.preheader
# in Loop: Header=BB1_1 Depth=1
leaq -1(%r15), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_57: # %.lr.ph194
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rcx, %rax
je .LBB1_65
# %bb.58: # %.lr.ph148
# in Loop: Header=BB1_57 Depth=2
movss 4(%r13,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 4(%r12,%rcx,4), %xmm0
movss 4(%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
incq %rcx
ucomiss %xmm0, %xmm1
jne .LBB1_59
jnp .LBB1_57
.LBB1_59: # %.lr.ph148._crit_edge
# in Loop: Header=BB1_1 Depth=1
cmpq %r15, %rcx
setb %bpl
.LBB1_60: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_75
# %bb.61: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_63
# %bb.62: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB1_64
.LBB1_30:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_70
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
jne .LBB1_32
# %bb.34:
.cfi_escape 0x2e, 0x00
jmp .LBB1_35
.LBB1_37:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_71
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i75
cmpb $0, 56(%rbx)
jne .LBB1_32
# %bb.39:
.cfi_escape 0x2e, 0x00
jmp .LBB1_35
.LBB1_41:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_72
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i80
cmpb $0, 56(%rbx)
jne .LBB1_32
# %bb.43:
.cfi_escape 0x2e, 0x00
jmp .LBB1_35
.LBB1_45:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_73
# %bb.46: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i85
cmpb $0, 56(%rbx)
je .LBB1_47
.LBB1_32:
movzbl 67(%rbx), %eax
jmp .LBB1_33
.LBB1_47:
.cfi_escape 0x2e, 0x00
.LBB1_35: # %.critedge108.sink.split
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_33: # %.critedge108.sink.split
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_66: # %.critedge108
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_69: # %.noexc11.i
.cfi_def_cfa_offset 224
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.LBB1_67: # %.noexc
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.LBB1_20: # %.critedge.i.i
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp1:
# %bb.21:
.LBB1_11:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp3:
# %bb.12:
.LBB1_74:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_68: # %.noexc.i
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.LBB1_75:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_70:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_71:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_72:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_73:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_13:
.Ltmp4:
movq %rax, %rbx
cmpl $0, (%r14)
jne .LBB1_15
# %bb.14:
movl %ebp, (%r14)
.LBB1_15: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_17
# %bb.16: # %.critedge.i.i71
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit73
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end1-.Ltmp3 # Call between .Ltmp3 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11vectors_addPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11vectors_addPfS_,@object # @_Z11vectors_addPfS_
.section .rodata,"a",@progbits
.globl _Z11vectors_addPfS_
.p2align 3, 0x0
_Z11vectors_addPfS_:
.quad _Z26__device_stub__vectors_addPfS_
.size _Z11vectors_addPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "stoi"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string: construction from null is not valid"
.size .L.str.2, 50
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11vectors_addPfS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__vectors_addPfS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z11vectors_addPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11vectors_addPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0005 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11vectors_addPfS_
.globl _Z11vectors_addPfS_
.p2align 8
.type _Z11vectors_addPfS_,@function
_Z11vectors_addPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11vectors_addPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11vectors_addPfS_, .Lfunc_end0-_Z11vectors_addPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11vectors_addPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11vectors_addPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001924af_00000000-6_lab01.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11vectors_addPfS_PfS_
.type _Z33__device_stub__Z11vectors_addPfS_PfS_, @function
_Z33__device_stub__Z11vectors_addPfS_PfS_:
.LFB3797:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11vectors_addPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z33__device_stub__Z11vectors_addPfS_PfS_, .-_Z33__device_stub__Z11vectors_addPfS_PfS_
.globl _Z11vectors_addPfS_
.type _Z11vectors_addPfS_, @function
_Z11vectors_addPfS_:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11vectors_addPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z11vectors_addPfS_, .-_Z11vectors_addPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "stoi"
.LC3:
.string "Error"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3768
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, 32(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $19, 44(%rsp)
movl $268435456, 12(%rsp)
.L45:
movq 32(%rsp), %rax
movq 8(%rax), %rbp
leaq 112(%rsp), %rax
movq %rax, 96(%rsp)
testq %rbp, %rbp
je .L55
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 80(%rsp)
cmpq $15, %rax
ja .L56
cmpq $1, %rax
jne .L16
movzbl 0(%rbp), %eax
movb %al, 112(%rsp)
.L17:
movq 80(%rsp), %rax
movq %rax, 104(%rsp)
movq 96(%rsp), %rdx
movb $0, (%rdx,%rax)
movq 96(%rsp), %rbp
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r12d
movl $0, (%rax)
leaq 80(%rsp), %rsi
movl $10, %edx
movq %rbp, %rdi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
cmpq 80(%rsp), %rbp
je .L57
movl (%rbx), %eax
cmpl $34, %eax
je .L20
movq 16(%rsp), %rcx
movl $2147483648, %edx
addq %rcx, %rdx
movl $4294967295, %ecx
cmpq %rdx, %rcx
jb .L20
movl 16(%rsp), %ebp
testl %eax, %eax
jne .L23
movl %r12d, (%rbx)
.L23:
movq 96(%rsp), %rdi
leaq 112(%rsp), %rax
cmpq %rax, %rdi
je .L24
movq 112(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L24:
movl 12(%rsp), %eax
cltd
idivl %ebp
movl %eax, 40(%rsp)
movl 12(%rsp), %ebx
movslq %ebx, %r13
salq $2, %r13
movq %r13, %rdi
.LEHB0:
call _Znam@PLT
movq %rax, %r14
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r15
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L29
movq %r14, %rbx
movq %r15, %rbp
leaq 0(%r13,%r14), %rax
movq %r13, 24(%rsp)
movq %rax, %r13
.L30:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r13, %rbx
jne .L30
movq 24(%rsp), %r13
.L29:
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L59
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L60
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl 16(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl 40(%rsp), %eax
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L36:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rax
imulq %rcx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L63
cmpb $0, 56(%rbp)
je .L39
movzbl 67(%rbp), %esi
.L40:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $0, 12(%rsp)
jle .L41
movl $0, %eax
.L44:
movss (%r14,%rax), %xmm0
addss (%r15,%rax), %xmm0
ucomiss (%r12,%rax), %xmm0
jp .L49
jne .L49
addq $4, %rax
cmpq %rax, %r13
jne .L44
.L41:
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movl 12(%rsp), %ecx
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
movl %eax, 12(%rsp)
subl $1, 44(%rsp)
jne .L45
jmp .L46
.L55:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
leaq .LC0(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L64:
call __stack_chk_fail@PLT
.L56:
leaq 80(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE0:
movq %rax, %rdi
movq %rax, 96(%rsp)
movq 80(%rsp), %rax
movq %rax, 112(%rsp)
.L15:
movq %rbx, %rdx
movq %rbp, %rsi
call memcpy@PLT
jmp .L17
.L16:
testq %rax, %rax
je .L17
leaq 112(%rsp), %rdi
jmp .L15
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L65
leaq .LC1(%rip), %rdi
.LEHB1:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L65:
call __stack_chk_fail@PLT
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
leaq .LC1(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE1:
.L48:
endbr64
movq %rax, %rbp
cmpl $0, (%rbx)
jne .L27
movl %r12d, (%rbx)
.L27:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L66:
call __stack_chk_fail@PLT
.L28:
movq %rbp, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.L58:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L59:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L60:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L61:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L62:
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z33__device_stub__Z11vectors_addPfS_PfS_
jmp .L36
.L63:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L67
call _ZSt16__throw_bad_castv@PLT
.L67:
call __stack_chk_fail@PLT
.L39:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L49:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
.L46:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3768:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3768-.LLSDACSB3768
.LLSDACSB3768:
.uleb128 .LEHB0-.LFB3768
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3768
.uleb128 .LEHE1-.LEHB1
.uleb128 .L48-.LFB3768
.uleb128 0
.uleb128 .LEHB2-.LFB3768
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3768:
.text
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11vectors_addPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vectors_addPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab01.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__vectors_addPfS_ # -- Begin function _Z26__device_stub__vectors_addPfS_
.p2align 4, 0x90
.type _Z26__device_stub__vectors_addPfS_,@function
_Z26__device_stub__vectors_addPfS_: # @_Z26__device_stub__vectors_addPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11vectors_addPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__vectors_addPfS_, .Lfunc_end0-_Z26__device_stub__vectors_addPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 96(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movl $268435456, 4(%rsp) # 4-byte Folded Spill
# imm = 0x10000000
jmp .LBB1_1
.LBB1_63: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_64: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
testb %bpl, %bpl
movq 88(%rsp), %rbx # 8-byte Reload
jne .LBB1_66
.LBB1_65: # %.critedge
# in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
movl 4(%rsp), %ecx # 4-byte Reload
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
incl %r14d
movl %eax, 4(%rsp) # 4-byte Spill
cmpl $19, %r14d
je .LBB1_66
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_28 Depth 2
# Child Loop BB1_57 Depth 2
movq %r14, 104(%rsp) # 8-byte Spill
movq 96(%rsp), %rax # 8-byte Reload
movq 8(%rax), %rbx
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
testq %rbx, %rbx
je .LBB1_67
# %bb.2: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB1_6
# %bb.3: # in Loop: Header=BB1_1 Depth=1
testq %r14, %r14
js .LBB1_68
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movq %r14, %rdi
incq %rdi
js .LBB1_69
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, 32(%rsp)
movq %r14, 48(%rsp)
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
testq %r14, %r14
je .LBB1_10
# %bb.7: # in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rdi
cmpq $1, %r14
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_1 Depth=1
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB1_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
# in Loop: Header=BB1_1 Depth=1
movq %r14, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax,%r14)
movq 32(%rsp), %r15
.cfi_escape 0x2e, 0x00
callq __errno_location
movq %rax, %r14
movl (%rax), %ebp
movl $0, (%rax)
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
leaq 72(%rsp), %rsi
movl $10, %edx
callq __isoc23_strtol
cmpq %r15, 72(%rsp)
je .LBB1_11
# %bb.18: # in Loop: Header=BB1_1 Depth=1
movq %rax, %rbx
movslq %ebx, %rax
cmpq %rbx, %rax
jne .LBB1_20
# %bb.19: # in Loop: Header=BB1_1 Depth=1
movl (%r14), %eax
cmpl $34, %eax
je .LBB1_20
# %bb.22: # in Loop: Header=BB1_1 Depth=1
testl %eax, %eax
jne .LBB1_24
# %bb.23: # in Loop: Header=BB1_1 Depth=1
movl %ebp, (%r14)
.LBB1_24: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
# in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_26
# %bb.25: # %.critedge.i.i70
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB1_1 Depth=1
movl 4(%rsp), %r14d # 4-byte Reload
movl %r14d, %eax
cltd
idivl %ebx
movl %eax, 28(%rsp) # 4-byte Spill
movslq %r14d, %rbp
leaq (,%rbp,4), %r15
testl %ebp, %ebp
movq %r15, 112(%rsp) # 8-byte Spill
movq $-1, %rax
cmovsq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Znam
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Znam
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Znam
movq %rax, 88(%rsp) # 8-byte Spill
movl %r14d, %r15d
testl %ebp, %ebp
jle .LBB1_29
# %bb.27: # %.lr.ph.preheader
# in Loop: Header=BB1_1 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_28: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r13,%rbp,4)
.cfi_escape 0x2e, 0x00
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq %rbp, %r15
jne .LBB1_28
.LBB1_29: # %._crit_edge
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movq 112(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_30
# %bb.36: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_37
# %bb.40: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_41
# %bb.44: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_45
# %bb.48: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
movl 28(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %ebx, %edx
orq %rax, %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_50
# %bb.49: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 152(%rsp), %rax
movq %rax, 40(%rsp)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
.cfi_escape 0x2e, 0x10
movl $_Z11vectors_addPfS_, %edi
leaq 32(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_50: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbp, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_74
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i90
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_53
# %bb.52: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%rbx), %ecx
jmp .LBB1_54
.p2align 4, 0x90
.LBB1_53: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB1_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit93
# in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp) # 4-byte Folded Reload
setg %bpl
movq 104(%rsp), %r14 # 8-byte Reload
jle .LBB1_65
# %bb.55: # %.lr.ph148.preheader
# in Loop: Header=BB1_1 Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss (%r12), %xmm1
ucomiss %xmm1, %xmm0
jne .LBB1_60
jp .LBB1_60
# %bb.56: # %.lr.ph194.preheader
# in Loop: Header=BB1_1 Depth=1
leaq -1(%r15), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_57: # %.lr.ph194
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rcx, %rax
je .LBB1_65
# %bb.58: # %.lr.ph148
# in Loop: Header=BB1_57 Depth=2
movss 4(%r13,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 4(%r12,%rcx,4), %xmm0
movss 4(%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
incq %rcx
ucomiss %xmm0, %xmm1
jne .LBB1_59
jnp .LBB1_57
.LBB1_59: # %.lr.ph148._crit_edge
# in Loop: Header=BB1_1 Depth=1
cmpq %r15, %rcx
setb %bpl
.LBB1_60: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_75
# %bb.61: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_63
# %bb.62: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB1_64
.LBB1_30:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_70
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
jne .LBB1_32
# %bb.34:
.cfi_escape 0x2e, 0x00
jmp .LBB1_35
.LBB1_37:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_71
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i75
cmpb $0, 56(%rbx)
jne .LBB1_32
# %bb.39:
.cfi_escape 0x2e, 0x00
jmp .LBB1_35
.LBB1_41:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_72
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i80
cmpb $0, 56(%rbx)
jne .LBB1_32
# %bb.43:
.cfi_escape 0x2e, 0x00
jmp .LBB1_35
.LBB1_45:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_73
# %bb.46: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i85
cmpb $0, 56(%rbx)
je .LBB1_47
.LBB1_32:
movzbl 67(%rbx), %eax
jmp .LBB1_33
.LBB1_47:
.cfi_escape 0x2e, 0x00
.LBB1_35: # %.critedge108.sink.split
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_33: # %.critedge108.sink.split
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_66: # %.critedge108
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_69: # %.noexc11.i
.cfi_def_cfa_offset 224
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.LBB1_67: # %.noexc
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt19__throw_logic_errorPKc
.LBB1_20: # %.critedge.i.i
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp1:
# %bb.21:
.LBB1_11:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp3:
# %bb.12:
.LBB1_74:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_68: # %.noexc.i
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.LBB1_75:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_70:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_71:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_72:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_73:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_13:
.Ltmp4:
movq %rax, %rbx
cmpl $0, (%r14)
jne .LBB1_15
# %bb.14:
movl %ebp, (%r14)
.LBB1_15: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_17
# %bb.16: # %.critedge.i.i71
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit73
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end1-.Ltmp3 # Call between .Ltmp3 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11vectors_addPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11vectors_addPfS_,@object # @_Z11vectors_addPfS_
.section .rodata,"a",@progbits
.globl _Z11vectors_addPfS_
.p2align 3, 0x0
_Z11vectors_addPfS_:
.quad _Z26__device_stub__vectors_addPfS_
.size _Z11vectors_addPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "stoi"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string: construction from null is not valid"
.size .L.str.2, 50
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11vectors_addPfS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__vectors_addPfS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z11vectors_addPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <chrono>
constexpr size_t kSize = 1000000;
class Stopwatch {
public:
using TimePoint = decltype(std::chrono::high_resolution_clock::now());
Stopwatch(): start(std::chrono::high_resolution_clock::now()) {}
~Stopwatch() {
end = std::chrono::high_resolution_clock::now();
std::cout << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count()
<< " us\n";
}
private:
TimePoint start;
TimePoint end;
};
void Transfer0(float* orig, float* target0, float* target1, float* target2) {
cudaMemcpy(target0, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(target1, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(target2, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
};
void Transfer1(float* orig, float* target0, float* target1, float* target2) {
cudaStream_t stream[3];
float* targets[3] = {target0, target1, target2};
for (int i = 0; i < 3; ++i) {
cudaStreamCreate(&stream[i]);
}
for (int i = 0; i < 3; ++i) {
cudaMemcpyAsync(targets[i], orig, kSize * sizeof(float), cudaMemcpyHostToDevice, stream[i]);
}
for (int i = 0; i < 3; ++i) {
cudaStreamDestroy(stream[i]);
}
};
int main() {
float* original = new float[kSize];
float* target0, *target1, *target2;
cudaMalloc(&target0, sizeof(float) * kSize);
cudaMalloc(&target1, sizeof(float) * kSize);
cudaMalloc(&target2, sizeof(float) * kSize);
{
Stopwatch s;
Transfer0(original, target0, target1, target2);
}
{
Stopwatch s;
Transfer1(original, target0, target1, target2);
}
cudaFree(target0);
cudaFree(target1);
cudaFree(target2);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <chrono>
constexpr size_t kSize = 1000000;
class Stopwatch {
public:
using TimePoint = decltype(std::chrono::high_resolution_clock::now());
Stopwatch(): start(std::chrono::high_resolution_clock::now()) {}
~Stopwatch() {
end = std::chrono::high_resolution_clock::now();
std::cout << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count()
<< " us\n";
}
private:
TimePoint start;
TimePoint end;
};
void Transfer0(float* orig, float* target0, float* target1, float* target2) {
cudaMemcpy(target0, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(target1, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(target2, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
};
void Transfer1(float* orig, float* target0, float* target1, float* target2) {
cudaStream_t stream[3];
float* targets[3] = {target0, target1, target2};
for (int i = 0; i < 3; ++i) {
cudaStreamCreate(&stream[i]);
}
for (int i = 0; i < 3; ++i) {
cudaMemcpyAsync(targets[i], orig, kSize * sizeof(float), cudaMemcpyHostToDevice, stream[i]);
}
for (int i = 0; i < 3; ++i) {
cudaStreamDestroy(stream[i]);
}
};
int main() {
float* original = new float[kSize];
float* target0, *target1, *target2;
cudaMalloc(&target0, sizeof(float) * kSize);
cudaMalloc(&target1, sizeof(float) * kSize);
cudaMalloc(&target2, sizeof(float) * kSize);
{
Stopwatch s;
Transfer0(original, target0, target1, target2);
}
{
Stopwatch s;
Transfer1(original, target0, target1, target2);
}
cudaFree(target0);
cudaFree(target1);
cudaFree(target2);
return 0;
} | .file "tmpxft_00002075_00000000-6_cuda-async-copy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3780:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3780:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._ZN9StopwatchD2Ev.str1.1,"aMS",@progbits,1
.LC0:
.string " us\n"
.section .text._ZN9StopwatchD2Ev,"axG",@progbits,_ZN9StopwatchD5Ev,comdat
.align 2
.weak _ZN9StopwatchD2Ev
.type _ZN9StopwatchD2Ev, @function
_ZN9StopwatchD2Ev:
.LFB3773:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3773
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rcx
movq %rax, 8(%rbx)
subq (%rbx), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
movl $4, %edx
leaq .LC0(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3773:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9StopwatchD2Ev,"aG",@progbits,_ZN9StopwatchD5Ev,comdat
.LLSDA3773:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3773-.LLSDACSB3773
.LLSDACSB3773:
.LLSDACSE3773:
.section .text._ZN9StopwatchD2Ev,"axG",@progbits,_ZN9StopwatchD5Ev,comdat
.size _ZN9StopwatchD2Ev, .-_ZN9StopwatchD2Ev
.weak _ZN9StopwatchD1Ev
.set _ZN9StopwatchD1Ev,_ZN9StopwatchD2Ev
.text
.globl _Z9Transfer0PfS_S_S_
.type _Z9Transfer0PfS_S_S_, @function
_Z9Transfer0PfS_S_S_:
.LFB3775:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq %rsi, %rdi
movq %rdx, %r12
movq %rcx, %rbp
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _Z9Transfer0PfS_S_S_, .-_Z9Transfer0PfS_S_S_
.globl _Z9Transfer1PfS_S_S_
.type _Z9Transfer1PfS_S_S_, @function
_Z9Transfer1PfS_S_S_:
.LFB3776:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 48(%rsp)
movq %rsp, %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %ebx
.L8:
movq 32(%rsp,%rbx), %rdi
movq (%rsp,%rbx), %r8
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
call cudaMemcpyAsync@PLT
addq $8, %rbx
cmpq $24, %rbx
jne .L8
movq (%rsp), %rdi
call cudaStreamDestroy@PLT
movq 8(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 16(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3776:
.size _Z9Transfer1PfS_S_S_, .-_Z9Transfer1PfS_S_S_
.globl main
.type main, @function
main:
.LFB3777:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3777
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000000, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
.LEHE0:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 32(%rsp)
movq $0, 40(%rsp)
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
.LEHB1:
call _Z9Transfer0PfS_S_S_
.LEHE1:
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 32(%rsp)
movq $0, 40(%rsp)
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
.LEHB2:
call _Z9Transfer1PfS_S_S_
.LEHE2:
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
movq 8(%rsp), %rdi
.LEHB3:
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L20:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3777:
.section .gcc_except_table,"a",@progbits
.LLSDA3777:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3777-.LLSDACSB3777
.LLSDACSB3777:
.uleb128 .LEHB0-.LFB3777
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3777
.uleb128 .LEHE1-.LEHB1
.uleb128 .L19-.LFB3777
.uleb128 0
.uleb128 .LEHB2-.LFB3777
.uleb128 .LEHE2-.LEHB2
.uleb128 .L20-.LFB3777
.uleb128 0
.uleb128 .LEHB3-.LFB3777
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3777:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <chrono>
constexpr size_t kSize = 1000000;
class Stopwatch {
public:
using TimePoint = decltype(std::chrono::high_resolution_clock::now());
Stopwatch(): start(std::chrono::high_resolution_clock::now()) {}
~Stopwatch() {
end = std::chrono::high_resolution_clock::now();
std::cout << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count()
<< " us\n";
}
private:
TimePoint start;
TimePoint end;
};
void Transfer0(float* orig, float* target0, float* target1, float* target2) {
cudaMemcpy(target0, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(target1, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(target2, orig, kSize * sizeof(float), cudaMemcpyHostToDevice);
};
void Transfer1(float* orig, float* target0, float* target1, float* target2) {
cudaStream_t stream[3];
float* targets[3] = {target0, target1, target2};
for (int i = 0; i < 3; ++i) {
cudaStreamCreate(&stream[i]);
}
for (int i = 0; i < 3; ++i) {
cudaMemcpyAsync(targets[i], orig, kSize * sizeof(float), cudaMemcpyHostToDevice, stream[i]);
}
for (int i = 0; i < 3; ++i) {
cudaStreamDestroy(stream[i]);
}
};
int main() {
float* original = new float[kSize];
float* target0, *target1, *target2;
cudaMalloc(&target0, sizeof(float) * kSize);
cudaMalloc(&target1, sizeof(float) * kSize);
cudaMalloc(&target2, sizeof(float) * kSize);
{
Stopwatch s;
Transfer0(original, target0, target1, target2);
}
{
Stopwatch s;
Transfer1(original, target0, target1, target2);
}
cudaFree(target0);
cudaFree(target1);
cudaFree(target2);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
constexpr size_t kSize = 1000000;
class Stopwatch {
public:
using TimePoint = decltype(std::chrono::high_resolution_clock::now());
Stopwatch(): start(std::chrono::high_resolution_clock::now()) {}
~Stopwatch() {
end = std::chrono::high_resolution_clock::now();
std::cout << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count()
<< " us\n";
}
private:
TimePoint start;
TimePoint end;
};
void Transfer0(float* orig, float* target0, float* target1, float* target2) {
hipMemcpy(target0, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(target1, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(target2, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
};
void Transfer1(float* orig, float* target0, float* target1, float* target2) {
hipStream_t stream[3];
float* targets[3] = {target0, target1, target2};
for (int i = 0; i < 3; ++i) {
hipStreamCreate(&stream[i]);
}
for (int i = 0; i < 3; ++i) {
hipMemcpyAsync(targets[i], orig, kSize * sizeof(float), hipMemcpyHostToDevice, stream[i]);
}
for (int i = 0; i < 3; ++i) {
hipStreamDestroy(stream[i]);
}
};
int main() {
float* original = new float[kSize];
float* target0, *target1, *target2;
hipMalloc(&target0, sizeof(float) * kSize);
hipMalloc(&target1, sizeof(float) * kSize);
hipMalloc(&target2, sizeof(float) * kSize);
{
Stopwatch s;
Transfer0(original, target0, target1, target2);
}
{
Stopwatch s;
Transfer1(original, target0, target1, target2);
}
hipFree(target0);
hipFree(target1);
hipFree(target2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
constexpr size_t kSize = 1000000;
class Stopwatch {
public:
using TimePoint = decltype(std::chrono::high_resolution_clock::now());
Stopwatch(): start(std::chrono::high_resolution_clock::now()) {}
~Stopwatch() {
end = std::chrono::high_resolution_clock::now();
std::cout << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count()
<< " us\n";
}
private:
TimePoint start;
TimePoint end;
};
void Transfer0(float* orig, float* target0, float* target1, float* target2) {
hipMemcpy(target0, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(target1, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(target2, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
};
void Transfer1(float* orig, float* target0, float* target1, float* target2) {
hipStream_t stream[3];
float* targets[3] = {target0, target1, target2};
for (int i = 0; i < 3; ++i) {
hipStreamCreate(&stream[i]);
}
for (int i = 0; i < 3; ++i) {
hipMemcpyAsync(targets[i], orig, kSize * sizeof(float), hipMemcpyHostToDevice, stream[i]);
}
for (int i = 0; i < 3; ++i) {
hipStreamDestroy(stream[i]);
}
};
int main() {
float* original = new float[kSize];
float* target0, *target1, *target2;
hipMalloc(&target0, sizeof(float) * kSize);
hipMalloc(&target1, sizeof(float) * kSize);
hipMalloc(&target2, sizeof(float) * kSize);
{
Stopwatch s;
Transfer0(original, target0, target1, target2);
}
{
Stopwatch s;
Transfer1(original, target0, target1, target2);
}
hipFree(target0);
hipFree(target1);
hipFree(target2);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
constexpr size_t kSize = 1000000;
class Stopwatch {
public:
using TimePoint = decltype(std::chrono::high_resolution_clock::now());
Stopwatch(): start(std::chrono::high_resolution_clock::now()) {}
~Stopwatch() {
end = std::chrono::high_resolution_clock::now();
std::cout << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count()
<< " us\n";
}
private:
TimePoint start;
TimePoint end;
};
void Transfer0(float* orig, float* target0, float* target1, float* target2) {
hipMemcpy(target0, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(target1, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(target2, orig, kSize * sizeof(float), hipMemcpyHostToDevice);
};
void Transfer1(float* orig, float* target0, float* target1, float* target2) {
hipStream_t stream[3];
float* targets[3] = {target0, target1, target2};
for (int i = 0; i < 3; ++i) {
hipStreamCreate(&stream[i]);
}
for (int i = 0; i < 3; ++i) {
hipMemcpyAsync(targets[i], orig, kSize * sizeof(float), hipMemcpyHostToDevice, stream[i]);
}
for (int i = 0; i < 3; ++i) {
hipStreamDestroy(stream[i]);
}
};
int main() {
float* original = new float[kSize];
float* target0, *target1, *target2;
hipMalloc(&target0, sizeof(float) * kSize);
hipMalloc(&target1, sizeof(float) * kSize);
hipMalloc(&target2, sizeof(float) * kSize);
{
Stopwatch s;
Transfer0(original, target0, target1, target2);
}
{
Stopwatch s;
Transfer1(original, target0, target1, target2);
}
hipFree(target0);
hipFree(target1);
hipFree(target2);
return 0;
} | .text
.file "cuda-async-copy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9Transfer0PfS_S_S_ # -- Begin function _Z9Transfer0PfS_S_S_
.p2align 4, 0x90
.type _Z9Transfer0PfS_S_S_,@function
_Z9Transfer0PfS_S_S_: # @_Z9Transfer0PfS_S_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rdi, %r15
movl $4000000, %edx # imm = 0x3D0900
movq %rsi, %rdi
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movq %r15, %rsi
movl $1, %ecx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end0:
.size _Z9Transfer0PfS_S_S_, .Lfunc_end0-_Z9Transfer0PfS_S_S_
.cfi_endproc
# -- End function
.globl _Z9Transfer1PfS_S_S_ # -- Begin function _Z9Transfer1PfS_S_S_
.p2align 4, 0x90
.type _Z9Transfer1PfS_S_S_,@function
_Z9Transfer1PfS_S_S_: # @_Z9Transfer1PfS_S_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %rcx, 16(%rsp)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r14), %rdi
addq $32, %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $24, %r14
jne .LBB1_1
# %bb.2: # %.preheader15.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader15
# =>This Inner Loop Header: Depth=1
movq (%rsp,%r14,8), %rdi
movq 32(%rsp,%r14,8), %r8
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpyAsync
incq %r14
cmpq $3, %r14
jne .LBB1_3
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 32(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $3, %rbx
jne .LBB1_5
# %bb.6:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9Transfer1PfS_S_S_, .Lfunc_end1-_Z9Transfer1PfS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 32(%rsp)
movq $0, 40(%rsp)
movq 24(%rsp), %rdi
movq 16(%rsp), %r15
movq 8(%rsp), %r14
.Ltmp0:
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp1:
# %bb.1: # %.noexc
.Ltmp2:
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.2: # %.noexc5
.Ltmp4:
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp5:
# %bb.3: # %_Z9Transfer0PfS_S_S_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 40(%rsp)
subq 32(%rsp), %rax
movabsq $2361183241434822607, %r14 # imm = 0x20C49BA5E353F7CF
imulq %r14
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.Ltmp7:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp8:
# %bb.4: # %_ZNSolsEl.exit.i
.Ltmp9:
movl $.L.str, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.5: # %_ZN9StopwatchD2Ev.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 64(%rsp)
movq $0, 72(%rsp)
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 96(%rsp)
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r15), %rdi
addq $32, %rdi
.Ltmp12:
callq hipStreamCreate
.Ltmp13:
# %bb.7: # %.noexc7
# in Loop: Header=BB2_6 Depth=1
addq $8, %r15
cmpq $24, %r15
jne .LBB2_6
# %bb.8: # %.preheader15.i.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_9: # %.preheader15.i
# =>This Inner Loop Header: Depth=1
movq 80(%rsp,%r15,8), %rdi
movq 32(%rsp,%r15,8), %r8
.Ltmp15:
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpyAsync
.Ltmp16:
# %bb.10: # %.noexc8
# in Loop: Header=BB2_9 Depth=1
incq %r15
cmpq $3, %r15
jne .LBB2_9
# %bb.11: # %.preheader.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_12: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq 32(%rsp,%rbx,8), %rdi
.Ltmp18:
callq hipStreamDestroy
.Ltmp19:
# %bb.13: # %.noexc9
# in Loop: Header=BB2_12 Depth=1
incq %rbx
cmpq $3, %rbx
jne .LBB2_12
# %bb.14: # %_Z9Transfer1PfS_S_S_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 72(%rsp)
subq 64(%rsp), %rax
imulq %r14
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.Ltmp21:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp22:
# %bb.15: # %_ZNSolsEl.exit.i11
.Ltmp23:
movl $.L.str, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp24:
# %bb.16: # %_ZN9StopwatchD2Ev.exit12
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 144
.Ltmp25:
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_23:
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_17:
.Ltmp6:
movq %rax, %rbx
leaq 32(%rsp), %rdi
jmp .LBB2_22
.LBB2_18: # %.loopexit
.Ltmp20:
jmp .LBB2_21
.LBB2_19: # %.loopexit.split-lp.loopexit
.Ltmp17:
jmp .LBB2_21
.LBB2_20: # %.loopexit.split-lp.loopexit.split-lp
.Ltmp14:
.LBB2_21: # %.loopexit.split-lp
movq %rax, %rbx
leaq 64(%rsp), %rdi
.LBB2_22:
callq _ZN9StopwatchD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp10-.Ltmp7 # Call between .Ltmp7 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp21 # Call between .Ltmp21 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 1 # On action: 1
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp24 # Call between .Ltmp24 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZN9StopwatchD2Ev,"axG",@progbits,_ZN9StopwatchD2Ev,comdat
.weak _ZN9StopwatchD2Ev # -- Begin function _ZN9StopwatchD2Ev
.p2align 4, 0x90
.type _ZN9StopwatchD2Ev,@function
_ZN9StopwatchD2Ev: # @_ZN9StopwatchD2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 8(%rbx)
subq (%rbx), %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.Ltmp26:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp27:
# %bb.1: # %_ZNSolsEl.exit
.Ltmp28:
movl $.L.str, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp29:
# %bb.2: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 16
.Ltmp30:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZN9StopwatchD2Ev, .Lfunc_end3-_ZN9StopwatchD2Ev
.cfi_endproc
.section .gcc_except_table._ZN9StopwatchD2Ev,"aG",@progbits,_ZN9StopwatchD2Ev,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase1-.Lttbaseref1
.Lttbaseref1:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp29-.Ltmp26 # Call between .Ltmp26 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin1 # jumps to .Ltmp30
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase1:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end4:
.size __clang_call_terminate, .Lfunc_end4-__clang_call_terminate
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " us\n"
.size .L.str, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00002075_00000000-6_cuda-async-copy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3780:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3780:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._ZN9StopwatchD2Ev.str1.1,"aMS",@progbits,1
.LC0:
.string " us\n"
.section .text._ZN9StopwatchD2Ev,"axG",@progbits,_ZN9StopwatchD5Ev,comdat
.align 2
.weak _ZN9StopwatchD2Ev
.type _ZN9StopwatchD2Ev, @function
_ZN9StopwatchD2Ev:
.LFB3773:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3773
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rcx
movq %rax, 8(%rbx)
subq (%rbx), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
movl $4, %edx
leaq .LC0(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3773:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9StopwatchD2Ev,"aG",@progbits,_ZN9StopwatchD5Ev,comdat
.LLSDA3773:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3773-.LLSDACSB3773
.LLSDACSB3773:
.LLSDACSE3773:
.section .text._ZN9StopwatchD2Ev,"axG",@progbits,_ZN9StopwatchD5Ev,comdat
.size _ZN9StopwatchD2Ev, .-_ZN9StopwatchD2Ev
.weak _ZN9StopwatchD1Ev
.set _ZN9StopwatchD1Ev,_ZN9StopwatchD2Ev
.text
.globl _Z9Transfer0PfS_S_S_
.type _Z9Transfer0PfS_S_S_, @function
_Z9Transfer0PfS_S_S_:
.LFB3775:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq %rsi, %rdi
movq %rdx, %r12
movq %rcx, %rbp
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _Z9Transfer0PfS_S_S_, .-_Z9Transfer0PfS_S_S_
.globl _Z9Transfer1PfS_S_S_
.type _Z9Transfer1PfS_S_S_, @function
_Z9Transfer1PfS_S_S_:
.LFB3776:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 48(%rsp)
movq %rsp, %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %ebx
.L8:
movq 32(%rsp,%rbx), %rdi
movq (%rsp,%rbx), %r8
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
call cudaMemcpyAsync@PLT
addq $8, %rbx
cmpq $24, %rbx
jne .L8
movq (%rsp), %rdi
call cudaStreamDestroy@PLT
movq 8(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 16(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3776:
.size _Z9Transfer1PfS_S_S_, .-_Z9Transfer1PfS_S_S_
.globl main
.type main, @function
main:
.LFB3777:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3777
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000000, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
.LEHE0:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 32(%rsp)
movq $0, 40(%rsp)
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
.LEHB1:
call _Z9Transfer0PfS_S_S_
.LEHE1:
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 32(%rsp)
movq $0, 40(%rsp)
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
.LEHB2:
call _Z9Transfer1PfS_S_S_
.LEHE2:
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
movq 8(%rsp), %rdi
.LEHB3:
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L20:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZN9StopwatchD1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3777:
.section .gcc_except_table,"a",@progbits
.LLSDA3777:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3777-.LLSDACSB3777
.LLSDACSB3777:
.uleb128 .LEHB0-.LFB3777
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3777
.uleb128 .LEHE1-.LEHB1
.uleb128 .L19-.LFB3777
.uleb128 0
.uleb128 .LEHB2-.LFB3777
.uleb128 .LEHE2-.LEHB2
.uleb128 .L20-.LFB3777
.uleb128 0
.uleb128 .LEHB3-.LFB3777
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3777:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-async-copy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9Transfer0PfS_S_S_ # -- Begin function _Z9Transfer0PfS_S_S_
.p2align 4, 0x90
.type _Z9Transfer0PfS_S_S_,@function
_Z9Transfer0PfS_S_S_: # @_Z9Transfer0PfS_S_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rdi, %r15
movl $4000000, %edx # imm = 0x3D0900
movq %rsi, %rdi
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movq %r15, %rsi
movl $1, %ecx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end0:
.size _Z9Transfer0PfS_S_S_, .Lfunc_end0-_Z9Transfer0PfS_S_S_
.cfi_endproc
# -- End function
.globl _Z9Transfer1PfS_S_S_ # -- Begin function _Z9Transfer1PfS_S_S_
.p2align 4, 0x90
.type _Z9Transfer1PfS_S_S_,@function
_Z9Transfer1PfS_S_S_: # @_Z9Transfer1PfS_S_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %rcx, 16(%rsp)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r14), %rdi
addq $32, %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $24, %r14
jne .LBB1_1
# %bb.2: # %.preheader15.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader15
# =>This Inner Loop Header: Depth=1
movq (%rsp,%r14,8), %rdi
movq 32(%rsp,%r14,8), %r8
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpyAsync
incq %r14
cmpq $3, %r14
jne .LBB1_3
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 32(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $3, %rbx
jne .LBB1_5
# %bb.6:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9Transfer1PfS_S_S_, .Lfunc_end1-_Z9Transfer1PfS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 32(%rsp)
movq $0, 40(%rsp)
movq 24(%rsp), %rdi
movq 16(%rsp), %r15
movq 8(%rsp), %r14
.Ltmp0:
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp1:
# %bb.1: # %.noexc
.Ltmp2:
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.2: # %.noexc5
.Ltmp4:
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp5:
# %bb.3: # %_Z9Transfer0PfS_S_S_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 40(%rsp)
subq 32(%rsp), %rax
movabsq $2361183241434822607, %r14 # imm = 0x20C49BA5E353F7CF
imulq %r14
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.Ltmp7:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp8:
# %bb.4: # %_ZNSolsEl.exit.i
.Ltmp9:
movl $.L.str, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.5: # %_ZN9StopwatchD2Ev.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 64(%rsp)
movq $0, 72(%rsp)
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 96(%rsp)
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r15), %rdi
addq $32, %rdi
.Ltmp12:
callq hipStreamCreate
.Ltmp13:
# %bb.7: # %.noexc7
# in Loop: Header=BB2_6 Depth=1
addq $8, %r15
cmpq $24, %r15
jne .LBB2_6
# %bb.8: # %.preheader15.i.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_9: # %.preheader15.i
# =>This Inner Loop Header: Depth=1
movq 80(%rsp,%r15,8), %rdi
movq 32(%rsp,%r15,8), %r8
.Ltmp15:
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpyAsync
.Ltmp16:
# %bb.10: # %.noexc8
# in Loop: Header=BB2_9 Depth=1
incq %r15
cmpq $3, %r15
jne .LBB2_9
# %bb.11: # %.preheader.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_12: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq 32(%rsp,%rbx,8), %rdi
.Ltmp18:
callq hipStreamDestroy
.Ltmp19:
# %bb.13: # %.noexc9
# in Loop: Header=BB2_12 Depth=1
incq %rbx
cmpq $3, %rbx
jne .LBB2_12
# %bb.14: # %_Z9Transfer1PfS_S_S_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 72(%rsp)
subq 64(%rsp), %rax
imulq %r14
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.Ltmp21:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp22:
# %bb.15: # %_ZNSolsEl.exit.i11
.Ltmp23:
movl $.L.str, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp24:
# %bb.16: # %_ZN9StopwatchD2Ev.exit12
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 144
.Ltmp25:
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_23:
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_17:
.Ltmp6:
movq %rax, %rbx
leaq 32(%rsp), %rdi
jmp .LBB2_22
.LBB2_18: # %.loopexit
.Ltmp20:
jmp .LBB2_21
.LBB2_19: # %.loopexit.split-lp.loopexit
.Ltmp17:
jmp .LBB2_21
.LBB2_20: # %.loopexit.split-lp.loopexit.split-lp
.Ltmp14:
.LBB2_21: # %.loopexit.split-lp
movq %rax, %rbx
leaq 64(%rsp), %rdi
.LBB2_22:
callq _ZN9StopwatchD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp10-.Ltmp7 # Call between .Ltmp7 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp21 # Call between .Ltmp21 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 1 # On action: 1
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp24 # Call between .Ltmp24 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZN9StopwatchD2Ev,"axG",@progbits,_ZN9StopwatchD2Ev,comdat
.weak _ZN9StopwatchD2Ev # -- Begin function _ZN9StopwatchD2Ev
.p2align 4, 0x90
.type _ZN9StopwatchD2Ev,@function
_ZN9StopwatchD2Ev: # @_ZN9StopwatchD2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 8(%rbx)
subq (%rbx), %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
.Ltmp26:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp27:
# %bb.1: # %_ZNSolsEl.exit
.Ltmp28:
movl $.L.str, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp29:
# %bb.2: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 16
.Ltmp30:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZN9StopwatchD2Ev, .Lfunc_end3-_ZN9StopwatchD2Ev
.cfi_endproc
.section .gcc_except_table._ZN9StopwatchD2Ev,"aG",@progbits,_ZN9StopwatchD2Ev,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase1-.Lttbaseref1
.Lttbaseref1:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp29-.Ltmp26 # Call between .Ltmp26 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin1 # jumps to .Ltmp30
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase1:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end4:
.size __clang_call_terminate, .Lfunc_end4-__clang_call_terminate
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " us\n"
.size .L.str, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by root on 2020/11/24.
//
#include "curand_kernel.h"
#include "cuda_runtime.h"
#include "stdio.h"
__global__ void initialize_state(curandState* states) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// init curand state for each thread
curand_init(9444, tid, 0, states + tid);
}
__global__ void refill_randoms(float *dRand, int N, curandState* states) {
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int nthreads = gridDim.x * blockDim.x;
curandState *state = states + tid;
for (int i = tid; i < N; i += nthreads) {
dRand[i] = curand_uniform(state);
// generate random number following uniform distribution for each thread
// the number of random numbers is N in total
}
}
float cuda_device_rand() {
// use device api to generate random numbers
static curandState *states = NULL;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
int block = 256;
int grid = 30;
if (dRand == NULL) {
// if dRand is null, then allocate memory and initialize states
cudaMalloc(&dRand, sizeof(float ) * dRand_length);
cudaMalloc(&states, sizeof(curandState) * block * grid);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
initialize_state<<<grid, block>>>(states);
}
if (dRand_used == dRand_length) {
// if all random data have been traversed, we should generate a new batch of data
refill_randoms<<<grid, block>>>(dRand, dRand_length, states);
cudaMemcpy(hRand, dRand, sizeof(float ) * dRand_length, cudaMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
float cuda_host_rand() {
// generate random data with host api
static curandGenerator_t randGen;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
if (dRand == NULL) {
// if dRand is null, then allocate memory and create generator
cudaMalloc(&dRand, sizeof(float ) * dRand_length);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
curandCreateGenerator(&randGen, CURAND_RNG_PSEUDO_DEFAULT);
}
if (dRand_used == dRand_length) {
// if all random data generated have been traversed, we should generate a batch of new data
curandGenerateUniform(randGen, dRand, dRand_length); // the new data are in device memory
cudaMemcpy(hRand, dRand, sizeof(float ) * dRand_length, cudaMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
// nvcc -lcurand ReplaceRand.cu -o ReplaceRand
int main() {
for (int i = 0; i < 256; i++) {
float h = cuda_host_rand();
float d = cuda_device_rand();
printf("h = %.2f, d = %.2f\n", h, d);
}
return 0;
} | .file "tmpxft_00103bdf_00000000-6_ReplaceRand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2276:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2276:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14cuda_host_randv
.type _Z14cuda_host_randv, @function
_Z14cuda_host_randv:
.LFB2272:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cmpq $0, _ZZ14cuda_host_randvE5dRand(%rip)
je .L7
.L4:
cmpl $1000000, _ZZ14cuda_host_randvE10dRand_used(%rip)
je .L8
.L5:
movl _ZZ14cuda_host_randvE10dRand_used(%rip), %eax
leal 1(%rax), %edx
movl %edx, _ZZ14cuda_host_randvE10dRand_used(%rip)
cltq
movq _ZZ14cuda_host_randvE5hRand(%rip), %rdx
movss (%rdx,%rax,4), %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl $4000000, %esi
leaq _ZZ14cuda_host_randvE5dRand(%rip), %rdi
call cudaMalloc@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, _ZZ14cuda_host_randvE5hRand(%rip)
movl $100, %esi
leaq _ZZ14cuda_host_randvE7randGen(%rip), %rdi
call curandCreateGenerator@PLT
jmp .L4
.L8:
movl $1000000, %edx
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movq _ZZ14cuda_host_randvE7randGen(%rip), %rdi
call curandGenerateUniform@PLT
movl $2, %ecx
movl $4000000, %edx
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movq _ZZ14cuda_host_randvE5hRand(%rip), %rdi
call cudaMemcpy@PLT
movl $0, _ZZ14cuda_host_randvE10dRand_used(%rip)
jmp .L5
.cfi_endproc
.LFE2272:
.size _Z14cuda_host_randv, .-_Z14cuda_host_randv
.globl _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
.type _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW, @function
_Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW:
.LFB2298:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16initialize_stateP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2298:
.size _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW, .-_Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
.globl _Z16initialize_stateP17curandStateXORWOW
.type _Z16initialize_stateP17curandStateXORWOW, @function
_Z16initialize_stateP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _Z16initialize_stateP17curandStateXORWOW, .-_Z16initialize_stateP17curandStateXORWOW
.globl _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
.type _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW, @function
_Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW:
.LFB2300:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14refill_randomsPfiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2300:
.size _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW, .-_Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
.globl _Z14refill_randomsPfiP17curandStateXORWOW
.type _Z14refill_randomsPfiP17curandStateXORWOW, @function
_Z14refill_randomsPfiP17curandStateXORWOW:
.LFB2301:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2301:
.size _Z14refill_randomsPfiP17curandStateXORWOW, .-_Z14refill_randomsPfiP17curandStateXORWOW
.globl _Z16cuda_device_randv
.type _Z16cuda_device_randv, @function
_Z16cuda_device_randv:
.LFB2271:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, _ZZ16cuda_device_randvE5dRand(%rip)
je .L31
.L26:
cmpl $1000000, _ZZ16cuda_device_randvE10dRand_used(%rip)
je .L32
.L28:
movl _ZZ16cuda_device_randvE10dRand_used(%rip), %eax
leal 1(%rax), %edx
movl %edx, _ZZ16cuda_device_randvE10dRand_used(%rip)
cltq
movq _ZZ16cuda_device_randvE5hRand(%rip), %rdx
movss (%rdx,%rax,4), %xmm0
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl $4000000, %esi
leaq _ZZ16cuda_device_randvE5dRand(%rip), %rdi
call cudaMalloc@PLT
movl $368640, %esi
leaq _ZZ16cuda_device_randvE6states(%rip), %rdi
call cudaMalloc@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, _ZZ16cuda_device_randvE5hRand(%rip)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $30, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movq _ZZ16cuda_device_randvE6states(%rip), %rdi
call _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
jmp .L26
.L32:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $30, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movl $2, %ecx
movl $4000000, %edx
movq _ZZ16cuda_device_randvE5dRand(%rip), %rsi
movq _ZZ16cuda_device_randvE5hRand(%rip), %rdi
call cudaMemcpy@PLT
movl $0, _ZZ16cuda_device_randvE10dRand_used(%rip)
jmp .L28
.L33:
movq _ZZ16cuda_device_randvE6states(%rip), %rdx
movl $1000000, %esi
movq _ZZ16cuda_device_randvE5dRand(%rip), %rdi
call _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
jmp .L29
.cfi_endproc
.LFE2271:
.size _Z16cuda_device_randv, .-_Z16cuda_device_randv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h = %.2f, d = %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2273:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movl $256, %ebx
leaq .LC0(%rip), %rbp
.L35:
call _Z14cuda_host_randv
movss %xmm0, 12(%rsp)
call _Z16cuda_device_randv
movaps %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
cvtss2sd %xmm1, %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
subl $1, %ebx
jne .L35
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z14refill_randomsPfiP17curandStateXORWOW"
.align 8
.LC2:
.string "_Z16initialize_stateP17curandStateXORWOW"
.section .rodata.str1.1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2303:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14refill_randomsPfiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16initialize_stateP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2303:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.data
.align 4
.type _ZZ14cuda_host_randvE10dRand_used, @object
.size _ZZ14cuda_host_randvE10dRand_used, 4
_ZZ14cuda_host_randvE10dRand_used:
.long 1000000
.local _ZZ14cuda_host_randvE5hRand
.comm _ZZ14cuda_host_randvE5hRand,8,8
.local _ZZ14cuda_host_randvE5dRand
.comm _ZZ14cuda_host_randvE5dRand,8,8
.local _ZZ14cuda_host_randvE7randGen
.comm _ZZ14cuda_host_randvE7randGen,8,8
.align 4
.type _ZZ16cuda_device_randvE10dRand_used, @object
.size _ZZ16cuda_device_randvE10dRand_used, 4
_ZZ16cuda_device_randvE10dRand_used:
.long 1000000
.local _ZZ16cuda_device_randvE5hRand
.comm _ZZ16cuda_device_randvE5hRand,8,8
.local _ZZ16cuda_device_randvE5dRand
.comm _ZZ16cuda_device_randvE5dRand,8,8
.local _ZZ16cuda_device_randvE6states
.comm _ZZ16cuda_device_randvE6states,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by root on 2020/11/24.
//
#include "curand_kernel.h"
#include "cuda_runtime.h"
#include "stdio.h"
__global__ void initialize_state(curandState* states) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// init curand state for each thread
curand_init(9444, tid, 0, states + tid);
}
__global__ void refill_randoms(float *dRand, int N, curandState* states) {
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int nthreads = gridDim.x * blockDim.x;
curandState *state = states + tid;
for (int i = tid; i < N; i += nthreads) {
dRand[i] = curand_uniform(state);
// generate random number following uniform distribution for each thread
// the number of random numbers is N in total
}
}
float cuda_device_rand() {
// use device api to generate random numbers
static curandState *states = NULL;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
int block = 256;
int grid = 30;
if (dRand == NULL) {
// if dRand is null, then allocate memory and initialize states
cudaMalloc(&dRand, sizeof(float ) * dRand_length);
cudaMalloc(&states, sizeof(curandState) * block * grid);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
initialize_state<<<grid, block>>>(states);
}
if (dRand_used == dRand_length) {
// if all random data have been traversed, we should generate a new batch of data
refill_randoms<<<grid, block>>>(dRand, dRand_length, states);
cudaMemcpy(hRand, dRand, sizeof(float ) * dRand_length, cudaMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
float cuda_host_rand() {
// generate random data with host api
static curandGenerator_t randGen;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
if (dRand == NULL) {
// if dRand is null, then allocate memory and create generator
cudaMalloc(&dRand, sizeof(float ) * dRand_length);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
curandCreateGenerator(&randGen, CURAND_RNG_PSEUDO_DEFAULT);
}
if (dRand_used == dRand_length) {
// if all random data generated have been traversed, we should generate a batch of new data
curandGenerateUniform(randGen, dRand, dRand_length); // the new data are in device memory
cudaMemcpy(hRand, dRand, sizeof(float ) * dRand_length, cudaMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
// nvcc -lcurand ReplaceRand.cu -o ReplaceRand
int main() {
for (int i = 0; i < 256; i++) {
float h = cuda_host_rand();
float d = cuda_device_rand();
printf("h = %.2f, d = %.2f\n", h, d);
}
return 0;
} | //
// Created by root on 2020/11/24.
//
#include "hiprand/hiprand_kernel.h"
#include "hip/hip_runtime.h"
#include "stdio.h"
__global__ void initialize_state(hiprandState* states) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// init curand state for each thread
hiprand_init(9444, tid, 0, states + tid);
}
__global__ void refill_randoms(float *dRand, int N, hiprandState* states) {
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int nthreads = gridDim.x * blockDim.x;
hiprandState *state = states + tid;
for (int i = tid; i < N; i += nthreads) {
dRand[i] = hiprand_uniform(state);
// generate random number following uniform distribution for each thread
// the number of random numbers is N in total
}
}
float cuda_device_rand() {
// use device api to generate random numbers
static hiprandState *states = NULL;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
int block = 256;
int grid = 30;
if (dRand == NULL) {
// if dRand is null, then allocate memory and initialize states
hipMalloc(&dRand, sizeof(float ) * dRand_length);
hipMalloc(&states, sizeof(hiprandState) * block * grid);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
initialize_state<<<grid, block>>>(states);
}
if (dRand_used == dRand_length) {
// if all random data have been traversed, we should generate a new batch of data
refill_randoms<<<grid, block>>>(dRand, dRand_length, states);
hipMemcpy(hRand, dRand, sizeof(float ) * dRand_length, hipMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
float cuda_host_rand() {
// generate random data with host api
static hiprandGenerator_t randGen;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
if (dRand == NULL) {
// if dRand is null, then allocate memory and create generator
hipMalloc(&dRand, sizeof(float ) * dRand_length);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
hiprandCreateGenerator(&randGen, HIPRAND_RNG_PSEUDO_DEFAULT);
}
if (dRand_used == dRand_length) {
// if all random data generated have been traversed, we should generate a batch of new data
hiprandGenerateUniform(randGen, dRand, dRand_length); // the new data are in device memory
hipMemcpy(hRand, dRand, sizeof(float ) * dRand_length, hipMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
// nvcc -lcurand ReplaceRand.cu -o ReplaceRand
int main() {
for (int i = 0; i < 256; i++) {
float h = cuda_host_rand();
float d = cuda_device_rand();
printf("h = %.2f, d = %.2f\n", h, d);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by root on 2020/11/24.
//
#include "hiprand/hiprand_kernel.h"
#include "hip/hip_runtime.h"
#include "stdio.h"
__global__ void initialize_state(hiprandState* states) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// init curand state for each thread
hiprand_init(9444, tid, 0, states + tid);
}
__global__ void refill_randoms(float *dRand, int N, hiprandState* states) {
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int nthreads = gridDim.x * blockDim.x;
hiprandState *state = states + tid;
for (int i = tid; i < N; i += nthreads) {
dRand[i] = hiprand_uniform(state);
// generate random number following uniform distribution for each thread
// the number of random numbers is N in total
}
}
float cuda_device_rand() {
// use device api to generate random numbers
static hiprandState *states = NULL;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
int block = 256;
int grid = 30;
if (dRand == NULL) {
// if dRand is null, then allocate memory and initialize states
hipMalloc(&dRand, sizeof(float ) * dRand_length);
hipMalloc(&states, sizeof(hiprandState) * block * grid);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
initialize_state<<<grid, block>>>(states);
}
if (dRand_used == dRand_length) {
// if all random data have been traversed, we should generate a new batch of data
refill_randoms<<<grid, block>>>(dRand, dRand_length, states);
hipMemcpy(hRand, dRand, sizeof(float ) * dRand_length, hipMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
float cuda_host_rand() {
// generate random data with host api
static hiprandGenerator_t randGen;
static float *dRand = NULL, *hRand = NULL;
static int dRand_length = 1000000, dRand_used = 1000000;
if (dRand == NULL) {
// if dRand is null, then allocate memory and create generator
hipMalloc(&dRand, sizeof(float ) * dRand_length);
hRand = (float *) malloc(sizeof(float ) * dRand_length);
hiprandCreateGenerator(&randGen, HIPRAND_RNG_PSEUDO_DEFAULT);
}
if (dRand_used == dRand_length) {
// if all random data generated have been traversed, we should generate a batch of new data
hiprandGenerateUniform(randGen, dRand, dRand_length); // the new data are in device memory
hipMemcpy(hRand, dRand, sizeof(float ) * dRand_length, hipMemcpyDeviceToHost);
dRand_used = 0;
}
return hRand[dRand_used++];
}
// nvcc -lcurand ReplaceRand.cu -o ReplaceRand
int main() {
for (int i = 0; i < 256; i++) {
float h = cuda_host_rand();
float d = cuda_device_rand();
printf("h = %.2f, d = %.2f\n", h, d);
}
return 0;
} | .text
.file "ReplaceRand.hip"
.globl _Z31__device_stub__initialize_stateP12hiprandState # -- Begin function _Z31__device_stub__initialize_stateP12hiprandState
.p2align 4, 0x90
.type _Z31__device_stub__initialize_stateP12hiprandState,@function
_Z31__device_stub__initialize_stateP12hiprandState: # @_Z31__device_stub__initialize_stateP12hiprandState
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16initialize_stateP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z31__device_stub__initialize_stateP12hiprandState, .Lfunc_end0-_Z31__device_stub__initialize_stateP12hiprandState
.cfi_endproc
# -- End function
.globl _Z29__device_stub__refill_randomsPfiP12hiprandState # -- Begin function _Z29__device_stub__refill_randomsPfiP12hiprandState
.p2align 4, 0x90
.type _Z29__device_stub__refill_randomsPfiP12hiprandState,@function
_Z29__device_stub__refill_randomsPfiP12hiprandState: # @_Z29__device_stub__refill_randomsPfiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14refill_randomsPfiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__refill_randomsPfiP12hiprandState, .Lfunc_end1-_Z29__device_stub__refill_randomsPfiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z16cuda_device_randv # -- Begin function _Z16cuda_device_randv
.p2align 4, 0x90
.type _Z16cuda_device_randv,@function
_Z16cuda_device_randv: # @_Z16cuda_device_randv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
cmpq $0, _ZZ16cuda_device_randvE5dRand(%rip)
jne .LBB2_3
# %bb.1:
movl $_ZZ16cuda_device_randvE5dRand, %edi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movl $_ZZ16cuda_device_randvE6states, %edi
movl $368640, %esi # imm = 0x5A000
callq hipMalloc
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, _ZZ16cuda_device_randvE5hRand(%rip)
movabsq $4294967326, %rdi # imm = 0x10000001E
leaq 226(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_2
.LBB2_3:
cmpl $1000000, _ZZ16cuda_device_randvE10dRand_used(%rip) # imm = 0xF4240
jne .LBB2_7
.LBB2_4:
movabsq $4294967326, %rdi # imm = 0x10000001E
leaq 226(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq _ZZ16cuda_device_randvE5dRand(%rip), %rax
movq _ZZ16cuda_device_randvE6states(%rip), %rcx
movq %rax, 32(%rsp)
movl $1000000, 44(%rsp) # imm = 0xF4240
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14refill_randomsPfiP12hiprandState, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq _ZZ16cuda_device_randvE5hRand(%rip), %rdi
movq _ZZ16cuda_device_randvE5dRand(%rip), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
movl $0, _ZZ16cuda_device_randvE10dRand_used(%rip)
.LBB2_7:
movq _ZZ16cuda_device_randvE5hRand(%rip), %rax
movslq _ZZ16cuda_device_randvE10dRand_used(%rip), %rcx
leal 1(%rcx), %edx
movl %edx, _ZZ16cuda_device_randvE10dRand_used(%rip)
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 112
movq _ZZ16cuda_device_randvE6states(%rip), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z16initialize_stateP12hiprandState, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $1000000, _ZZ16cuda_device_randvE10dRand_used(%rip) # imm = 0xF4240
je .LBB2_4
jmp .LBB2_7
.Lfunc_end2:
.size _Z16cuda_device_randv, .Lfunc_end2-_Z16cuda_device_randv
.cfi_endproc
# -- End function
.globl _Z14cuda_host_randv # -- Begin function _Z14cuda_host_randv
.p2align 4, 0x90
.type _Z14cuda_host_randv,@function
_Z14cuda_host_randv: # @_Z14cuda_host_randv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, _ZZ14cuda_host_randvE5dRand(%rip)
je .LBB3_1
# %bb.2:
cmpl $1000000, _ZZ14cuda_host_randvE10dRand_used(%rip) # imm = 0xF4240
jne .LBB3_4
.LBB3_3:
movq _ZZ14cuda_host_randvE7randGen(%rip), %rdi
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movl $1000000, %edx # imm = 0xF4240
callq hiprandGenerateUniform
movq _ZZ14cuda_host_randvE5hRand(%rip), %rdi
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
movl $0, _ZZ14cuda_host_randvE10dRand_used(%rip)
.LBB3_4:
movq _ZZ14cuda_host_randvE5hRand(%rip), %rax
movslq _ZZ14cuda_host_randvE10dRand_used(%rip), %rcx
leal 1(%rcx), %edx
movl %edx, _ZZ14cuda_host_randvE10dRand_used(%rip)
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 16
movl $_ZZ14cuda_host_randvE5dRand, %edi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, _ZZ14cuda_host_randvE5hRand(%rip)
movl $_ZZ14cuda_host_randvE7randGen, %edi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
cmpl $1000000, _ZZ14cuda_host_randvE10dRand_used(%rip) # imm = 0xF4240
je .LBB3_3
jmp .LBB3_4
.Lfunc_end3:
.size _Z14cuda_host_randv, .Lfunc_end3-_Z14cuda_host_randv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl $256, %ebx # imm = 0x100
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
callq _Z14cuda_host_randv
movss %xmm0, 12(%rsp) # 4-byte Spill
callq _Z16cuda_device_randv
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str, %edi
movaps %xmm2, %xmm0
movb $2, %al
callq printf
decl %ebx
jne .LBB4_1
# %bb.2:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16initialize_stateP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14refill_randomsPfiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16initialize_stateP12hiprandState,@object # @_Z16initialize_stateP12hiprandState
.section .rodata,"a",@progbits
.globl _Z16initialize_stateP12hiprandState
.p2align 3, 0x0
_Z16initialize_stateP12hiprandState:
.quad _Z31__device_stub__initialize_stateP12hiprandState
.size _Z16initialize_stateP12hiprandState, 8
.type _Z14refill_randomsPfiP12hiprandState,@object # @_Z14refill_randomsPfiP12hiprandState
.globl _Z14refill_randomsPfiP12hiprandState
.p2align 3, 0x0
_Z14refill_randomsPfiP12hiprandState:
.quad _Z29__device_stub__refill_randomsPfiP12hiprandState
.size _Z14refill_randomsPfiP12hiprandState, 8
.type _ZZ16cuda_device_randvE6states,@object # @_ZZ16cuda_device_randvE6states
.local _ZZ16cuda_device_randvE6states
.comm _ZZ16cuda_device_randvE6states,8,8
.type _ZZ16cuda_device_randvE5dRand,@object # @_ZZ16cuda_device_randvE5dRand
.local _ZZ16cuda_device_randvE5dRand
.comm _ZZ16cuda_device_randvE5dRand,8,8
.type _ZZ16cuda_device_randvE5hRand,@object # @_ZZ16cuda_device_randvE5hRand
.local _ZZ16cuda_device_randvE5hRand
.comm _ZZ16cuda_device_randvE5hRand,8,8
.type _ZZ16cuda_device_randvE10dRand_used,@object # @_ZZ16cuda_device_randvE10dRand_used
.data
.p2align 2, 0x0
_ZZ16cuda_device_randvE10dRand_used:
.long 1000000 # 0xf4240
.size _ZZ16cuda_device_randvE10dRand_used, 4
.type _ZZ14cuda_host_randvE7randGen,@object # @_ZZ14cuda_host_randvE7randGen
.local _ZZ14cuda_host_randvE7randGen
.comm _ZZ14cuda_host_randvE7randGen,8,8
.type _ZZ14cuda_host_randvE5dRand,@object # @_ZZ14cuda_host_randvE5dRand
.local _ZZ14cuda_host_randvE5dRand
.comm _ZZ14cuda_host_randvE5dRand,8,8
.type _ZZ14cuda_host_randvE5hRand,@object # @_ZZ14cuda_host_randvE5hRand
.local _ZZ14cuda_host_randvE5hRand
.comm _ZZ14cuda_host_randvE5hRand,8,8
.type _ZZ14cuda_host_randvE10dRand_used,@object # @_ZZ14cuda_host_randvE10dRand_used
.p2align 2, 0x0
_ZZ14cuda_host_randvE10dRand_used:
.long 1000000 # 0xf4240
.size _ZZ14cuda_host_randvE10dRand_used, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h = %.2f, d = %.2f\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16initialize_stateP12hiprandState"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14refill_randomsPfiP12hiprandState"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__initialize_stateP12hiprandState
.addrsig_sym _Z29__device_stub__refill_randomsPfiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16initialize_stateP12hiprandState
.addrsig_sym _Z14refill_randomsPfiP12hiprandState
.addrsig_sym _ZZ16cuda_device_randvE6states
.addrsig_sym _ZZ16cuda_device_randvE5dRand
.addrsig_sym _ZZ14cuda_host_randvE7randGen
.addrsig_sym _ZZ14cuda_host_randvE5dRand
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00103bdf_00000000-6_ReplaceRand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2276:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2276:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14cuda_host_randv
.type _Z14cuda_host_randv, @function
_Z14cuda_host_randv:
.LFB2272:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cmpq $0, _ZZ14cuda_host_randvE5dRand(%rip)
je .L7
.L4:
cmpl $1000000, _ZZ14cuda_host_randvE10dRand_used(%rip)
je .L8
.L5:
movl _ZZ14cuda_host_randvE10dRand_used(%rip), %eax
leal 1(%rax), %edx
movl %edx, _ZZ14cuda_host_randvE10dRand_used(%rip)
cltq
movq _ZZ14cuda_host_randvE5hRand(%rip), %rdx
movss (%rdx,%rax,4), %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl $4000000, %esi
leaq _ZZ14cuda_host_randvE5dRand(%rip), %rdi
call cudaMalloc@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, _ZZ14cuda_host_randvE5hRand(%rip)
movl $100, %esi
leaq _ZZ14cuda_host_randvE7randGen(%rip), %rdi
call curandCreateGenerator@PLT
jmp .L4
.L8:
movl $1000000, %edx
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movq _ZZ14cuda_host_randvE7randGen(%rip), %rdi
call curandGenerateUniform@PLT
movl $2, %ecx
movl $4000000, %edx
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movq _ZZ14cuda_host_randvE5hRand(%rip), %rdi
call cudaMemcpy@PLT
movl $0, _ZZ14cuda_host_randvE10dRand_used(%rip)
jmp .L5
.cfi_endproc
.LFE2272:
.size _Z14cuda_host_randv, .-_Z14cuda_host_randv
.globl _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
.type _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW, @function
_Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW:
.LFB2298:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16initialize_stateP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2298:
.size _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW, .-_Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
.globl _Z16initialize_stateP17curandStateXORWOW
.type _Z16initialize_stateP17curandStateXORWOW, @function
_Z16initialize_stateP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _Z16initialize_stateP17curandStateXORWOW, .-_Z16initialize_stateP17curandStateXORWOW
.globl _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
.type _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW, @function
_Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW:
.LFB2300:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14refill_randomsPfiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2300:
.size _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW, .-_Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
.globl _Z14refill_randomsPfiP17curandStateXORWOW
.type _Z14refill_randomsPfiP17curandStateXORWOW, @function
_Z14refill_randomsPfiP17curandStateXORWOW:
.LFB2301:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2301:
.size _Z14refill_randomsPfiP17curandStateXORWOW, .-_Z14refill_randomsPfiP17curandStateXORWOW
.globl _Z16cuda_device_randv
.type _Z16cuda_device_randv, @function
_Z16cuda_device_randv:
.LFB2271:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, _ZZ16cuda_device_randvE5dRand(%rip)
je .L31
.L26:
cmpl $1000000, _ZZ16cuda_device_randvE10dRand_used(%rip)
je .L32
.L28:
movl _ZZ16cuda_device_randvE10dRand_used(%rip), %eax
leal 1(%rax), %edx
movl %edx, _ZZ16cuda_device_randvE10dRand_used(%rip)
cltq
movq _ZZ16cuda_device_randvE5hRand(%rip), %rdx
movss (%rdx,%rax,4), %xmm0
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl $4000000, %esi
leaq _ZZ16cuda_device_randvE5dRand(%rip), %rdi
call cudaMalloc@PLT
movl $368640, %esi
leaq _ZZ16cuda_device_randvE6states(%rip), %rdi
call cudaMalloc@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, _ZZ16cuda_device_randvE5hRand(%rip)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $30, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movq _ZZ16cuda_device_randvE6states(%rip), %rdi
call _Z54__device_stub__Z16initialize_stateP17curandStateXORWOWP17curandStateXORWOW
jmp .L26
.L32:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $30, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movl $2, %ecx
movl $4000000, %edx
movq _ZZ16cuda_device_randvE5dRand(%rip), %rsi
movq _ZZ16cuda_device_randvE5hRand(%rip), %rdi
call cudaMemcpy@PLT
movl $0, _ZZ16cuda_device_randvE10dRand_used(%rip)
jmp .L28
.L33:
movq _ZZ16cuda_device_randvE6states(%rip), %rdx
movl $1000000, %esi
movq _ZZ16cuda_device_randvE5dRand(%rip), %rdi
call _Z55__device_stub__Z14refill_randomsPfiP17curandStateXORWOWPfiP17curandStateXORWOW
jmp .L29
.cfi_endproc
.LFE2271:
.size _Z16cuda_device_randv, .-_Z16cuda_device_randv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h = %.2f, d = %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2273:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movl $256, %ebx
leaq .LC0(%rip), %rbp
.L35:
call _Z14cuda_host_randv
movss %xmm0, 12(%rsp)
call _Z16cuda_device_randv
movaps %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
cvtss2sd %xmm1, %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
subl $1, %ebx
jne .L35
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z14refill_randomsPfiP17curandStateXORWOW"
.align 8
.LC2:
.string "_Z16initialize_stateP17curandStateXORWOW"
.section .rodata.str1.1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2303:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14refill_randomsPfiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16initialize_stateP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2303:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.data
.align 4
.type _ZZ14cuda_host_randvE10dRand_used, @object
.size _ZZ14cuda_host_randvE10dRand_used, 4
_ZZ14cuda_host_randvE10dRand_used:
.long 1000000
.local _ZZ14cuda_host_randvE5hRand
.comm _ZZ14cuda_host_randvE5hRand,8,8
.local _ZZ14cuda_host_randvE5dRand
.comm _ZZ14cuda_host_randvE5dRand,8,8
.local _ZZ14cuda_host_randvE7randGen
.comm _ZZ14cuda_host_randvE7randGen,8,8
.align 4
.type _ZZ16cuda_device_randvE10dRand_used, @object
.size _ZZ16cuda_device_randvE10dRand_used, 4
_ZZ16cuda_device_randvE10dRand_used:
.long 1000000
.local _ZZ16cuda_device_randvE5hRand
.comm _ZZ16cuda_device_randvE5hRand,8,8
.local _ZZ16cuda_device_randvE5dRand
.comm _ZZ16cuda_device_randvE5dRand,8,8
.local _ZZ16cuda_device_randvE6states
.comm _ZZ16cuda_device_randvE6states,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ReplaceRand.hip"
.globl _Z31__device_stub__initialize_stateP12hiprandState # -- Begin function _Z31__device_stub__initialize_stateP12hiprandState
.p2align 4, 0x90
.type _Z31__device_stub__initialize_stateP12hiprandState,@function
_Z31__device_stub__initialize_stateP12hiprandState: # @_Z31__device_stub__initialize_stateP12hiprandState
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16initialize_stateP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z31__device_stub__initialize_stateP12hiprandState, .Lfunc_end0-_Z31__device_stub__initialize_stateP12hiprandState
.cfi_endproc
# -- End function
.globl _Z29__device_stub__refill_randomsPfiP12hiprandState # -- Begin function _Z29__device_stub__refill_randomsPfiP12hiprandState
.p2align 4, 0x90
.type _Z29__device_stub__refill_randomsPfiP12hiprandState,@function
_Z29__device_stub__refill_randomsPfiP12hiprandState: # @_Z29__device_stub__refill_randomsPfiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14refill_randomsPfiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__refill_randomsPfiP12hiprandState, .Lfunc_end1-_Z29__device_stub__refill_randomsPfiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z16cuda_device_randv # -- Begin function _Z16cuda_device_randv
.p2align 4, 0x90
.type _Z16cuda_device_randv,@function
_Z16cuda_device_randv: # @_Z16cuda_device_randv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
cmpq $0, _ZZ16cuda_device_randvE5dRand(%rip)
jne .LBB2_3
# %bb.1:
movl $_ZZ16cuda_device_randvE5dRand, %edi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movl $_ZZ16cuda_device_randvE6states, %edi
movl $368640, %esi # imm = 0x5A000
callq hipMalloc
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, _ZZ16cuda_device_randvE5hRand(%rip)
movabsq $4294967326, %rdi # imm = 0x10000001E
leaq 226(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_2
.LBB2_3:
cmpl $1000000, _ZZ16cuda_device_randvE10dRand_used(%rip) # imm = 0xF4240
jne .LBB2_7
.LBB2_4:
movabsq $4294967326, %rdi # imm = 0x10000001E
leaq 226(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq _ZZ16cuda_device_randvE5dRand(%rip), %rax
movq _ZZ16cuda_device_randvE6states(%rip), %rcx
movq %rax, 32(%rsp)
movl $1000000, 44(%rsp) # imm = 0xF4240
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rsp, %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14refill_randomsPfiP12hiprandState, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq _ZZ16cuda_device_randvE5hRand(%rip), %rdi
movq _ZZ16cuda_device_randvE5dRand(%rip), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
movl $0, _ZZ16cuda_device_randvE10dRand_used(%rip)
.LBB2_7:
movq _ZZ16cuda_device_randvE5hRand(%rip), %rax
movslq _ZZ16cuda_device_randvE10dRand_used(%rip), %rcx
leal 1(%rcx), %edx
movl %edx, _ZZ16cuda_device_randvE10dRand_used(%rip)
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 112
movq _ZZ16cuda_device_randvE6states(%rip), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z16initialize_stateP12hiprandState, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $1000000, _ZZ16cuda_device_randvE10dRand_used(%rip) # imm = 0xF4240
je .LBB2_4
jmp .LBB2_7
.Lfunc_end2:
.size _Z16cuda_device_randv, .Lfunc_end2-_Z16cuda_device_randv
.cfi_endproc
# -- End function
.globl _Z14cuda_host_randv # -- Begin function _Z14cuda_host_randv
.p2align 4, 0x90
.type _Z14cuda_host_randv,@function
_Z14cuda_host_randv: # @_Z14cuda_host_randv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, _ZZ14cuda_host_randvE5dRand(%rip)
je .LBB3_1
# %bb.2:
cmpl $1000000, _ZZ14cuda_host_randvE10dRand_used(%rip) # imm = 0xF4240
jne .LBB3_4
.LBB3_3:
movq _ZZ14cuda_host_randvE7randGen(%rip), %rdi
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movl $1000000, %edx # imm = 0xF4240
callq hiprandGenerateUniform
movq _ZZ14cuda_host_randvE5hRand(%rip), %rdi
movq _ZZ14cuda_host_randvE5dRand(%rip), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
movl $0, _ZZ14cuda_host_randvE10dRand_used(%rip)
.LBB3_4:
movq _ZZ14cuda_host_randvE5hRand(%rip), %rax
movslq _ZZ14cuda_host_randvE10dRand_used(%rip), %rcx
leal 1(%rcx), %edx
movl %edx, _ZZ14cuda_host_randvE10dRand_used(%rip)
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 16
movl $_ZZ14cuda_host_randvE5dRand, %edi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, _ZZ14cuda_host_randvE5hRand(%rip)
movl $_ZZ14cuda_host_randvE7randGen, %edi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
cmpl $1000000, _ZZ14cuda_host_randvE10dRand_used(%rip) # imm = 0xF4240
je .LBB3_3
jmp .LBB3_4
.Lfunc_end3:
.size _Z14cuda_host_randv, .Lfunc_end3-_Z14cuda_host_randv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl $256, %ebx # imm = 0x100
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
callq _Z14cuda_host_randv
movss %xmm0, 12(%rsp) # 4-byte Spill
callq _Z16cuda_device_randv
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str, %edi
movaps %xmm2, %xmm0
movb $2, %al
callq printf
decl %ebx
jne .LBB4_1
# %bb.2:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16initialize_stateP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14refill_randomsPfiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16initialize_stateP12hiprandState,@object # @_Z16initialize_stateP12hiprandState
.section .rodata,"a",@progbits
.globl _Z16initialize_stateP12hiprandState
.p2align 3, 0x0
_Z16initialize_stateP12hiprandState:
.quad _Z31__device_stub__initialize_stateP12hiprandState
.size _Z16initialize_stateP12hiprandState, 8
.type _Z14refill_randomsPfiP12hiprandState,@object # @_Z14refill_randomsPfiP12hiprandState
.globl _Z14refill_randomsPfiP12hiprandState
.p2align 3, 0x0
_Z14refill_randomsPfiP12hiprandState:
.quad _Z29__device_stub__refill_randomsPfiP12hiprandState
.size _Z14refill_randomsPfiP12hiprandState, 8
.type _ZZ16cuda_device_randvE6states,@object # @_ZZ16cuda_device_randvE6states
.local _ZZ16cuda_device_randvE6states
.comm _ZZ16cuda_device_randvE6states,8,8
.type _ZZ16cuda_device_randvE5dRand,@object # @_ZZ16cuda_device_randvE5dRand
.local _ZZ16cuda_device_randvE5dRand
.comm _ZZ16cuda_device_randvE5dRand,8,8
.type _ZZ16cuda_device_randvE5hRand,@object # @_ZZ16cuda_device_randvE5hRand
.local _ZZ16cuda_device_randvE5hRand
.comm _ZZ16cuda_device_randvE5hRand,8,8
.type _ZZ16cuda_device_randvE10dRand_used,@object # @_ZZ16cuda_device_randvE10dRand_used
.data
.p2align 2, 0x0
_ZZ16cuda_device_randvE10dRand_used:
.long 1000000 # 0xf4240
.size _ZZ16cuda_device_randvE10dRand_used, 4
.type _ZZ14cuda_host_randvE7randGen,@object # @_ZZ14cuda_host_randvE7randGen
.local _ZZ14cuda_host_randvE7randGen
.comm _ZZ14cuda_host_randvE7randGen,8,8
.type _ZZ14cuda_host_randvE5dRand,@object # @_ZZ14cuda_host_randvE5dRand
.local _ZZ14cuda_host_randvE5dRand
.comm _ZZ14cuda_host_randvE5dRand,8,8
.type _ZZ14cuda_host_randvE5hRand,@object # @_ZZ14cuda_host_randvE5hRand
.local _ZZ14cuda_host_randvE5hRand
.comm _ZZ14cuda_host_randvE5hRand,8,8
.type _ZZ14cuda_host_randvE10dRand_used,@object # @_ZZ14cuda_host_randvE10dRand_used
.p2align 2, 0x0
_ZZ14cuda_host_randvE10dRand_used:
.long 1000000 # 0xf4240
.size _ZZ14cuda_host_randvE10dRand_used, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h = %.2f, d = %.2f\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16initialize_stateP12hiprandState"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14refill_randomsPfiP12hiprandState"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__initialize_stateP12hiprandState
.addrsig_sym _Z29__device_stub__refill_randomsPfiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16initialize_stateP12hiprandState
.addrsig_sym _Z14refill_randomsPfiP12hiprandState
.addrsig_sym _ZZ16cuda_device_randvE6states
.addrsig_sym _ZZ16cuda_device_randvE5dRand
.addrsig_sym _ZZ14cuda_host_randvE7randGen
.addrsig_sym _ZZ14cuda_host_randvE5dRand
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
__global__ void Array_add(int *a,int *b,int *c,int *n)
{
unsigned short tid=threadIdx.x;
if(tid<*n)
c[tid]=a[tid]+b[tid];
}
int main()
{
int n=5,i;
//printf("Enter N:");
//scanf("%d",&n);
int a[n],b[n],c[n];
int *cuda_a,*cuda_b,*cuda_c,*cuda_n;
for(i=0;i<n;i++)
a[i]=rand()%100;
for(i=0;i<n;i++)
b[i]=rand()%100;
cudaMalloc((void**)&cuda_a,n*sizeof(int));
cudaMalloc((void**)&cuda_b,n*sizeof(int));
cudaMalloc((void**)&cuda_c,n*sizeof(int));
cudaMalloc((void**)&cuda_n,sizeof(int));
cudaMemcpy(cuda_a,a,n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cuda_b,b,n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cuda_n,&n,sizeof(int),cudaMemcpyHostToDevice);
Array_add <<<1,n>>>(cuda_a,cuda_b,cuda_c,cuda_n);
cudaMemcpy(c,cuda_c,n*sizeof(int),cudaMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d + %d = %d\n",a[i],b[i],c[i]);
cudaFree(cuda_a);
cudaFree(cuda_b);
cudaFree(cuda_c);
cudaFree(cuda_n);
return 0;
} | code for sm_80
Function : _Z9Array_addPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0060*/ LOP3.LUT R6, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06067812 */
/* 0x001fc800078ec0ff */
/*0070*/ ISETP.GE.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x004fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*00b0*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00f0*/ IMAD.IADD R9, R4, 0x1, R3 ; /* 0x0000000104097824 */
/* 0x004fca00078e0203 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
__global__ void Array_add(int *a,int *b,int *c,int *n)
{
unsigned short tid=threadIdx.x;
if(tid<*n)
c[tid]=a[tid]+b[tid];
}
int main()
{
int n=5,i;
//printf("Enter N:");
//scanf("%d",&n);
int a[n],b[n],c[n];
int *cuda_a,*cuda_b,*cuda_c,*cuda_n;
for(i=0;i<n;i++)
a[i]=rand()%100;
for(i=0;i<n;i++)
b[i]=rand()%100;
cudaMalloc((void**)&cuda_a,n*sizeof(int));
cudaMalloc((void**)&cuda_b,n*sizeof(int));
cudaMalloc((void**)&cuda_c,n*sizeof(int));
cudaMalloc((void**)&cuda_n,sizeof(int));
cudaMemcpy(cuda_a,a,n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cuda_b,b,n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cuda_n,&n,sizeof(int),cudaMemcpyHostToDevice);
Array_add <<<1,n>>>(cuda_a,cuda_b,cuda_c,cuda_n);
cudaMemcpy(c,cuda_c,n*sizeof(int),cudaMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d + %d = %d\n",a[i],b[i],c[i]);
cudaFree(cuda_a);
cudaFree(cuda_b);
cudaFree(cuda_c);
cudaFree(cuda_n);
return 0;
} | .file "tmpxft_001b1433_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
.type _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_, @function
_Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9Array_addPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_, .-_Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
.globl _Z9Array_addPiS_S_S_
.type _Z9Array_addPiS_S_S_, @function
_Z9Array_addPiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9Array_addPiS_S_S_, .-_Z9Array_addPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $5, 4(%rsp)
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 64(%rsp,%rbx,4)
movl 4(%rsp), %esi
addq $1, %rbx
cmpl %ebx, %esi
jg .L12
testl %esi, %esi
jle .L13
movl $0, %ebx
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 96(%rsp,%rbx,4)
movl 4(%rsp), %esi
addq $1, %rbx
cmpl %ebx, %esi
jg .L14
.L13:
movslq %esi, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
leaq 96(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movslq 4(%rsp), %rdx
salq $2, %rdx
leaq 128(%rsp), %rdi
movl $2, %ecx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 4(%rsp)
jle .L16
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L17:
movl 96(%rsp,%rbx,4), %ecx
movl 64(%rsp,%rbx,4), %edx
movl 128(%rsp,%rbx,4), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L17
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9Array_addPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9Array_addPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
__global__ void Array_add(int *a,int *b,int *c,int *n)
{
unsigned short tid=threadIdx.x;
if(tid<*n)
c[tid]=a[tid]+b[tid];
}
int main()
{
int n=5,i;
//printf("Enter N:");
//scanf("%d",&n);
int a[n],b[n],c[n];
int *cuda_a,*cuda_b,*cuda_c,*cuda_n;
for(i=0;i<n;i++)
a[i]=rand()%100;
for(i=0;i<n;i++)
b[i]=rand()%100;
cudaMalloc((void**)&cuda_a,n*sizeof(int));
cudaMalloc((void**)&cuda_b,n*sizeof(int));
cudaMalloc((void**)&cuda_c,n*sizeof(int));
cudaMalloc((void**)&cuda_n,sizeof(int));
cudaMemcpy(cuda_a,a,n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cuda_b,b,n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cuda_n,&n,sizeof(int),cudaMemcpyHostToDevice);
Array_add <<<1,n>>>(cuda_a,cuda_b,cuda_c,cuda_n);
cudaMemcpy(c,cuda_c,n*sizeof(int),cudaMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d + %d = %d\n",a[i],b[i],c[i]);
cudaFree(cuda_a);
cudaFree(cuda_b);
cudaFree(cuda_c);
cudaFree(cuda_n);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void Array_add(int *a,int *b,int *c,int *n)
{
unsigned short tid=threadIdx.x;
if(tid<*n)
c[tid]=a[tid]+b[tid];
}
int main()
{
int n=5,i;
//printf("Enter N:");
//scanf("%d",&n);
int a[n],b[n],c[n];
int *cuda_a,*cuda_b,*cuda_c,*cuda_n;
for(i=0;i<n;i++)
a[i]=rand()%100;
for(i=0;i<n;i++)
b[i]=rand()%100;
hipMalloc((void**)&cuda_a,n*sizeof(int));
hipMalloc((void**)&cuda_b,n*sizeof(int));
hipMalloc((void**)&cuda_c,n*sizeof(int));
hipMalloc((void**)&cuda_n,sizeof(int));
hipMemcpy(cuda_a,a,n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cuda_b,b,n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cuda_n,&n,sizeof(int),hipMemcpyHostToDevice);
Array_add <<<1,n>>>(cuda_a,cuda_b,cuda_c,cuda_n);
hipMemcpy(c,cuda_c,n*sizeof(int),hipMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d + %d = %d\n",a[i],b[i],c[i]);
hipFree(cuda_a);
hipFree(cuda_b);
hipFree(cuda_c);
hipFree(cuda_n);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void Array_add(int *a,int *b,int *c,int *n)
{
unsigned short tid=threadIdx.x;
if(tid<*n)
c[tid]=a[tid]+b[tid];
}
int main()
{
int n=5,i;
//printf("Enter N:");
//scanf("%d",&n);
int a[n],b[n],c[n];
int *cuda_a,*cuda_b,*cuda_c,*cuda_n;
for(i=0;i<n;i++)
a[i]=rand()%100;
for(i=0;i<n;i++)
b[i]=rand()%100;
hipMalloc((void**)&cuda_a,n*sizeof(int));
hipMalloc((void**)&cuda_b,n*sizeof(int));
hipMalloc((void**)&cuda_c,n*sizeof(int));
hipMalloc((void**)&cuda_n,sizeof(int));
hipMemcpy(cuda_a,a,n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cuda_b,b,n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cuda_n,&n,sizeof(int),hipMemcpyHostToDevice);
Array_add <<<1,n>>>(cuda_a,cuda_b,cuda_c,cuda_n);
hipMemcpy(c,cuda_c,n*sizeof(int),hipMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d + %d = %d\n",a[i],b[i],c[i]);
hipFree(cuda_a);
hipFree(cuda_b);
hipFree(cuda_c);
hipFree(cuda_n);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9Array_addPiS_S_S_
.globl _Z9Array_addPiS_S_S_
.p2align 8
.type _Z9Array_addPiS_S_S_,@function
_Z9Array_addPiS_S_S_:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9Array_addPiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9Array_addPiS_S_S_, .Lfunc_end0-_Z9Array_addPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9Array_addPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9Array_addPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void Array_add(int *a,int *b,int *c,int *n)
{
unsigned short tid=threadIdx.x;
if(tid<*n)
c[tid]=a[tid]+b[tid];
}
int main()
{
int n=5,i;
//printf("Enter N:");
//scanf("%d",&n);
int a[n],b[n],c[n];
int *cuda_a,*cuda_b,*cuda_c,*cuda_n;
for(i=0;i<n;i++)
a[i]=rand()%100;
for(i=0;i<n;i++)
b[i]=rand()%100;
hipMalloc((void**)&cuda_a,n*sizeof(int));
hipMalloc((void**)&cuda_b,n*sizeof(int));
hipMalloc((void**)&cuda_c,n*sizeof(int));
hipMalloc((void**)&cuda_n,sizeof(int));
hipMemcpy(cuda_a,a,n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cuda_b,b,n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cuda_n,&n,sizeof(int),hipMemcpyHostToDevice);
Array_add <<<1,n>>>(cuda_a,cuda_b,cuda_c,cuda_n);
hipMemcpy(c,cuda_c,n*sizeof(int),hipMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d + %d = %d\n",a[i],b[i],c[i]);
hipFree(cuda_a);
hipFree(cuda_b);
hipFree(cuda_c);
hipFree(cuda_n);
return 0;
} | .text
.file "q2.hip"
.globl _Z24__device_stub__Array_addPiS_S_S_ # -- Begin function _Z24__device_stub__Array_addPiS_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__Array_addPiS_S_S_,@function
_Z24__device_stub__Array_addPiS_S_S_: # @_Z24__device_stub__Array_addPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9Array_addPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__Array_addPiS_S_S_, .Lfunc_end0-_Z24__device_stub__Array_addPiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $192, %rsp
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsp, %r15
movl $5, -36(%rbp)
movq %rsp, %rbx
addq $-32, %rbx
movq %rbx, %rsp
movq %rsp, %r14
addq $-32, %r14
movq %r14, %rsp
cmpl $0, -36(%rbp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, -224(%rbp,%r12,4)
incq %r12
movslq -36(%rbp), %rax
cmpq %rax, %r12
jl .LBB1_2
.LBB1_3: # %.preheader
movl -36(%rbp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph20.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph20
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
movslq -36(%rbp), %rax
cmpq %rax, %r12
jl .LBB1_5
.LBB1_6: # %._crit_edge
movslq %eax, %rsi
shlq $2, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
movslq -36(%rbp), %rsi
shlq $2, %rsi
leaq -64(%rbp), %rdi
callq hipMalloc
movslq -36(%rbp), %rsi
shlq $2, %rsi
leaq -56(%rbp), %rdi
callq hipMalloc
leaq -48(%rbp), %rdi
movl $4, %esi
callq hipMalloc
movq -72(%rbp), %rdi
movslq -36(%rbp), %rdx
shlq $2, %rdx
leaq -224(%rbp), %rsi
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movslq -36(%rbp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq -48(%rbp), %rdi
leaq -36(%rbp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl -36(%rbp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq -48(%rbp), %rsi
movq %rax, -152(%rbp)
movq %rcx, -144(%rbp)
movq %rdx, -136(%rbp)
movq %rsi, -128(%rbp)
leaq -152(%rbp), %rax
movq %rax, -192(%rbp)
leaq -144(%rbp), %rax
movq %rax, -184(%rbp)
leaq -136(%rbp), %rax
movq %rax, -176(%rbp)
leaq -128(%rbp), %rax
movq %rax, -168(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -192(%rbp), %r9
movl $_Z9Array_addPiS_S_S_, %edi
pushq -80(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_8:
movq -56(%rbp), %rsi
movslq -36(%rbp), %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, -36(%rbp)
jle .LBB1_11
# %bb.9: # %.lr.ph23.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_10: # %.lr.ph23
# =>This Inner Loop Header: Depth=1
movl -224(%rbp,%r12,4), %esi
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
movslq -36(%rbp), %rax
cmpq %rax, %r12
jl .LBB1_10
.LBB1_11: # %._crit_edge24
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq -48(%rbp), %rdi
callq hipFree
movq %r15, %rsp
xorl %eax, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9Array_addPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9Array_addPiS_S_S_,@object # @_Z9Array_addPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z9Array_addPiS_S_S_
.p2align 3, 0x0
_Z9Array_addPiS_S_S_:
.quad _Z24__device_stub__Array_addPiS_S_S_
.size _Z9Array_addPiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9Array_addPiS_S_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__Array_addPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9Array_addPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9Array_addPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0060*/ LOP3.LUT R6, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06067812 */
/* 0x001fc800078ec0ff */
/*0070*/ ISETP.GE.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x004fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*00b0*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00f0*/ IMAD.IADD R9, R4, 0x1, R3 ; /* 0x0000000104097824 */
/* 0x004fca00078e0203 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9Array_addPiS_S_S_
.globl _Z9Array_addPiS_S_S_
.p2align 8
.type _Z9Array_addPiS_S_S_,@function
_Z9Array_addPiS_S_S_:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9Array_addPiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9Array_addPiS_S_S_, .Lfunc_end0-_Z9Array_addPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9Array_addPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9Array_addPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b1433_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
.type _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_, @function
_Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9Array_addPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_, .-_Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
.globl _Z9Array_addPiS_S_S_
.type _Z9Array_addPiS_S_S_, @function
_Z9Array_addPiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9Array_addPiS_S_S_, .-_Z9Array_addPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $5, 4(%rsp)
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 64(%rsp,%rbx,4)
movl 4(%rsp), %esi
addq $1, %rbx
cmpl %ebx, %esi
jg .L12
testl %esi, %esi
jle .L13
movl $0, %ebx
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 96(%rsp,%rbx,4)
movl 4(%rsp), %esi
addq $1, %rbx
cmpl %ebx, %esi
jg .L14
.L13:
movslq %esi, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
leaq 96(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movslq 4(%rsp), %rdx
salq $2, %rdx
leaq 128(%rsp), %rdi
movl $2, %ecx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 4(%rsp)
jle .L16
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L17:
movl 96(%rsp,%rbx,4), %ecx
movl 64(%rsp,%rbx,4), %edx
movl 128(%rsp,%rbx,4), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L17
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z9Array_addPiS_S_S_PiS_S_S_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9Array_addPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9Array_addPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q2.hip"
.globl _Z24__device_stub__Array_addPiS_S_S_ # -- Begin function _Z24__device_stub__Array_addPiS_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__Array_addPiS_S_S_,@function
_Z24__device_stub__Array_addPiS_S_S_: # @_Z24__device_stub__Array_addPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9Array_addPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__Array_addPiS_S_S_, .Lfunc_end0-_Z24__device_stub__Array_addPiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $192, %rsp
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsp, %r15
movl $5, -36(%rbp)
movq %rsp, %rbx
addq $-32, %rbx
movq %rbx, %rsp
movq %rsp, %r14
addq $-32, %r14
movq %r14, %rsp
cmpl $0, -36(%rbp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, -224(%rbp,%r12,4)
incq %r12
movslq -36(%rbp), %rax
cmpq %rax, %r12
jl .LBB1_2
.LBB1_3: # %.preheader
movl -36(%rbp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph20.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph20
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
movslq -36(%rbp), %rax
cmpq %rax, %r12
jl .LBB1_5
.LBB1_6: # %._crit_edge
movslq %eax, %rsi
shlq $2, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
movslq -36(%rbp), %rsi
shlq $2, %rsi
leaq -64(%rbp), %rdi
callq hipMalloc
movslq -36(%rbp), %rsi
shlq $2, %rsi
leaq -56(%rbp), %rdi
callq hipMalloc
leaq -48(%rbp), %rdi
movl $4, %esi
callq hipMalloc
movq -72(%rbp), %rdi
movslq -36(%rbp), %rdx
shlq $2, %rdx
leaq -224(%rbp), %rsi
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movslq -36(%rbp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq -48(%rbp), %rdi
leaq -36(%rbp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl -36(%rbp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq -72(%rbp), %rax
movq -64(%rbp), %rcx
movq -56(%rbp), %rdx
movq -48(%rbp), %rsi
movq %rax, -152(%rbp)
movq %rcx, -144(%rbp)
movq %rdx, -136(%rbp)
movq %rsi, -128(%rbp)
leaq -152(%rbp), %rax
movq %rax, -192(%rbp)
leaq -144(%rbp), %rax
movq %rax, -184(%rbp)
leaq -136(%rbp), %rax
movq %rax, -176(%rbp)
leaq -128(%rbp), %rax
movq %rax, -168(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -192(%rbp), %r9
movl $_Z9Array_addPiS_S_S_, %edi
pushq -80(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_8:
movq -56(%rbp), %rsi
movslq -36(%rbp), %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, -36(%rbp)
jle .LBB1_11
# %bb.9: # %.lr.ph23.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_10: # %.lr.ph23
# =>This Inner Loop Header: Depth=1
movl -224(%rbp,%r12,4), %esi
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
movslq -36(%rbp), %rax
cmpq %rax, %r12
jl .LBB1_10
.LBB1_11: # %._crit_edge24
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq -48(%rbp), %rdi
callq hipFree
movq %r15, %rsp
xorl %eax, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9Array_addPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9Array_addPiS_S_S_,@object # @_Z9Array_addPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z9Array_addPiS_S_S_
.p2align 3, 0x0
_Z9Array_addPiS_S_S_:
.quad _Z24__device_stub__Array_addPiS_S_S_
.size _Z9Array_addPiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9Array_addPiS_S_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__Array_addPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9Array_addPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
__global__ void mallocTest()
{
size_t size = 123;
char* ptr = (char*)malloc(size);
memset(ptr, 0, size);
printf("Thread %d got pointer: %p\n", threadIdx.x, ptr);
free(ptr);
}
int main()
{
// Set a heap size of 128 megabytes. Note that this must
// be done before any kernel is launched.
cudaDeviceSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);
mallocTest<<<1, 5>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10mallocTestv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x7b ; /* 0x0000007bff047424 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R6, c[0x4][R0] ; /* 0x0100000000067b82 */
/* 0x0000620000000a00 */
/*0060*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R18, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff127624 */
/* 0x000fe400000e06ff */
/*0090*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fcc0000000000 */
/*00a0*/ MOV R3, 0x110 ; /* 0x0000011000037802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R20, 0x90 ; /* 0x0000009000147802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*00e0*/ IADD3 R20, P0, P1, -R20, R3, R8 ; /* 0x0000000314147210 */
/* 0x000fc8000791e108 */
/*00f0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0100*/ CALL.ABS.NOINC R6 ; /* 0x0000000006007343 */
/* 0x002fea0003c00000 */
/*0110*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0120*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0004 */
/*0130*/ MOV R8, 0x8 ; /* 0x0000000800087802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0005 */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0012 */
/*0170*/ ST.E.U8 [R16.64], RZ ; /* 0x000000ff10007985 */
/* 0x0003e2000c101124 */
/*0180*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000ea20000000a00 */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fc400078e00ff */
/*01a0*/ ST.E.U8 [R16.64+0x1], RZ ; /* 0x000001ff10007985 */
/* 0x0003e2000c101124 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fc600078e00ff */
/*01c0*/ ST.E.U8 [R16.64+0x2], RZ ; /* 0x000002ff10007985 */
/* 0x0003e8000c101124 */
/*01d0*/ ST.E.U8 [R16.64+0x3], RZ ; /* 0x000003ff10007985 */
/* 0x0003e8000c101124 */
/*01e0*/ ST.E.U8 [R16.64+0x4], RZ ; /* 0x000004ff10007985 */
/* 0x0003e8000c101124 */
/*01f0*/ ST.E.U8 [R16.64+0x5], RZ ; /* 0x000005ff10007985 */
/* 0x0003e8000c101124 */
/*0200*/ ST.E.U8 [R16.64+0x6], RZ ; /* 0x000006ff10007985 */
/* 0x0003e8000c101124 */
/*0210*/ ST.E.U8 [R16.64+0x7], RZ ; /* 0x000007ff10007985 */
/* 0x0003e8000c101124 */
/*0220*/ ST.E.U8 [R16.64+0x8], RZ ; /* 0x000008ff10007985 */
/* 0x0003e8000c101124 */
/*0230*/ ST.E.U8 [R16.64+0x9], RZ ; /* 0x000009ff10007985 */
/* 0x0003e8000c101124 */
/*0240*/ ST.E.U8 [R16.64+0xa], RZ ; /* 0x00000aff10007985 */
/* 0x0003e8000c101124 */
/*0250*/ ST.E.U8 [R16.64+0xb], RZ ; /* 0x00000bff10007985 */
/* 0x0003e8000c101124 */
/*0260*/ ST.E.U8 [R16.64+0xc], RZ ; /* 0x00000cff10007985 */
/* 0x0003e8000c101124 */
/*0270*/ ST.E.U8 [R16.64+0xd], RZ ; /* 0x00000dff10007985 */
/* 0x0003e8000c101124 */
/*0280*/ ST.E.U8 [R16.64+0xe], RZ ; /* 0x00000eff10007985 */
/* 0x0003e8000c101124 */
/*0290*/ ST.E.U8 [R16.64+0xf], RZ ; /* 0x00000fff10007985 */
/* 0x0003e8000c101124 */
/*02a0*/ ST.E.U8 [R16.64+0x10], RZ ; /* 0x000010ff10007985 */
/* 0x0003e8000c101124 */
/*02b0*/ ST.E.U8 [R16.64+0x11], RZ ; /* 0x000011ff10007985 */
/* 0x0003e8000c101124 */
/*02c0*/ ST.E.U8 [R16.64+0x12], RZ ; /* 0x000012ff10007985 */
/* 0x0003e8000c101124 */
/*02d0*/ ST.E.U8 [R16.64+0x13], RZ ; /* 0x000013ff10007985 */
/* 0x0003e8000c101124 */
/*02e0*/ ST.E.U8 [R16.64+0x14], RZ ; /* 0x000014ff10007985 */
/* 0x0003e8000c101124 */
/*02f0*/ ST.E.U8 [R16.64+0x15], RZ ; /* 0x000015ff10007985 */
/* 0x0003e8000c101124 */
/*0300*/ ST.E.U8 [R16.64+0x16], RZ ; /* 0x000016ff10007985 */
/* 0x0003e8000c101124 */
/*0310*/ ST.E.U8 [R16.64+0x17], RZ ; /* 0x000017ff10007985 */
/* 0x0003e8000c101124 */
/*0320*/ ST.E.U8 [R16.64+0x18], RZ ; /* 0x000018ff10007985 */
/* 0x0003e8000c101124 */
/*0330*/ ST.E.U8 [R16.64+0x19], RZ ; /* 0x000019ff10007985 */
/* 0x0003e8000c101124 */
/*0340*/ ST.E.U8 [R16.64+0x1a], RZ ; /* 0x00001aff10007985 */
/* 0x0003e8000c101124 */
/*0350*/ ST.E.U8 [R16.64+0x1b], RZ ; /* 0x00001bff10007985 */
/* 0x0003e8000c101124 */
/*0360*/ ST.E.U8 [R16.64+0x1c], RZ ; /* 0x00001cff10007985 */
/* 0x0003e8000c101124 */
/*0370*/ ST.E.U8 [R16.64+0x1d], RZ ; /* 0x00001dff10007985 */
/* 0x0003e8000c101124 */
/*0380*/ ST.E.U8 [R16.64+0x1e], RZ ; /* 0x00001eff10007985 */
/* 0x0003e8000c101124 */
/*0390*/ ST.E.U8 [R16.64+0x1f], RZ ; /* 0x00001fff10007985 */
/* 0x0003e8000c101124 */
/*03a0*/ ST.E.U8 [R16.64+0x20], RZ ; /* 0x000020ff10007985 */
/* 0x0003e8000c101124 */
/*03b0*/ ST.E.U8 [R16.64+0x21], RZ ; /* 0x000021ff10007985 */
/* 0x0003e8000c101124 */
/*03c0*/ ST.E.U8 [R16.64+0x22], RZ ; /* 0x000022ff10007985 */
/* 0x0003e8000c101124 */
/*03d0*/ ST.E.U8 [R16.64+0x23], RZ ; /* 0x000023ff10007985 */
/* 0x0003e8000c101124 */
/*03e0*/ ST.E.U8 [R16.64+0x24], RZ ; /* 0x000024ff10007985 */
/* 0x0003e8000c101124 */
/*03f0*/ ST.E.U8 [R16.64+0x25], RZ ; /* 0x000025ff10007985 */
/* 0x0003e8000c101124 */
/*0400*/ ST.E.U8 [R16.64+0x26], RZ ; /* 0x000026ff10007985 */
/* 0x0003e8000c101124 */
/*0410*/ ST.E.U8 [R16.64+0x27], RZ ; /* 0x000027ff10007985 */
/* 0x0003e8000c101124 */
/*0420*/ ST.E.U8 [R16.64+0x28], RZ ; /* 0x000028ff10007985 */
/* 0x0003e8000c101124 */
/*0430*/ ST.E.U8 [R16.64+0x29], RZ ; /* 0x000029ff10007985 */
/* 0x0003e8000c101124 */
/*0440*/ ST.E.U8 [R16.64+0x2a], RZ ; /* 0x00002aff10007985 */
/* 0x0003e8000c101124 */
/*0450*/ ST.E.U8 [R16.64+0x2b], RZ ; /* 0x00002bff10007985 */
/* 0x0003e8000c101124 */
/*0460*/ ST.E.U8 [R16.64+0x2c], RZ ; /* 0x00002cff10007985 */
/* 0x0003e8000c101124 */
/*0470*/ ST.E.U8 [R16.64+0x2d], RZ ; /* 0x00002dff10007985 */
/* 0x0003e8000c101124 */
/*0480*/ ST.E.U8 [R16.64+0x2e], RZ ; /* 0x00002eff10007985 */
/* 0x0003e8000c101124 */
/*0490*/ ST.E.U8 [R16.64+0x2f], RZ ; /* 0x00002fff10007985 */
/* 0x0003e8000c101124 */
/*04a0*/ ST.E.U8 [R16.64+0x30], RZ ; /* 0x000030ff10007985 */
/* 0x0003e8000c101124 */
/*04b0*/ ST.E.U8 [R16.64+0x31], RZ ; /* 0x000031ff10007985 */
/* 0x0003e8000c101124 */
/*04c0*/ ST.E.U8 [R16.64+0x32], RZ ; /* 0x000032ff10007985 */
/* 0x0003e8000c101124 */
/*04d0*/ ST.E.U8 [R16.64+0x33], RZ ; /* 0x000033ff10007985 */
/* 0x0003e8000c101124 */
/*04e0*/ ST.E.U8 [R16.64+0x34], RZ ; /* 0x000034ff10007985 */
/* 0x0003e8000c101124 */
/*04f0*/ ST.E.U8 [R16.64+0x35], RZ ; /* 0x000035ff10007985 */
/* 0x0003e8000c101124 */
/*0500*/ ST.E.U8 [R16.64+0x36], RZ ; /* 0x000036ff10007985 */
/* 0x0003e8000c101124 */
/*0510*/ ST.E.U8 [R16.64+0x37], RZ ; /* 0x000037ff10007985 */
/* 0x0003e8000c101124 */
/*0520*/ ST.E.U8 [R16.64+0x38], RZ ; /* 0x000038ff10007985 */
/* 0x0003e8000c101124 */
/*0530*/ ST.E.U8 [R16.64+0x39], RZ ; /* 0x000039ff10007985 */
/* 0x0003e8000c101124 */
/*0540*/ ST.E.U8 [R16.64+0x3a], RZ ; /* 0x00003aff10007985 */
/* 0x0003e8000c101124 */
/*0550*/ ST.E.U8 [R16.64+0x3b], RZ ; /* 0x00003bff10007985 */
/* 0x0003e8000c101124 */
/*0560*/ ST.E.U8 [R16.64+0x3c], RZ ; /* 0x00003cff10007985 */
/* 0x0003e8000c101124 */
/*0570*/ ST.E.U8 [R16.64+0x3d], RZ ; /* 0x00003dff10007985 */
/* 0x0003e8000c101124 */
/*0580*/ ST.E.U8 [R16.64+0x3e], RZ ; /* 0x00003eff10007985 */
/* 0x0003e8000c101124 */
/*0590*/ ST.E.U8 [R16.64+0x3f], RZ ; /* 0x00003fff10007985 */
/* 0x0003e8000c101124 */
/*05a0*/ ST.E.U8 [R16.64+0x40], RZ ; /* 0x000040ff10007985 */
/* 0x0003e8000c101124 */
/*05b0*/ ST.E.U8 [R16.64+0x41], RZ ; /* 0x000041ff10007985 */
/* 0x0003e8000c101124 */
/*05c0*/ ST.E.U8 [R16.64+0x42], RZ ; /* 0x000042ff10007985 */
/* 0x0003e8000c101124 */
/*05d0*/ ST.E.U8 [R16.64+0x43], RZ ; /* 0x000043ff10007985 */
/* 0x0003e8000c101124 */
/*05e0*/ ST.E.U8 [R16.64+0x44], RZ ; /* 0x000044ff10007985 */
/* 0x0003e8000c101124 */
/*05f0*/ ST.E.U8 [R16.64+0x45], RZ ; /* 0x000045ff10007985 */
/* 0x0003e8000c101124 */
/*0600*/ ST.E.U8 [R16.64+0x46], RZ ; /* 0x000046ff10007985 */
/* 0x0003e8000c101124 */
/*0610*/ ST.E.U8 [R16.64+0x47], RZ ; /* 0x000047ff10007985 */
/* 0x0003e8000c101124 */
/*0620*/ ST.E.U8 [R16.64+0x48], RZ ; /* 0x000048ff10007985 */
/* 0x0003e8000c101124 */
/*0630*/ ST.E.U8 [R16.64+0x49], RZ ; /* 0x000049ff10007985 */
/* 0x0003e8000c101124 */
/*0640*/ ST.E.U8 [R16.64+0x4a], RZ ; /* 0x00004aff10007985 */
/* 0x0003e8000c101124 */
/*0650*/ ST.E.U8 [R16.64+0x4b], RZ ; /* 0x00004bff10007985 */
/* 0x0003e8000c101124 */
/*0660*/ ST.E.U8 [R16.64+0x4c], RZ ; /* 0x00004cff10007985 */
/* 0x0003e8000c101124 */
/*0670*/ ST.E.U8 [R16.64+0x4d], RZ ; /* 0x00004dff10007985 */
/* 0x0003e8000c101124 */
/*0680*/ ST.E.U8 [R16.64+0x4e], RZ ; /* 0x00004eff10007985 */
/* 0x0003e8000c101124 */
/*0690*/ ST.E.U8 [R16.64+0x4f], RZ ; /* 0x00004fff10007985 */
/* 0x0003e8000c101124 */
/*06a0*/ ST.E.U8 [R16.64+0x50], RZ ; /* 0x000050ff10007985 */
/* 0x0003e8000c101124 */
/*06b0*/ ST.E.U8 [R16.64+0x51], RZ ; /* 0x000051ff10007985 */
/* 0x0003e8000c101124 */
/*06c0*/ ST.E.U8 [R16.64+0x52], RZ ; /* 0x000052ff10007985 */
/* 0x0003e8000c101124 */
/*06d0*/ ST.E.U8 [R16.64+0x53], RZ ; /* 0x000053ff10007985 */
/* 0x0003e8000c101124 */
/*06e0*/ ST.E.U8 [R16.64+0x54], RZ ; /* 0x000054ff10007985 */
/* 0x0003e8000c101124 */
/*06f0*/ ST.E.U8 [R16.64+0x55], RZ ; /* 0x000055ff10007985 */
/* 0x0003e8000c101124 */
/*0700*/ ST.E.U8 [R16.64+0x56], RZ ; /* 0x000056ff10007985 */
/* 0x0003e8000c101124 */
/*0710*/ ST.E.U8 [R16.64+0x57], RZ ; /* 0x000057ff10007985 */
/* 0x0003e8000c101124 */
/*0720*/ ST.E.U8 [R16.64+0x58], RZ ; /* 0x000058ff10007985 */
/* 0x0003e8000c101124 */
/*0730*/ ST.E.U8 [R16.64+0x59], RZ ; /* 0x000059ff10007985 */
/* 0x0003e8000c101124 */
/*0740*/ ST.E.U8 [R16.64+0x5a], RZ ; /* 0x00005aff10007985 */
/* 0x0003e8000c101124 */
/*0750*/ ST.E.U8 [R16.64+0x5b], RZ ; /* 0x00005bff10007985 */
/* 0x0003e8000c101124 */
/*0760*/ ST.E.U8 [R16.64+0x5c], RZ ; /* 0x00005cff10007985 */
/* 0x0003e8000c101124 */
/*0770*/ ST.E.U8 [R16.64+0x5d], RZ ; /* 0x00005dff10007985 */
/* 0x0003e8000c101124 */
/*0780*/ ST.E.U8 [R16.64+0x5e], RZ ; /* 0x00005eff10007985 */
/* 0x0003e8000c101124 */
/*0790*/ ST.E.U8 [R16.64+0x5f], RZ ; /* 0x00005fff10007985 */
/* 0x0003e8000c101124 */
/*07a0*/ ST.E.U8 [R16.64+0x60], RZ ; /* 0x000060ff10007985 */
/* 0x0003e8000c101124 */
/*07b0*/ ST.E.U8 [R16.64+0x61], RZ ; /* 0x000061ff10007985 */
/* 0x0003e8000c101124 */
/*07c0*/ ST.E.U8 [R16.64+0x62], RZ ; /* 0x000062ff10007985 */
/* 0x0003e8000c101124 */
/*07d0*/ ST.E.U8 [R16.64+0x63], RZ ; /* 0x000063ff10007985 */
/* 0x0003e8000c101124 */
/*07e0*/ ST.E.U8 [R16.64+0x64], RZ ; /* 0x000064ff10007985 */
/* 0x0003e8000c101124 */
/*07f0*/ ST.E.U8 [R16.64+0x65], RZ ; /* 0x000065ff10007985 */
/* 0x0003e8000c101124 */
/*0800*/ ST.E.U8 [R16.64+0x66], RZ ; /* 0x000066ff10007985 */
/* 0x0003e8000c101124 */
/*0810*/ ST.E.U8 [R16.64+0x67], RZ ; /* 0x000067ff10007985 */
/* 0x0003e8000c101124 */
/*0820*/ ST.E.U8 [R16.64+0x68], RZ ; /* 0x000068ff10007985 */
/* 0x0003e8000c101124 */
/*0830*/ ST.E.U8 [R16.64+0x69], RZ ; /* 0x000069ff10007985 */
/* 0x0003e8000c101124 */
/*0840*/ ST.E.U8 [R16.64+0x6a], RZ ; /* 0x00006aff10007985 */
/* 0x0003e8000c101124 */
/*0850*/ ST.E.U8 [R16.64+0x6b], RZ ; /* 0x00006bff10007985 */
/* 0x0003e8000c101124 */
/*0860*/ ST.E.U8 [R16.64+0x6c], RZ ; /* 0x00006cff10007985 */
/* 0x0003e8000c101124 */
/*0870*/ ST.E.U8 [R16.64+0x6d], RZ ; /* 0x00006dff10007985 */
/* 0x0003e8000c101124 */
/*0880*/ ST.E.U8 [R16.64+0x6e], RZ ; /* 0x00006eff10007985 */
/* 0x0003e8000c101124 */
/*0890*/ ST.E.U8 [R16.64+0x6f], RZ ; /* 0x00006fff10007985 */
/* 0x0003e8000c101124 */
/*08a0*/ ST.E.U8 [R16.64+0x70], RZ ; /* 0x000070ff10007985 */
/* 0x0003e8000c101124 */
/*08b0*/ ST.E.U8 [R16.64+0x71], RZ ; /* 0x000071ff10007985 */
/* 0x0003e8000c101124 */
/*08c0*/ ST.E.U8 [R16.64+0x72], RZ ; /* 0x000072ff10007985 */
/* 0x0003e8000c101124 */
/*08d0*/ ST.E.U8 [R16.64+0x73], RZ ; /* 0x000073ff10007985 */
/* 0x0003e8000c101124 */
/*08e0*/ ST.E.U8 [R16.64+0x74], RZ ; /* 0x000074ff10007985 */
/* 0x0003e8000c101124 */
/*08f0*/ ST.E.U8 [R16.64+0x75], RZ ; /* 0x000075ff10007985 */
/* 0x0003e8000c101124 */
/*0900*/ ST.E.U8 [R16.64+0x76], RZ ; /* 0x000076ff10007985 */
/* 0x0003e8000c101124 */
/*0910*/ ST.E.U8 [R16.64+0x77], RZ ; /* 0x000077ff10007985 */
/* 0x0003e8000c101124 */
/*0920*/ ST.E.U8 [R16.64+0x78], RZ ; /* 0x000078ff10007985 */
/* 0x0003e8000c101124 */
/*0930*/ ST.E.U8 [R16.64+0x79], RZ ; /* 0x000079ff10007985 */
/* 0x0003e8000c101124 */
/*0940*/ ST.E.U8 [R16.64+0x7a], RZ ; /* 0x00007aff10007985 */
/* 0x0003e8000c101124 */
/*0950*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0013e80000100800 */
/*0960*/ STL.64 [R1+0x8], R16 ; /* 0x0000081001007387 */
/* 0x0003e40000100a00 */
/*0970*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x004fe40000000000 */
/*0980*/ MOV R11, 0x9f0 ; /* 0x000009f0000b7802 */
/* 0x000fe40000000f00 */
/*0990*/ MOV R20, 0x970 ; /* 0x0000097000147802 */
/* 0x000fc40000000f00 */
/*09a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*09b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*09c0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*09d0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*09e0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*09f0*/ MOV R0, 0x10 ; /* 0x0000001000007802 */
/* 0x000fe20000000f00 */
/*0a00*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*0a10*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0011 */
/*0a20*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0a30*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x000fe40000000000 */
/*0a40*/ MOV R9, 0xab0 ; /* 0x00000ab000097802 */
/* 0x000fe40000000f00 */
/*0a50*/ MOV R20, 0xa30 ; /* 0x00000a3000147802 */
/* 0x000fe40000000f00 */
/*0a60*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0a70*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*0a80*/ IADD3 R20, P0, P1, -R20, R9, R6 ; /* 0x0000000914147210 */
/* 0x000fc8000791e106 */
/*0a90*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0aa0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0ab0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ac0*/ BRA 0xac0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
__global__ void mallocTest()
{
size_t size = 123;
char* ptr = (char*)malloc(size);
memset(ptr, 0, size);
printf("Thread %d got pointer: %p\n", threadIdx.x, ptr);
free(ptr);
}
int main()
{
// Set a heap size of 128 megabytes. Note that this must
// be done before any kernel is launched.
cudaDeviceSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);
mallocTest<<<1, 5>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00012fef_00000000-6_perthreadmalloc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10mallocTestvv
.type _Z29__device_stub__Z10mallocTestvv, @function
_Z29__device_stub__Z10mallocTestvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10mallocTestv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10mallocTestvv, .-_Z29__device_stub__Z10mallocTestvv
.globl _Z10mallocTestv
.type _Z10mallocTestv, @function
_Z10mallocTestv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10mallocTestvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10mallocTestv, .-_Z10mallocTestv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $134217728, %esi
movl $2, %edi
call cudaDeviceSetLimit@PLT
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10mallocTestvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10mallocTestv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mallocTestv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
__global__ void mallocTest()
{
size_t size = 123;
char* ptr = (char*)malloc(size);
memset(ptr, 0, size);
printf("Thread %d got pointer: %p\n", threadIdx.x, ptr);
free(ptr);
}
int main()
{
// Set a heap size of 128 megabytes. Note that this must
// be done before any kernel is launched.
cudaDeviceSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);
mallocTest<<<1, 5>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void mallocTest()
{
size_t size = 123;
char* ptr = (char*)malloc(size);
memset(ptr, 0, size);
printf("Thread %d got pointer: %p\n", threadIdx.x, ptr);
free(ptr);
}
int main()
{
// Set a heap size of 128 megabytes. Note that this must
// be done before any kernel is launched.
hipDeviceSetLimit(hipLimitMallocHeapSize, 128*1024*1024);
mallocTest<<<1, 5>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void mallocTest()
{
size_t size = 123;
char* ptr = (char*)malloc(size);
memset(ptr, 0, size);
printf("Thread %d got pointer: %p\n", threadIdx.x, ptr);
free(ptr);
}
int main()
{
// Set a heap size of 128 megabytes. Note that this must
// be done before any kernel is launched.
hipDeviceSetLimit(hipLimitMallocHeapSize, 128*1024*1024);
mallocTest<<<1, 5>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "perthreadmalloc.hip"
.globl _Z25__device_stub__mallocTestv # -- Begin function _Z25__device_stub__mallocTestv
.p2align 4, 0x90
.type _Z25__device_stub__mallocTestv,@function
_Z25__device_stub__mallocTestv: # @_Z25__device_stub__mallocTestv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10mallocTestv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__mallocTestv, .Lfunc_end0-_Z25__device_stub__mallocTestv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $134217728, %esi # imm = 0x8000000
movl $2, %edi
callq hipDeviceSetLimit
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10mallocTestv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mallocTestv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mallocTestv,@object # @_Z10mallocTestv
.section .rodata,"a",@progbits
.globl _Z10mallocTestv
.p2align 3, 0x0
_Z10mallocTestv:
.quad _Z25__device_stub__mallocTestv
.size _Z10mallocTestv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10mallocTestv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mallocTestv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mallocTestv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00012fef_00000000-6_perthreadmalloc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10mallocTestvv
.type _Z29__device_stub__Z10mallocTestvv, @function
_Z29__device_stub__Z10mallocTestvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10mallocTestv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10mallocTestvv, .-_Z29__device_stub__Z10mallocTestvv
.globl _Z10mallocTestv
.type _Z10mallocTestv, @function
_Z10mallocTestv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10mallocTestvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10mallocTestv, .-_Z10mallocTestv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $134217728, %esi
movl $2, %edi
call cudaDeviceSetLimit@PLT
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10mallocTestvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10mallocTestv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mallocTestv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "perthreadmalloc.hip"
.globl _Z25__device_stub__mallocTestv # -- Begin function _Z25__device_stub__mallocTestv
.p2align 4, 0x90
.type _Z25__device_stub__mallocTestv,@function
_Z25__device_stub__mallocTestv: # @_Z25__device_stub__mallocTestv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10mallocTestv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__mallocTestv, .Lfunc_end0-_Z25__device_stub__mallocTestv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $134217728, %esi # imm = 0x8000000
movl $2, %edi
callq hipDeviceSetLimit
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10mallocTestv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mallocTestv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mallocTestv,@object # @_Z10mallocTestv
.section .rodata,"a",@progbits
.globl _Z10mallocTestv
.p2align 3, 0x0
_Z10mallocTestv:
.quad _Z25__device_stub__mallocTestv
.size _Z10mallocTestv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10mallocTestv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mallocTestv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mallocTestv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cudaSBilinearTF_Forward_kernel( unsigned int outputWidth, unsigned int outputHeight, unsigned int nbChannels, unsigned int batchSize, unsigned int inputWidth, unsigned int inputHeight, const unsigned int* yLowIdx, const unsigned int* yHighIdx, const float* yInter, const unsigned int* xLowIdx, const unsigned int* xHighIdx, const float* xInter, const float* input, float* outputs)
{
const unsigned int inputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*inputWidth*inputHeight;
const unsigned int outputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*outputWidth*outputHeight;
for (unsigned int ch = blockIdx.x; ch < nbChannels; ch += gridDim.x)
{
for (unsigned int oy = threadIdx.y; oy < outputHeight; oy += blockDim.y)
{
for (unsigned int ox = threadIdx.x; ox < outputWidth; ox += blockDim.x)
{
const unsigned int indexTL = xLowIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexTR = xHighIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBL = xLowIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBR = xHighIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const float top_left = input[indexTL];
const float top_right = input[indexTR];
const float bottom_left = input[indexBL];
const float bottom_right = input[indexBR];
const float top = top_left + (top_right - top_left) * xInter[ox];
const float bottom = bottom_left + (bottom_right - bottom_left) * xInter[ox];
outputs[ ox + oy*outputWidth
+ ch*outputWidth*outputHeight + outputOffset] = top + (bottom - top) * yInter[oy];
}
}
}
} | code for sm_80
Function : _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Z ; /* 0x0000000000037919 */
/* 0x000e680000002700 */
/*0030*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x001fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x006e220000002200 */
/*0070*/ IMAD R3, R3, c[0x0][0x8], R4 ; /* 0x0000020003037a24 */
/* 0x000fe200078e0204 */
/*0080*/ MOV R4, R5 ; /* 0x0000000500047202 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*00b0*/ IMAD R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD R5, R3, c[0x0][0x170], RZ ; /* 0x00005c0003057a24 */
/* 0x000fe400078e02ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x001fe20003f06070 */
/*00e0*/ BSSY B0, 0x450 ; /* 0x0000036000007945 */
/* 0x000fd80003800000 */
/*00f0*/ @P0 BRA 0x440 ; /* 0x0000034000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R6, R4, c[0x0][0x170], R5 ; /* 0x00005c0004067a24 */
/* 0x000fe200078e0205 */
/*0110*/ IADD3 R7, R3, R4, RZ ; /* 0x0000000403077210 */
/* 0x000fe40007ffe0ff */
/*0120*/ MOV R22, R0 ; /* 0x0000000000167202 */
/* 0x000fe40000000f00 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x002fe20003f06070 */
/*0140*/ BSSY B1, 0x410 ; /* 0x000002c000017945 */
/* 0x000fd80003800000 */
/*0150*/ @P0 BRA 0x400 ; /* 0x000002a000000947 */
/* 0x001fea0003800000 */
/*0160*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0170*/ IMAD R9, R7, c[0x0][0x164], R22 ; /* 0x0000590007097a24 */
/* 0x000fe200078e0216 */
/*0180*/ MOV R28, R2 ; /* 0x00000002001c7202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD R26, R9, c[0x0][0x160], R2 ; /* 0x00005800091a7a24 */
/* 0x000fca00078e0202 */
/*01a0*/ IMAD.WIDE.U32 R8, R22, R23, c[0x0][0x178] ; /* 0x00005e0016087625 */
/* 0x000fc800078e0017 */
/*01b0*/ IMAD.WIDE.U32 R10, R22, R23, c[0x0][0x180] ; /* 0x00006000160a7625 */
/* 0x000fc800078e0017 */
/*01c0*/ IMAD.WIDE.U32 R12, R22, R23, c[0x0][0x188] ; /* 0x00006200160c7625 */
/* 0x000fc800078e0017 */
/*01d0*/ IMAD.WIDE.U32 R16, R28.reuse, R23.reuse, c[0x0][0x190] ; /* 0x000064001c107625 */
/* 0x0c0fe200078e0017 */
/*01e0*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x001ea6000c1e1900 */
/*01f0*/ IMAD.WIDE.U32 R18, R28, R23, c[0x0][0x198] ; /* 0x000066001c127625 */
/* 0x000fe200078e0017 */
/*0200*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD R15, R6, c[0x0][0x174], R17 ; /* 0x00005d00060f7a24 */
/* 0x010fc400078e0211 */
/*0240*/ IMAD R21, R6, c[0x0][0x174], R19 ; /* 0x00005d0006157a24 */
/* 0x020fe400078e0213 */
/*0250*/ IMAD R20, R14.reuse, c[0x0][0x170], R15 ; /* 0x00005c000e147a24 */
/* 0x044fe400078e020f */
/*0260*/ IMAD R24, R14, c[0x0][0x170], R21 ; /* 0x00005c000e187a24 */
/* 0x000fe400078e0215 */
/*0270*/ IMAD R27, R25.reuse, c[0x0][0x170], R15 ; /* 0x00005c00191b7a24 */
/* 0x048fe400078e020f */
/*0280*/ IMAD R21, R25, c[0x0][0x170], R21 ; /* 0x00005c0019157a24 */
/* 0x000fe400078e0215 */
/*0290*/ IMAD.WIDE.U32 R14, R20, R23, c[0x0][0x1a8] ; /* 0x00006a00140e7625 */
/* 0x000fc800078e0017 */
/*02a0*/ IMAD.WIDE.U32 R16, R24, R23.reuse, c[0x0][0x1a8] ; /* 0x00006a0018107625 */
/* 0x080fe400078e0017 */
/*02b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R18, R27, R23.reuse, c[0x0][0x1a8] ; /* 0x00006a001b127625 */
/* 0x080fe400078e0017 */
/*02d0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ IMAD.WIDE.U32 R20, R21, R23.reuse, c[0x0][0x1a8] ; /* 0x00006a0015147625 */
/* 0x080fe400078e0017 */
/*02f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1900 */
/*0300*/ IMAD.WIDE.U32 R24, R28, R23, c[0x0][0x1a0] ; /* 0x000068001c187625 */
/* 0x000fc400078e0017 */
/*0310*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000f62000c1e1900 */
/*0340*/ IADD3 R28, R28, c[0x0][0x0], RZ ; /* 0x000000001c1c7a10 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R28, c[0x0][0x160], PT ; /* 0x000058001c007a0c */
/* 0x000fe20003f06070 */
/*0360*/ FADD R29, R17, -R14 ; /* 0x8000000e111d7221 */
/* 0x004fe40000000000 */
/*0370*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x008fe40000000000 */
/*0380*/ FFMA R29, R29, R25, R14 ; /* 0x000000191d1d7223 */
/* 0x010fe4000000000e */
/*0390*/ FFMA R18, R25, R21, R18 ; /* 0x0000001519127223 */
/* 0x000fc80000000012 */
/*03a0*/ FADD R18, -R29, R18 ; /* 0x000000121d127221 */
/* 0x000fe40000000100 */
/*03b0*/ IMAD.WIDE.U32 R14, R26, R23, c[0x0][0x1b0] ; /* 0x00006c001a0e7625 */
/* 0x000fc800078e0017 */
/*03c0*/ FFMA R27, R18, R27, R29 ; /* 0x0000001b121b7223 */
/* 0x020fca000000001d */
/*03d0*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0001e2000c101904 */
/*03e0*/ IADD3 R26, R26, c[0x0][0x0], RZ ; /* 0x000000001a1a7a10 */
/* 0x000fe20007ffe0ff */
/*03f0*/ @!P0 BRA 0x1d0 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R22, R22, c[0x0][0x4], RZ ; /* 0x0000010016167a10 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R22, c[0x0][0x164], PT ; /* 0x0000590016007a0c */
/* 0x000fda0003f06070 */
/*0430*/ @!P0 BRA 0x130 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R4, R4, c[0x0][0xc], RZ ; /* 0x0000030004047a10 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06070 */
/*0470*/ @!P0 BRA 0xd0 ; /* 0xfffffc5000008947 */
/* 0x000fea000383ffff */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cudaSBilinearTF_Forward_kernel( unsigned int outputWidth, unsigned int outputHeight, unsigned int nbChannels, unsigned int batchSize, unsigned int inputWidth, unsigned int inputHeight, const unsigned int* yLowIdx, const unsigned int* yHighIdx, const float* yInter, const unsigned int* xLowIdx, const unsigned int* xHighIdx, const float* xInter, const float* input, float* outputs)
{
const unsigned int inputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*inputWidth*inputHeight;
const unsigned int outputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*outputWidth*outputHeight;
for (unsigned int ch = blockIdx.x; ch < nbChannels; ch += gridDim.x)
{
for (unsigned int oy = threadIdx.y; oy < outputHeight; oy += blockDim.y)
{
for (unsigned int ox = threadIdx.x; ox < outputWidth; ox += blockDim.x)
{
const unsigned int indexTL = xLowIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexTR = xHighIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBL = xLowIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBR = xHighIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const float top_left = input[indexTL];
const float top_right = input[indexTR];
const float bottom_left = input[indexBL];
const float bottom_right = input[indexBR];
const float top = top_left + (top_right - top_left) * xInter[ox];
const float bottom = bottom_left + (bottom_right - bottom_left) * xInter[ox];
outputs[ ox + oy*outputWidth
+ ch*outputWidth*outputHeight + outputOffset] = top + (bottom - top) * yInter[oy];
}
}
}
} | .file "tmpxft_00069035_00000000-6_cudaSBilinearTF_Forward_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.type _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, @function
_Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movl %ecx, 80(%rsp)
movl %r8d, 76(%rsp)
movl %r9d, 72(%rsp)
movq 304(%rsp), %rax
movq %rax, 64(%rsp)
movq 312(%rsp), %rax
movq %rax, 56(%rsp)
movq 320(%rsp), %rax
movq %rax, 48(%rsp)
movq 328(%rsp), %rax
movq %rax, 40(%rsp)
movq 336(%rsp), %rax
movq %rax, 32(%rsp)
movq 344(%rsp), %rax
movq %rax, 24(%rsp)
movq 352(%rsp), %rax
movq %rax, 16(%rsp)
movq 360(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 76(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
leaq 64(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rax
movq %rax, 216(%rsp)
leaq 48(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rax
movq %rax, 240(%rsp)
leaq 24(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .-_Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.globl _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.type _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, @function
_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 72(%rsp)
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .-_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cudaSBilinearTF_Forward_kernel( unsigned int outputWidth, unsigned int outputHeight, unsigned int nbChannels, unsigned int batchSize, unsigned int inputWidth, unsigned int inputHeight, const unsigned int* yLowIdx, const unsigned int* yHighIdx, const float* yInter, const unsigned int* xLowIdx, const unsigned int* xHighIdx, const float* xInter, const float* input, float* outputs)
{
const unsigned int inputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*inputWidth*inputHeight;
const unsigned int outputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*outputWidth*outputHeight;
for (unsigned int ch = blockIdx.x; ch < nbChannels; ch += gridDim.x)
{
for (unsigned int oy = threadIdx.y; oy < outputHeight; oy += blockDim.y)
{
for (unsigned int ox = threadIdx.x; ox < outputWidth; ox += blockDim.x)
{
const unsigned int indexTL = xLowIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexTR = xHighIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBL = xLowIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBR = xHighIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const float top_left = input[indexTL];
const float top_right = input[indexTR];
const float bottom_left = input[indexBL];
const float bottom_right = input[indexBR];
const float top = top_left + (top_right - top_left) * xInter[ox];
const float bottom = bottom_left + (bottom_right - bottom_left) * xInter[ox];
outputs[ ox + oy*outputWidth
+ ch*outputWidth*outputHeight + outputOffset] = top + (bottom - top) * yInter[oy];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSBilinearTF_Forward_kernel( unsigned int outputWidth, unsigned int outputHeight, unsigned int nbChannels, unsigned int batchSize, unsigned int inputWidth, unsigned int inputHeight, const unsigned int* yLowIdx, const unsigned int* yHighIdx, const float* yInter, const unsigned int* xLowIdx, const unsigned int* xHighIdx, const float* xInter, const float* input, float* outputs)
{
const unsigned int inputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*inputWidth*inputHeight;
const unsigned int outputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*outputWidth*outputHeight;
for (unsigned int ch = blockIdx.x; ch < nbChannels; ch += gridDim.x)
{
for (unsigned int oy = threadIdx.y; oy < outputHeight; oy += blockDim.y)
{
for (unsigned int ox = threadIdx.x; ox < outputWidth; ox += blockDim.x)
{
const unsigned int indexTL = xLowIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexTR = xHighIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBL = xLowIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBR = xHighIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const float top_left = input[indexTL];
const float top_right = input[indexTR];
const float bottom_left = input[indexBL];
const float bottom_right = input[indexBR];
const float top = top_left + (top_right - top_left) * xInter[ox];
const float bottom = bottom_left + (bottom_right - bottom_left) * xInter[ox];
outputs[ ox + oy*outputWidth
+ ch*outputWidth*outputHeight + outputOffset] = top + (bottom - top) * yInter[oy];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSBilinearTF_Forward_kernel( unsigned int outputWidth, unsigned int outputHeight, unsigned int nbChannels, unsigned int batchSize, unsigned int inputWidth, unsigned int inputHeight, const unsigned int* yLowIdx, const unsigned int* yHighIdx, const float* yInter, const unsigned int* xLowIdx, const unsigned int* xHighIdx, const float* xInter, const float* input, float* outputs)
{
const unsigned int inputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*inputWidth*inputHeight;
const unsigned int outputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*outputWidth*outputHeight;
for (unsigned int ch = blockIdx.x; ch < nbChannels; ch += gridDim.x)
{
for (unsigned int oy = threadIdx.y; oy < outputHeight; oy += blockDim.y)
{
for (unsigned int ox = threadIdx.x; ox < outputWidth; ox += blockDim.x)
{
const unsigned int indexTL = xLowIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexTR = xHighIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBL = xLowIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBR = xHighIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const float top_left = input[indexTL];
const float top_right = input[indexTR];
const float bottom_left = input[indexBL];
const float bottom_right = input[indexBR];
const float top = top_left + (top_right - top_left) * xInter[ox];
const float bottom = bottom_left + (bottom_right - bottom_left) * xInter[ox];
outputs[ ox + oy*outputWidth
+ ch*outputWidth*outputHeight + outputOffset] = top + (bottom - top) * yInter[oy];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.globl _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.p2align 8
.type _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf,@function
_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s14, s3
s_cbranch_scc1 .LBB0_9
s_load_b32 s2, s[0:1], 0x68
v_bfe_u32 v1, v0, 20, 10
s_add_u32 s12, s0, 0x58
s_addc_u32 s13, s1, 0
s_clause 0x2
s_load_b64 s[24:25], s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b256 s[16:23], s[0:1], 0x30
v_and_b32_e32 v9, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b32 s15, s[0:1], 0x58
s_load_b64 s[26:27], s[0:1], 0x50
v_bfe_u32 v1, v0, 10, 10
s_mul_i32 s5, s5, s4
v_cmp_gt_u32_e64 s0, s24, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s25, v1
v_mul_lo_u32 v4, v2, s3
v_add_nc_u32_e32 v5, s14, v4
v_mul_lo_u32 v0, s5, v4
s_waitcnt lgkmcnt(0)
s_mul_i32 s28, s15, s25
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s25, v5, v[1:2]
v_mov_b32_e32 v3, 0
s_mul_i32 s28, s28, s24
v_mul_lo_u32 v10, s24, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s29
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, s28, v10
s_add_i32 s14, s15, s14
s_cmp_ge_u32 s14, s3
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_and_saveexec_b32 s29, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s1, s[12:13], 0xc
v_mad_u64_u32 v[4:5], null, s5, s14, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v2, v1
s_mov_b32 s33, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s30, s1, 16
s_mul_i32 s31, s24, s30
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s34
v_add_nc_u32_e32 v2, s30, v2
v_add_nc_u32_e32 v11, s31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s1, s25, v2
s_or_b32 s33, s1, s33
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s33
s_cbranch_execz .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s34, s0
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_mov_b32 s36, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s1, s6, v5
v_add_co_ci_u32_e64 v8, s1, s7, v6, s1
v_add_co_u32 v12, s1, s8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s1, s9, v6, s1
v_add_co_u32 v5, s1, s10, v5
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[12:13], off
s_load_b32 s2, s[12:13], 0xc
v_add_co_ci_u32_e64 v6, s1, s11, v6, s1
s_waitcnt lgkmcnt(0)
s_and_b32 s35, s2, 0xffff
s_waitcnt vmcnt(1)
v_mul_lo_u32 v12, v7, s4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v13, v8, s4
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v7, v9 :: v_dual_add_nc_u32 v14, v4, v12
.LBB0_8:
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[7:8]
v_add_co_u32 v17, s1, s16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v18, s1, s17, v16, s1
v_add_co_u32 v19, s1, s18, v15
v_add_co_ci_u32_e64 v20, s1, s19, v16, s1
global_load_b32 v21, v[17:18], off
global_load_b32 v23, v[19:20], off
s_waitcnt vmcnt(1)
v_add3_u32 v17, v4, v21, v12
s_waitcnt vmcnt(0)
v_dual_mov_b32 v18, v8 :: v_dual_add_nc_u32 v19, v14, v23
v_mov_b32_e32 v20, v8
v_mov_b32_e32 v22, v8
v_add3_u32 v21, v4, v21, v13
v_mov_b32_e32 v24, v8
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_lshlrev_b64 v[19:20], 2, v[19:20]
v_add3_u32 v23, v4, v23, v13
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v17, s1, s22, v17
v_add_co_ci_u32_e64 v18, s1, s23, v18, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[23:24], 2, v[23:24]
v_add_co_u32 v19, s1, s22, v19
v_add_co_ci_u32_e64 v20, s1, s23, v20, s1
v_add_co_u32 v21, s1, s22, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v22, s1, s23, v22, s1
v_add_co_u32 v23, s1, s22, v23
v_add_co_ci_u32_e64 v24, s1, s23, v24, s1
v_add_co_u32 v15, s1, s20, v15
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s1, s21, v16, s1
s_clause 0x3
global_load_b32 v17, v[17:18], off
global_load_b32 v18, v[19:20], off
global_load_b32 v19, v[21:22], off
global_load_b32 v20, v[23:24], off
global_load_b32 v16, v[15:16], off
global_load_b32 v21, v[5:6], off
v_add_nc_u32_e32 v15, v11, v7
v_add_nc_u32_e32 v7, s35, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s1, s24, v7
s_or_b32 s36, s1, s36
s_waitcnt vmcnt(2)
v_sub_f32_e32 v20, v20, v19
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v18, v18, v17 :: v_dual_fmac_f32 v19, v20, v16
v_dual_fmac_f32 v17, v18, v16 :: v_dual_mov_b32 v16, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v19, v17
v_lshlrev_b64 v[15:16], 2, v[15:16]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, v21, v8
v_add_co_u32 v15, s2, s26, v15
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s2, s27, v16, s2
global_store_b32 v[15:16], v17, off
s_and_not1_b32 exec_lo, exec_lo, s36
s_cbranch_execnz .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 37
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .Lfunc_end0-_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 39
.sgpr_spill_count: 0
.symbol: _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSBilinearTF_Forward_kernel( unsigned int outputWidth, unsigned int outputHeight, unsigned int nbChannels, unsigned int batchSize, unsigned int inputWidth, unsigned int inputHeight, const unsigned int* yLowIdx, const unsigned int* yHighIdx, const float* yInter, const unsigned int* xLowIdx, const unsigned int* xHighIdx, const float* xInter, const float* input, float* outputs)
{
const unsigned int inputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*inputWidth*inputHeight;
const unsigned int outputOffset
= (blockIdx.z * blockDim.z + threadIdx.z) * nbChannels*outputWidth*outputHeight;
for (unsigned int ch = blockIdx.x; ch < nbChannels; ch += gridDim.x)
{
for (unsigned int oy = threadIdx.y; oy < outputHeight; oy += blockDim.y)
{
for (unsigned int ox = threadIdx.x; ox < outputWidth; ox += blockDim.x)
{
const unsigned int indexTL = xLowIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexTR = xHighIdx[ox] + yLowIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBL = xLowIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const unsigned int indexBR = xHighIdx[ox] + yHighIdx[oy]*inputWidth
+ ch*inputWidth*inputHeight
+ inputOffset;
const float top_left = input[indexTL];
const float top_right = input[indexTR];
const float bottom_left = input[indexBL];
const float bottom_right = input[indexBR];
const float top = top_left + (top_right - top_left) * xInter[ox];
const float bottom = bottom_left + (bottom_right - bottom_left) * xInter[ox];
outputs[ ox + oy*outputWidth
+ ch*outputWidth*outputHeight + outputOffset] = top + (bottom - top) * yInter[oy];
}
}
}
} | .text
.file "cudaSBilinearTF_Forward_kernel.hip"
.globl _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf # -- Begin function _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.p2align 4, 0x90
.type _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf,@function
_Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf: # @_Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 208(%rsp), %rax
movq %rax, 128(%rsp)
leaq 216(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .Lfunc_end0-_Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf,@object # @_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.section .rodata,"a",@progbits
.globl _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.p2align 3, 0x0
_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
.quad _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.size _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf"
.size .L__unnamed_1, 64
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Z ; /* 0x0000000000037919 */
/* 0x000e680000002700 */
/*0030*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x001fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x006e220000002200 */
/*0070*/ IMAD R3, R3, c[0x0][0x8], R4 ; /* 0x0000020003037a24 */
/* 0x000fe200078e0204 */
/*0080*/ MOV R4, R5 ; /* 0x0000000500047202 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*00b0*/ IMAD R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD R5, R3, c[0x0][0x170], RZ ; /* 0x00005c0003057a24 */
/* 0x000fe400078e02ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x001fe20003f06070 */
/*00e0*/ BSSY B0, 0x450 ; /* 0x0000036000007945 */
/* 0x000fd80003800000 */
/*00f0*/ @P0 BRA 0x440 ; /* 0x0000034000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R6, R4, c[0x0][0x170], R5 ; /* 0x00005c0004067a24 */
/* 0x000fe200078e0205 */
/*0110*/ IADD3 R7, R3, R4, RZ ; /* 0x0000000403077210 */
/* 0x000fe40007ffe0ff */
/*0120*/ MOV R22, R0 ; /* 0x0000000000167202 */
/* 0x000fe40000000f00 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x002fe20003f06070 */
/*0140*/ BSSY B1, 0x410 ; /* 0x000002c000017945 */
/* 0x000fd80003800000 */
/*0150*/ @P0 BRA 0x400 ; /* 0x000002a000000947 */
/* 0x001fea0003800000 */
/*0160*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0170*/ IMAD R9, R7, c[0x0][0x164], R22 ; /* 0x0000590007097a24 */
/* 0x000fe200078e0216 */
/*0180*/ MOV R28, R2 ; /* 0x00000002001c7202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD R26, R9, c[0x0][0x160], R2 ; /* 0x00005800091a7a24 */
/* 0x000fca00078e0202 */
/*01a0*/ IMAD.WIDE.U32 R8, R22, R23, c[0x0][0x178] ; /* 0x00005e0016087625 */
/* 0x000fc800078e0017 */
/*01b0*/ IMAD.WIDE.U32 R10, R22, R23, c[0x0][0x180] ; /* 0x00006000160a7625 */
/* 0x000fc800078e0017 */
/*01c0*/ IMAD.WIDE.U32 R12, R22, R23, c[0x0][0x188] ; /* 0x00006200160c7625 */
/* 0x000fc800078e0017 */
/*01d0*/ IMAD.WIDE.U32 R16, R28.reuse, R23.reuse, c[0x0][0x190] ; /* 0x000064001c107625 */
/* 0x0c0fe200078e0017 */
/*01e0*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x001ea6000c1e1900 */
/*01f0*/ IMAD.WIDE.U32 R18, R28, R23, c[0x0][0x198] ; /* 0x000066001c127625 */
/* 0x000fe200078e0017 */
/*0200*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD R15, R6, c[0x0][0x174], R17 ; /* 0x00005d00060f7a24 */
/* 0x010fc400078e0211 */
/*0240*/ IMAD R21, R6, c[0x0][0x174], R19 ; /* 0x00005d0006157a24 */
/* 0x020fe400078e0213 */
/*0250*/ IMAD R20, R14.reuse, c[0x0][0x170], R15 ; /* 0x00005c000e147a24 */
/* 0x044fe400078e020f */
/*0260*/ IMAD R24, R14, c[0x0][0x170], R21 ; /* 0x00005c000e187a24 */
/* 0x000fe400078e0215 */
/*0270*/ IMAD R27, R25.reuse, c[0x0][0x170], R15 ; /* 0x00005c00191b7a24 */
/* 0x048fe400078e020f */
/*0280*/ IMAD R21, R25, c[0x0][0x170], R21 ; /* 0x00005c0019157a24 */
/* 0x000fe400078e0215 */
/*0290*/ IMAD.WIDE.U32 R14, R20, R23, c[0x0][0x1a8] ; /* 0x00006a00140e7625 */
/* 0x000fc800078e0017 */
/*02a0*/ IMAD.WIDE.U32 R16, R24, R23.reuse, c[0x0][0x1a8] ; /* 0x00006a0018107625 */
/* 0x080fe400078e0017 */
/*02b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R18, R27, R23.reuse, c[0x0][0x1a8] ; /* 0x00006a001b127625 */
/* 0x080fe400078e0017 */
/*02d0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ IMAD.WIDE.U32 R20, R21, R23.reuse, c[0x0][0x1a8] ; /* 0x00006a0015147625 */
/* 0x080fe400078e0017 */
/*02f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1900 */
/*0300*/ IMAD.WIDE.U32 R24, R28, R23, c[0x0][0x1a0] ; /* 0x000068001c187625 */
/* 0x000fc400078e0017 */
/*0310*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000f62000c1e1900 */
/*0340*/ IADD3 R28, R28, c[0x0][0x0], RZ ; /* 0x000000001c1c7a10 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R28, c[0x0][0x160], PT ; /* 0x000058001c007a0c */
/* 0x000fe20003f06070 */
/*0360*/ FADD R29, R17, -R14 ; /* 0x8000000e111d7221 */
/* 0x004fe40000000000 */
/*0370*/ FADD R21, R21, -R18 ; /* 0x8000001215157221 */
/* 0x008fe40000000000 */
/*0380*/ FFMA R29, R29, R25, R14 ; /* 0x000000191d1d7223 */
/* 0x010fe4000000000e */
/*0390*/ FFMA R18, R25, R21, R18 ; /* 0x0000001519127223 */
/* 0x000fc80000000012 */
/*03a0*/ FADD R18, -R29, R18 ; /* 0x000000121d127221 */
/* 0x000fe40000000100 */
/*03b0*/ IMAD.WIDE.U32 R14, R26, R23, c[0x0][0x1b0] ; /* 0x00006c001a0e7625 */
/* 0x000fc800078e0017 */
/*03c0*/ FFMA R27, R18, R27, R29 ; /* 0x0000001b121b7223 */
/* 0x020fca000000001d */
/*03d0*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0001e2000c101904 */
/*03e0*/ IADD3 R26, R26, c[0x0][0x0], RZ ; /* 0x000000001a1a7a10 */
/* 0x000fe20007ffe0ff */
/*03f0*/ @!P0 BRA 0x1d0 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R22, R22, c[0x0][0x4], RZ ; /* 0x0000010016167a10 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R22, c[0x0][0x164], PT ; /* 0x0000590016007a0c */
/* 0x000fda0003f06070 */
/*0430*/ @!P0 BRA 0x130 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R4, R4, c[0x0][0xc], RZ ; /* 0x0000030004047a10 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06070 */
/*0470*/ @!P0 BRA 0xd0 ; /* 0xfffffc5000008947 */
/* 0x000fea000383ffff */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.globl _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.p2align 8
.type _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf,@function
_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s14, s3
s_cbranch_scc1 .LBB0_9
s_load_b32 s2, s[0:1], 0x68
v_bfe_u32 v1, v0, 20, 10
s_add_u32 s12, s0, 0x58
s_addc_u32 s13, s1, 0
s_clause 0x2
s_load_b64 s[24:25], s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b256 s[16:23], s[0:1], 0x30
v_and_b32_e32 v9, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b32 s15, s[0:1], 0x58
s_load_b64 s[26:27], s[0:1], 0x50
v_bfe_u32 v1, v0, 10, 10
s_mul_i32 s5, s5, s4
v_cmp_gt_u32_e64 s0, s24, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s25, v1
v_mul_lo_u32 v4, v2, s3
v_add_nc_u32_e32 v5, s14, v4
v_mul_lo_u32 v0, s5, v4
s_waitcnt lgkmcnt(0)
s_mul_i32 s28, s15, s25
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s25, v5, v[1:2]
v_mov_b32_e32 v3, 0
s_mul_i32 s28, s28, s24
v_mul_lo_u32 v10, s24, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s29
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, s28, v10
s_add_i32 s14, s15, s14
s_cmp_ge_u32 s14, s3
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_and_saveexec_b32 s29, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s1, s[12:13], 0xc
v_mad_u64_u32 v[4:5], null, s5, s14, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v2, v1
s_mov_b32 s33, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s30, s1, 16
s_mul_i32 s31, s24, s30
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s34
v_add_nc_u32_e32 v2, s30, v2
v_add_nc_u32_e32 v11, s31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s1, s25, v2
s_or_b32 s33, s1, s33
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s33
s_cbranch_execz .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s34, s0
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_mov_b32 s36, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s1, s6, v5
v_add_co_ci_u32_e64 v8, s1, s7, v6, s1
v_add_co_u32 v12, s1, s8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s1, s9, v6, s1
v_add_co_u32 v5, s1, s10, v5
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[12:13], off
s_load_b32 s2, s[12:13], 0xc
v_add_co_ci_u32_e64 v6, s1, s11, v6, s1
s_waitcnt lgkmcnt(0)
s_and_b32 s35, s2, 0xffff
s_waitcnt vmcnt(1)
v_mul_lo_u32 v12, v7, s4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v13, v8, s4
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v7, v9 :: v_dual_add_nc_u32 v14, v4, v12
.LBB0_8:
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[7:8]
v_add_co_u32 v17, s1, s16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v18, s1, s17, v16, s1
v_add_co_u32 v19, s1, s18, v15
v_add_co_ci_u32_e64 v20, s1, s19, v16, s1
global_load_b32 v21, v[17:18], off
global_load_b32 v23, v[19:20], off
s_waitcnt vmcnt(1)
v_add3_u32 v17, v4, v21, v12
s_waitcnt vmcnt(0)
v_dual_mov_b32 v18, v8 :: v_dual_add_nc_u32 v19, v14, v23
v_mov_b32_e32 v20, v8
v_mov_b32_e32 v22, v8
v_add3_u32 v21, v4, v21, v13
v_mov_b32_e32 v24, v8
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_lshlrev_b64 v[19:20], 2, v[19:20]
v_add3_u32 v23, v4, v23, v13
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v17, s1, s22, v17
v_add_co_ci_u32_e64 v18, s1, s23, v18, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[23:24], 2, v[23:24]
v_add_co_u32 v19, s1, s22, v19
v_add_co_ci_u32_e64 v20, s1, s23, v20, s1
v_add_co_u32 v21, s1, s22, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v22, s1, s23, v22, s1
v_add_co_u32 v23, s1, s22, v23
v_add_co_ci_u32_e64 v24, s1, s23, v24, s1
v_add_co_u32 v15, s1, s20, v15
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s1, s21, v16, s1
s_clause 0x3
global_load_b32 v17, v[17:18], off
global_load_b32 v18, v[19:20], off
global_load_b32 v19, v[21:22], off
global_load_b32 v20, v[23:24], off
global_load_b32 v16, v[15:16], off
global_load_b32 v21, v[5:6], off
v_add_nc_u32_e32 v15, v11, v7
v_add_nc_u32_e32 v7, s35, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s1, s24, v7
s_or_b32 s36, s1, s36
s_waitcnt vmcnt(2)
v_sub_f32_e32 v20, v20, v19
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v18, v18, v17 :: v_dual_fmac_f32 v19, v20, v16
v_dual_fmac_f32 v17, v18, v16 :: v_dual_mov_b32 v16, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v19, v17
v_lshlrev_b64 v[15:16], 2, v[15:16]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, v21, v8
v_add_co_u32 v15, s2, s26, v15
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s2, s27, v16, s2
global_store_b32 v[15:16], v17, off
s_and_not1_b32 exec_lo, exec_lo, s36
s_cbranch_execnz .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 37
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .Lfunc_end0-_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 39
.sgpr_spill_count: 0
.symbol: _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00069035_00000000-6_cudaSBilinearTF_Forward_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.type _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, @function
_Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movl %ecx, 80(%rsp)
movl %r8d, 76(%rsp)
movl %r9d, 72(%rsp)
movq 304(%rsp), %rax
movq %rax, 64(%rsp)
movq 312(%rsp), %rax
movq %rax, 56(%rsp)
movq 320(%rsp), %rax
movq %rax, 48(%rsp)
movq 328(%rsp), %rax
movq %rax, 40(%rsp)
movq 336(%rsp), %rax
movq %rax, 32(%rsp)
movq 344(%rsp), %rax
movq %rax, 24(%rsp)
movq 352(%rsp), %rax
movq %rax, 16(%rsp)
movq 360(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 76(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
leaq 64(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rax
movq %rax, 216(%rsp)
leaq 48(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rax
movq %rax, 240(%rsp)
leaq 24(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .-_Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.globl _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.type _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, @function
_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 72(%rsp)
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z77__device_stub__Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_PfjjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .-_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaSBilinearTF_Forward_kernel.hip"
.globl _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf # -- Begin function _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.p2align 4, 0x90
.type _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf,@function
_Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf: # @_Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 208(%rsp), %rax
movq %rax, 128(%rsp)
leaq 216(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, .Lfunc_end0-_Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf,@object # @_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.section .rodata,"a",@progbits
.globl _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.p2align 3, 0x0
_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf:
.quad _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.size _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf"
.size .L__unnamed_1, 64
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30cudaSBilinearTF_Forward_kerneljjjjjjPKjS0_PKfS0_S0_S2_S2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
// compile with:
// nvcc sgemv.cu -o sgemv
__global__ void
sgemv_rowmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[row*n+col] * x[col];
}
y[row] = a*sum;
}
}
__global__ void
sgemv_colmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[col*n+row] * x[col];
}
y[row] = a*sum;
}
}
int main() {
int n=2000;
int memSize = n*sizeof(int);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float *a, *d_a;
a = (float*) malloc (n*sizeof(*a));
cudaMalloc( (void**) &d_a, memSize);
float *b, *d_b;
b = (float*) malloc (n*sizeof(*b));
cudaMalloc( (void**) &d_b, memSize);
float *m, *d_m;
m = (float*) malloc (n*n*sizeof(*b));
cudaMalloc( (void**) &d_m, memSize*n);
for(int j=0; j<n; j++){
a[j] = (float) j;
b[j] = (float) 0;
for(int k=0; k<n; k++)
m[j*n+k] = (float) j+k;
}
float p = 1.0;
cudaMemcpy( d_a, a, memSize, cudaMemcpyHostToDevice);
cudaMemcpy( d_b, b, memSize, cudaMemcpyHostToDevice);
cudaMemcpy( d_m, m, memSize*n, cudaMemcpyHostToDevice);
dim3 block(256);
dim3 grid((n+block.x-1)/(block.x));
cudaEventRecord(start);
sgemv_rowmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
cudaEventRecord(stop);
cudaMemcpy( b, d_b, memSize, cudaMemcpyDeviceToHost);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime row-major sgemv [s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
cudaEventRecord(start);
sgemv_colmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
cudaEventRecord(stop);
cudaMemcpy( b, d_b, memSize, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime col-major sgemv[s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
cudaFree(d_a);
free(a);
cudaFree(d_b);
free(b);
cudaFree(d_m);
free(m);
return 0;
} | .file "tmpxft_0018446f_00000000-6_sgemv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
.type _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_, @function
_Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sgemv_rowmajorifPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_, .-_Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
.globl _Z14sgemv_rowmajorifPfS_S_
.type _Z14sgemv_rowmajorifPfS_S_, @function
_Z14sgemv_rowmajorifPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14sgemv_rowmajorifPfS_S_, .-_Z14sgemv_rowmajorifPfS_S_
.globl _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
.type _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_, @function
_Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sgemv_colmajorifPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_, .-_Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
.globl _Z14sgemv_colmajorifPfS_S_
.type _Z14sgemv_colmajorifPfS_S_, @function
_Z14sgemv_colmajorifPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14sgemv_colmajorifPfS_S_, .-_Z14sgemv_colmajorifPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\n\nruntime row-major sgemv [s]: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nresult:\n"
.LC5:
.string "%f\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "\n\nruntime col-major sgemv[s]: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $8000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $8000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $16000000, %edi
call malloc@PLT
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $16000000, %esi
call cudaMalloc@PLT
movq %r12, %rdx
movl $0, %esi
movl $0, %ecx
.L21:
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
movss %xmm1, 0(%rbp,%rcx,4)
movl $0x00000000, (%rbx,%rcx,4)
movl $0, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $2000, %rax
jne .L20
addq $1, %rcx
addl $2000, %esi
addq $8000, %rdx
cmpl $4000000, %esi
jne .L21
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16000000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $8, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 48(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L22:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %r13
leaq 40(%rbx), %r15
movq %rbx, %r14
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r14
cmpq %r15, %r14
jne .L23
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L24:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %r14
.L25:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r15, %r13
jne .L25
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movss .LC1(%rip), %xmm0
movl $2000, %edi
call _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
jmp .L22
.L33:
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movss .LC1(%rip), %xmm0
movl $2000, %edi
call _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
jmp .L24
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z14sgemv_colmajorifPfS_S_"
.LC8:
.string "_Z14sgemv_rowmajorifPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sgemv_colmajorifPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sgemv_rowmajorifPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
// compile with:
// nvcc sgemv.cu -o sgemv
__global__ void
sgemv_rowmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[row*n+col] * x[col];
}
y[row] = a*sum;
}
}
__global__ void
sgemv_colmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[col*n+row] * x[col];
}
y[row] = a*sum;
}
}
int main() {
int n=2000;
int memSize = n*sizeof(int);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float *a, *d_a;
a = (float*) malloc (n*sizeof(*a));
cudaMalloc( (void**) &d_a, memSize);
float *b, *d_b;
b = (float*) malloc (n*sizeof(*b));
cudaMalloc( (void**) &d_b, memSize);
float *m, *d_m;
m = (float*) malloc (n*n*sizeof(*b));
cudaMalloc( (void**) &d_m, memSize*n);
for(int j=0; j<n; j++){
a[j] = (float) j;
b[j] = (float) 0;
for(int k=0; k<n; k++)
m[j*n+k] = (float) j+k;
}
float p = 1.0;
cudaMemcpy( d_a, a, memSize, cudaMemcpyHostToDevice);
cudaMemcpy( d_b, b, memSize, cudaMemcpyHostToDevice);
cudaMemcpy( d_m, m, memSize*n, cudaMemcpyHostToDevice);
dim3 block(256);
dim3 grid((n+block.x-1)/(block.x));
cudaEventRecord(start);
sgemv_rowmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
cudaEventRecord(stop);
cudaMemcpy( b, d_b, memSize, cudaMemcpyDeviceToHost);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime row-major sgemv [s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
cudaEventRecord(start);
sgemv_colmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
cudaEventRecord(stop);
cudaMemcpy( b, d_b, memSize, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime col-major sgemv[s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
cudaFree(d_a);
free(a);
cudaFree(d_b);
free(b);
cudaFree(d_m);
free(m);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// compile with:
// nvcc sgemv.cu -o sgemv
__global__ void
sgemv_rowmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[row*n+col] * x[col];
}
y[row] = a*sum;
}
}
__global__ void
sgemv_colmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[col*n+row] * x[col];
}
y[row] = a*sum;
}
}
int main() {
int n=2000;
int memSize = n*sizeof(int);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float *a, *d_a;
a = (float*) malloc (n*sizeof(*a));
hipMalloc( (void**) &d_a, memSize);
float *b, *d_b;
b = (float*) malloc (n*sizeof(*b));
hipMalloc( (void**) &d_b, memSize);
float *m, *d_m;
m = (float*) malloc (n*n*sizeof(*b));
hipMalloc( (void**) &d_m, memSize*n);
for(int j=0; j<n; j++){
a[j] = (float) j;
b[j] = (float) 0;
for(int k=0; k<n; k++)
m[j*n+k] = (float) j+k;
}
float p = 1.0;
hipMemcpy( d_a, a, memSize, hipMemcpyHostToDevice);
hipMemcpy( d_b, b, memSize, hipMemcpyHostToDevice);
hipMemcpy( d_m, m, memSize*n, hipMemcpyHostToDevice);
dim3 block(256);
dim3 grid((n+block.x-1)/(block.x));
hipEventRecord(start);
sgemv_rowmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
hipEventRecord(stop);
hipMemcpy( b, d_b, memSize, hipMemcpyDeviceToHost);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime row-major sgemv [s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
hipEventRecord(start);
sgemv_colmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
hipEventRecord(stop);
hipMemcpy( b, d_b, memSize, hipMemcpyDeviceToHost);
hipEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime col-major sgemv[s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
hipFree(d_a);
free(a);
hipFree(d_b);
free(b);
hipFree(d_m);
free(m);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// compile with:
// nvcc sgemv.cu -o sgemv
__global__ void
sgemv_rowmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[row*n+col] * x[col];
}
y[row] = a*sum;
}
}
__global__ void
sgemv_colmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[col*n+row] * x[col];
}
y[row] = a*sum;
}
}
int main() {
int n=2000;
int memSize = n*sizeof(int);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float *a, *d_a;
a = (float*) malloc (n*sizeof(*a));
hipMalloc( (void**) &d_a, memSize);
float *b, *d_b;
b = (float*) malloc (n*sizeof(*b));
hipMalloc( (void**) &d_b, memSize);
float *m, *d_m;
m = (float*) malloc (n*n*sizeof(*b));
hipMalloc( (void**) &d_m, memSize*n);
for(int j=0; j<n; j++){
a[j] = (float) j;
b[j] = (float) 0;
for(int k=0; k<n; k++)
m[j*n+k] = (float) j+k;
}
float p = 1.0;
hipMemcpy( d_a, a, memSize, hipMemcpyHostToDevice);
hipMemcpy( d_b, b, memSize, hipMemcpyHostToDevice);
hipMemcpy( d_m, m, memSize*n, hipMemcpyHostToDevice);
dim3 block(256);
dim3 grid((n+block.x-1)/(block.x));
hipEventRecord(start);
sgemv_rowmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
hipEventRecord(stop);
hipMemcpy( b, d_b, memSize, hipMemcpyDeviceToHost);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime row-major sgemv [s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
hipEventRecord(start);
sgemv_colmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
hipEventRecord(stop);
hipMemcpy( b, d_b, memSize, hipMemcpyDeviceToHost);
hipEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime col-major sgemv[s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
hipFree(d_a);
free(a);
hipFree(d_b);
free(b);
hipFree(d_m);
free(m);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sgemv_rowmajorifPfS_S_
.globl _Z14sgemv_rowmajorifPfS_S_
.p2align 8
.type _Z14sgemv_rowmajorifPfS_S_,@function
_Z14sgemv_rowmajorifPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:
global_load_b32 v4, v[2:3], off
s_load_b32 s3, s[6:7], 0x0
v_add_co_u32 v2, vcc_lo, v2, 4
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s3, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v3, s2, v0
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sgemv_rowmajorifPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sgemv_rowmajorifPfS_S_, .Lfunc_end0-_Z14sgemv_rowmajorifPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14sgemv_colmajorifPfS_S_
.globl _Z14sgemv_colmajorifPfS_S_
.p2align 8
.type _Z14sgemv_colmajorifPfS_S_,@function
_Z14sgemv_colmajorifPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
s_mov_b32 s3, s2
.p2align 6
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v3
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v0, 0
.LBB1_5:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v3, s2, v0
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sgemv_colmajorifPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14sgemv_colmajorifPfS_S_, .Lfunc_end1-_Z14sgemv_colmajorifPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sgemv_rowmajorifPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sgemv_rowmajorifPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sgemv_colmajorifPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sgemv_colmajorifPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// compile with:
// nvcc sgemv.cu -o sgemv
__global__ void
sgemv_rowmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[row*n+col] * x[col];
}
y[row] = a*sum;
}
}
__global__ void
sgemv_colmajor(int n, float a, float *m, float *x, float *y){
int row = blockIdx.x*blockDim.x + threadIdx.x;
float sum = 0.0;
if (row < n){
for( int col=0; col<n; col++){
sum+= m[col*n+row] * x[col];
}
y[row] = a*sum;
}
}
int main() {
int n=2000;
int memSize = n*sizeof(int);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float *a, *d_a;
a = (float*) malloc (n*sizeof(*a));
hipMalloc( (void**) &d_a, memSize);
float *b, *d_b;
b = (float*) malloc (n*sizeof(*b));
hipMalloc( (void**) &d_b, memSize);
float *m, *d_m;
m = (float*) malloc (n*n*sizeof(*b));
hipMalloc( (void**) &d_m, memSize*n);
for(int j=0; j<n; j++){
a[j] = (float) j;
b[j] = (float) 0;
for(int k=0; k<n; k++)
m[j*n+k] = (float) j+k;
}
float p = 1.0;
hipMemcpy( d_a, a, memSize, hipMemcpyHostToDevice);
hipMemcpy( d_b, b, memSize, hipMemcpyHostToDevice);
hipMemcpy( d_m, m, memSize*n, hipMemcpyHostToDevice);
dim3 block(256);
dim3 grid((n+block.x-1)/(block.x));
hipEventRecord(start);
sgemv_rowmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
hipEventRecord(stop);
hipMemcpy( b, d_b, memSize, hipMemcpyDeviceToHost);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime row-major sgemv [s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
hipEventRecord(start);
sgemv_colmajor<<<grid,block>>>(n, p, d_m, d_a, d_b);
hipEventRecord(stop);
hipMemcpy( b, d_b, memSize, hipMemcpyDeviceToHost);
hipEventElapsedTime(&milliseconds, start, stop);
printf("\n\nruntime col-major sgemv[s]: %f\n", milliseconds/1000.0);
printf("\nresult:\n");
for(int j=0; j<10; j++)
printf("%f\n",b[j]);
hipFree(d_a);
free(a);
hipFree(d_b);
free(b);
hipFree(d_m);
free(m);
return 0;
} | .text
.file "sgemv.hip"
.globl _Z29__device_stub__sgemv_rowmajorifPfS_S_ # -- Begin function _Z29__device_stub__sgemv_rowmajorifPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__sgemv_rowmajorifPfS_S_,@function
_Z29__device_stub__sgemv_rowmajorifPfS_S_: # @_Z29__device_stub__sgemv_rowmajorifPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sgemv_rowmajorifPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sgemv_rowmajorifPfS_S_, .Lfunc_end0-_Z29__device_stub__sgemv_rowmajorifPfS_S_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__sgemv_colmajorifPfS_S_ # -- Begin function _Z29__device_stub__sgemv_colmajorifPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__sgemv_colmajorifPfS_S_,@function
_Z29__device_stub__sgemv_colmajorifPfS_S_: # @_Z29__device_stub__sgemv_colmajorifPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sgemv_colmajorifPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__sgemv_colmajorifPfS_S_, .Lfunc_end1-_Z29__device_stub__sgemv_colmajorifPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movl $16000000, %edi # imm = 0xF42400
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $16000000, %esi # imm = 0xF42400
callq hipMalloc
xorl %r12d, %r12d
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movq %r15, %rax
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss %xmm0, (%rbx,%r12,4)
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rax,%rcx,4)
incq %rcx
cmpq $2000, %rcx # imm = 0x7D0
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %r12
addq $8000, %rax # imm = 0x1F40
cmpq $2000, %r12 # imm = 0x7D0
jne .LBB2_1
# %bb.4:
movabsq $4294967304, %r12 # imm = 0x100000008
movq 32(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16000000, %edx # imm = 0xF42400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 248(%r12), %r13
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl $2000, 12(%rsp) # imm = 0x7D0
movl $1065353216, 8(%rsp) # imm = 0x3F800000
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14sgemv_rowmajorifPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 40(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $10, %rbp
jne .LBB2_7
# %bb.8:
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl $2000, 12(%rsp) # imm = 0x7D0
movl $1065353216, 8(%rsp) # imm = 0x3F800000
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14sgemv_colmajorifPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 40(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_11
# %bb.12:
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sgemv_rowmajorifPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sgemv_colmajorifPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sgemv_rowmajorifPfS_S_,@object # @_Z14sgemv_rowmajorifPfS_S_
.section .rodata,"a",@progbits
.globl _Z14sgemv_rowmajorifPfS_S_
.p2align 3, 0x0
_Z14sgemv_rowmajorifPfS_S_:
.quad _Z29__device_stub__sgemv_rowmajorifPfS_S_
.size _Z14sgemv_rowmajorifPfS_S_, 8
.type _Z14sgemv_colmajorifPfS_S_,@object # @_Z14sgemv_colmajorifPfS_S_
.globl _Z14sgemv_colmajorifPfS_S_
.p2align 3, 0x0
_Z14sgemv_colmajorifPfS_S_:
.quad _Z29__device_stub__sgemv_colmajorifPfS_S_
.size _Z14sgemv_colmajorifPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\nruntime row-major sgemv [s]: %f\n"
.size .L.str, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nruntime col-major sgemv[s]: %f\n"
.size .L.str.3, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14sgemv_rowmajorifPfS_S_"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14sgemv_colmajorifPfS_S_"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\nresult:"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sgemv_rowmajorifPfS_S_
.addrsig_sym _Z29__device_stub__sgemv_colmajorifPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sgemv_rowmajorifPfS_S_
.addrsig_sym _Z14sgemv_colmajorifPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018446f_00000000-6_sgemv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
.type _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_, @function
_Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sgemv_rowmajorifPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_, .-_Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
.globl _Z14sgemv_rowmajorifPfS_S_
.type _Z14sgemv_rowmajorifPfS_S_, @function
_Z14sgemv_rowmajorifPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14sgemv_rowmajorifPfS_S_, .-_Z14sgemv_rowmajorifPfS_S_
.globl _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
.type _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_, @function
_Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sgemv_colmajorifPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_, .-_Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
.globl _Z14sgemv_colmajorifPfS_S_
.type _Z14sgemv_colmajorifPfS_S_, @function
_Z14sgemv_colmajorifPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14sgemv_colmajorifPfS_S_, .-_Z14sgemv_colmajorifPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\n\nruntime row-major sgemv [s]: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nresult:\n"
.LC5:
.string "%f\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "\n\nruntime col-major sgemv[s]: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $8000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $8000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $16000000, %edi
call malloc@PLT
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $16000000, %esi
call cudaMalloc@PLT
movq %r12, %rdx
movl $0, %esi
movl $0, %ecx
.L21:
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
movss %xmm1, 0(%rbp,%rcx,4)
movl $0x00000000, (%rbx,%rcx,4)
movl $0, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $2000, %rax
jne .L20
addq $1, %rcx
addl $2000, %esi
addq $8000, %rdx
cmpl $4000000, %esi
jne .L21
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16000000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $8, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 48(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L22:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %r13
leaq 40(%rbx), %r15
movq %rbx, %r14
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r14
cmpq %r15, %r14
jne .L23
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L24:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %r14
.L25:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r15, %r13
jne .L25
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movss .LC1(%rip), %xmm0
movl $2000, %edi
call _Z40__device_stub__Z14sgemv_rowmajorifPfS_S_ifPfS_S_
jmp .L22
.L33:
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movss .LC1(%rip), %xmm0
movl $2000, %edi
call _Z40__device_stub__Z14sgemv_colmajorifPfS_S_ifPfS_S_
jmp .L24
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z14sgemv_colmajorifPfS_S_"
.LC8:
.string "_Z14sgemv_rowmajorifPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sgemv_colmajorifPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sgemv_rowmajorifPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgemv.hip"
.globl _Z29__device_stub__sgemv_rowmajorifPfS_S_ # -- Begin function _Z29__device_stub__sgemv_rowmajorifPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__sgemv_rowmajorifPfS_S_,@function
_Z29__device_stub__sgemv_rowmajorifPfS_S_: # @_Z29__device_stub__sgemv_rowmajorifPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sgemv_rowmajorifPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sgemv_rowmajorifPfS_S_, .Lfunc_end0-_Z29__device_stub__sgemv_rowmajorifPfS_S_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__sgemv_colmajorifPfS_S_ # -- Begin function _Z29__device_stub__sgemv_colmajorifPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__sgemv_colmajorifPfS_S_,@function
_Z29__device_stub__sgemv_colmajorifPfS_S_: # @_Z29__device_stub__sgemv_colmajorifPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sgemv_colmajorifPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__sgemv_colmajorifPfS_S_, .Lfunc_end1-_Z29__device_stub__sgemv_colmajorifPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movl $16000000, %edi # imm = 0xF42400
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $16000000, %esi # imm = 0xF42400
callq hipMalloc
xorl %r12d, %r12d
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movq %r15, %rax
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss %xmm0, (%rbx,%r12,4)
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rax,%rcx,4)
incq %rcx
cmpq $2000, %rcx # imm = 0x7D0
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %r12
addq $8000, %rax # imm = 0x1F40
cmpq $2000, %r12 # imm = 0x7D0
jne .LBB2_1
# %bb.4:
movabsq $4294967304, %r12 # imm = 0x100000008
movq 32(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16000000, %edx # imm = 0xF42400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 248(%r12), %r13
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl $2000, 12(%rsp) # imm = 0x7D0
movl $1065353216, 8(%rsp) # imm = 0x3F800000
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14sgemv_rowmajorifPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 40(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $10, %rbp
jne .LBB2_7
# %bb.8:
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl $2000, 12(%rsp) # imm = 0x7D0
movl $1065353216, 8(%rsp) # imm = 0x3F800000
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14sgemv_colmajorifPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 40(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_11
# %bb.12:
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sgemv_rowmajorifPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sgemv_colmajorifPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sgemv_rowmajorifPfS_S_,@object # @_Z14sgemv_rowmajorifPfS_S_
.section .rodata,"a",@progbits
.globl _Z14sgemv_rowmajorifPfS_S_
.p2align 3, 0x0
_Z14sgemv_rowmajorifPfS_S_:
.quad _Z29__device_stub__sgemv_rowmajorifPfS_S_
.size _Z14sgemv_rowmajorifPfS_S_, 8
.type _Z14sgemv_colmajorifPfS_S_,@object # @_Z14sgemv_colmajorifPfS_S_
.globl _Z14sgemv_colmajorifPfS_S_
.p2align 3, 0x0
_Z14sgemv_colmajorifPfS_S_:
.quad _Z29__device_stub__sgemv_colmajorifPfS_S_
.size _Z14sgemv_colmajorifPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\nruntime row-major sgemv [s]: %f\n"
.size .L.str, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nruntime col-major sgemv[s]: %f\n"
.size .L.str.3, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14sgemv_rowmajorifPfS_S_"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14sgemv_colmajorifPfS_S_"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\nresult:"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sgemv_rowmajorifPfS_S_
.addrsig_sym _Z29__device_stub__sgemv_colmajorifPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sgemv_rowmajorifPfS_S_
.addrsig_sym _Z14sgemv_colmajorifPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits